7-444 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | copyright ?intersil corporation 1999 cd4071bms, cd4072bms cd4075bms cmos or gate pinout cd4071bms top view cd4072bms top view cd4075bms top view a b j = a + b k = c + c c d vss vdd h g m = g + h l = e + f f e 1 2 3 4 5 6 7 14 13 12 11 10 9 8 j = a + b + c + d a b c d nc vss vdd k = e +f + g + h h g f e nc 1 2 3 4 5 6 7 14 13 12 11 10 9 8 nc = no connection a b d e f k = d + e + f vss vdd g h i l = g + h + i j = a + b + c c 1 2 3 4 5 6 7 14 13 12 11 10 9 8 features high-voltage types (20v rating) cd4071bms quad 2-input or gate cd4072bms dual 4-input or gate cd4075bms triple 3-input or gate medium speed operation: - tphl, tplh = 60ns (typ) at 10v 100% tested for quiescent current at 20v maximum input current of 1 a at 18v over full pack- age temperature range; 100na at 18v and +25 o c standardized symmetrical output characteristics noise margin (over full package temperature range): - 1v at vdd = 5v - 2v at vdd = 10v - 2.5v at vdd = 15v 5v, 10v and 15v parametric ratings meets all requirements of jedec tentative standard no. 13b, ?tandard speci?ations for description of ??series cmos devices description cd4071bms, cd4072bms and cd4075bms or gates pro- vide the system designer with direct implementation of the positive-logic or function and supplement the existing fam- ily of cmos gates. the cd4071bms, cd4072bms and cd4075bms are supplied in these 14 lead outline packages: braze seal dip *h4h ?h4q frit seal dip h1b ceramic flatpack h3w *cd4071, cd4072 ?cd4075 only file number 3323 december 1992
7-445 cd4071bms, cd4072bms, cd4075bms functional diagram cd4071bms cd4072bms cd4075bms b a d c f e h g 1 2 5 6 8 9 12 13 3 4 10 11 j k l m vss vdd 14 7 1 13 j k vss vdd 14 7 a b c d e f g h 2 3 4 5 9 10 11 12 10 l vss vdd 14 7 i h g 11 12 13 9 j c b a 1 2 8 6 k f e d 3 4 5
7-446 speci?ations cd4071bms, cd4072bms, cd4075bms absolute maximum ratings reliability information dc supply voltage range, (vdd) . . . . . . . . . . . . . . . -0.5v to +20v (voltage referenced to vss terminals) input voltage range, all inputs . . . . . . . . . . . . .-0.5v to vdd +0.5v dc input current, any one input . . . . . . . . . . . . . . . . . . . . . . . . 10ma operating temperature range . . . . . . . . . . . . . . . . -55 o c to +125 o c package types d, f, k, h storage temperature range (tstg) . . . . . . . . . . . -65 o c to +150 o c lead temperature (during soldering) . . . . . . . . . . . . . . . . . +265 o c at distance 1/16 1/32 inch (1.59mm 0.79mm) from case for 10s maximum thermal resistance . . . . . . . . . . . . . . . . ja jc ceramic dip and frit package . . . . . 80 o c/w 20 o c/w flatpack package . . . . . . . . . . . . . . . . 70 o c/w 20 o c/w maximum package power dissipation (pd) at +125 o c for ta = -55 o c to +100 o c (package type d, f, k) . . . . . . 500mw for ta = +100 o c to +125 o c (package type d, f, k) . . . . . derate linearity at 12mw/ o c to 200mw device dissipation per output transistor . . . . . . . . . . . . . . . 100mw for ta = full package temperature range (all package types) junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c table 1. dc electrical performance characteristics parameter symbol conditions (note 1) group a subgroups temperature limits units min max supply current idd vdd = 20v, vin = vdd or gnd 1 +25 o c - 0.5 a 2 +125 o c-50 a vdd = 18v, vin = vdd or gnd 3 -55 o c - 0.5 a input leakage current iil vin = vdd or gnd vdd = 20 1 +25 o c -100 - na 2 +125 o c -1000 - na vdd = 18v 3 -55 o c -100 - na input leakage current iih vin = vdd or gnd vdd = 20 1 +25 o c - 100 na 2 +125 o c - 1000 na vdd = 18v 3 -55 o c - 100 na output voltage vol15 vdd = 15v, no load 1, 2, 3 +25 o c, +125 o c, -55 o c - 50 mv output voltage voh15 vdd = 15v, no load (note 3) 1, 2, 3 +25 o c, +125 o c, -55 o c 14.95 - v output current (sink) iol5 vdd = 5v, vout = 0.4v 1 +25 o c 0.53 - ma output current (sink) iol10 vdd = 10v, vout = 0.5v 1 +25 o c 1.4 - ma output current (sink) iol15 vdd = 15v, vout = 1.5v 1 +25 o c 3.5 - ma output current (source) ioh5a vdd = 5v, vout = 4.6v 1 +25 o c - -0.53 ma output current (source) ioh5b vdd = 5v, vout = 2.5v 1 +25 o c - -1.8 ma output current (source) ioh10 vdd = 10v, vout = 9.5v 1 +25 o c - -1.4 ma output current (source) ioh15 vdd = 15v, vout = 13.5v 1 +25 o c - -3.5 ma n threshold voltage vnth vdd = 10v, iss = -10 a 1 +25 o c -2.8 -0.7 v p threshold voltage vpth vss = 0v, idd = 10 a 1 +25 o c 0.7 2.8 v functional f vdd = 2.8v, vin = vdd or gnd 7 +25 o c voh > vdd/2 vol < vdd/2 v vdd = 20v, vin = vdd or gnd 7 +25 o c vdd = 18v, vin = vdd or gnd 8a +125 o c vdd = 3v, vin = vdd or gnd 8b -55 o c input voltage low (note 2) vil vdd = 5v, voh > 4.5v, vol < 0.5v 1, 2, 3 +25 o c, +125 o c, -55 o c - 1.5 v input voltage high (note 2) vih vdd = 5v, voh > 4.5v, vol < 0.5v 1, 2, 3 +25 o c, +125 o c, -55 o c 3.5 - v input voltage low (note 2) vil vdd = 15v, voh > 13.5v, vol < 1.5v 1, 2, 3 +25 o c, +125 o c, -55 o c- 4 v input voltage high (note 2) vih vdd = 15v, voh > 13.5v, vol < 1.5v 1, 2, 3 +25 o c, +125 o c, -55 o c11 - v notes: 1. all voltages referenced to device gnd, 100% testing being implemented. 2. go/no go test with limits applied to inputs. 3. for accuracy, voltage is measured differentially to vdd. limit is 0.050v max.
7-447 speci?ations cd4071bms, cd4072bms, cd4075bms table 2. ac electrical performance characteristics parameter symbol conditions (notes 1, 2) group a subgroups temperature limits units min max propagation delay tphl tplh vdd = 5v, vin = vdd or gnd 9 +25 o c - 250 ns 10, 11 +125 o c, -55 o c - 338 ns transition time tthl ttlh vdd = 5v, vin = vdd or gnd 9 +25 o c - 200 ns 10, 11 +125 o c, -55 o c - 270 ns notes: 1. cl = 50pf, rl = 200k, input tr, tf < 20ns. 2. -55 o c and +125 o c limits guaranteed, 100% testing being implemented. table 3. electrical performance characteristics parameter symbol conditions notes temperature limits units min max supply current idd vdd = 5v, vin = vdd or gnd 1, 2 -55 o c, +25 o c - 0.25 a +125 o c - 7.5 a vdd = 10v, vin = vdd or gnd 1, 2 -55 o c, +25 o c - 0.5 a +125 o c-15 a vdd = 15v, vin = vdd or gnd 1, 2 -55 o c, +25 o c - 0.5 a +125 o c-30 a output voltage vol vdd = 5v, no load 1, 2 +25 o c, +125 o c, -55 o c -50mv output voltage vol vdd = 10v, no load 1, 2 +25 o c, +125 o c, -55 o c -50mv output voltage voh vdd = 5v, no load 1, 2 +25 o c, +125 o c, -55 o c 4.95 - v output voltage voh vdd = 10v, no load 1, 2 +25 o c, +125 o c, -55 o c 9.95 - v output current (sink) iol5 vdd = 5v, vout = 0.4v 1, 2 +125 o c 0.36 - ma -55 o c 0.64 - ma output current (sink) iol10 vdd = 10v, vout = 0.5v 1, 2 +125 o c 0.9 - ma -55 o c 1.6 - ma output current (sink) iol15 vdd = 15v, vout = 1.5v 1, 2 +125 o c 2.4 - ma -55 o c 4.2 - ma output current (source) ioh5a vdd = 5v, vout = 4.6v 1, 2 +125 o c - -0.36 ma -55 o c - -0.64 ma output current (source) ioh5b vdd = 5v, vout = 2.5v 1, 2 +125 o c - -1.15 ma -55 o c - -2.0 ma output current (source) ioh10 vdd = 10v, vout = 9.5v 1, 2 +125 o c - -0.9 ma -55 o c - -2.6 ma output current (source) ioh15 vdd =15v, vout = 13.5v 1, 2 +125 o c - -2.4 ma -55 o c - -4.2 ma input voltage low vil vdd = 10v, voh > 9v, vol < 1v 1, 2 +25 o c, +125 o c, -55 o c -3v input voltage high vih vdd = 10v, voh > 9v, vol < 1v 1, 2 +25 o c, +125 o c, -55 o c 7-v propagation delay tphl tplh vdd = 10v 1, 2, 3 +25 o c - 120 ns vdd = 15v 1, 2, 3 +25 o c - 90 ns
7-448 speci?ations cd4071bms, cd4072bms, cd4075bms transition time tthl ttlh vdd = 10v 1, 2, 3 +25 o c - 100 ns vdd = 15v 1, 2, 3 +25 o c - 80 ns input capacitance cin any input 1, 2 +25 o c - 7.5 pf notes: 1. all voltages referenced to device gnd. 2. the parameters listed on table 3 are controlled via design or process and are not directly tested. these parameters are chara cterized on initial design release and upon design changes which would affect these characteristics. 3. cl = 50pf, rl = 200k, input tr, tf < 20ns. table 4. post irradiation electrical performance characteristics parameter symbol conditions notes temperature limits units min max supply current idd vdd = 20v, vin = vdd or gnd 1, 4 +25 o c - 2.5 a n threshold voltage vnth vdd = 10v, iss = -10 a 1, 4 +25 o c -2.8 -0.2 v n threshold voltage delta ? vtn vdd = 10v, iss = -10 a 1, 4 +25 o c- 1v p threshold voltage vtp vss = 0v, idd = 10 a 1, 4 +25 o c 0.2 2.8 v p threshold voltage delta ? vtp vss = 0v, idd = 10 a 1, 4 +25 o c- 1v functional f vdd = 18v, vin = vdd or gnd 1 +25 o c voh > vdd/2 vol < vdd/2 v vdd = 3v, vin = vdd or gnd propagation delay time tphl tplh vdd = 5v 1, 2, 3, 4 +25 o c - 1.35 x +25 o c limit ns notes: 1. all voltages referenced to device gnd. 2. cl = 50pf, rl = 200k, input tr, tf < 20ns. 3. see table 2 for +25 o c limit. 4. read and record table 5. burn-in and life test delta parameters +25 o c parameter symbol delta limit supply current - ssi idd 0.1 a output current (sink) iol5 20% x pre-test reading output current (source) ioh5a 20% x pre-test reading table 6. applicable subgroups conformance group mil-std-883 method group a subgroups read and record initial test (pre burn-in) 100% 5004 1, 7, 9 idd, iol5, ioh5a interim test 1 (post burn-in) 100% 5004 1, 7, 9 idd, iol5, ioh5a interim test 2 (post burn-in) 100% 5004 1, 7, 9 idd, iol5, ioh5a pda (note 1) 100% 5004 1, 7, 9, deltas interim test 3 (post burn-in) 100% 5004 1, 7, 9 idd, iol5, ioh5a pda (note 1) 100% 5004 1, 7, 9, deltas final test 100% 5004 2, 3, 8a, 8b, 10, 11 group a sample 5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11 table 3. electrical performance characteristics (continued) parameter symbol conditions notes temperature limits units min max
7-449 speci?ations cd4071bms, cd4072bms, cd4075bms group b subgroup b-5 sample 5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11, deltas subgroups 1, 2, 3, 9, 10, 11 subgroup b-6 sample 5005 1, 7, 9 group d sample 5005 1, 2, 3, 8a, 8b, 9 subgroups 1, 2 3 note: 1. 5% parameteric, 3% functional; cumulative for static 1 and 2. table 7. total dose irradiation conformance groups mil-std-883 method test read and record pre-irrad post-irrad pre-irrad post-irrad group e subgroup 2 5005 1, 7, 9 table 4 1, 9 table 4 table 8. burn-in and irradiation test connections function open ground vdd 9v -0.5v oscillator 50khz 25khz part number cd4071bms static burn-in 1 note 1 3, 4, 10, 11 1, 2, 5 - 9, 12 - 13 14 static burn-in 2 note 1 3, 4, 10, 11 7 1, 2, 5, 6, 8, 9, 12 - 14 dynamic burn- in note 1 - 7 14 3, 4, 10, 11 1, 2, 5, 6, 8, 9, 12, 13 irradiation note 2 3, 4, 10, 11 7 1, 2, 5, 6, 8, 9, 12 - 14 part number cd4072bms static burn-in 1 note 1 1, 6, 8, 13 2 - 5, 7, 9 - 12 14 static burn-in 2 note 1 1, 6, 8, 13 7 2 - 5, 9 - 12, 14 dynamic burn- in note 1 6, 8 7 14 1, 13 2 - 5, 9 - 12 irradiation note 2 1, 6, 8, 13 7 2 - 5, 9 - 12, 14 part number cd4075bms static burn-in 1 note 1 6, 9, 10 1 - 5, 7, 8, 11 - 13 14 static burn-in 2 note 1 6, 9, 10 7 1 - 5, 8, 11 - 14 dynamic burn- in note 1 - 7 14 6, 9, 10 1 - 5, 8, 11 - 13 irradiation note 2 6, 9, 10 7 1 - 5, 8, 11 - 14 note: 1. each pin except vdd and gnd will have a series resistor of 10k 5%, vdd = 18v 0.5v 2. each pin except vdd and gnd will have a series resistor of 47k 5%; group e, subgroup 2, sample size is 4 dice/wafer, 0 failures, vdd = 10v 0.5v table 6. applicable subgroups (continued) conformance group mil-std-883 method group a subgroups read and record
7-450 cd4071bms, cd4072bms, cd4075bms figure 1. schematic diagram for cd4071bms (1 of 4 identical gates) figure 2. logic diagram for cd4071bms (1 of 4 identical gates) figure 3. schematic diagram for cd4072bms (1 of 2 identical gates) figure 4. logic diagram for cd4072bms (1 of 2 identical gates) n p all inputs protected by * cmos protection network vdd vss * 1 (6, 8, 13) n p * 2 (5,9, 12) n p n 3 (4, 10, 11) pp nn vss 7 vdd 14 p j 3 (4, 10, 11) 2 (5, 9, 12) 1 (6, 8, 13) b a n p all inputs protected by * cmos protection network vdd vss * 2 (12) n p n 1 (13) p inv 2 ** inv 3 ** inv 4 ** * 3 (11) * 5 (9) * 4 (10) p p n n n p p vss vdd n n p vdd vdd vdd vss vss vss vss vdd inv.1 ** ** inverters 2, 3 and 4 are identical to inverter 1. j 1 (13) 3 (11) 2 (12) a b 4 (10) 5 (9) d c
7-451 cd4071bms, cd4072bms, cd4075bms figure 5. schematic diagram for cd4075bms (1 of 3 identical gates) figure 6. logic diagram for cd4075bms (1 of 3 identical gates) typical performance characteristics figure 7. typical voltage transfer characteris- tics figure 8. typical propagation delay time as a function of load capacitance n p * 8 (5, 13) p p * 2 (4, 12) * 1 (3, 11) n p n p n p all inputs protected by * cmos protection network vdd vss n p n 9 (6, 10) n p vdd 14 vss 7 n n j 9 (6, 10) 2 (4, 12) 1 (3, 11) a b 8 (5, 13) c ambient temperature (t a ) = +25 o c input voltage (vin) (v) 0 5 supply voltage (vdd) = 15v 10 15 20 output voltage (vo) (v) 5101520 10v 5v ambient temperature (t a ) = +25 o c load capacitance (cl) (pf) 0 supply voltage (vdd) = 5v 200 10v 15v 150 100 50 20 40 60 80 propagation delay time (tphl, tplh) (ns)
7-452 cd4071bms, cd4072bms, cd4075bms figure 9. typical output low (sink) current characteristics figure 10. minimum output low (sink) current characteristics figure 11. typical output high (source) current characteristics figure 12. minimum output high (source) current characteristics figure 13. typical transition time as a function of load capacitance figure 14. typical dynamic power dissipationas a function of frequency typical performance characteristics (continued) 10v 5v ambient temperature (t a ) = +25 o c gate-to-source voltage (vgs) = 15v 0 5 10 15 15 10 5 20 25 30 drain-to-source voltage (vds) (v) output low (sink) current (iol) (ma) 10v 5v ambient temperature (t a ) = +25 o c gate-to-source voltage (vgs) = 15v 0 5 10 15 7.5 5.0 2.5 10.0 12.5 15.0 drain-to-source voltage (vds) (v) output low (sink) current (iol) (ma) -10v -15v ambient temperature (t a ) = +25 o c gate-to-source voltage (vgs) = -5v 0 -5 -10 -15 drain-to-source voltage (vds) (v) -20 -25 -30 0 -5 -10 -15 output high (source) current (ioh) (ma) -10v -15v ambient temperature (t a ) = +25 o c 0 -5 -10 -15 drain-to-source voltage (vds) (v) 0 -5 -10 -15 output high (source) current (ioh) (ma) gate-to-source voltage (vgs) = -5v ambient temperature (t a ) = +25 o c load capacitance (cl) (pf) 0 40 60 80 100 20 0 50 100 150 200 supply voltage (vdd) = 5v 10v 15v transition time (tthl, ttlh) (ns) cl = 15pf cl = 50pf ambient temperature (t a ) = +25 o c supply voltage (vdd) = 15v 10v 5v 10v 8 6 4 28 6 4 22 input frequency (fi) (khz) 11010 2 10 3 10 4 8 6 4 28 6 4 8 6 4 2 8 6 4 2 8 6 4 2 8 6 4 2 10 4 10 3 10 2 10 10 5 power dissipation per gate (pd) ( w)
453 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?ations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com cd4071bms, cd4072bms, cd4075bms chip dimensions and pad layouts cd4071bms cd4072bms cd4075bms dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. grid graduations are in mils (10 -3 inch) metallization: thickness: 11k ? ? 14k ?, al. passivation: 10.4k? - 15.6k ? , silane bond pads: 0.004 inches x 0.004 inches min die thickness: 0.0198 inches - 0.0218 inches
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