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1 www.semtech.com sc2451 high efficiency dual synchronous dc/dc controller with current sharing circuitry power management preliminary revision december 5, 2003 description features applications typical application circuit ? bicmos two phase current share or dual indepen- dent voltage mode pwm controller ? out of phase operation to reduce input and output ripple ? controlled sequencing (output1 followed by out- put2) ? 4.5v to 30v input voltage range ? output voltages as low as 0.5v ? programmable operating frequency up to 1.2mhz ? soft start ? hiccup or shutdown over current protection ? high efficiency synchronous switching ? 0% to 100% duty cycle range (250ns minimum off time, dmax 70% at 1.2mhz) ? thermal shut down ? 2a peak current driver ? asynchronous start-up (during soft start) ? sync (oscillator synchronizes to an external clock) ? -40 to 105c operating temperature ? 28 pin tssop package ? distributed power system ? internet/network servers ? point of use low voltage high current applications ? rf power supply ? local microprocessor core power supplies ? large memory arrays sync q2 r8 rsense2 lout_phase1 l1 r22 r12 v2out+ c15 cs1- r9 u1 sc2451 1 24 13 12 8 10 14 6 7 9 28 4 27 5 15 25 26 22 11 21 23 16 20 19 18 17 2 3 cs1+ phase1 cs2- eo2 pwrgd ilim_mode cs2+ ss/en sync osc bdi fb1 vin ishout agnd dh1 bst1 pvcc fb2 pgnd dl1 avcc dl2 phase2 dh2 bst2 cs1- eo1 c13 vin avcc r3 d4 cs2- r17 c8 cs2+ c2 r13 r21 q5 r7 rsense1 cs2+ c17 r14 c4 dual independent output lout_phase2 l2 c12 pwrgd vin r11 r5 q4 q1 v1out+ r10 q3 r6 ss/en v1out- cs1+ d3 r4 avcc cout c5 v2out- r16 d2 c7 c1 c3 vin c18 c14 cs1- r2 cs1+ c11 cout c6 c9 c16 c10 r1 cs2- d1 r15 the sc2451 is a versatile 2 phase, synchronous, voltage mode pwm controller that may be used in two distinct ways from input supply range 4.5v to 30v. first, the sc2451 is ideal for applications where point of use output power ex- ceeds any single output power budget. alternatively, the sc2451 can be used as a dual switcher. the sc2451 features a temperature compensated voltage reference, hiccup or shutdown mode of over current pro- tection, internal level-shifted drive circuitry, programmable operating frequency up to 1.2mhz, soft start and sync functions. sc2451 implements an asynchronous soft start mode, which keeps the lower side mosfet off during soft start, a desired feature when a converter turns on to a preset ex- ternal voltage or pre-bias voltage. with the lower mosfet off, the external bus is not discharged, preventing any dis- turbances in the start-up slope and any latch-up of mod- ern day asic circuits. in a current sharing configuration, the sc2451 can pro- duce a single output voltage from two separate voltage sources while maintaining current sharing between the channels. current sharing is programmable to allow the loading of each input supply as required by the applica- tion. in a dual switcher configuration, two feedback paths are provided for independent control of the separate outputs. the two switchers are 180 out of phase to minimize in- put and output ripple. also a controlled output sequencing (output1 first followed by output2) ensures an orderly start- up.
2 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary absolute maximum ratings r e t e m a r a pl o b m y sm u m i x a ms t i n u d n g p o t e g a t l o v y l p p u sn i v5 3 o t 3 . 0 -v i d b 3 3 o t 3 . 0 -v o t 2 b f , 1 b f , n e / s s , d g r w p , c c v a , c c v p d n g p 7 o t 3 . 0 -v ) c n y s , e d o m _ m i l i , b f , - s c , + s c ( s t u p n i 7 o t 3 . 0 -v d n g a o t d n g p 0 0 3 - / +v m d n g p o t 2 l d , 1 l d v 3 . 0 + c c v p o t 3 . 0 -v d n g p o t 2 e s a h p , 1 e s a h p , 2 t s b , 1 t s b 5 3 + o t 3 . 0 -v 2 e s a h p o t 2 h d , 1 e s a h p o t 1 h d v 3 . 0 + c c v p o t 3 . 0 -v 2 t s b o t 2 e s a h p , 1 t s b o t 1 e s a h p 3 . 0 o t 6 -v s t n e r r u c s r e v i r d t u p t u o k a e p s u o u n i t n o c ) 2 h d , 1 h d , 2 l d , 1 l d ( 0 0 . 2 - / +a e s a c o t n o i t c n u j e c n a t s i s e r l a m r e h tc j6 . 2 1w / c t n e i b m a o t n o i t c n u j e c n a t s i s e r l a m r e h ta j6 . 6 3w / c e g n a r e r u t a r e p m e t t n e i b m aa t5 0 1 o t 0 4 -c e g n a r e r u t a r e p m e t n o i t c n u jt j 0 5 1 + o t 5 5 -c e g n a r e r u t a r e p m e t e g a r o t st g t s 0 5 1 + o t 5 6 -c . c e s 0 1 ) g n i r e d l o s ( e r u t a r e p m e t d a e lt d a e l 0 0 3 +c all voltages with respect to agnd. positive currents are into, and negative currents are out of the specified terminal. pulsed is defined as a less than 10% duty cycle with a maximum duration of 500ns. consult packaging section of data sheet for thermal limitations and considerations of packages. exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of th e parameters specified in the electrical characteristics section is not implied.
3 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary r e t e m a r a ps n o i t i d n o c t s e tn i mp y tx a mt i n u y l p p u s r e w o p n i v 5 . 40 3v t n e r r u c g n i t a r e p od a o l o n1 1a m c c v av 5 . 5 > n i v4 . 566 . 6v c c v pv 5 . 5 > n i v4 . 566 . 6v t u o k c o l e g a t l o v r e d n u d l o h s e r h t t r a t s 2 1 3 . 44 . 48 8 4 . 4v s i s e r e t s y h o l v u 1 . 0v r e i f i l p m a r o r r e e g a t l o v k c a b d e e f 9 4 . 05 . 01 5 . 0v t n e r r u c s a i b t u p n i 0 0 2a n e g a t l o v t e s f f o t u p n i 5v m n i a g p o o l n e p o 0 9b d h t d i w d n a b n i a g y t i n u 3z h m t n e r r u c k n i s t u p t u o 2a m t n e r r u c e c r u o s t u p t u o 2a m e t a r w e l s 1s / v r o t a l l i c s o y c a r u c c a l a i t i n it a s m h o k 1 2 = t r , c 5 2 =0 5 40 0 50 5 5z h k y t i l i b a t s e g a t l o vt a s m h o k 1 2 = t r , c 5 2 =1% n o i t a i r a v l a t o ts m h o k 1 2 = t r , e r u t a r e p m e t , e n i l0 1z h k n o i t a r e p o m u m i x a m y c n e u q e r f 0 0 2 1z h k e l c y c y t u d x a m r o t a l l i c s o 5 9% y e l l a v o t k a e p p m a r 3 . 15 . 17 . 1v e g a t l o v k a e p p m a r 0 . 25 1 . 2v e g a t l o v y e l l a v p m a r 5 4 . 05 . 0v electrical characteristics unless otherwise specified, vin = 12v, rosc = 41.8k ? , fosc = fphase1 = fphase2 = 250khz, 0mv < (cs(+) - cs(-)) < 60mv t a = -40 c to 105 c , t a = tj notes: (1). guaranteed by design.
4 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary note: (1). guaranteed by design. electrical characteristics (cont.) r e t e m a r a ps n o i t i d n o c t s e tn i mp y tx a mt i n u k c o l c / c n y s d l o h s e r h t c n y s k c o l c 0 . 1v e g n a r y c n e u q e r f c n y s f c s o 3 . 1 *z h k t i m i l t n e r r u c e g a t l o v t i m i l t n e r r u c 0 60 70 8v m e d o m n o m m o c e s n e s t n e r r u c e g a t l o v d n g s o t - s c d n a , + s c5v t n e r r u c k c a b d l o fv t u o v 0 =% 0 5i m i l e e n k e g a t l o v k c a b d l o f= ii m i l v t u o v t n e r r u c s a i b t u p n i1 - s c , 1 + s c 2 - s c , 2 + s c 1a n e / s s d l o h s e r h t n w o d t u h s 0 0 6v m t n e r r u c e g r a h c t r a t s t f o s 5a e l b a n e t r a t s t f o s d b tv d o o g r e w o p w o d n i w d o o g r e w o p 0 1 v % t u o e v i r d e t a g t n e r r u c k n i s l df n 7 . 4 = t u o c , v 5 . 3 = d n g p - l d2a t n e r r u c e c r u o s l df n 7 . 4 = t u o c , v 5 = l d - c c v p2a t n e r r u c k n i s h df n 7 . 4 = t u o c , v 5 . 3 = d n g p - h d2a t n e r r u c e c r u o s h df n 7 . 4 = t u o c , v 5 = h d - t s b2a e m i t d a e d 0 5s n e m i t e s i r t u p t u of n 7 . 4 = t u o c , v 3 . 3 = s g v6 1s n e m i t l l a f t u p t u of n 7 . 4 = t u o c , v 3 . 3 = s g v6 1s n p a l r e v o - n o n m u m i n i m ) 1 ( 0 5s n n w o d t u h s l a m r e h t e r u t a r e p m e t n w o d t u h st j 0 6 1c s i s e r e t s y h 0 1c unless otherwise specified, vin = 12v, rosc = 41.8k ? , fosc = fphase1 = fphase2 = 250khz, 0mv < (cs(+) - cs(-)) < 60mv t a = -40 c to 105 c , t a = tj
5 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary pin configuration ordering information r e b m u n t r a pe g a k c a p ) 1 ( t ( e g n a r . p m e t a ) r t s t i 1 5 4 2 c s8 2 - p o s s tc 5 0 1 + o t c 0 4 - (28 pin tssop) note: (1) only available in tape and reel packaging. a reel contains 2500 devices. top view cs1+ cs1- eo1 fb1 ishout ss/en pwrgd osc sync ilim_mode fb2 eo2 cs2- cs2+ agnd avcc bst2 dh2 phase2 dl2 pgnd pvcc dl1 phase1 dh1 bst1 vin bdi
6 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary pin descriptions vin : input supply ranging from 4.5v to 30v. avcc : chip analog circuitry supply voltage should be bypassed with a decoupling capacitor (70 to 100 mohms esr) in parallel to a 1uf ceramic capacitor to agnd. avcc is inter- nally regulated from the external supply connected to vin. if vin is below 6.5v , the supply could be directly connected to the avcc pin. pvcc : supply for the output mosfets gate drive. agnd : analog signal ground. sc2451 sensitive internal circuitry are referenced to agnd. pgnd : power gnd. return of gate drive currents. eo1 : error amplifier 1 output. a compensation network is con- nected from this pin to fb1. in current sharing operation, a resistor is also connected between eo1 and eo2. eo2 : error amplifier 2 output. a compensation network is con- nected from this pin to fb2. in current sharing operation, no compensation network is required and a resistor is con- nected between eo1 and eo2. fb1 : feedback pin used to sense the output voltage via a resis- tive divider. fb2 : feedback pin used to sense the output voltage via a resis- tive divider. by connecting this pin to avcc, the device will be operating in the current sharing mode. cs-1, cs-2 : current limit amplifiers negative inputs for the two chan- nels. cs-1, and cs-2 are connected via a current limit pro- graming resistor to the output side of the inductor current sense resistors. the current limit programing resistor in conjunction with an internal current source (approximately equal to iosc), programs the current limit threshold. once the voltage drop (approximately 70mv) across the current sense resistor is larger than the drop across the programming resistor, cur- rent limit condition occurs, and the shutdown or hiccup current limit protection is activated. cs+1, cs+2 : current limit amplifiers positive inputs for the two chan- nels. cs+1, and cs+2 are connected to inductor side of the inductor current sense resistors. a resistor equal to the current limit threshold resistor (connected to cs- pins) should be also connected in series with the cs+ pins. bdi : base drive for the avcc/pvcc regulator, a 2.7kohms resis- tor is recommended to be connected in series from bdi pin to the base of the external drop out transistor. phase1, phase2 : the return path for the high side gate drive, also used to sense the voltage at the phase node for adaptive gate drive protection. bst1, bst2 : bst signal. supply for high side driver; can be directly con- nected to an external supply or to a bootstrap circuit. dh1, dh2 : dh signal (drive high). gate drive for top mosfets; requires a small series resistor. dl1, dl2 : dl signal (drive low). gate drive for bottom mosfets; re- quires a small series resistor. ss/ena : soft start pin. internal current source connected to exter- nal capacitor will determine the softstart duration. inhibits the chip if pulled down. pwrgd : open collector power good signal. pulled low if output volt- age are outside the power good window. a pull up resistor to an external supply is usually connected to pwrgd. osc : oscillator frequency set pin. the peak voltage at this pin will be approximately equal to the bandgap voltage of 1.225v. an external resistor to agnd will program the os- cillator frequency. the formula below can be used to ap- proximate the oscillator frequency: iosc = bandgap voltage/rosc fosc = 1.225v/(rosc)*(117*10 -12 ) fosc = fphase1 = fphase2
7 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary sync : synchronization input pin. an external clock signal con- nected to this pin will synchronize the internal oscillator to the external frequency. also can be connected to a multi phase clock generator (sc4201) when multiple sc2451 are used in multi phase configuration. ishout : this pin is used in the current sharing mode. a 0.1uf ca- pacitor is connected from this pin to agnd. in an indepen- dent mode of operation this pin should be connected to the agnd. ilim_mode : in the shut down current limit (ilim_mode pin pulled low to agnd), if out1 has a continuous fault , both out1 and out2 will be latched off. if a fault condition occurs only at output2, it will be latched off while output1 continues normal operation. in the hiccup current limit (ilim_mode pin pulled high to avcc), when the current limit has been triggered for a mini- mum of 16 (maximum of 31) clock pulses (at the switching frequency) the output is disabled for the duration of 7 dummy soft start cycles and the output is then restarted. this sequence repeats indefinitely until the over current condition is removed. pin descriptions (cont.)
8 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary block diagram yyww = datecode (example: 9912) xxxxxx = semtech lot # (example: 90101) top mark yyww sc2451its xxxxxx marking information 1v
9 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary application information introduction the sc2451 is a versatile 2 phase synchronous, voltage mode pwm controller with an input supply ranging 4.5v to 30v that may be used in two distinct ways. the sc2451 can be configured as a dual converter or a bi- phase converter capable of driving n-channel mosfets for phase currents beyond 20a in high current applications. the power dissipation is controlled using a novel low volt- age supply technique, allowing high speed and integration with the high drive currents to ensure low mosfet switch- ing loss. the synchronous buck configuration also allows converter sinking current from load without losing output regulation. load current sharing within 10% typical can be achieved between phases by using precise feedback voltage divider resistors (typically 0.1%) to match individual phase output voltage in conjunction with the current share circuitry pro- vided by the sc2451. the internal reference is trimmed to 500mv with 2% ac- curacy, and the outputs voltages can be adjusted by two external resistors. a fixed oscillator frequency (up to 1.2mhz) can be pro- grammed by an external resistor. in bi-phase operation, the dual switching regulators are operated 180 out of phase. the oscillator can also be synchronized to an exter- nal reference clock for noise sensitive applications. other features of the sc2451 include: controlled output sequencing, wide operating voltage range (4.5v to 30v), low output voltages down to 500mv, softstart, hiccup or shut down over current protection, wide duty cycle range (0% to 100%), thermal shutdown, asyn- chronous start-up, and a -40 to 105 c operating tem- perature range. theory of operation supplies three pins (vin, avcc, and pvcc) are used to power up the sc2451. a supply connected to the vin pin is initially used to provide the base drive to the bdi pin to regulate the vcc. this supply should be by passed with a low esr ce- ramic capacitor right at the ic. the avcc supply provides the bias for the internal refer- ence, oscillator, and control circuitry. this supply should be bypassed with a low esr (70 to 100 mohms) tantalum or similar capacitor, and a 1uf ceramic capacitor directly at the avcc to agnd pins of the sc2451. the pvcc supply provides the bias for the low and the high side mosfet gate drive. a low esr capacitor directly at the pvcc to pgnd pins of the sc2451 should be used to by- pass the pvcc supply. if an input supply greater than 6.5v will be used, bdi pro- vides an on board drop out regulator control to an external pnp pass transistor that can be used to generate the avcc and pvcc supplies. the maximum rating for vcc supplies is 7v and for appli- cations where input supply is below 6.5v, it may be con- nected directly to avcc and pvcc, leaving the bdi pin open. start up sequence initially during the power up (vcc<4.4v), the sc2451 is in under voltage lockout condition and the ss/en pin is pulled low by an internal switch. meanwhile, the high side and low side gate drivers dh, and dl, are kept low. once vcc exceeds the uvlo thresh- old, the external soft start capacitor starts to be charged by a 5ua current source. the gate drives are still kept off until the soft start capaci- tor voltage rises above 1v, at which point the low side gate is turned on and the high side gate is kept off for duration of one clock period . at this point the top gate will start switching while keeping the bottom gate off, resulting in an asynchronous start up mode of operation. as the ss/en pin continues to rise, the error amplifier out- put also rises at the same rate and the duty cycle increases. when the ss pin reaches 2v, the low side mosfet will begin to switch and the convertor is fully operational in the syn- chronous mode. once the output voltage has reached regulation and is within 10%, an open collector power good flag is acti- vated, and the error amplifier output will no longer be clamped to the ss/en voltage. the ss/en voltage contin- ues to rise up to avcc and will stay at that voltage level during normal operation. if an over current condition occurs, the ss/en pin will dis- charge to 500mv by an internal switch. during this time, both dh and dl will be turned off. once the ss/en reaches 1v, the low side gate will be turned on and the ss/en pin will again start to be charged by the 5a current source and the same soft start sequence mentioned above will be repeated.
10 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary application information (cont.) bias generation bias generation bias generation bias generation bias generation a 4.5 to 6.5v supply voltage is required to power up the sc2451. this voltage could be provided by an external power supply or derived from vin (vin>6.5v) through an external pnp pass transistor. bdi is the control signal to the base of the pnp pass tran- sistor that will regulate avcc. the voltage at avcc pin is compared to the bandgap, and the bdi output is adjusted to produce 5.4v to 6.6v at the avcc pin. sof sof sof sof sof t star t star t star t star t star t / shut do t / shut do t / shut do t / shut do t / shut do wn wn wn wn wn an external capacitor at the ss/en pin is used to set up the soft start duration. the capacitor value in conjunction with the internal current source, controls the duration of soft start time. below is an explanation of the soft start cycle: if the ss/en pin is pulled down to agnd, the sc2451 is disabled. the soft start pin is charged by a 5ua current source and discharged by an internal switch. when ss/en is released it charges up to 0.5v as the control circuit starts up. the error amp outputs are now held off until the ss_en pin has reached 1.0v (this prevents overshoot in the no load situation). the error amp output will vary between 0.7 and 3.7v, de- pending on the duty cycle selected. (the 3v range repre- sents 0 to 100% duty cycle). the error amp will be off until ss/en reaches 1.0v and will move the output up to its desired voltage by the time ss/en reaches 1.5v. the gate drivers will be in asynchronous mode until the ss/en pin reaches 3.0v. the intention for the asynchro- nous start up is to keep the low side mosfet from being switched on which forces the low side mosfet?s body diode or the parallel schottky diode to conduct. the conduction by the diode prevents any dips in an existing output volt- age that might be present, allowing for a glitch free start up in applications that are sensitive to any bus distur- bances. in dual output mode, phase1 will start first followed by phase2. in single output mode (ishare) both outputs come up together (the two phases are still 180 degrees out of phase). this sequencing change is automatic once the current share mode of operation is selected. in case of a current limit, if phase 1 current limits and goes into hiccup mode both outputs will switch off. the outputs will be held off for the duration of 7 dummy soft start cycles. this period is defined by the ss cap being charged to 2v and sharply discharged to 1v making a 1v sawtooth. the part will try to restart on the next softstart cycle. if the fault has cleared, the outputs will start in sequence again. if the fault still remains, the part will repeat the soft start cycle above indefinitely until the fault has been removed.
11 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary if phase2 current limits, it will go through the same softstart cycle as above but phase1 will be unaffected. in ishare mode, both outputs start together and will both shutdown and restart in the event of a current limit fault. the soft start time is determined by the value of the softstart capacitor (see formula below). ) 10 167 ( 3 ? ? ss ss c t oscillat oscillat oscillat oscillat oscillat or f or f or f or f or f req req req req req uency selection uency selection uency selection uency selection uency selection the internal oscillator sawtooth signal is generated by charging an internal capacitor with a current source. the charge current is set by an external resistor connected from osc to agnd pins. following is the equation to calculate the oscillator fre- quency and some typical rosc values: osc osc r f 9 10 5 . 10 ? rosc = 21kohms. produces; fosc = fphase1 = fphase2 = 500khz s s s s s ync ync ync ync ync in noise sensitive applications where synchronization of the oscillator frequency to a reference frequency is required, the sync pin can accept the external clock. an external control signal running at a higher frequency (fosc*1.1) than the oscillator connected to the sync pin will result in synchronization of the internal oscillator frequency to the positive edge of the external control signal. sync is a posi- tive edge triggered input with a threshold set to 1.5v. p p p p p o o o o o w w w w w er good er good er good er good er good pwrgd pin provides an open collector output which will be pulled low if the output voltage is not within tolerance (vo 10% typical). the pwrgd pin will stay low until softstart cycle has been completed and the output voltage is with in the power good limits. this indicator signal could be used to flag supervisory cir- cuit to a fault condition. a 10kohms pull up resistor to avcc or an external supply is recommended at the pwrgd pin. current limit (hiccup or shut do current limit (hiccup or shut do current limit (hiccup or shut do current limit (hiccup or shut do current limit (hiccup or shut do wn mode) wn mode) wn mode) wn mode) wn mode) hiccup and shutdown modes of over current protection are available to the designer using the sc2451. the output inductor current is sensed via a current sense resistor, or lossless inductive sensing. the voltage across rsense is filtered by placing resistors in series from rsense to the cs+ and cs- pins of the sc2451. a small capacitor is also placed between the cs+ and cs- pins. this signal is then used for over current protection and the current sharing mode of operation. the current limit level is set by the value of the series resis- tor connected to the cs- pin. the following formula can be used to approximate the current limit level: r sense = current sensing resistor v i_limit = current limit threshold (typical 70mv) i out_max = maximum output current limit r osc = oscillator resistor v bg = bandgap voltage (typical 1.225v) max out limit i sense i v r _ _ ? bg osc sense max out cs v r r i r ? ? _ once an over current event has occurred, the pwm cycle will end until the current decays below 2/3 of the selected current limit level (30% hysteresis). it should be noted that the operational limit for the cs- and cs+ inputs is 0.5v below the avcc supply. hiccup current limit hiccup current limit hiccup current limit hiccup current limit hiccup current limit with the hiccup mode selected (ilim_mode pin pulled high), the cycle by cycle current limit will trigger a counter which will cause the output to go into hiccup mode. the phase which goes into current limit first will dictate how the outputs will switch off. if phase1 current limits first, then both channels will be switched off and re-soft started in sequence. if phase 2 current limits first, only phase 2 will switch off and be re-soft started while phase1 is undis- turbed. application information (cont.)
12 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary when the current limit has been triggered for a minimum of 16 (maximum of 31) clock pulses (at the switching fre- quency) the output is disabled for the duration of 7 dummy soft start cycles and the output is then restarted. this se- quence repeats indefinitely until the over current condi- tion is removed. shut do shut do shut do shut do shut do wn current limit wn current limit wn current limit wn current limit wn current limit in the shut down current limit (ilim_mode pin pulled low to agnd), if out1 has a continuous fault , both out1 and out2 will be latched off. if a fault condition occurs only at output2, it will be latched off while output1 continues normal operation. the latched off condition can be reset by either powering down the supply and then bringing it up above the uvlo limit, or by pulling down the ss/en pin and then releasing it to be pulled up high again. f f f f f ault pr ault pr ault pr ault pr ault pr o o o o o t t t t t ection ection ection ection ection in addition to current limit, the sc2451 monitors over tem- perature and vcc supply under-voltage conditions. the over temperature detect will shut the part down if the die tem- perature exceeds 160 c. u u u u u nder v nder v nder v nder v nder v oltage lock out oltage lock out oltage lock out oltage lock out oltage lock out under voltage lock out (uvlo) circuitry senses the vcc through a voltage divider. if this signal falls below 4.4v (typi- cal) with a 100mv hysteresis (typical), the error amplifier and the pwm comparator outputs are pulled low, hence causing the lower mosfet gate to be on while keeping the upper mosfet gate off for both phases. during the ther- mal shutdown, the same fault shutdown sequence is ap- plied as mentioned above. current sharing mode current sharing mode current sharing mode current sharing mode current sharing mode (ishout) in addition to the standard dual output synchronous buck configuration, sc2451 also can be setup for a single out- put dual phase operation (running 180 out of phase) pro- viding the benefits of input and output current ripple can- cellation for the higher power applications. the current share mode is simply set up by placing a current sharing amplifier gain resistor between the eo1 and eo2 pins and an averaging capacitor placed from the ishout pin to agnd. the inductor current of the two phases is sensed via the current sensing resistors. the current difference between the two phases is then averaged via the ishare capacitor. this averaged value is used to produce a current source or sink which has a full range of 80ua. this offset cur- rent will then create an offset voltage in conjunction with the resistor connected between the eo1 and eo2. the off- application information (cont.) set produced will in turn cause the duty cycle of the phases to be adjusted in order to achieve current sharing between them. the maximum offset possible is 3v, which is the oscillator ramp amplitude (0 to 100% duty cycle). the resistor connected between the eo1 and eo2 value dictates the gain and hence the accuracy of the ishare loop. the following example can be used for choosing the resistor value: vin=12v vo=5v d = 41.7% fosc = fphase1 = fphase2 = 500khz io = 20a, io1 = 9a, io2 = 11a rsense = 5mohms oscillator ramp peak = 3v (100% duty cycle) approximate error voltage is about: d*ramp peak = .417*3 = 1.25v. the current error between the two phases is 2a, which is about 10mv (10%). the 10% offset voltage needed to balance the current sharing at the output of the eo1 and eo2 (voltage across the resistor) will be about 125mv. keeping the center point of the current source around 40ua, the resistor value that can be used is: 125mv/40ua = 3.125 kohms.
13 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary application information (cont.) the optimum capacitor value will depend on the switching frequency, since the output ripple current is being averaged. gat gat gat gat gat e driv e driv e driv e driv e driv e/contr e/contr e/contr e/contr e/contr ol ol ol ol ol the sc2451 also provides integrated high current gate drives for fast switching of large mosfets. the high side and low side mosfet gates could be switched with a peak gate current of 2a. the higher gate current will reduce switching losses of the larger mosfets. the low side gate drives are supplied from the pvcc. the high side gate drives could be provided with either the clas- sical boot strapping technique or an external supply volt- age up to 12v connected to the bst pin. cross conduction prevention circuitry ensures a non over- lapping (50ns typical) gate drive between the top and bot- tom mosfets. this prevents shoot through losses which provides higher efficiency. typical total minimum off time for the sc2451 is about 250ns which will cause the maxi- mum duty cycle at higher frequencies to be limited to lower than 100% (70% at 1.2mhz).
14 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary where, cout lout c r r c r o z z = + = = 1 , ) ( 1 , 1 2 3 1 2 1 2 1 3 1 3 1 2 2 2 3 1 3 1 1 1 , 1 , ) ( 1 c c c c r c r c c r p p i + = = + = the design guidelines are as following: 1. set the loop gain crossover frequency w c for given switch- ing frequency. 2. place an integrator in the origin to increase dc and low frequency gains. 3. select w z1 and w z2 such that they are placed near w o to dampen peaking; the loop gain has ?20 db rate to go across the 0 db line for obtaining a wide bandwidth. 4. cancel w esr with compensation pole w p1 (w p1 = w esr ). 5. place a high frequency compensation pole w p2 at half the switching frequency to get the maximum attenuation of the switching ripple and the high frequency noise with the adequate phase lag at w c . 0db gd t z1 z2 p1 p2 c esr o loop gain t(s) figure 2. simplified asymptotic diagram of buck power stage and its compensated loop gain. err err err err err or amplifier design or amplifier design or amplifier design or amplifier design or amplifier design the sc2451 is a voltage mode buck controller that utilizes an externally compensated high bandwidth error amplifier to regulate output voltage. the power stage of the synchro- nous rectified buck converter control-to-output transfer function is as shown below: ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + + = lc s l r l s c c sesr s v in v s vd g 2 1 1 ) ( where, v in ? input voltage r l ? load resistance l ? output inductance c ? output capacitance esr c ? output capacitor esr v s ? peak to peak ramp voltage the classical type iii compensation network can be built around the error amplifier as shown below: r3 c3 r2 r1 c1 vref c2 - + figure 1. voltage mode buck converter compensation net- work the transfer function of the compensation network is as follows: ) 1 )( 1 ( ) 1 )( 1 ( ) ( 2 1 2 1 p p z z i comp s s s s s s g + + + + ? = application information (cont.)
15 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary pcb layout guidelines careful attention to layout is necessary for successful imple- mentation of the sc2451 pwm controller. high switching currents are present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1). the high power section of the circuit should be laid out first. a ground plane should be used. the number and po- sition of ground plane interruptions should not unneces- sarily compromise ground plane integrity. isolated or semi- isolated areas of the ground plane may be deliberately in- troduced to constrain ground currents to particular areas; for example, the input capacitor and bottom fet ground. 2). the loop formed by the input capacitor(s) (cin), the top fet (m1), and the bottom fet (m2) must be kept as small as possible. this loop contains all the high current, fast transition switching. connections should be as wide and as short as possible to minimize loop inductance. minimiz- ing this loop area will a) reduce emi, b) lower ground injec- tion currents, resulting in electrically ?cleaner? grounds for the rest of the system and c) minimize source ringing, re- sulting in more reliable gate switching signals. 3). the connection between the junction of m1, m2 and the output inductor should be a wide trace or copper re- gion. it should be as short as practical. since this connec- tion has fast voltage transitions, keeping this connection short will minimize emi. also keep the phase connection to the ic short. top fet gate charge currents flow in this trace. 4) the output capacitor(s) (cout) should be located as close to the load as possible. fast transient load currents are supplied by cout only, and therefore, connections between cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) the sc2451 is best placed over a quiet ground plane area. avoid pulse currents in the cin, m1, m2 loop flowing in this area. gnd should be returned to the ground plane close to the package and close to the ground side of (one of) the output capacitor(s). if this is not possible, the gnd pin may be connected to the ground path between the output capacitor(s) and the cin, m1, m2 loop. under no circumstances should gnd be returned to a ground inside the cin, m1, m2 loop. 6)if the bst for the sc2451 is supplied from the 12v sup- ply, the bst pin should be decoupled directly to gnd by a 0.1uf ceramic capacitor. trace lengths should be as short as possible. if a 12v supply is not available, a classical boot strap method could be implemented to achieve the upper mosfets gate drive. 7) for current share mode of operation, the two convert- ers should be laid out as symmetrical as possible for the best current sharing accuracy. 8) allow adequate heat sinking area for the power compo- nents. if multiple layers will be used, provide sufficent vias for heat ransfer application information (cont.) voltage and current waveforms of buck power stage . vout vin + + ids (top fet) ids ( bottom fet ) i (input capacitor) vphase i (inductor) vout i (output capacitor)
16 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary component selection: switching section output capacitors - selection begins with the most critical component. because of fast transient load current requirements in modern microprocessor core supplies, the output capacitors must supply all transient load current requirements until the current in the output inductor ramps up to the new level. output capacitor esr is therefore one of the most important criteria. the maximum esr can be simply calculated from: step current transient excursion voltage transient maximum where = = t t t t esr i v i v r for example, to meet a 100mv transient limit with a 10a load step, the output capacitor esr must be less than 10m ? . to meet this kind of esr level, there are three avail- able capacitor technologies. y g o l o n h c e t h c a e r o t i c a p a c y t q . d q r l a t o t c ) f u ( r s e m ( ? ) c ) f u ( r s e m ( ? ) m u l a t n a t r s e w o l0 3 30 66 0 0 0 20 1 n o c - s o0 3 35 23 0 9 93 . 8 m u n i m u l a r s e w o l0 0 5 14 45 0 0 5 78 . 8 the choice of which to use is simply a cost/performance issue, with low esr aluminum being the cheapest, but tak- ing up the most space. inductor - having decided on a suitable type and value of output capacitor, the maximum allowable value of in- ductor can be calculated. too large an inductor will pro- duce a slow current ramp rate and will cause the output capacitor to supply more of the transient load current for longer - leading to an output voltage sag below the esr excursion calculated above. the maximum inductor value may be calculated from: () o in t esr v v i c r l ? the calculated maximum inductor value assumes 100% duty cycle, so some allowance must be made. choosing an inductor value of 50 to 75% of the calculated maximum will guarantee that the inductor current will ramp fast enough to reduce the voltage dropped across the esr at a faster rate than the capacitor sags, hence ensuring a good recovery from transient with no additional excursions. we must also be concerned with ripple current in the output inductor and a general rule of thumb has been to allow 10% of maximum output current as ripple current. note that most of the output voltage ripple is produced by the inductor ripple current flowing in the output capacitor esr. ripple current can be calculated from: osc in l f l 4 v i ripple ? ? = ripple current allowance will define the minimum permit- ted inductor value. power fets - the fets are chosen based on several cri- teria with probably the most important being power dissi- pation and power handling capability. top fet - the power dissipation in the top fet is a combi- nation of conduction losses, switching losses and bottom fet body diode recovery losses. a) conduction losses are simply calculated as: in o on ds o cond v v d d r i p ? ? = cycle duty = where ) ( 2 b) switching losses can be estimated by assuming a switch- ing time, if we assume 100ns then: 3 in o sw 10 v i p ? ? ? = or more generally, 4 ) ( osc f t t v i p f r in o sw ? + ? ? = c) body diode recovery losses are more difficult to esti- mate, but to a first approximation, it is reasonable to as- application information (cont.)
17 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary sume that the stored charge on the bottom fet body di- ode will be moved through the top fet as it starts to turn on. the resulting power dissipation in the top fet will be: osc in rr rr f v q p ? ? = to a first order approximation, it is convenient to only con- sider conduction losses to determine fet suitability. for a 5v in, 2.8v out at 14.2a requirement, typical fet losses would be: e p y t t e fr ) n o ( s d m ( ? )) w ( d pe g a k c a p s 2 0 4 3 l r i5 19 6 . 1d 2 k a p 3 0 2 2 l r i5 . 0 19 1 . 1d 2 k a p 0 1 4 4 i s0 26 2 . 28 - o s using 1.5x room temp r ds(on) to allow for temperature rise. bottom fet - bottom fet losses are almost entirely due to conduction. the body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the fet turns on and off, there is very little voltage across it resulting in low switching losses. conduc- tion losses for the fet can be determined by: ) 1 ( ) ( 2 d r i p on ds o cond ? ? ? = for the example above: e p y t t e fr ) n o ( s d m ( ? )p d ) w (e g a k c a p s 2 0 4 3 l r i5 13 3 . 1d 2 k a p 3 0 2 2 l r i5 . 0 13 9 . 0d 2 k a p 0 1 4 4 i s0 27 7 . 18 - o s each of the package types has a characteristic thermal impedance, for the to-220 package, thermal impedance is mostly determined by the heatsink used. for the sur- face mount packages on double sided fr4, 2 oz printed circuit board material, thermal impedances of 40 o c/w for the d 2 pak and 80 o c/w for the so-8 are readily achievable. the corresponding temperature rise is detailed below: ( e s i r e r u t a r e p m e t 0 ) c e p y t t e ft e f p o tt e f m o t t o b s 2 0 4 3 l r i6 . 7 62 . 3 5 3 0 2 2 l r i6 . 7 42 . 7 3 0 1 4 4 i s8 . 0 8 16 . 1 4 1 it is apparent that single so-8 si4410 are not adequate for this application, by using parallel pairs in each position, power dissipation will be approximately halved and tem- perature rise reduced by a factor of 4. input capacitors - since the rms ripple current in the input capacitors may be as high as 50% of the output cur- rent, suitable capacitors must be chosen accordingly. also, during fast load transients, there may be restrictions on input di/dt. these restrictions require useable energy stor- age within the converter circuitry, either as extra output capacitance or, more usually, additional input capacitors. choosing low esr input capacitors will help maximize ripple rating for a given size. application information (cont.)
18 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary applications information (cont.) single phase two phase three phase four phase i in i in i in i in note: during the gray areas, the input capacitor is being charged, and as the top mosfet is turned on the capacitor has to support the large current required by the load. as the number of phases are incresed, less current is required by the input capacitor, hence decreasing the input capaci tor size, and cost. top mosfet current capacitor discharging capacitor charging f f f f f ollo ollo ollo ollo ollo wing pr wing pr wing pr wing pr wing pr ocedure will de ocedure will de ocedure will de ocedure will de ocedure will de t t t t t ermine the in ermine the in ermine the in ermine the in ermine the in put capacit put capacit put capacit put capacit put capacit or rms current: or rms current: or rms current: or rms current: or rms current: 1- 1- 1- 1- 1- calculat calculat calculat calculat calculat e duty cy e duty cy e duty cy e duty cy e duty cy cle ratio = v cle ratio = v cle ratio = v cle ratio = v cle ratio = v out/vin. out/vin. out/vin. out/vin. out/vin. 2- 2- 2- 2- 2- use the calculat use the calculat use the calculat use the calculat use the calculat ed duty cy ed duty cy ed duty cy ed duty cy ed duty cy cle and the number of phases in the con cle and the number of phases in the con cle and the number of phases in the con cle and the number of phases in the con cle and the number of phases in the con v v v v v er er er er er t t t t t er t er t er t er t er t o f o f o f o f o f ind the multiplier f ind the multiplier f ind the multiplier f ind the multiplier f ind the multiplier f act act act act act or or or or or fr fr fr fr fr om the cur om the cur om the cur om the cur om the cur v v v v v e abo e abo e abo e abo e abo v v v v v e. e. e. e. e. 3- 3- 3- 3- 3- multiply the full load current b multiply the full load current b multiply the full load current b multiply the full load current b multiply the full load current b y the multiplier f y the multiplier f y the multiplier f y the multiplier f y the multiplier f act act act act act or; this will be the rms current that the in or; this will be the rms current that the in or; this will be the rms current that the in or; this will be the rms current that the in or; this will be the rms current that the in put put put put put capacit capacit capacit capacit capacit or or or or or s need t s need t s need t s need t s need t o suppor o suppor o suppor o suppor o suppor t. t. t. t. t. 0 10 20 30 40 50 60 70 80 90 100 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 single p hase dual p hase th ree p h as e four p hase vout/vin (%) multiplier factor
19 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary typical characteristics
20 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary gain & phase margin typical step load sc2451 (independent mode) vin = 12, vout = 5v, iout = 5a fosc =500khz -60 -40 -20 0 20 40 60 10 100 1000 10000 100000 freq (hz) gain (db) -180 -150 -120 -90 -60 -30 0 30 60 90 120 150 180 phase (deg) gain phase (deg) gain phase v in =12v , v out=5v , iout=10a dual output mode ishar e mode
21 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary evaluation board schematic q1 pzt3906 e b c r24 2.7k 100pf c33 8.2nf c32 r22 31.6k r21 2.7k r28 500 avcc 0.1uf c13 avcc sync fesr_zero = 8.84khz j3 pwrgood 1 100u,6.3v x6 c21 d3 cmosh-3 a c note: ss/en r7 5mohms 2 1 1.2nf c35 c24 total capacitance = 600uf r3 5.1 c17 j1 ss/en 1 c22 l1 1.3uh m7 si4842dy 4 5 3 2 1 6 7 8 sync connector j2 must be grounded if not used to synchronize to an external clock. r9 5 cs2+ jp1 jumper on (ishare mode) 1 2 cs2- jp3 jumper on (shutdown ocp) 1 2 note: d4 cmsh3-40 5.1nf c29 r2 100k c23 r19 24.3k fb2 100u,6.3v x 6 c15 tp4 1 2 100pf c30 0.1uf c14 v1out- 1uf c1 c26 d2 1n5819hw r10 5mohms 2 1 c9 10uf c19 r14 2.2k flc = 5.7khz r5 2.2 c20 1.2nf c34 m5 si4842dy 4 5 3 2 1 6 7 8 flc = 5.7khz c8 47uf, 16v r18 3.16k r16 3.16k ilim_mode cs1+ r8 5 r23 2.7k total esr = 30mohms m1 si4842dy 4 5 3 2 1 6 7 8 tp1 1 2 agnd 5.1nf c28 c6 47uf, 16v l2 1.3uh r13 41k vin tp3 1 2 m2 si4842dy 4 5 3 2 1 6 7 8 con1 1 2 +input -input c7 47uf, 16v fesr_zero = 8.84khz r17 2.7k r1 1k c36 placed for ishare mode r11 2.2 tp2 1 2 c18 v2out+ v1out+ m6 si4842dy 4 5 3 2 1 6 7 8 r6 2.2 pwrgd con3 1 2 +ou t -ou t total capacitance = 600uf r4 2.7k m8 si4842dy 4 5 3 2 1 6 7 8 c16 avcc con2 1 2 +output -output 1uf c11 r12 2.2 m4 si4842dy 4 5 3 2 1 6 7 8 s1 push button switch note: r20 31.6k c5 47uf, 16v 1uf c12 cs1+ r27 4.99k 0.47uf c27 1uf c10 sync 8.2nf c36 r15 24.3k c36 shorted for independant mode fb1 jp2 jumper on (hiccup ocp) 1 2 8.2nf c31 r25 5.6k ilim_mode c2 47uf, 16v c3 33uf,10v, poscap r27 placed for ishare mode cs1- cs2- m3 si4842dy 4 5 3 2 1 6 7 8 cs2+ v2out- cs1- pwrgd ss/en d5 cmosh-3 d6 cmsh3-40 total esr = 30mohms r26 5.6k u1 sc2451 1 24 13 12 8 10 14 6 7 9 28 4 27 5 15 25 26 22 11 21 23 16 20 19 18 17 2 3 cs1+ phase1 cs2- eo2 pwrgd ilim_mode cs2+ ss/en sync osc bdi fb1 vin ishout agnd dh1 bst1 pvcc fb2 pgnd dl1 avcc dl2 phase2 dh2 bst2 cs1- eo1 j2 extclk 1 2 3 4 5 c25 fb2 agnd vin vin c4 10uf d1 1n5819hw a c r18, r19, r22, r26, c35, c29,c33 not placed for ishare mode vin
22 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary evaluation board bill of materials sc2451 evaluation board 12vin 3.3vout sc2451_12vin_3.3vout revision: 1a bill of materials november 5,2003 16:22:25 1 3 con1,con2,con3 dual_banana dual_bananasocket 2 4 c1,c10,c11,c12 1uf sm/c_0805 3 5 c2,c5,c6,c7,c8 47uf, 16v tdk (c5750x5r1c476mt) sm/c_2220 4 1 c3 33uf,10v, poscap 10tpb33m (sanyo) sm/c_b2 5 2 c4,c9 10uf sm/c_1206 6 2 c14,c13 0.1uf sm/c_0603 c15,c16,c17,c18,c19,c20, c21,c22,c23,c24,c25,c26 8 1 c27 0.47uf sm/c_0805 9 2 c28,c29 5.1nf sm/c_0603 10 2 c33,c30 100pf sm/c_0603 11 3 c31,c32,c36 8.2nf sm/c_0603 12 2 c35,c34 1.2nf sm/c_0603 13 2 d1,d2 1n5819hw 1n5819hw(diodes inc.) sod123 14 2 d5,d3 cmosh-3 cmosh-3 (central semiconductor) sod523 15 2 d4,d6 cmsh3-40 cmsh3-40(central semiconductor) sm/d_smc 16 1 jp1 jumper on (ishare mode) via\2p 17 1 jp2 jumper on (hiccup ocp) via\2p 18 1 jp3 jumper on (shutdown ocp) via\2p 19 1 j1 ss/en tp 20 1 j2 extclk rf/pcb/bnc/f 21 1 j3 pwrgood tp 22 2 l1,l2 1.3uh pulse (pg0077.142) pcc-s1 23 8 m1,m2,m3,m4,m5,m6,m7,m8 si4842dy vishay so-8 24 1 q1 pzt3906 sm/sot223_bcec 25 1 r1 1k sm/r_0603 26 1 r2 100k sm/r_0603 27 1 r3 5.1 sm/r_0603 28 5 r4,r17,r21,r23,r24 2.7k sm/r_0603 29 4 r5,r6,r11,r12 2.2 sm/r_0603 30 2 r7,r10 5mohms sm/r_2512 31 2 r9,r8 5 sm/r_0603 32 1 r13 41k sm/r_0603 33 1 r14 2.2k sm/r_0603 34 2 r15,r19 24.3k sm/r_0603 35 2 r18,r16 3.16k sm/r_0603 36 2 r20,r22 31.6k sm/r_0603 37 2 r26,r25 5.6k sm/r_0603 38 1 r27 4.99k sm/r_0603 39 1 r28 500 sm/r_0603 40 4 tp1,tp2,tp3,tp4 probe_tp probe_tp 41 1 u1 sc2451 semtech tssop28 manufacturer # foot print item quantity reference part sm/c_1210_grm 7 12 100u,6.3v 12106d107mat(avx)
23 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary evaluation board gerber plots board layout assembly top board layout assembly bottom board layout top board layout bottom
24 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary board layout inner1 board layout inner2 evaluation board gerber plots (cont.)
25 ? 2003 semtech corp. www.semtech.com sc2451 power management preliminary semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805)498-2111 fax (805)498-3804 contact information land pattern - tssop-28 outline drawing - tssop-28

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