description 2.5ghz min. f max 2.3v to 5.7v power supply single bit register memory synchronizes 1 bit of data to a clock optimized to work with superlite family fully differential accepts cml, pecl, lvpecl input logic levels source terminated cml outputs for fast edge rates available in a tiny 10-pin msop the SY55852U is a flip-flop used to synchronize data to a clock. its differential output will reproduce and remember the value on its input at the rising edge of the clock. in addition, an asynchronous, level sensitive reset is provided. for a synchonous reset, the sy55851u anygate can be used. SY55852U inputs can be terminated with a single resistor between the true and complement pins of a given input. the SY55852U is a member of micrel's superlite family of high-speed cml logic. this family features very small packaging and 2.3v to 5.7v operation. features d flip-flop superlite SY55852U applications high-speed logic oc-48 communication systems pin configuration functional block diagram 1 rev.: a amendment: /0 issue date: january 2001 pin names pin function d, /d cml/pecl/lvpecl data input clk, /clk cml/pecl/lvpecl clock input r, /r cml/pecl/lvpecl reset input q, /q cml data output gnd ground v cc v cc d /d clk /clk gnd vcc /r r q /q 76 45 1 10 98 23 top view msop superlite is a trademark of micrel, inc. dq r clock reset data o u t
2 superlite SY55852U micrel pin descriptions d, /d cml/pecl/lvpecl input (differential) this is the single bit of data that gets clocked in and remembered. clk, /clk cml/pecl/lvpecl input (differential) the rising edge of this signal is the clock signal that determines when the boolean value at the data input gets stored. r, /r cml/pecl/lvpecl input (differential) this is an asynchronous active high level reset, that forces the flip-flop into a known state, namely zero. q, /q cml output (differential) this is the output of the flip-flop. functional description v cc nc x /x figure 1. hard wiring a logic 1 (1) nc v cc > 3.0v nc x /x nc v cc 3.0v x /x v cc figure 2. hard wiring a logic 0 (1) establishing static logic inputs the true pin of an input pair is internally biased to ground through a 75k ? resistor. the complement pin of an input pair is internally biased halfway between v cc and ground by a voltage divider consisting of two 75k ? resistors. to keep an input at static logic zero at v cc > 3.0v, leave both inputs unconnected. for v cc 3.0v, connect the complement inputs to v cc and leave the true inputs unconnected. to make an input static logic one, connect the true input to v cc , leave the complement input unconnected. these are the only safe ways to cause inputs to be at a static value. in particular, no input pin should be directly connected to ground. all nc (no connect) pins should be unconnected. note: 1. x is either d, clk, r input. /x is either /d, /clk, /r input. d clk r q /q xx1 0 1 x00q n-1 /q n-1 x10q n-1 /q n-1 0 00 1 1 01 0 truth table
3 superlite SY55852U micrel cml termination 100 ? 100 ? 100 ? 100 ? SY55852U v cc v cc 100 ? 50 ? 50 ? 8ma figure 3a. differentially terminated (50 ? load cml output) all inputs accept the output from any other member of this family. all outputs are source terminated 100 ? cml differential drivers as shown in figures 3 and 4. SY55852U expects the inputs to be terminated, and that good high speed design practices be adhered to. SY55852U inputs are designed to accept a termination resistor between the true and complement inputs of a differential pair. 0402 form factor chip resistors will fit with some trace fanout. 100 ? 100 ? 100 ? 50 ? SY55852U v cc 50 ? 8ma 50 ? 100 ? 50 ? figure 3b. individually terminated (50 ? load cml output) 100 ? 100 ? 200 ? SY55852U v cc 8ma 100 ? 100 ? figure 4. 100 ? load cml output symbol rating value unit v cc power supply voltage 0.5 to +6.0 v v i input voltage 0.5 to v cc +0.5 v v o cml output voltage v cc 1.0 to v cc +0.5 v t a operating temperature range 40 to +85 c t store storage temperature range 65 to +150 c absolute maximum ratings (1) note: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional oper ation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum ratlng co nditions for extended periods may affect device reliability.
4 superlite SY55852U micrel t a = 40 ct a = 0 ct a = +25 ct a = +85 c symbol parameter min. max. min. max. min. max. min. max. unit v cc power supply voltage 2.3 5.7 2.3 5.7 2.3 5.7 2.3 5.7 v i cc power supply current 36 36 36 36 ma dc electrical characteristics v cc = 2.3v to 5.7v; gnd = 0v symbol parameter min. typ. max. unit condition (1) f max max. operating frequency 2.5 ghz t plh propagation delay, clk to q 400 ps t phl r to q 500 t s set-up time 40 ps t h hold time 40 ps t rr reset recovery 400 ps t pw minimum pulse width clk to q v cc < 3v 160 ps v cc 3v 140 r to q 250 t r cml output rise/fall times 35 150 ps t f (20% to 80%) ac electrical characteristics v cc = 2.3v to 5.7v; gnd = 0v; t a = 40 c to +85 c note: 1. tested using environment of figure 3b, 50 ? load cml output. symbol parameter min. typ. max. unit condition v id differential input voltage 100 mv v ih input high voltage (5) 1.6 v cc v v il input low voltage (5) 1.5 v cc 0.1 v v oh output high voltage v cc 0.020 v cc 0.010 v cc v no load v ol output low voltage v cc 0.97 v cc 0.825 v cc 0.660 v no load v os output voltage swing (2) 0.660 0.800 0.950 v no load 0.400 100 ? environment (4) 0.200 50 ? environment (3) r drive output source impedance 80 100 120 ? cml dc electrical characteristics v cc = 2.3v to 5.7v; gnd = 0v; t a = 40 c to +85 c (1) notes: 1. equilibrium temperature. 2. actual voltage levels and differential swing will depend on customer termination scheme. typically, a 400mv swing is availabl e in the 100 ? environment and a 200mv swing in the 50 ? environment. refer to the cml termination diagram for more details. 3. see figure 3a and 3b. 4. see figure 4. 5. inputs must be biased to logic low or high when v cc is less than 3.0v.
5 superlite SY55852U micrel product ordering code ordering package operating code type range SY55852Ukc k10-1 commercial timing diagrams clk data reset q 50% t h 50% t s t rr t plh 50% 50% t phl
6 superlite SY55852U micrel 10 lead msop (k10-1) rev. 00 micrel-synergy 3250 scott boulevard santa clara ca 95054 usa tel + 1 (408) 980-9191 fax + 1 (408) 914-7878 web http://www.synergysemi.com http://www.micrel.com this information is believed to be accurate and reliable, however no responsibility is assumed by micrel for its use nor for an y infringement of patents or other rights of third parties resulting from its use. no license is granted by implication or otherwise under any patent or pat ent right of micrel inc. ? 2001 micrel incorporated
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