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? data device corporation 105 wilbur place bohemia, new york 11716 631-567-5600 fax: 631-567-7358 www.ddc-web.com for more information contact: technical support: 1-800-ddc-5757 ext. 7771 features ? small size (2.25? x 2.1? x 0.39?) 200 v and 500 v capability 30 a current capability high-efficiency mosfet or igbt drive stage direct drive from pwm drives brushless dc or brush motors four quadrant operation 0.85 c/w ? j-c max military processing available description the pwr-82340 and pwr-82342 are 30 a h-bridge motor drive hybrids. the pwr-82340 has a 200 v rating and uses mosfets in the output stage while the pwr-82342 has a 500 v rating and an igbt output stage. both types have individual fast recovery diodes internally connected across the output drive transistors to clamp inductive flyback. this new series of smart power motor drives has cmos schmitt trigger inputs for high noise immunity. high- and low-side input logic signals are xor'd in each phase to prevent simulta- neous turn-on of in-line transistors, thus eliminating a shoot-thru condition. the internal logic controls the high- and low-side gate drives for each phase and can operate from +5 to +15 v logic levels. the internal power supply pro- vides a constant voltage source to the floating high side gate drives. this pro- vides constant output performance for switching frequencies from dc to 50 khz. applications packaged in small cases, these hybrids are an excellent choice for high per- formance, high reliability motor drives for military and aerospace servo-amps and speed controls. among the many applications are robotics; electro- mechanical valve assemblies; actuator systems for flight control surfaces on military and commercial aircraft; antenna and radar positioning; fan and blow- er motors for environmental conditioning; thrust and vector position control of mini subs, drones, and rpv's; compressor motors for cryogenic coolers; and high-power inverters. the pwr-82340/342 hybrids are ideal for harsh military environments where shock, vibration, and temperature extremes are evident, such as missile applications where fin actuator systems control missile direc- tion. the pwr-82340 and pwr-82342 operate over the -55c to +125c temperature range and are available with military processing. pwr-82340 and pwr-82342 smart power h-bridge motor drives make sure the next card you purchase has... ? 1991, 1999 data device corporation all trademarks are the property of their respective owners.
2 data device corporation www.ddc-web.com pwr-82340/pwr-82342 h-06/05-0 figure 1. pwr-82340/342 block diagram 1 2 3 digital control and protection circuitry 8 9 11 12 14 13 7 17 16 18 15 4 5 6
parameter symbol pwr-82340 value pwr-82342 value units supply voltage v cc 200 500 v bias voltage v b 50 50 v logic power-in voltage v lpi 18 18 v input logic voltage v u v l v sd v lpi + 0.5 v lpi + 0.5 v output current continuous pulsed i o l op 30 50 30 50 a a operating frequency f o 50 25 khz case operating temperature t c -55 to +125 -55 to +125 c case storage temperature t cs -55 to +150 -55 to +150 c table 1. pwr-82340 and pwr-82342 absolute maximum ratings (tc = +25c unless otherwise specified) table 2. pwr-82340 and pwr-82342 specifications tc = +25c unless otherwise specified) pwr-82340 pwr-82342 parameters symbol test condi tions min typ max min typ max unit output output current continuous (see figures 19 and 15) supply voltage output on resistance (each fet)(see figure 14a) output voltage drop (each igbt)(see figures 14b) instant forward voltage (flyback diode)(see figure 13) reverse recovery time (flyback diode) reverse leakage current at t c = +25c reverse leakage current at t c = +125c i o v cc r on v ce ( sat ) v f t rr i r i r see note 1 i o = 30 a i o = 30 a i p = 30 a (see note 2) i f = 1 a, i r = 1 a see note 3 see note 3 140 30 200 0.1 1.15 50 10 1 270 30 500 3.8 1.70 50 10 1 a v ohm v v nsec a ma bias supply input bias voltage (t c = -55 to +125c) quiescent bias current (see note 4)(see figure 16) bias current (t c = -55 to +125c) (see figures 17 and 18) inrush current (t c = -55 to +125c) logic power input current v b i bq i b i ir i lpi v = 28 v v b = 28 v(see note 5) v b = 28 v see note 6 14 30 27 50 40 1.4 2 15 24 27 50 35 1.4 2 v ma ma a ma input signals (see figure 7) positive trigger threshold voltage negative trigger threshold voltage positive trigger threshold voltage negative trigger threshold voltage v p v n v p v n pin connections pin 11 and 12 connected pin 11 and 12 connected see note 6 see note 6 6.8 4.0 2.2 0.9 10 7 3 2 6.8 4.0 2.2 0.9 10 7 3 2 v v v v switching characteristics (see figure 2) upper drive: turn-on propagation delay turn-off propagation delay shut down propagation delay turn-on rise time turn-off fall time lower drive: turn-on propagation delay turn-off propagation delay shut down propagation delay (see figure 9) turn-on rise time turn-off fall time t d (on) t d (off) t sd t r t f t d (on) t d (off) t sd t r t f test 1 conditions pin 11 and 12 connected +15 v logic i o = 30 a peak pwr-82340 v cc = 140 v pwr-82342 v cc = 270 v 840 1020 800 125 125 850 1000 800 125 125 810 860 810 100 150 800 870 770 100 150 nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec 3 data device corporation www.ddc-web.com model number rev code
4 data device corporation www.ddc-web.com pwr-82340/pwr-82342 h-06/05-0 table 2. pwr-82340 and pwr-82342 specifications (continued) tc = +25c unless otherwise specified) pwr-82340 pwr-82342 parameters symbol test condi tions min typ max min typ max unit switching characteristics (see figure 2) upper drive: turn-on propagation delay turn-off propagation delay shut down propagation delay turn-on rise time turn-off fall time t d (on) t d (off) t sd t r t f test 2 conditions see note 6 +5 v logic i o = 30 a peak pwr-82340 v cc = 140 v pwr-82342 v cc = 270 v 1090 1315 1100 125 125 1050 1150 850 100 150 nsec nsec nsec nsec nsec notes: 1. for hi-rel applications, derating per mil-s-19500 should be observed. (derate v cc to 70%.) 2. pulse width 300 s, duty cycle 2%. 3. for pwr-82340 v cc = 140 v, v u , v l = logic '0' and for pwr-82342 v cc = 350 v, v u , v l = logic '0.' 4. v u , v l = logic '0' on pins 13 to 17. 5. for pwr-82340 f o = 30 khz and for pwr-82342 f o = 10 khz. 6. pin 12 connected to external +5 v supply. 7. solder 1/8" from case for 5 seconds maximum. switching characteristics lowerdrive: turn-on propagation delay turn-off propagation delay shut-down propagation delay (see figure 9) turn-on rise time turn-off fall time t d(on) t d(off) t sd t r t f t est 2 conditions see note 6 +5v logic i o = 30 a peak pwr-82340 v cc =140 v pwr-82342 v cc = 270 v 1125 1290 1100 125 125 1050 1150 850 100 150 nsec nsec nsec nsec nsec dead time t dt 400 500 nsec minimum pulse width t pw 150 175 nsec thermal maximum thermal resistance maximum lead soldering temp. junction temperature range case operating temperature case storage temperature j-c t s t j t co t cs each transistor see note 7 -55 -55 -55 0.85 250 150 125 150 -55 -55 -55 0.85 250 150 125 150 c/ w c c c weight 3.88 (110) 3.88 (110) oz (g) introduction the pwr-82340 and pwr-82342 are 30 a motor drive hybrids rated at 200 v and 500 v respectively. the pwr-82340 uses a mosfet output stage and the pwr-82342 has an igbt output stage for high speed, high current, and high efficiency operation. the pwr-82342 also offers high voltage performance of an igbt for use in 270 v systems. these motor drives are ideal for use in high performance motion control systems, servo ampli- fiers, and motor speed control designs. furthermore, multiaxis systems requiring multiple drive stages can benefit from the small size of these power drives. the pwr-82340/342 can be driven directly from a pwm, dsp, or a custom asic that supplies digital signals to control the upper and lower transistors of each phase. these highly inte- grated drive stages have schmitt trigger digital inputs that con- trol the high and low side of each phase. digital protection of each phase eliminates an in-line firing condition by preventing inputs (pins 13 - 17) 50% t f t r outputs: 90% 10% 50% t d (on) t d (off) (pins 2,5) (reference table 2 also.) figure 2. input/output timing relationships simultaneous turn-on of both the upper and lower transistors. the logic controls the high- and low-side gate drivers. operation from +5 to +15 v logic levels can be programmed by applying the appropriate voltage to pin 12 (v lpi ). the pwr- 82340/342 has a ground referenced low-side gate drive.
5 data device corporation www.ddc-web.com pwr-82340/pwr-82342 h-06/05-0 an internal dc-dc converter supplies a floating output to each of the two high-side drives. this provides a continuous high-side gate drive even during a motor stall. pin 11 (vlpo) supplies a +15 v output, which can be used to power the internal logic when system usage requires +15 v logic. the high- and low-side gate drivers control the n-channel mosfet or igbt output stage. the mosfets used in the pwr-82340 allow output switching up to 50 khz, while the high-speed igbts in the pwr-82342 can switch at 25 khz. a flyback diode parallels each output transis- tor and controls the regenerative energy produced by the motor. these fast recovery diodes have faster reverse switching times than the intrinsic body diode of the mosfets used in the pwr- 82340. they also protect the igbts used in the pwr-82342 from exceeding their emitter-to-collector breakdown voltage. use of a copper case and solder attachment of the output tran- sistors achieves a low thermal resistance of 0.85c/w maximum. care should be taken to adequately heatsink these motor drives to maintain a case temperature of +125c. junction tempera- tures should not exceed +150c. the pwr-82340/342 does not have internal short circuit or overcurrent protection which, if required, must be added externally to the hybrid. bias voltages the pwr-82340 and pwr-82342 motor drive hybrids only require a single power supply for operation. the hybrid gener- ates two independent, floating supplies, which eliminates the need for external bias voltages for each phase. in order for the internal power supply to generate these voltages, the input bias voltage (vb) must be from +15 to +50 vdc. in most avionic systems this can be accomplished by connecting the vb pin to the mil-std-704d, +28 volt bus. see figure 3a. if the system bus voltage is greater than +50 vdc (and a lower voltage is not available), then the vb pin and vz pin can be tied together with an external power resistor (rb) and connected from these pins to the system power bus. see figure 3b. see figures 4 and 5 for bias resistor characteristics. if additional power dissipation in rb is a concern, figure 3c shows a more efficient design, using a low-power resistor (r0) and an additional transistor. to determine the proper resistor to use, refer to figure 6. if there is another voltage available in the system in the +15 to +50 vdc range, then this voltage can be directly connected to the vb pin of the hybrid. in any case, a 0.01 mf decoupling capac- itor (cb) must be connected between vb (pin 8) and gnd. figure 3. connection to bus voltage to develop proper input bias voltage v cc (volts) r b (o hms) 6000 5000 4000 3000 2000 1000 0 40 60 80 100 120 140 160 180 200 v cc (volts) r b (k ohms) 50 100 150 200 250 300 350 400 450 500 0.1 1 10 100 figure 4a. bias resistor value vs. bus voltage pwr-82340 figure 4b. bias resistor value vs. bus voltage pwr-82342
6 data device corporation www.ddc-web.com pwr-82340/pwr-82342 h-06/05-0 figure 5a. power dissipated in bias resistor (rb) vs. bus voltage pwr-82340 figure 5b. power dissipated in bias resistor (rb) vs. bus voltage pwr-82342 figure 6. rt resistor value vs. bus voltage rt resistor value, rt (k ohms)
7 data device corporation www.ddc-web.com pwr-82340/pwr-82342 h-06/05-0 digitally controlled inputs the pwr-82340 and pwr-82342 use schmitt triggered digital inputs (with hysteresis) to ensure high noise immunity. the trig- ger switches at different points for positive and negative going signals. hysteresis voltage (vh) is the difference between the positive going voltage (vp) and the negative going voltage (vn) (see figure 7). the digital inputs have programmable logic lev- els, which allows the hybrid to be used with different types of control logic with an input voltage range of +5 to +15 v, such as ttl or cmos logic. the pwr-82340 and pwr-82342 internal power supply generates a +15 vdc (vlpo) on pin 11. this out- put can only be used to power the internal digital circuitry within the hybrid. do not use this +15 v output to power any cir- cuitry external to the hybrid . pin 12 is the logic power input (vlpi) for the digital circuitry inside the hybrid. a 0.01 uf, 50 v ceramic capacitor must be placed between this pin (12) and gnd as close to the hybrid as possible . when using 15 v control circuitry, the logic power input (pin 12) can be connected directly to the logic power output (pin 11) of the hybrid. there is no need for an additional external power supply. when using 5 v control logic, an external +5 vdc supply must be con- nected between pin 12 of the hybrid, and gnd ? leave pin 11 open (n/c) . the control circuitry can be as simple as a pwm, or as sophisticated as a microprocessor or custom asic, depending on the system requirements. the block diagram in figure 8 shows a typical interface of the pwr-82340 and pwr-82342 with a motor and control logic in a servo-amp system. figure 7. hysteresis definition and characteristics figure 8. pwr-82340/342 typical interface with a motor and pwm +28v power supply/bias generation v b 0.01 f 0.01 f v ua v v la lpi v z gnd v lpo drive a v pwr-82340 pwr-82342 cc v oa 0.1 f tant + motor 1 f v ss digital control and protection circuitry position loop and pwm position command v ub v lb gnd drive b v cc v ob v 0.1 f ss 1 f pwr-82340 / pwr-82342 critical ground path v sd to prevent damage to the internal drive circuitry, the differential voltage between gnd (pins 7,18) and vss (pins 1,4) must not exceed 3v max, dc or peak.
8 data device corporation www.ddc-web.com pwr-82340/pwr-82342 h-06/05-0 shut-down input (vsd) pin 15 (vsd) provides a digital shut-down input, which allows the user to completely turn off both the upper and lower output tran- sistors in both phases. application of a logic '1' to the vsd input will latch the digital control/protection circuitry thereby turning off all output transistors. the digital control/protection circuitry remains latched in the off state and will not respond to signals on the vl or vu inputs while the vsd has a logic '1' applied. when the user or the sense circuitry (as in figure 10) returns the vsd input to a logic '0,' and then the user sets the vl and vu inputs to a logic '0' the output of the digital control/protection circuitry will clear the internal latch. when the next rising edge (see fig- ure 9) occurs on the vl or vu digital inputs, the output transis- tors will respond to the corresponding digital input. this feature can be used with external current limit or temperature sense cir- cuitry to disable the drive if a fault condition occurs (see figure 10). internal protection circuitry the hybrid contains digital protection circuitry, which prevents in- line transistors from conducting simultaneously. this, in effect, would short circuit the power supply and would damage the out- put stage of the hybrid. the circuitry allows only proper input sig- nal patterns to cause output conduction. figure 9 and table 3 (see page 13) show these timing relationships. if an improper input requested that the upper and lower transistors of the same phase conduct together, the output would be a high impedance until removal of the illegal code from the input of the pwr- 82340 or pwr-82342. a dead time of 500 nsec minimum should still be maintained between the signals at the vu and vl pins; this ensures the complete turn off of any transistor before turning on its associated in-line transistor. 1 0 1 0 1 0 1 0 1 0 h z l h z l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t sd v sd v oa h z l 1 0 v ua v ub v la v lb v sd v oa v ob figure 9. shut-down (vsd) timing relationships figure 10. functional shut-down input used with current-sensing circuitry r b v cc input commands 14 6 9 8 3 11 motor 5 12 pwr-82340/342 13 uc 1637 pwm a b out out velocity command 16 17 2 7,18 4 1 v sd 15 current sense circuitry thermal sense input r sense
9 data device corporation www.ddc-web.com pwr-82340/pwr-82342 h-06/05-0 pwr-82340 power dissipation (see figure 11) there are three major contributors to power dissipation in the motor driver: conduction losses, switching losses, and flyback diode losses. vcc = 140 v(bus voltage) ioa = 20 a (see figure 11) ; iob = 30 a; (see figure 11) ton = 20 ms (see figure 11); t = 40 ms (period) ron = 0.1 w (on resistance see table 2, io = 30 a, tc = 25 c) ts1 = 250 ns (see figure 11); ts2 = 250 ns (see figure 11) fo = 25 khz(switching frequency) vf is the diode forward voltage, table 2, io = 30 a,tc = 25 c vf(avg) = 1.15 v if is the diode forward current 1. conduction losses (pc) pc = i(t)2 x ron = i motor rms2 x ron pwr-82342 power dissipation (see figure 11) there are three major contributors to power dissipation in the motor driver: conduction losses, switching losses, and flyback diode losses. vcc = 270 v(bus voltage) ioa = 20 a (see figure 11) ; iob = 30 a; (see figure 11) ton = 50 ms (see figure 11); t = 100 ms (period) vce(sat) = 3.8 v (see table 2, io = 30 a, tc = 25 c) ts1 = 300 ns (see figure 11); ts2 = 300 ns (see figure 11) fo = 10 khz(switching frequency) vf is the diode forward voltage, table 2, io = 30 a,tc = 25 c vf(avg) = 1.70 v if is the diode forward current 1. conduction losses (pc) pc = i(t)2 x vce(sat) = iavg x vce(sat) i rms = i 2 ob -i ob (i ob -i oa )+ (i ob -i oa ) 2 3 t on t motor i rms = 30 2 -30(30-20)+ (30 - 20) 2 3 20 40 motor p c = (17.80 a) 2 x (0.1 ? ) p c = 31.68 watts 2. switching losses (p s ) p s = {v cc [i oa (t s1 ) + i ob (t s2 )] f o } / 2 p s = {140 [20 (250 ns) + 30 (250 ns)] 25k} / 2 p s = 21.88 watts 3. flyback diode losses (p df ) p df = i f (avg) x v f (avg) i f (avg) = [(i ob + i oa )/2] / 2 = [(30 + 20)/2] / 2 = 12.5 a p df = 12.5 a x 1.15 v p df = 14.38 watts to calculate the maximum power dissipation of the output tran- sistor as a function of the case temperature use the following equation. (reference figure 20 to ensure you don't exceed the maximum allowable power dissipation of each transistor.) p q = p c + p s to calculate total power dissipated in the hybrid use: where i = each transistor or diode. p total = 4 i=1 [p ci +p si +p dfi ] i avg = + (i ob i oa ) 2 t on t i avg = + (30 20 ) 2 50 100 p c = (12.5 a) x (3.8 v) p c = 47.50 watts 2. switching losses (p s ) p s = {v cc [i oa (t s1 ) + i ob (t s2 )]f o } / 2 p s = {270 [20 (300ns) + 30 (300ns)]10k} / 2 p s = 20.25 watts 3. flyback diode losses (p df ) p df = i s (avg) x v f (avg) i f (avg) = [(i ob + i oa ) / 2] / 2 = [(30 + 20) / 2] / 2 = 12.5 a p df = 12.5 a x 1.70 v p df = 21.25 watts to calculate the maximum power dissipation of the output tran- sistor as a function of the case temperature use the following equation. (reference figure 20 to ensure you don't exceed the maximum allowable power dissipation of each transistor.) p q = p c + p s to calculate total power dissipated in the hybrid use: where i = each transistor or diode. p total = 4 i=1 [p ci +p si +p dfi ] figure 11. output characteristics
10 data device corporation www.ddc-web.com pwr-82340/pwr-82342 h-06/05-0 ground connections layout and external components important information - the following information regarding lay- out guidelines and required external components is critical to the proper operation of these motor drives. external connections can be easily made to the hybrid by any of the following methods: solder a wire around each pin. use a printed circuit board with a cutout that will enable the printed circuit board to slide over the pins. permanent damage will result to the motor drive if the user does not make the following recommended ground connections that will ensure the proper operation of the hybrid. the vb and logic grounds are on pins 7 and 18 (gnd). the vss connections for the output stage are on pins 1 and 4 (vss). to prevent damage to the internal drive circuitry, the differential volt- age between gnd (pins 7, 18) and vss (pins 1, 4) must not exceed 3 v max, dc or peak. this includes the combined volt- age drop of the associated ground paths and the voltage drop across rsense (see figure 12). for example, a value for rsense of 0.025 w will give a voltage drop of 1.25 v at 50 a and allow enough margin for the voltage drop in the ground conduc- tors. locate rsense 1" - 2" maximum from the hybrid. it is criti- cal that all ground connections be as short, and of lowest imped- ance, as the system allows. c1 and c2 are 1 mf, 10 v ceramic capacitors that provide a low ac impedance between each vss pin and gnd. you must use one capacitor for each vss pin-to-gnd connection (total of two capacitors in all). these capacitors are independent of the type of drive scheme used. since placement of these capacitors is critical, place these capacitors across the hybrid, if possible. please note, on figure 12, that c1 and c2 must go directly from terminal to terminal on the hybrid ? do not daisy chain along the ground return. c3 and c4 are the 0.1 mf ceramic bypass capacitors that sup- press high frequency spiking. the voltage rating should be 2x the maximum system voltage. these capacitors should be locat- ed as close to the hybrid as possible. care must be taken to control the regenerative energy produced by the motor in order to prevent excessive voltage spiking on the vcc line. accomplish this by placing a capacitor or clamping diode between vcc and the high power ground return. v cc pwr 82340/342 motor r sense c1 14 13 18 17 16 7 8 12 c5 c6 2 1 3 5 4 6 c3 c4 c2 tant + figure 12. pwr-82340/342 ground connections notes: c1, c2 = 1.00 mf, 10 v ceramic capacitors c3, c4 = 0.10 mf, ceramic capacitors c5 = 0.01 mf, 100 v ceramic capacitor c6 = 0.01 mf, 50 v ceramic capacitor tant = refer to magnum motor drive power supply capacitior selection application note (an/h-7)
11 data device corporation www.ddc-web.com pwr-82340/pwr-82342 h-06/05-0 forward voltage, v f (volts) output current pulsed, i op (amps) forward voltage, v f (volts) output current pulsed, i op (amps) 6.0 5.0 4.0 3.0 output vo l tage dro p , v ce(sat) (volts) case temperature, t c ( c) 2.0 -75 -50 -25 0 25 50 75 100 125 150 i op =50a i op =30a i op =10a 180 160 140 120 100 80 40 60 20 output on-resistance, r on (milliohms ) 0 -75 -50 -25 0 25 case temperature, t c ( ) 50 75 100 125 150 i op =50a i op =30a i op =10a figure 14b. pwr-82342 typical vce(sat) variation with temperature figure 14a. pwr-82340 typical on resistance variation with temperature figure 13b. pwr-82342 typical forward voltage drop of flyback diodes figure 13a. pwr-82340 typical forward voltage drop of flyback diodes
12 data device corporation www.ddc-web.com pwr-82340/pwr-82342 h-06/05-0 figure 16. pwr-82340/342 typical quiescent bias current versus bias voltage figure 15b. pwr-82342 typical output on voltage drop versus output current figure 15a. pwr-82340 typical output on voltage drop versus output current
13 data device corporation www.ddc-web.com pwr-82340/pwr-82342 h-06/05-0 v ua v lb v ub v la input switching conditions v ua v lb v ub v la input switching conditions 0 10 15 20 25 30 35 40 45 50 55 2.5 5 7.5 10 operating frequency, f o (khz) bias current, i b (m illiam ps ) 12.5 15 17.5 20 22.5 25 v b =50v v b =28v v b =15v 0 10 20 30 40 50 60 70 80 5101525 operating frequency, f o (khz) bi as curre nt, i b (milliam ps ) 30 35 40 40 45 50 v b =15v v b =28v v b =50v figure 18b. pwr-82342 bias current versus operating frequency figure 18a. pwr-82340 bias current versus operating frequency figure 17b. pwr-82342 typical bias current versus bias voltage at f 0 = 10 khz figure 17a. pwr-82340 typical bias current versus bias voltage at f 0 = 30 khz
14 data device corporation www.ddc-web.com pwr-82340/pwr-82342 h-06/05-0 mounting the package bolts to part of the chassis or even the motor assembly itself, depending on system requirements. in applica- tions where this isn't convenient, the hybrid can be mounted to its own heatsink. the heat transfer in a hybrid is from semicon- ductor junction to the bottom of the hybrid case. the flatness and maximum temperature of this mounting surface are critical to proper performance and reliability, because this is the only method of dissipating the power created in the hybrid. use a mounting surface flatness of 0.004 inches/inch maximum. this interface can be improved with the use of a thermal compound or pad. the heatsink should be designed to insure that the case temperature does not exceeded +125c. figure 19a. pwr-82340 maximum allowable continuous output current versus case temperature figure 19b. pwr-82342 maximum allowable continuous output current versus case temperature figure 20. pwr-82340 and pwr-82342 maximum allowable power dissipation of each output transistor versus case temperature table 3. input-output truth table inputs outputs uppers lowers control v ua v ub v la v lb v sd v oa v ob 0 0 1 1 1 x 0 x 0 1 0 1 x 1 0 x 1 1 0 0 1 x 0 x 1 0 1 0 x 1 0 x 0 0 0 0 0 0 0 1 l l h h z x z z l h l h x z z z h = high level, l = low level, x = irrelevant, z = high impedance (off)
15 data device corporation www.ddc-web.com pwr-82340/pwr-82342 h-06/05-0 2.100 (53.34) 0.120 (3.05) 0.250 (6.35) 2.250 (57.15) 0.125 (3.38) i.d. bead 2000 (50.8) 0.390 max (9.91) 0.140 (3.56) 0.215 (5.46) flatness is 0.004 inches per inch side view note: dimensions in inches (mm). top view 90 5 typ 0.115 (2.92) 0.050 (1.27) 0.002 dia typ 0.010 (0.26) r typ 0.100 (2.54) 0.325 (8.26) 8 eq. sp. @ 0.200 = 1.600 (5.08) (40.64) (tol. (noncum.) 0.200 (5.08) typ 0.128 (3.25) +0.002-0.005 (4 holes) 1.860 (47.24) 1.600 (40.64) 1 9 10 18 figure 21. pwr-82340 and pwr-82342 mechanical outline table 4. pin assignments pin function pin function 1 v ss 18 gnd 2 v ob 17 v ub 3 v cc 16 v lb 4 v ss 15 v sd 5 v oa 14 v ua 6 v cc 13 v la 7 gnd 12 v lpi 8 v b 11 v lpo 9 v z 10 n/c note: pins 3 and 6 are internally connected;pins 7 and 18 are internally connected. table 1 1015 (note 1) , 1030 (note 2) burn-in notes: 1. for process requirement "b*" (refer to ordering information), devices may be non-compliant with mil- std-883, test method 1015, paragraph 3.2. contact factory for details. 2. when applicable. 3000g 2001 constant acceleration c 1010 temperature cycle a and c 1014 seal 2009, 2010, 2017, and 2032 inspection condition(s) method(s) mil-std-883 test standard ddc processing for hybrid and monolithic hermetic products
16 pwr-82340/pwr-82342 h-06/05-0 printed in the u.s.a. data device corporation registered to iso 9001:2000 file no. a5976 r e g i s t e r e d f i r m ? u the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. please visit our web site at www.ddc-web.com for the latest information. 105 wilbur place, bohemia, new york, u.s.a. 11716-2482 for technical support - 1-800-ddc-5757 ext. 7771 headquarters, n.y., u.s.a. - tel: (631) 567-5600, fax: (631) 567-7358 southeast, u.s.a. - tel: (703) 450-7900, fax: (703) 450-6610 west coast, u.s.a. - tel: (714) 895-9777, fax: (714) 895-4988 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)89-150012-11, fax: +49-(0)89-150012-22 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com data device corporation registered to iso 9001:2000 file no. a5976 r e g i s t e r e d f i r m ? u ordering information pwr-8234x -x x 0 reliability grade: 0 = standard ddc procedures. 1 = military processing available. 2 = military processing available without qci testing. temperature range: 1 = -55 to +125c 3 = 0 to +70c rating: 0 = 200 v using mosfets 2 = 500 v using igbts

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