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| toshiba original cmos 16-bit microcontroller tlcs-900/l1 series TMP91C820AFG semiconductor company
preface thank you very much for making use of toshiba microcomputer lsis. before use this lsi, refer the section, ?points of note and restrictions?. especially, take care below cautions. ** caution ** how to release the halt mode usually, interrupts can release all halts status. however, the interrupts = ( nmi , int0 to int3, intrtc, intalm0 to intalm4, intkey), which can release the halt mode may not be able to do so if they are input during the period cpu is shifting to the halt mode (for about 5 clocks of f fph ) with idle1 or stop mode (idle2 is not applicable to this case). (in this case, an interrupt request is kept on hold internally.) if another interrupt is generated after it has shifted to halt mode completely, halt status can be released without difficultly. the priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. tmp91c820a 2008-02-20 91c820a-1 cmos 16-bit microcontrollers TMP91C820AFG/jt5aw4-s 1. outline and features tmp91c820a/jt5aw4 is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment. TMP91C820AFG comes in a 144-pin flat package. jt5aw4-s comes in a 144-pad chip. listed below are the features. (1) high-speed 16-bit cpu (900/l1 cpu) instruction mnemonics are upward compatible with tlcs-90 16 mbytes of linear address space general-purpose registers and register banks 16-bit multiplication and division instructions; bit transfer and arithmetic instructions micro dma: 4 channels (444 ns/2 bytes at 36 mhz) (2) minimum instruction execution time: 111ns (at 36 mhz) restrictions on product use 20070701-en ? the information contained herein is subject to change without notice. ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc. ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in his document shall be made at the customer?s own risk. ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patents or other rights of toshiba or the third parties. ? please contact your sales representative for product-by-product details in this document regarding rohs compatibility. please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. ? for a discussion of how the reliability of microcontrollers can be predicted, please refer to section 1.3 of the chapter entitled quality and reliability assurance/handling precautions. tmp91c820a 2008-02-20 91c820a-2 (3) built-in ram: 8 kbytes built-in rom: 8 kbytes (however, 9999 (rom code) has no internal rom.) (4) external memory expansion ? expandable up to 136 mbytes (shared program/data area) ? can simultaneously support 8- or 16-bit width external data bus ... dynamic data bus sizing ? separate bus system (5) 8-bit timers: 4 channels (6) 16-bit timer: 1 channel (7) general-purpose serial interface: 3 channels ? uart/synchronous m ode ? irda (8) serial bus interface: 1 channel i 2 c bus mode/clock synchronous select mode (9) lcd controller ? shift register/built-in ram lcd driver ? supported 16, 8 and 4 gray levels and black and white ? hardware blinking cursor (10) sdram controller supported 16-m, 64-m and 128-mbit sdram with 16-bit data bus (11) timer for real time clock (rtc) ? based on tc8521a (12) key-on wakeup (interrupt key input) (13) 10-bit ad converter: 8 channels (14) watchdog timer (15) melody/alarm generator ? m elody: output of clock 4 to 5461 hz ? alarm: output of the 8 kinds of alarm pattern ? output of the 5 kinds of interval interrupt (16) chip select/wait controller: 4 channels (17) mmu ? expandable up to 136 mbytes (4 local area/8-bank method) (18) interrupts: 46 interrupts ? 9 cpu interrupts: software interrupt instruction and illegal instruction ? 31 internal interrupts: seven selectable priority levels ? 6 external interrupts: seven selectable priority levels (4-edge selectable) (19) input/output ports: 77 pins (at external 16-bit data bus memory) (20) standby function three halt modes: idle2 (programmable), idle1, stop (21) hardware standby function (power save function) tmp91c820a 2008-02-20 91c820a-3 (22) triple-clock controller clock doubler (dfm) clock gear function: select a high-frequency clock fc to fc/16 rtc (fs = 32.768 khz) (23) operating voltage ? vcc = 2.7 v to 3.6 v (fc = 27 mhz) ? vcc = 3.0 v to 3.6 v (fc max = 36 mhz) (24) package ? 144-pin qfp: lqfp144-p-1616-0.40c ? chip form supply also available. for details, contact your local toshiba sales representative. tmp91c820a 2008-02-20 91c820a-4 note: when rom code is 9999, it has no rom. figure 1.1 tmp91c820a block diagram 8-kbyte sram cpu (tlcs-900/l1) 10-bit 8ch ad converter h-osc sio/uart/irda (sio0) 8-bit timer (tmra0) 32 bits f sr xwa xbc xde xhl xix xiy xiz xsp w a ix iy iz sp txd0 (pc0) rxd0 (pc1) txd1 (pc3) rxd1 ( pc4 ) dvcc [3] x1 x2 p00 to p07(d0 to d7) p10 to p17(d8 to d15) p20 to p27 (a16 to a23) p30 to p37(a8 to a15) p40 to p47(a0 to a7) a n0 to a n7 (p80 to p87) avcc, avss vrefh, vrefl reset am0 a m1 wdt (watchdog timer) pc clock gear, clock doubler sio/uart (sio1) rd (pz0) l-osc emu0 emu1 port 4 cs0 to cs3 , cs2a interrupt controller int0 to int3,ta3out, keyboard i/f ki0 to ki7 (p90 to p97) ko0 to ko7 (pa0 to pa7) melody/ alarm out mldalm (pd7) 8-bit timer (tmra1) rxd2/ta1out (pb1) 8-bit timer (tmra2) 8-bit timer (tmra3) ta3out/int2 (pb5) ( ): initial function after reset b c d e h l adtrg (p83) sclk1/ cts1 ( pc5 ) (p60 to p63) port 3 d1bscp (pd0) d2blp (pd1) d3bfr (pd2) dlebcd (pd3) doffb (pd4) port 6 port 7 msk (p76), veeclk (p77) tb0out0 (pb3 to pb6) sclk0/ cts0 (pc2) optrx0, sck (p70) opttx0, so/sda (p71) serial bus i/f (sbi) si/scl (p72) rtc a larm , mldalm (pd6) xt1 xt2 txd2/ta0in (pb0) nmi / ps ea24, cs2b (p64), ld0 to ld7 (pe0 to pe7) sdram controller sdcke (pf5) sdclk (pf6) sdldqm (pf3) sdudqm (pf4) sdwe (pf2) sdras (pf0) sdcas (pf1) sdcs (p61) sio/uart (sio2) txd2/ta0in (pb0) rxd2/ta1out (pb1) dvss [7] 8-kbyte mrom (note) tb0out0/int3 (pb6) cs2e / srub (p67) cs2f (p73) cs2g (p74) csexa (p75) port 1 port 0 wr (pz1) hwr (pz2) w / r , srwr (pz3) wait (p56) port 2 port 5/ port z cs/wait controller (4 blocks) mmu lcd controller port 8 port 9 port a port b port c port d port e port f 16-bit timer (tmrb0) cs2f (p73) cs2g (p74) csexa (p75) ea25, cs2c (p65), cs2d / srlb (p66), tmp91c820a 2008-02-20 91c820a-5 2. pin assignment and pin functions the assignment of input/output pins for the tmp91c820a, their names and functions are as follows: 2.1 pin assignment diagram figure 2.1.1 shows the pin assignment of the TMP91C820AFG. figure 2.1.1 pin assignment diagram (144-pin qfp) p64/ea24/ cs2a cs2 p62 / / srub srlb cs2c cs2b pz2/ dvcc3 p75/ p74/ p73/ cs0 cs1 wait r/w hwr alarm mldalm csexa cs2g cs2e cs2f cs2d txd1/pc3 rxd0/pc1 vrefl p87/an7 a vss vrefh TMP91C820AFG qfp144 to p v i e w 1 5 10 15 20 25 30 40 45 50 55 60 75 80 85 90 95 110 115 120 125 avcc ki2/p92 ki3/p93 ki4/p94 ki 5/p95 ki6/p96 ki7/p97 ko0/pa0 ko1/pa1 ko2/pa2 ko3/pa3 ko4/pa4 ko5/pa5 ko6/pa6 k o 7 / pa7 txd2/ta0in/pb0 rxd2/ta1out/pb1 int0/pb3 int1/pb4 ta3out/int2/pb5 tb0out0/int3/pb6 txd 0/ p c0 sclk0 / cts 0 /pc2 pz0/ rd p27/a23 p26/a22 p25/a21 p24/a20 p2 3/ a1 9 p22/a18 p21/a17 dvcc2 p20/a16 p37/a15 p36/a14 p35/a13 p34/a12 p33/a11 p32/a10 p31/a9 p30/a8 p47/a7 p46/a6 p45/a5 p44/a4 p43/a3 p42/a2 p41/a1 p40/a0 p07/d7 p06/d6 p05/d5 p04/d4 p03/d3 p02/d2 p01/d1 p00/d0 doffb/pd4 dlebcd/pd3 d3bfr/pd2 d2blp/pd1 d1bscp/pd0 /pf2 emu1 emu0 xt2 xt1 am1 x1 x2 p82/an2 pd6/ / p77/veeclk p76/msk p72/si/scl p71/so/sda/opttx0 p70/sck/optrx0 p67/ / p66 / / p65/ea25/ 35 65 70 100 105 130 135 140 rxd1/pc4 ld0/pe0 ld1/pe1 ld2/pe2 ld3/pe3 sclk1/ cts1 /pc5 ld4/pe4 ld5/pe5 ld6/pe6 ld7/pe7 d13/p15 d14/p16 d15/p17 p61/ / dvss1 dvss2 dvss3 dvss4 dvss5 dvss6 dvcc1 am0 /pf1 /pf0 d8/p10 d9/p11 d10/p12 d11/p13 d12/p14 pz1/ p83/an3/ adtrg p84/an4 p85/an5 p86/an6 p81/an1 p80/an0 p91/ki1 p90/ki0 pf7 pf6/sdclk dvss7 pf5/sdcke pf4/sdudqm pf3/sdldqm pd7/mldalm sdwe sdras sdcas sdcs cs3 srwe wr reset pz3/ / p63/ p60/ p56/ / ps nmi tmp91c820a 2008-02-20 91c820a-6 2.2 pad layout (chip size 5.75 mm 5.63 mm) unit: m pin no. name x point y point pin no. name x point y point pin no. name x point y point 1 p81 ? 2742 2128 49 xt2 ? 485 ? 2682 97 p37 2736 758 2 p82 ? 2742 2004 50 emu0 ? 370 ? 2682 98 dvcc2 2736 872 3 p83 ? 2742 1888 51 emu1 ? 256 ? 2682 99 p20 2736 986 4 p84 ? 2742 1774 52 pd1 ? 142 ? 2682 100 dvss5 2736 1202 5 p85 ? 2742 1660 53 pd2 ? 28 ? 2682 101 p21 2736 1318 6 p86 ? 2742 1546 54 pd3 86 ? 2682 102 p22 2736 1432 7 p87 ? 2742 1432 55 pd4 200 ? 2682 103 p23 2736 1546 8 avss ? 2742 1318 56 pe0 314 ? 2682 104 p24 2736 1660 9 avcc ? 2742 1204 57 pe1 428 ? 2682 105 p25 2736 1774 10 p92 ? 2742 892 58 pe2 542 ? 2682 106 p26 2736 1888 11 p93 ? 2742 778 59 pe3 656 ? 2682 107 p27 2736 2004 12 p94 ? 2742 664 60 pe4 770 ? 2682 108 pz0 2736 2128 13 p95 ? 2742 550 61 pe5 884 ? 2682 109 pz1 2188 2676 14 p96 ? 2742 436 62 pe6 998 ? 2682 110 pz2 2062 2676 15 p97 ? 2742 322 63 pe7 1112 ? 2682 111 pz3 1948 2676 16 pa0 ? 2742 208 64 dvss3 1246 ? 2682 112 p56 1834 2676 17 pa1 ? 2742 94 65 p00 1378 ? 2682 113 p60 1720 2676 18 pa2 ? 2742 ? 20 66 p01 1492 ? 2682 114 p61 1606 2676 19 pa3 ? 2742 ? 134 67 p02 1606 ? 2682 115 p62 1492 2676 20 pa4 ? 2742 ? 248 68 p03 1720 ? 2682 116 dvss6 1378 2676 21 pa5 ? 2742 ? 362 69 p04 1834 ? 2682 117 p63 1264 2676 22 pa6 ? 2742 ? 476 70 p05 1948 ? 2682 118 p64 1150 2676 23 pa7 ? 2742 ? 590 71 p06 2062 ? 2682 119 p65 1036 2676 24 pb0 ? 2742 ? 704 72 p07 2188 ? 2682 120 p66 922 2676 25 pb1 ? 2742 ? 818 73 p10 2736 ? 2134 121 p67 808 2676 26 pb3 ? 2742 ? 932 74 p11 2736 ? 2010 122 p70 694 2676 27 pb4 ? 2742 ? 1046 75 p12 2736 ? 1894 123 p71 580 2676 28 dvss1 ? 2742 ? 1210 76 p13 2736 ? 1780 124 p72 382 2676 29 pb5 ? 2742 ? 1324 77 p14 2736 ? 1666 125 dvcc3 268 2676 30 pb6 ? 2742 ? 1438 78 p15 2736 ? 1552 126 p73 68 2676 31 pc0 ? 2742 ? 1552 79 p16 2736 ? 1438 127 p74 ? 46 2676 32 pc1 ? 2742 ? 1666 80 dvss4 2736 ? 1318 128 p75 ? 160 2676 33 pc2 ? 2742 ? 1780 81 p17 2736 ? 1066 129 p76 ? 274 2676 34 pc3 ? 2742 ? 1894 82 p40 2736 ? 952 130 p77 ? 388 2676 35 pc4 ? 2742 ? 2010 83 p41 2736 ? 838 131 pd6 ? 520 2676 36 pc5 ? 2742 ? 2134 84 p42 2736 ? 724 132 pd7 ? 634 2676 37 pf0 ? 2194 ? 2682 85 p43 2736 ? 610 133 pf3 ? 748 2676 38 pf1 ? 2068 ? 2682 86 p44 2736 ? 496 134 pf4 ? 862 2676 39 pf2 ? 1954 ? 2682 87 p45 2736 ? 382 135 pf5 ? 976 2676 40 pd0 ? 1840 ? 2682 88 p46 2736 ? 268 136 dvss7 ? 1090 2676 41 am0 ? 1726 ? 2682 89 p47 2736 ? 154 137 pf6 ? 1204 2676 42 dvcc1 ? 1612 ? 2682 90 p30 2736 ? 40 138 pf7 ? 1318 2676 43 x2 ? 1410 ? 2682 91 p31 2736 74 139 p90 ? 1432 2676 44 dvss2 ? 1244 ? 2682 92 p32 2736 188 140 p91 ? 1546 2676 45 x1 ? 1079 ? 2682 93 p33 2736 302 141 nmi ? 1660 2676 46 am1 ? 963 ? 2682 94 p34 2736 416 142 vrefl ? 1954 2676 47 reset ? 849 ? 2682 95 p35 2736 530 143 vrefh ? 2068 2676 48 xt1 ? 734 ? 2682 96 p36 2736 644 144 p80 ? 2194 2676 tmp91c820a 2008-02-20 91c820a-7 2.3 pin names and functions the names of the input/output pins and their functions are described below. table 2.3.1 pin names and functions (1/4) pin name number of pins i/o functions p00 to p07 d0 to d7 8 i/o i/o port 0: i/o port that allows i/o to be selected at the bit level data (lower): bits 0 to 7 of data bus p10 to p17 d8 to d15 8 i/o i/o port 1: i/o port that allows i/o to be selected at the bit level (when used to the external 8-bit bus) data (upper): bits 8 to15 of data bus p20 to p27 a16 to a23 8 output output port 2: i/o port address: bits 16 to 23 of address bus p30 to p37 a8 to a15 8 output output port 3: i/o port address: bits 8 to 15 of address bus p40 o p47 a0 to a7 8 output output port 4: i/o port address: bits 0 to 7 of address bus pz0 rd 1 output output port z0: output port read: strobe signal for reading external memory pz1 wr 1 output output port z1: output port write: strobe signal for writing data to pins d0 to d7 pz2 hwr 1 i/o output port z2: i/o port (with pull-up resistor) high write: strobe signal for writing data to pins d8 to d15 pz3 r/ w srwr 1 i/o output output port z3: i/o port (with pull-up resistor) read/write: 1 represents read or dummy cycle; 0 represents write cycle. write for sram: strobe signal for writing data. p56 wait 1 i/o input port 56: i/o port (with pull-up resistor) wait: pin used to request cpu bus wait p60 cs0 1 output output port 60: output port chip select 0: outputs 0 when address is within specified address area. p61 cs1 sdcs 1 output output output port 61: output port chip select 1: outputs 0 when address is within specified address area chip select for sdram: outputs 0 when address is within sdram address area p62 cs2 cs2a 1 output output output port 62: output port chip select 2: outputs 0 when address is within specified address area expand chip select 2a: outputs 0 when address is within specified address area p63 cs3 1 output output port 63: output port chip select 3: outputs 0 when address is within specified address area p64 ea24 cs2b 1 output output output port 64: output port chip select 24: outputs 0 when address is within specified address area expand chip select 2b: outputs 0 when address is within specified address area p65 ea25 cs2c 1 output output output port 65: output port chip select 25: outputs 0 when address is within specified address area expand chip select 2c: outputs 0 when address is within specified address area p66 cs2d srlb 1 output output output port 66: output port expand chip select 2d: outputs 0 when address is within specified address area lower byte enable for sram: outputs 0 when lower data is enable. p67 cs2e srub 1 output output output port 67: output port expand chip select 2e: outputs 0 when address is within specified address area upper byte enable for sram: outputs 0 when upper data is enable. tmp91c820a 2008-02-20 91c820a-8 table 2.3.2 pin names and functions (2/4) pin name number of pins i/o functions p70 sck optrx0 1 i/o i/o input port 70: i/o port serial bus interface clock i/o data at sio mode serial 0 recive data p71 s0 sda optrx0 1 i/o output i/o output port 71: i/o port serial bus interface send data at sio mode serial bus interface send/recive data at i 2 c bus mode (open-drain output mode by programmable) serial 0 send data p72 si scl 1 i/o input i/o port 72: i/o port serial bus interface recive data at sio mode serial bus interface clock i/o data at i 2 c bus mode (open-drain output mode by programmable) p73 cs2f 1 i/o output port 73: i/o port expand chip select 2f: outputs 0 when address is within specified address area p74 cs2g 1 i/o output port 74: i/o port expand chip select 2g: outputs 0 when address is within specified address area p75 csexa 1 i/o output port 75: i/o port expand chip select exa: outputs 0 when address is within specified address area p76 msk 1 i/o input port 76: i/o port mask: use for disable to output veeclk for lcd driver p77 veeclk 1 i/o output port 77: i/o port output 32.768 khz clock to lcd driver. (can be disabled by msk pin.) p80 to p87 an0 to an7 adtrg 8 input input input port 80 to 87: pin used to input ports analog input 0 to 7: pin used to input to ad conveter ad trigger: signal used to request ad start (with used to p83) p90 to p97 ki0 to ki7 8 input input port 90 to 97: pin used to input ports key input 0 to 7: pin used of key-on wakeup 0 to 7 (schmitt input, with pull-up resistor) pa0 to pa7 ko0 to ko7 8 output output port a0 to a7: pin used to output ports key output 0 to 7: pin used of key-scan strobe 0 to 7 pb0 ta0in txd2 1 i/o input output port b0: i/o port 8-bit timer 0 input: timer 0 input serial 2 send data: open-drain output pin by programmable pb1 ta1out rxd2 1 i/o output input port b1: i/o port 8-bit timer 1 output: timer 1 output serial 2 receive data pb3 int0 1 i/o input port b3: i/o port interrupt request pin0: interrupt request pin with programmable level/rising/falling edge pb4 int1 1 i/o input port b4: i/o port interrupt request pin1: interrupt request pin with programmable rising/falling edge tmp91c820a 2008-02-20 91c820a-9 table 2.3.3 pin names and functions (3/4) pin name number of pins i/o functions pb5 int2 ta3out 1 i/o input output port b5: i/o port interrupt request pin2: interrupt request pin with programmable rising/falling edge 8-bit timer 3 output: timer 3 output pb6 int3 tb0out0 1 i/o input outout port b6: i/o port interrupt request pin3: interrupt request pin with programmable rising/falling edge timer b0 output pc0 txd0 1 i/o output port c0: i/o port serial 0 send data: open-drain output pin by programmable pc1 rxd0 1 i/o input port c1: i/o port serial 0 receive data pc2 sclk0 cts0 1 i/o i/o input port c2: i/o port serial 0 clock i/o serial 0 data send enable (clear to send) pc3 txd1 1 i/o output port c3: i/o port serial 1 send data (open-drain output pin by programmable) pc4 rxd1 1 i/o input port c4: i/o port serial 1 receive data pc5 sclk1 cts1 1 i/o i/o input port c5: i/o port serial 1 clock i/o serial 1 data send enable (clear to send) pd0 d1bscp 1 output output port d0: output port lcd driver output pin pd1 d2blp 1 output output port d1: output port lcd driver output pin pd2 d3bfr 1 output output port d2: output port lcd driver output pin pd3 dlebcd 1 output output port d3: output port lcd driver output pin pd4 doffb 1 output output port d4: output port lcd driver output pin pd6 alarm mldalm 1 output output output port d6: output port rtc alarm output pin melody/alarm output pin (inverted) pd7 mldalm 1 output output port d7: output port melody/alarm output pin pe0 to pe7 ld0 to ld7 8 i/o output port e0 to e7: i/o port data bus for lcd driver pf0 sdras 1 i/o output port f0: output port row address storobe for sdram: outputs 0 when address is within sdram address area pf1 sdcas 1 i/o output port f1: output port column address storobe for sdram: outputs 0 when address is within sdram address area tmp91c820a 2008-02-20 91c820a-10 table 2.3.4 pin names and functions (4/4) pin name number of pins i/o functions pf2 sdwe 1 output output port f2: output port write enable for sdram pf3 sdldqm 1 output output port f3: output port lower data enable for sdram pf4 sdudqm 1 output output port f4: output port upper data enable for sdram pf5 sdcke 1 output output port f5: output port clock enable for sdram pf6 sdclk 1 output output port f6: output port clock for sdram pf7 1 output port f7: output port ps nmi (note) 1 input input power save mode setting terminal non-maskable interrupt request: interrupt request pin with programmable falling edge level or with both edge levels programmable am0 to am1 2 input operation mode: fixed to am1 = 1, am0 = 1 when using internal rom (when rom code is 9999, setting is prohibitted). fixed to am1 = 0, am0 = 1 when using external rom by 16-bit external bus, or 8- or 16-bit dynamic sizing. fixed to am1 = 0, am0 = 0 when using external rom by 8-bit external bus. emu0 1 output open pin emu1 1 output open pin reset 1 input reset: initializes tmp91c820a (with pull-up resistor). vrefh 1 input pin for reference voltage input to ad converter (h) vrefl 1 input pin for reference voltage input to ad converter (l) x1/x2 2 i/o high-frequency oscillator connection pins xt1/xt2 2 i/o low-frequency oscillator connection pins avcc 1 power supply pin for ad converter avss 1 gnd pin for ad converter (0 v) dvcc 3 power supply pins (all vcc pins should be connecyed with the power supply pin). dvss 7 gnd pins (all pins should be connected with gnd (0 v).) note: please input 1 into nmi / ps pin, because nmi / ps = 0 means power save mode after reset. tmp91c820a 2008-02-20 91c820a-11 3. operation this following describes block by block the functions and operation of the tmp91c820a. notes and restrictions for eatch b ook are outlined in 6 ?points of note and restrictions? at the end of this manual. 3.1 cpu the tmp91c820a incorporates a high-performance 16-bit cpu (the 900/l1 cpu). for cpu operation, see the ?tlcs-900/l1 cpu?. the following describe the unique function of the cpu used in the tmp91c820a; these functions are not covered in the tlcs-900/l1 cpu section. 3.1.1 reset when resetting the tmp91c820a microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. then hold the reset input to low level for at least 10 system clocks (9 s at 36mhz). thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequ ency oscillator has stabilized. then hold the reset input to low level at least for 10 system clocks. clock gear is initialized 1/16 mode by reset operation. it means that the system clock mode f sys is set to fc/32 ( = fc/16 1/2). when the reset is accept, the cpu: ? sets as follows the program counter (pc) in accordance with the reset vector stored at address ffff00h to ffff02h: pc<7:0> value at ffff00h address pc<15:8> value at ffff01h address pc<23:16> value at ffff02h address ? sets the stack pointer (xsp) to 100h. ? sets bits tmp91c820a 2008-02-20 91c820a-12 read write f fph a23 to a0 data-in d0 to d15 d0 to d15 sampling (after reset released, startting 2 waits read cycle) : pull up (internal) : high-z data-out sampling (pz2 input mode) 0ffff00h data-in xt1, xt2 reset cs0, cs1, cs3 cs2 rd w r hw r figure 3.1.1 tmp91c820a-9999 reset timing example (the case of using external rom) tmp91c820a 2008-02-20 91c820a-13 3.2 memory map figure 3.2.1 is a memory map of the tmp91c820a. 000000h 001000h 16-mbyte area (r) ( ? r) (r + ) (r + r8/16) (r + d8/16) (nnn) direct area ( n ) 64-kbyte area (nn) internal i/o (4 kbytes) 003000h 010000h ( = internal area ) ffff00h ffffffh vector table ( 256 b y tes ) external memory 000100h 000fe0h mask rom (8 kbytes ) ffe000h internal ram (8 kbytes) figure 3.2.1 memory map note: address 000fe0h to 000fffh is assigned for the external memory area of built-in ram type lcd driver. and when rom code is 9999, internal mask rom area also defines external memory area. tmp91c820a 2008-02-20 91c820a-14 3.3 triple clock function and standby function tmp91c820a contains (1) clock gear, (2) clock doubler (dfm), (3) standby controller, and (4) noise-reducing circuit. it is used for low-power, low-noise systems. this chapter is organized as follows: 3.3.1 block diagram of system clock 3.3.2 sfrs 3.3.3 system clock controller 3.3.4 prescaler clock controller 3.3.5 clock doubler (dfm) 3.3.6 noise reduction circuits 3.3.7 standby controller tmp91c820a 2008-02-20 91c820a-15 the clock operating modes are as follows: (a) single clock mode (x1, x2 pins only), (b) dual clock mode (x1, x2, xt1 and xt2 pins) and (c) triple clock mode (the x1, x2, xt1 and xt2 pins and dfm). figure 3.3.1 shows a transition figure. using dfm instruction reset (f osch /32) release reset instruction interrupt stop mode (stops all circuits) normal mode (f osch /gear value/2) idle2 mode (i/o operate) idle1 mode (operate only oscillator) (a) single clock mode transition figure (b) dual clock mode transition fiigure stop mode (stops all circuits) slow mode (fs/2) reset (f osch /32) release reset normal mode (f osch /gear value/2) idle2 mode (i/o operate) idle1 mode (operate only oscillator) idle2 mode (i/o operate) idle1 mode (operate only oscillator) reset (f osch /32) release reset normal mode (f osch /gear value/2) idle2 mode (i/o operate) idle1 mode (operate only oscillator) stop mode (stops all circuits) slow mode (fs/2) normal mode (4 f osch /gear value/2) idle2 mode (i/o operate) idle1 mode (operate oscillator and dfm) idle2 mode (i/o operate) idle1 mode (operate only oscillator) (c) triple clock mode transition figure instruction instruction interrupt interrupt instruction instruction interrupt interrupt instruction instruction interrupt interrupt instruction interrupt instruction instruction interrupt interrupt instruction instruction instruction interrupt * note * note note 1: it?s prohibited to control dfm in slow mode when shiftin g from slow mode to normal mode with use o f dfm. (dfm start up/stop/change write to dfmcr0 tmp91c820a 2008-02-20 91c820a-16 3.3.1 block diagram of system clock clock gear syscr1 tmp91c820a 2008-02-20 91c820a-17 3.3.2 sfrs 7 6 5 4 3 2 1 0 bit symbol xen xten rxen rxten rsysck wuef prck1 prck0 read/write r/w after reset 1 1 1 0 0 0 0 0 function high- frequency oscillator (fc) 0: stop 1: oscillation low- frequency oscillator (fs) 0: stop 1: oscillation (note 1) high- frequency oscillator (fc) after release of stop mode 0: stop 1: oscillation low- frequency oscillator (fs) after release of stop mode 0: stop 1: oscillation selects clock after release of stop mode 0: fc 1: fs warm-up timer 0: write don?t care 1: write start timer 0: read end warm up 1: read do not end warm up select prescaler clock 00: f fph (note 2) 01: reserved 10: fc/16 11: reserved 7 6 5 4 3 2 1 0 bit symbol sysck gear2 gear1 gear0 read/write r/w after reset 0 1 0 0 function select system clock 0: fc 1: fs select gear value of high frequency (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (reserved) 110: (reserved) 111: (reserved) 7 6 5 4 3 2 1 0 bit symbol psenv wuptm1 wuptm0 haltm1 haltm0 seldrv drve read/write r/w r/w r/w r/w r/w r/w r/w after reset 0 1 0 1 1 0 0 function 1:disable 0:power save mode enable (note 3) warm-up timer 00: reserved 01: 2 8 inputted frequency 10:2 14 11:2 16 halt mode 00: reserved 01: stop mode 10: idle1 mode 11: idle2 mode tmp91c820a 2008-02-20 91c820a-18 symbol name address 7 6 5 4 3 2 1 0 act1 act0 dlupfg dluptm r/w r/w r r/w 0 0 0 0 dfm lup select f fph dfmcr0 dfm control register 0 e8h 00 01 10 11 stop run run run stop run stop stop f osch f osch f dfm f osch lockup status flag 0: end 1: not end lockup time 0: 2 12 /f osch 1: 2 10 /f osch d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 1 0 0 1 1 dfmcr1 dfm control register 1 e9h dfm revision input frequency 4 to 9 mhz (at 2.7 v to 3.6 v): write 0bh figure 3.3.4 sfr for dfm limitation point on the use of dfm 1. it?s prohibited to execute dfm enable/disable control in the slow mode (fs) (write to dfmcr0 tmp91c820a 2008-02-20 91c820a-19 7 6 5 4 3 2 1 0 bit symbol protect ta3lcde ahold ta3mlde ? extin drvosch drvoscl read/write r r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 1 1 function protect flag 0: off 1: on lcdc source clock 0: 32 khz 1: ta3out address hold (note) 0: disable 1: enable melody/alarm source clock 0: 32 khz 1: ta3out always write ?0?. 1: external clock fc oscillator driver ability 1: normal 0: weak fs oscillator driver ability 1: normal 0: weak bit symbol read/write after reset function bit symbol read/write after reset function switching the protect on/off by write to following 1st-key, 2nd-key 1st-key: emccr1 = 5ah, emccr2 = a5h in succession write 2nd-key: emccr1 = a5h, emccr2 = 5ah in succession write bit symbol enfrom endrom enprom fflag dflag pflag read/write r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 cs1a write operation flag cs2b 2g write operation flag cs2a write operation flag function cs1a area detect control 0: disable 1: enable cs2b 2g area detect control 0: disable 1: enable cs2a area detect control 0: disable 1: enable when reading 0: not written 1: written when writing 0: clear flag note1: when getting access to the logic address 000000h to 000fdfh, 001000h to 002fffh and ffe000h to ffffffh, a0 to a23 holds the previous address of external access. note2: in case restarting the oscillator in the stop oscillation state (e.g. restart the oscillator in stop mode), set emccr0 tmp91c820a 2008-02-20 91c820a-20 3.3.3 system clock controller the system clock controller generates the system clock signal (f sys ) for the cpu core and internal i/o. it contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. the register syscr1 tmp91c820a 2008-02-20 91c820a-21 example 1: setting the clock changing from high frequency (fc) to low frequency (fs). syscr0 equ 00e0h syscr1 equ 00e1h syscr2 equ 00e2h ld (syscr2), ? x11 ? ? ? ? b ; sets warm-up time to 2 16 /fs. set 6, (syscr0) ; enables low-frequency oscillation. set 2, (syscr0) ; clears and starts warm-up timer. wup: bit 2, (syscr0) ; jr nz, wup ; detects stopping of warm-up timer. set 3, (syscr1) ; changes f sys from fc to fs. res 7, (syscr0) ; disables high-frequency oscillation. x: don?t care, ? : no change fc fs counts up by fs tmp91c820a 2008-02-20 91c820a-22 example 2: setting the clock changing from low frequency (fs) to high frequency (fc). syscr0 equ 00e0h syscr1 equ 00e1h syscr2 equ 00e2h ld (syscr2), ? x10 ? ? ? ? b ; sets warm-up time to 2 14 /fc. set 7, (syscr0) ; enables high-frequency oscillation. set 2, (syscr0) ; clears and starts warm-up timer. wup: bit 2, (syscr0) ; jr nz, wup ; detects stopping of warm-up timer. res 3, (syscr1) ; changes f sys from fs to fc. res 6, (syscr0) ; disables low-frequency oscillation. x: don?t care, ? : no change counts up by f sys counts up by f osch tmp91c820a 2008-02-20 91c820a-23 (2) clock gear controller when the high-frequency clock fc is selected by setting syscr1 tmp91c820a 2008-02-20 91c820a-24 3.3.4 prescaler clock controller for the internal i/o (tmra01 to tmra23, sio0 to sio1,sbi) there is a prescaler which can divide the clock. the t clock input to the prescaler is either the clock f fph divided by 2 or the clock fc/16 divided by 2. the setting of the syscr0 tmp91c820a 2008-02-20 91c820a-25 limitation point on the use of dfm 1. it?s prohibited to execute dfm enable/disable control in the slow mode (fs) (write to dfmcr0 tmp91c820a 2008-02-20 91c820a-26 (2) change/stop control (ok) dfm use mode (f dfm ) high-frequency oscillator operation mode (f osch ) dfm stop low-frequency oscillator operation mode (fs) high-frequency oscillator stop ld (dfmcr0), 11 ? ? ? ? ? ? b ; change the system clock f dfm to f osch . ld (dfmcr0), 00 ? ? ? ? ? ? b; dfm stop. ld (syscr1), ? ? ? ? 1 ? ? ? b ; change the system clock f osch to fs. ld (syscr0), 0 ? ? ? ? ? ? ? b ; high-frequency oscillator stop. (error) dfm use mode (f dfm ) low-frequency oscillator operation mode (fs) dfm stop high-frequency oscillator stop ld (syscr1), ? ? ? ? 1 ? ? ? b ; change the system clock f dfm to fs. ld (dfmcr0), 11 ? ? ? ? ? ? b ; change the internal clock (fc) f dfm to f osch . ld (dfmcr0), 00 ? ? ? ? ? ? b; dfm stop. ld (syscr0), 0 ? ? ? ? ? ? ? b ; high-frequency oscillator stop. (ok) dfm use mode (f dfm ) set the stop mode high-frequency oscillator operation mode (f osch ) dfm stop halt (high-frequency oscillator stop) ld (syscr2), ? ? ? ? 01 ? ? b ; set the stop mode. (this command can execute before use of dfm.) ld (dfmcr0), 11 ? ? ? ? ? ? b ; change the system clock f dfm to f osch . ld (dfmcr0), 00 ? ? ? ? ? ? b; dfm stop. halt ; shift to stop mode. (error) dfm use mode (f dfm ) set the stop mode halt (high-frequency oscillator stop) ld (syscr2), ? ? ? ? 01 ? ? b ; set the stop mode. (this command can execute before use of dfm.) halt ; shift to stop mode. tmp91c820a 2008-02-20 91c820a-27 3.3.6 noise reduction circuits noise reduction circuits are built in, allowing implementation of the following features. (1) reduced drivability for high-frequency oscillator (2) reduced drivability for low-frequency oscillator (3) single drive for high-frequency oscillator (4) runaway provision with sfr protection register (5) runaway provision with rom protection register the above functions are performed by making the appropriate settings in the emccr0 to emccr3 registers. (1) reduced drivability for high-frequency oscillator (purpose) reduces noise and power for oscillator when a resonator is used. (block diagram) (setting method) the drivability of the oscillator is reduced by writing 0 to emccr0 tmp91c820a 2008-02-20 91c820a-28 (2) reduced drivability for low-frequency oscillator (purpose) reduces noise and power for oscillator when a resonator is used. (block diagram) (setting method) the drivability of the oscillator is reduced by writing 0 to the emccr0 tmp91c820a 2008-02-20 91c820a-29 (4) runaway provision with sfr protection register (purpose) provision in runaway of program by noise mixing. write operation to specified sfr is prohibited so that provision program in runaway prevents that it is it in the state which is fetch impossibility by stopping of clock, memory control register (cs/wait controller, mmu) is changed. and error handling in runaway becomes easy by intp0 interruption. specified sfr list 1. cs/wait controller b0cs, b1cs, b2cs, b3cs, bexcs, msar0, msar1, msar2, msar3, mamr0, mamr1, mamr2, mamr3 2. mmu local0/1/2/3 3. clock gear syscr0, syscr1, syscr2, emccr0, emccr3 4. dfm dfmcr0/1 (operation explanation) execute and release of protection (write operation to specified sfr) become possible by setting up a double key to emccr1 and emccr2 register. (double key) 1st-key: succession writes in 5ah at emccr1 and a5h at emccr2 2nd-key: succession writes in a5h at emccr1 and 5ah at emccr2 a state of protection can be confirmed by reading emccr0 tmp91c820a 2008-02-20 91c820a-30 (5) runaway provision with rom protection register (purpose) provision in runaway of program by noise mixing. (operation explanation) when writes operation was executed for external three kinds of rom by runaway of program, intp1 is occurred and detects runaway function. three kinds of rom is fixed as for flash rom (option program rom), data rom, program rom are as follows on the logical address memory map. 1. flash rom: address 400000h to 7fffffh 2. data rom: address 800000h to bfffffh 3. program rom: address c00000h to ffffffh for these address, admission/prohibition of detection of write operation sets it up with emccr3 tmp91c820a 2008-02-20 91c820a-31 3.3.7 standby controller (1) halt modes when the halt instruction is executed, the operating mode switches to idle2, idle1 or stop mode, depending on the contents of the syscr2 tmp91c820a 2008-02-20 91c820a-32 (2) how to release the halt mode these halt states can be released by resetti ng or requesting an interrupt. the halt release sources are determined by the combination between the states of interrupt mask register tmp91c820a 2008-02-20 91c820a-33 table 3.3.4 source of halt state clearance and halt clearance operation status of received interrupt interrupt enabled (interrupt level) (interrupt mask) interrupt disabled (interrupt level) < (interrupt mask) halt mode idle2 idle1 stop idle2 idle1 stop nmi ? ? ? * 1 ? ? ? intwdt ? ? ? ? int0 to int3 (note 1) ? ? ? * 1 * 1 intalm0 to intalm4 ? ? intta0 to intta3, inttb00 to inttb01 ? intrx0 to intrx2, tx0 to tx2 ? intss0 to intss2 ? intad ? intkey ? ? ? * 1 * 1 intrtc ? ? intsbi ? interrupt intlcd ? source of halt state clearance reset initialize lsi. ? : after clearing the halt mode, cpu starts interrupt processing. : after clearing the halt mode, cpu resumes executing starting from instruction following the halt instruction. : it can not be used to release the halt mode . ? : the priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. there is not this combination type. * 1: releasing the halt mode is executed after passing the warm-up time. note: when the halt mode is cleared by an int0 interrupt of the level mode in the interrupt enabled status, hold level h until starting interrupt processing. if level l is set before holding level l, interrupt processing is correctly started. (example releasing idle1 mode) an int0 interrupt clears the halt state when the device is in idle1 mode. address 8200h ld (pbfc), 08h ; sets pb3 to int0. 8203h ld (iimc), 00h ; selects int0 interrupt rising edge. 8206h ld (inte0ad), 06h ; sets int0 interrupt level to 6. 8209h ei 5 ; sets interrupt level to 5 for cpu. 820bh ld (syscr2), 88h ; sets halt mode to idle1 mode. 820eh halt ; halts cpu. int0 int0 interrupt routine reti 820fh ld xx, xx tmp91c820a 2008-02-20 91c820a-34 (3) operation a. idle2 mode in idle2 mode only specific internal i/o operations, as designated by the idle2 setting register, can take place. instruction execution by the cpu stops. figure 3.3.6 illustrates an example of the timing for clearance of the idle2 mode halt state by an interrupt. x1 a0 to a23 d0 to d15 data data idle2 mode interrupt fo r release rd wr figure 3.3.6 timing chart for idle2 mode halt state cleared by interrupt b. idle1 mode in idle1 mode, only the internal oscillator and the rtc, mld continue to operate. the system clock in the mcu stops. the pin status in the idle1 mode is depended on setting the register syscr2 tmp91c820a 2008-02-20 91c820a-35 c. stop mode when stop mode is selected, all internal circuits stop, including the internal oscillator pin status in stop mode depends on the settings in the syscr2 tmp91c820a 2008-02-20 91c820a-36 (setting example) the stop mode is entered when the low frequency operates, and high frequency operates after releasing due to nmi. address syscr0 equ 00e0h syscr1 equ 00e1h syscr2 equ 00e2h 8ffdh ld (syscr1), 08h ; f sys = fs/2. 9000h ld (syscr2), ? x1001x1b ; sets warm-up time to 2 14 /f osch . 9002h ld (syscr0), 011000 ? ? b ; operates high-frequency after released. 9005h halt nmi 9006h ld xx, xx reti ? : no change note: when different m odes are used before and after stop mode as the above mentioned, there is possible to release the halt mode without changing the operation mode by acceptance of the halt release interrupt request during execution of halt instruction (during 6 state). in the system which accepts the interrupts during execution halt instruction, set the same operation mode before and after the stop mode. clears and starts hit warm-up timer (high frequency) end nmi interrupt routine tmp91c820a 2008-02-20 91c820a-37 table 3.3.6 input buffer state table (1/2) input buffer state in halt mode(idle1/stop) when the cpu is operating in halt mode (idle2) condition a (note) condition b (note) port name input function name during reset when used as function pin when used as input port when used as function pin when used as input port when used as function pin when used as input port when used as function pin when used as input port p00-p07 d0-d7 off on upon port read p10-p17 d8-d15 8bit start: off 16bit start: on built-in rom start: on on upon external read on upon external read of lcdc off off p20-p27 ? p30-p37 ? p40-p47 ? 8bit start: off 16bit start: off built-in rom start: on pz2 (*1) ? pz3 (*1) ? ? ? off ? ? off p56 (*1) wait p70 sck, optrx0 p71 sda off p72 si, scl on on on on p73 ? p74 ? p75 ? ? ? ? ? p76 msk on on on off on p77 ? on on on on p80 (*2) ? p81 (*2) ? p82 (*2) ? ? ? ? ? p83 (*2) adtrg on on on on p84 (*2) ? p85 (*2) ? p86 (*2) ? p87 (*2) ? off ? on upon port read ? off ? off ? off p90 (*1) ki0 p91 (*1) ki1 p92 (*1) ki2 p93 (*1) ki3 p94 (*1) ki4 p95 (*1) ki5 p96 (*1) ki6 p97 (*1) ki7 on on pb0 ta0in pb1 rxd2 off off pb3 int0 on on on pb4 int1 pb5 int2 pb6 int3 on on on on off on off on off tmp91c820a 2008-02-20 91c820a-38 input buffer state table (2/2) input buffer state in halt mode(idle1/stop) when the cpu is operating in halt mode (idle2) condition a (note) condition b (note) port name input function name during reset when used as function pin when used as input port when used as function pin when used as input port when used as function pin when used as input port when used as function pin when used as input port pb0 ta0in pb1 rxd2 off off pb3 int0 on on on pb4 int1 pb5 int2 pb6 int3 on on off on on off pc0 ? ? ? ? ? pc1 rxd0 pc2 sclk0, cts0 on on off on pc3 ? ? ? ? ? pc4 rxd1 pc5 sclk1, cts1 on on on off on on pe0-pe7 ? ? on ? off ? off ? off nmi/ps ? reset (*1) ? am0, am1 ? on ? on ? x1, xt1 ? on on ? on ? idle1: on, stop: off *1: port having a pull-up/pull-down resistor. on: the buffer is always turned on. a current flows the input buffer if the input pin is not driven. *2: ain input does not cause a current to flow through the buffer. off: the buffer is always turned off. ? : no applicable note: condition a/b are as follows. syscr2 register setting halt mode tmp91c820a 2008-02-20 91c820a-39 table 3.3.7 output buffer state table (1/2) output buffer state in halt mode (idle1/stop) when the cpu is operating in halt mode (idle2) condition a (note) condition b (note) port name output function name during reset when used as function pin when used as output port when used as function pin when used as output port when used as function pin when used as output port when used as function pin when used as output port p00-p07 d0-d7 p10-p17 d8-d15 off on upon external read off off p20-p27 a16-a23 p30-p37 a8-a15 p40-p47 a0-a7 8bit start: on 16bit start: on built-in rom start: off pz0 rd pz1 wr on pz2 hwr pz3 r/w, srwe on on off on p56 ? off (*1) ? ? ? ? p60 cs0 p61 cs1, sdcs p62 cs2, cs2a p63 cs3 p64 ea24, cs2b p65 ea25, cs2c p66 cs2d, srlb p67 cs2e, srub on p70 sck p71 so, sda, opttx0 p72 scl p73 cs2f p74 cs2g p75 csexa on on off on p76 ? ? ? ? ? p77 veeclk pa0 ko0 pa1 ko1 pa2 ko2 pa3 ko3 pa4 ko4 pa5 ko5 pa6 ko6 pa7 ko7 off on on on on off off on on tmp91c820a 2008-02-20 91c820a-40 output buffer state table (1/2) output buffer state in halt mode (idle1/stop) when the cpu is operating in halt mode (idle2) condition a (note) condition b (note) port name output function name during reset when used as function pin when used as output port when used as function pin when used as output port when used as function pin when used as output port when used as function pin when used as output port pb0 txd2 pb1 ta1out on on off on pb3 ? pb4 ? ? ? ? ? pb5 ta3out pb6 tb0out0 pc0 txd0 on on off on pc1 ? ? ? ? ? pc2 sclk0 pc3 txd1 on on off on pc4 ? ? ? ? ? pc5 sclk1 off pd0 d1bscp pd1 d2blp pd2 d3bfr pd3 dlebcd pd4 doffb pd6 alarm, mldalm pd7 mldalm on pe0-7 ld0-ld7 off pf0 sdras pf1 sdcas pf2 sdwe pf3 sdldqm pf4 sdudqm off pf5 sdcke on in self refresh cycle pf6 sdclk on on off off on on x2, xt2 ? on on ? on ? idle1: on, stop: output ?h? level on: the buffer is always turned on. off: the buffer is always turned off. ? : no applicable note: condition a/b are as follows. syscr2 register setting halt mode tmp91c820a 2008-02-20 91c820a-41 3.4 interrupts interrupts are controlled by the cpu interrupt mask register sr tmp91c820a 2008-02-20 91c820a-42 figure 3.4.1 interrupt and micro dma processing sequence general-purpose interrupt processing interrupt specified by micro dma start vector? yes interrupt processing push pc push sr sr tmp91c820a 2008-02-20 91c820a-43 3.4.1 general-purpose interrupt processing when the cpu accepts an interrupt, it usua lly performs the following sequence of operations. however, in the case of software interrupts and illegal instruction interrupts generated by the cpu, the cpu skips steps a and c and executes only steps b, d and e. a. the cpu reads the interrupt vector from the interrupt controller. if there are simultaneous interrupts set to same level, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request. (the default priority is already fixed for each interrupt: the smaller the vector value, the higher the priority level.) b. the cpu pushes the program counter (pc) and status register (sr) onto the top of the stack (pointed to by xsp). c. the cpu sets the value of the cpu?s in terrupt mask register tmp91c820a 2008-02-20 91c820a-44 table 3.4.1 tmp91c820a interrupt vectors and micro dma start vectors default priority type interrupt source and source of micro dma request vector value (v) vector reference address micro dma start vector 1 ?reset? or ?swi0? instruction 0000h ffff00h ? 2 ?swi1? instruction 0004h ffff04h ? 3 intundef: illegal instruction or ?swi2? instruction 0008h ffff08h ? 4 ?swi3? instruction 000ch ffff0ch ? 5 ?swi4? instruction 0010h ffff10h ? 6 ?swi5? instruction 0014h ffff14h ? 7 ?swi6? instruction 0018h ffff18h ? 8 ?swi7? instruction 001ch ffff1ch ? 9 nmi pin 0020h ffff20h ? 10 non- maskable intwd: watchdog timer 0024h ffff24h ? ? (micro dma) ? ? ? 11 int0 pin 0028h ffff28h 0ah 12 int1 pin 002ch ffff2ch 0bh 13 int2 pin 0030h ffff30h 0ch 14 int3 pin 0034h ffff34h 0dh 15 intalm0: alm0 (8 khz) 0038h ffff38h 0eh 16 intalm1: alm1 (512 hz) 003ch ffff3ch 0fh 17 intalm2: alm2 (64 hz) 0040h ffff40h 10h 18 intalm3: alm3 (2 hz) 0044h ffff44h 11h 19 intalm4: alm4 (1 hz) 0048h ffff48h 12h 20 intta0: 8-bit timer 0 004ch ffff4ch 13h 21 intta1: 8-bit timer 1 0050h ffff50h 14h 22 intta2: 8-bit timer 2 0054h ffff54h 15h 23 intta3: 8-bit timer 3 0058h ffff58h 16h 24 intrx0: serial receives (channel 0) 005ch ffff5ch 17h 25 inttx0: serial transmission (channel 0) 0060h ffff60h 18h 26 intrx1: serial receives (channel 1) 0064h ffff64h 19h 27 inttx1: serial transmission (channel 1) 0068h ffff68h 1ah 28 intad: ad conversion end 006ch ffff6ch 1bh 29 intkey: key-on wakeup 0070h ffff70h 1ch 30 intrtc: rtc (alarm interrupt) 0074h ffff74h 1dh 31 intsbi: sbi interrupt 0078h ffff78h 1eh 32 intlcd: lcdc/lp pin 007ch ffff7ch 1fh 33 intp0: protect 0 (wr to special sfr) 0080h ffff80h 20h 34 intp1: protect 1 (wr to rom) 0084h ffff84h 21h 35 inttc0: micro dma end (channel 0) 0088h ffff88h ? 36 inttc1: micro dma end (channel 1) 008ch ffff8ch ? 37 inttc2: micro dma end (channel 2) 0090h ffff90h ? 38 inttc3: micro dma end (channel 3) 0094h ffff94h ? 39 reserved ? ? ? 40 reserved ? ? ? 41 reserved ? ? ? 42 intrx2: serial receive (channel 2) 00a4h ffffa4h 29h 43 inttx2: serial transmission (channel 2) 00a8h ffffa8h 2ah 44 inttb00: 16-bit timer 0 (tb0rg0) 00ach ffffach 2bh 45 inttb01: 16-bit timer 1 (tb0rg1) 00b0h ffffb0h 2ch maskable (reserved) to (reserved) 00b4h to 00fch ffffb4h to fffffch ? to ? tmp91c820a 2008-02-20 91c820a-45 3.4.2 micro dma processing in addition to general-purpose interrupt processing, the tmp91c 820a supprots a micro dma function. interrupt requests set by micr o dma perform micro dma processing at the highest priority level for maskable interrupts (l evel 6), regardless of the priority level of the particular interrupt source. because the micro dma function has been im plemented with the cooperative operation of cpu, when cpu is a state of standby by halt instruction, the requirement of micro dma will be ignored (pending). (1) micro dma operation when an interrupt request is generated by an interrupt source specified by the micro dma start vector register, the micro dma triggers a micro dma request to the cpu at interrupt priority level 6 and starts processing the request. the four micro dma channels allow micro dma processing to be set for up to four types of interrupts at any one time. when micro dma is accepted, the interrupt request flip-flop assigned to that channel is cleared. the data are automatically transferred from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented by 1. if the decr emented counter reads other than 0, dma processing ends with no change in the valu e of the micro dma start vector register. if the decremented reading is 0, the micro dma transfer end interrupt (inttc0 to inttc3) passes from the cpu to the interru pt controller. in addition, the micro dma start vector register is cleared to 0, the next micro dma is disabled and micro dma processing completes. if a micro dma request is set for more than one channel at a time, the priority is not based on the interrupt priority level but on the channel number: the smaller the channel number the higher the priority (channel 0 (high) channel 3 (low)). if an interrupt request is triggered for the interrupt source in use during the interval between the clearing of the micro dma start vector and the next setting, general-purpose interrupt processing executes at the interrupt level set. therefore, if only using the interrupt for starting the micro dma (not using the interrupts as a general-purpose interrupt), first set the in terrupts level to 0 (interrupt requests disabled). if using micro dma and general-purpose interrupts together as described above, first set the level of the interrupt used to start micro dma processing lower than all the other interrupt levels. in this case, the cause of general interrupt is limited to the edge interrupt. (note) as with other maskable interrupts, the priority of the micro dma transfer end interrupts is determined by the interrupt level and by the default priority. note: if the priority level of micro dma is set higher than that of other interrupts, cpu operates as follows. in case intxxx interrupt is generated first and t hen intyyy interrup t is generated between checking ?interrupt specified by micro dma start vector? (in the figure 3.4.1) and reading interrupt vector with setting below. the vector shifts to that of intyyy at the time. this is because the priority level of intyyy is higher than that of intxxx. in the interrupt routine, cpu reads the vector of intyyy because cheking of micro dma has finished. and intyyy is generated regardless of transfer counter of micro dma. intxxx: level 1 without micro dma intyyy: level 6 with micro dma tmp91c820a 2008-02-20 91c820a-46 while the register for setting the transfer source/transfer destination addresses is a 32-bit control register, this register can only effectively output 24-bit addresses. accordingly, micro dma can access 16 mbytes (the upper 8 bits of the 32 bits are not valid). three micro dma transfer modes are supported: 1-byte transfer, 2-byte (one-word) transfer, and 4-byte transfer. after a transfer in any mode, the transfer source/destination addresses are incremented, decremented, or remain unchanged. this simplifies the transfer of data from i/o to memory, from memory to i/o, and from i/o to i/o. for details of the transfer modes, see 3.4.2 (4) ?detailed description of the transfer mode register?. as the transfer counter is a 16-bit counter, micro dma processing can be set for up to 65536 times per interrupt source. (the micro dma processing count is maximized when the transfer counter initial value is set to 0000h.) micro dma processing can be started by the 31 interrupts shown in the micro dma start vectors of table 3.4.1 and by the micro dma soft start, making a total of 32 interrupts. figure 3.4.2 shows the word transfer micro dma cycle in transfer destination address inc mode (except for counter mode, the same as for other modes). (the conditions for this cycle are based on an external 16-bit bus, 0 waits, transfer source/transfer destination addresses both even-numberd values). output input transfer destination address one state d0 to d15 x1 a0 to a23 dm1 dm2 dm3 dm4 dm5 dm6 dm7 dm8 (note 1) (note 2) rd wr / hwr transfer source address figure 3.4.2 timing for micro dma cycle states 1 to 3: instruction fetch cycle (gets next address code). if three or more instruction codes are inserted in the instruction queue buffer, this cycle becomes a dummy cycle. states 4 to 5 : micro dma read cycle. state 6 : dummy cycle (the address bus remains unchanged from state 5). states 7 to 8 : micro dma write cycle. note 1: if the source address area is an 8-bit bus, it is incremented by two states. if the source address area is a 16-bit bus and the address starts from an odd number, it is incremented by two states. note 2: if the destination address area is an 8-bit bus, it is incremented by two states. if the destination address area is a 16-bit bus and the address starts from an odd number, it is incremented by two states. tmp91c820a 2008-02-20 91c820a-47 (2) soft start function in addition to starting the micro dma function by interrupts, tmp91c820a includes a micro dma software start function that starts micro dma on the generation of the write cycle to the dmar register. writing 1 to each bit of dmar register causes micro dma once (if write ?0? to each bit, micro dma doesn?t operate). at the end of transfer, the corresponding bit of the dmar register which support the end ch annel are automatically cleared to 0. only one channel can be set for dma request at once. (do not write 1 to plural bits) when writing again 1 to the dmar regist er, check whether the bit is 0 before writing 1. if read ?1?, micro dma transfer isn?t started yet. when a burst is specified by dmab register, data is continuously transferred until the value in the micro dma transfer counter is 0 after start up of the micro dma. if execute soft start during micro dma transfer by interrupt source, micro dma transfer counter doesn?t change. don?t use read-modif y-write instruction to avoid writing to other bits by mistake. symbol name address 7 6 5 4 3 2 1 0 dma request dmar3 dmar2 dmar1 dmar0 r/w dmar dma request register 89h (prohibit rmw) 0 0 0 0 (3) transfer control registers the transfer source address and the transfer destination address are set in the following registers. an instruction of the form ?ldc cr, r? can be used to set these registers. channel 0 dmas0 dma source address register 0. dmad0 dma destination address register 0. dmac0 dma counter register 0. dmam0 dma mode register 0. channel 3 dmas3 dma source address register 3. dmad3 dma destination address register 3. dmac3 dma counter register 3. dmam3 dma mode register 3. 8 bits 16 bits 32 bits tmp91c820a 2008-02-20 91c820a-48 (4) detailed description of the transfer mode register 8 bits 0 0 0 mode number of transfer bytes mode description number of execution states ( * ) minimum execution time at fc = 36 mhz 000 (fixed) 000 00 byte transfer 8 states 444 ns 01 word transfer 10 4-byte transfer transfer destination address inc mode ................................................. i/o to memory (dmadn + ) (dmasn) dmacn dmacn ? 1 if dmacn = 0, then inttcn is generated. 12 sates 667 ns 001 00 byte transfer 8 states 444 ns 01 word transfer 10 4-byte transfer transfer destination address dec mode ................................................. i/o to memory (dmadn ? ) (dmasn) dmacn dmacn ? 1 if dmacn = 0, then inttcn is generated. 12 sates 667 ns 010 00 byte transfer 8 states 444 ns 01 word transfer 10 4-byte transfer transfer source address inc mode ................................................. memory to i/o (dmadn) (dmasn + ) dmacn dmacn ? 1 if dmacn = 0, then inttcn is generated. 12 sates 667 ns 011 00 byte transfer 8 states 444 ns 01 word transfer 10 4-byte transfer transfer source address dec mode ................................................. memory to i/o (dmadn) (dmasn ? ) dmacn dmacn ? 1 if dmacn = 0, then inttcn is generated. 12 sates 667 ns 100 00 byte transfer 8 states 444 ns 01 word transfer 10 4-byte transfer fixed address mode ......................................................... i/o to i/o (dmadn) (dmasn ? ) dmacn dmacn ? 1 if dmacn = 0, then inttcn is generated. 12 sates 667 ns 101 00 counter mode .....................for counting number of times interrupt is generated. dmasn dmasn + 1 dmacn dmacn ? 1 if dmacn = 0, then inttcn is generated. 5 sates 278 ns note: when setting a value in this register, write 0 to the upper three bits. dmam0 to dmam3 ( * ) for external 16-bit bus, 0 waits, word/4-byte transfer mode, transfer source/transfer destination addresses both have even-numbered values. note: n: corresponding micro dma channels 0 to 3. dmadn + /dmasn + : post increment (increments register value after transfer). dmadn ? /dmasn ? : post decrement (decrements register value after transfer). the i/os in the table mean fixed address; memory means increment and decrement addresses. do not use undefined code, that is, codes other than those listed above for the transfer mode register. tmp91c820a 2008-02-20 91c820a-49 3.4.3 interrupt controller operation the block diagram in figure 3.4.3 shows the interrupt circuits. the left-hand side of the diagram shows the interrupt controller circuit. the right-hand side shows the cpu interrupt request signal circuit and the halt release circuit. for each of the 36 interrupt channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro dma start vector register. the interrupt request flag latches interrupt requests from the peripherals. the flag is cleared to zero in the following cases: when reset occurs, when the cpu reads the channel vector of an interrupt it has received, when the cpu receives a micro dma request (when micro dma is set), when the micro dma burst transfer is terminated, and when an instruction that clears the interrupt for that channel is executed (by writing 0 to the clear bit in the interrupt priority setting register). an interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., inte0ad or inte12). six interrupt priorities levels (1 to 6) are provided. setting an interrupt source?s priority level to 0 (or 7) disables interrupt requests from that source. the priority of non-maskable interrupts (nmi pin interrupts and watchdog timer interrupts) is fixed at 7. if interrupt request with the same level are generated at the same time, the default priority (the interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. the 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. the interrupt controller sends the interrupt request with the highest priority among the simulateous interrupts and its vector address to the cpu. the cpu compares the priority value tmp91c820a 2008-02-20 91c820a-50 interrupt request signal to cpu if iff = 7 then 0 micro dma start vector setting register reserved intrx2 inttx2 inttb00 inttb01 v = a4h v = a8h v = ach v = b0h soft start 6 inttc0 during idle1 36 3 3 3 1 6 1 7 2 2 4 6 34 4 input or int0 to int3, intkey, intrtc, intalm micro dma channel priority encoder priority encoder dma0v dma1v dma2v dma3v reset interrupt request f/f reset decoder reset priority setting register v = 20h v = 24h interrupt controller cpu s q r v = 28h v = 2ch v = 30h v = 34h v = 38h v = 3ch v = 40h v = 44h v = 48h v = 4ch d q clr y1 y2 y3 y4 y5 y6 a b c dn dn + 1 dn + 2 interrupt request f/f interrupt vector read micro dma acknowledge interrupt request f/f dn + 3 a b c interrupt vector read d2 d3 d4 d5 d6 d7 selector s q r 0 1 2 3 a b d0 d1 interrupt vector read interrupt mask f/f micro dma request halt release nmi if intrq2 to 0 iff2 to 0 then 1. intrq2 to intrq0 iff2:0 interrupt level detect reset ei1 to 7 di interrupt request signal during stop micro dma channel specification reset nmi intwd int0 int1 int2 int3 intalm0 intalm1 intalm2 intalm3 intalm4 intta0 s interrupt vector generator highest priority interrupt level select 1 2 3 4 5 6 7 d5 d4 d3 d2 d1 d0 d q clr figure 3.4.3 block diagram of interrupt controller tmp91c820a 2008-02-20 91c820a-51 (1) interrupt level setting registers symbol name address 7 6 5 4 3 2 1 0 intad int0 iadc iadm2 iadm1 iadm0 i0c i0m2 i0m1 i0m0 r r/w r r/w inte0ad int0 and intad enable 90h 0 0 0 0 0 0 0 0 int2 int1 i2c i2m2 i2m1 i2m0 i1c i1m2 i1m1 i1m0 r r/w r r/w inte12 int1 and int2 enable 91h 0 0 0 0 0 0 0 0 intalm4 int3 ia4c ia4m2 ia4m1 ia4m0 i3c i3m2 i3m1 i3m0 r r/w r r/w inte3alm4 int3 and intalm4 enable 92h 0 0 0 0 0 0 0 0 intalm1 intalm0 ia1c ia1m2 ia1m1 ia1m0 ia0c ia0m2 ia0m1 ia0m0 r r/w r r/w intealm01 intalm0 and intalm1 enable 93h 0 0 0 0 0 0 0 0 intalm3 intalm2 ia3c ia3m2 ia3m1 ia3m0 ia2c ia2m2 ia2m1 ia2m0 r r/w r r/w intealm23 intalm2 and intalm3 enable 94h 0 0 0 0 0 0 0 0 intta1 (tmra1) intta0 (tmra0) ita1c ita1m2 ita1m1 ita1m0 ita0c ita0m2 ita0m1 ita0m0 r r/w r r/w inteta01 intta0 and intta1 enable 95h 0 0 0 0 0 0 0 0 intta3 (tmra3) intta2 (tmra2) ita3c ita3m2 ita3m1 ita3m0 ita2c ita2m2 ita2m1 ita2m0 r r/w r r/w inteta23 intta2 and intta3 enable 96h 0 0 0 0 0 0 0 0 intkey intrtc ikc ikm2 ikm1 ikm0 irc irm2 irm1 irm0 r r/w r r/w intertckey intrtc and intkey enable 97h 0 0 0 0 0 0 0 0 inttx0 intrx0 itx0c itx0m2 itx0m1 itx0m0 irx0c irx0m2 irx0m1 irx0m0 r r/w r r/w intes0 interrupt enable serial 0 98h 0 0 0 0 0 0 0 0 interrupt request flag lxxm2 lxxm1 lxxm0 function (write) 0 0 0 disables interrupt requests 0 0 1 sets interrupt priority level to 1 0 1 0 sets interrupt priority level to 2 0 1 1 sets interrupt priority level to 3 1 0 0 sets interrupt priority level to 4 1 0 1 sets interrupt priority level to 5 1 1 0 sets interrupt priority level to 6 1 1 1 disables interrupt requests tmp91c820a 2008-02-20 91c820a-52 symbol name address 7 6 5 4 3 2 1 0 inttx1 intrx1 itxt1c itx1m2 itx1m1 itx1m0 irx1c irx1m2 irx1m1 irx1m0 r r/w r r/w intes1 intrx1 and inttx1 enable 99h 0 0 0 0 0 0 0 0 intlcd intsbi ilcd1c ilcdm2 ilcdm1 ilcdm0 isbic isbim2 isbim1 isbim0 r r/w r r/w intes2lcd intsbi and intlcd enable 9ah 0 0 0 0 0 0 0 0 inttc1 inttc0 itc1c itc1m2 itc1m1 itc1m0 itc0c itc0m2 itc0m1 itc0m0 r r/w r r/w intetc01 inttc0 and inttc1 enable 9bh 0 0 0 0 0 0 0 0 inttc3 inttc2 itc3c itc3m2 itc3m1 itc3m0 itc2c itc2m2 itc2m1 itc2m0 r r/w r r/w intetc23 inttc2 and inttc3 enable 9ch 0 0 0 0 0 0 0 0 intp1 intp0 ip1c ip1m2 ip1m1 ip1m0 ip0c ip0m2 ip0m1 ip0m0 r r/w r r/w intep01 intp0 and intp1 enable 9dh 0 0 0 0 0 0 0 0 inttx2 intrx2 itx2c itx2m2 itx2m1 itx2m0 irx2c irx2m2 irx2m1 irx2m0 r r/w r r/w intes3 intrx2 and inttx2 enable a0h 0 0 0 0 0 0 0 0 inttb01 inttb00 itb1c itb1m2 itb1m1 itb1m0 itb0c itb0m2 itb0m1 itb0m0 r r/w r r/w intetb0 inttb00 and inttb01 enable a1h 0 0 0 0 0 0 0 0 interrupt request flag lxxm2 lxxm1 lxxm0 function (write) 0 0 0 disables interrupt requests 0 0 1 sets interrupt priority level to 1 0 1 0 sets interrupt priority level to 2 0 1 1 sets interrupt priority level to 3 1 0 0 sets interrupt priority level to 4 1 0 1 sets interrupt priority level to 5 1 1 0 sets interrupt priority level to 6 1 1 1 disables interrupt requests tmp91c820a 2008-02-20 91c820a-53 (2) external interrupt control symbol name address 7 6 5 4 3 2 1 0 ? ? i3edge i2edge i1edge i0edge i0le nmiree w 0 0 0 0 0 0 0 0 iimc interrupt input mode control 8ch (prohibit rmw) always write ?0?. always write ?0?. int3edge 0: rising 1: falling int2edge 0: rising 1: falling int1edge 0: rising 1: falling int0edge 0: rising 1: falling 0: int0 edge mode 1: int0 level mode 1: operates even on rising/ falling edge of nmi int0 level enable 0 edge detect int 1 h level int nmi rising edge enable 0 int request generation at falling edge 1 int request generation at rising/falling edge (3) interrupt request flag clear register the interrupt request flag is cleared by writing the appropriate micro dma start vector, as given in table 3.4.1 to the register intclr. for example, to clear the interrupt flag int0, perform the following register operation after execution of the di instruction. intclr 0ah: clears interrupt request flag int0. symbol name address 7 6 5 4 3 2 1 0 clrv5 clrv4 clrv3 clrv2 clrv1 clrv0 w 0 0 0 0 0 0 intclr interrupt clear control 88h (prohibit rmw) interrupt vector (4) micro dma start vector registers this register assigns micro dma processing to an interrupt source. the interrupt source with a micro dma start vector that matches the vector set in this register is assigned as the micro dma start source. wh en the micro dma transfer counter value reaches zero, the micro dma transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro dma start vector register is cleared, and the micro dma start source for the channel is cleared. therefore, to continue micro dma processing, set the micro dma start vector re gister again during the processing of the micro dma transfer end interrupt. if the same vector is set in the micro dm a start vector registers of more than one channel; the channel with the lowest number has a higher priority. accordingly, if the same vector is set in the micro dma start vector registers of two channels, the interrupt generated in the channel with the lower number is executed until micro dma transfer is complete. if the micro dma start vector for this channel is not set again, the next micro dma is started for the channel with the higher number. (micro dma chaining.) tmp91c820a 2008-02-20 91c820a-54 symbol name address 7 6 5 4 3 2 1 0 dma0 start vector dma0v5 dma0v4 dma0v3 dma0v2 dma0v1 dma0v0 r/w dma0v dma0 start vector 80h 0 0 0 0 0 0 dma1 start vector dma1v5 dma1v4 dma1v3 dma1v2 dma1v1 dma1v0 r/w dma1v dma1 start vector 81h 0 0 0 0 0 0 dma2 start vector dma2v5 dma2v4 dma2v3 dma2v2 dma2v1 dma2v0 r/w dma2v dma2 start vector 82h 0 0 0 0 0 0 dma3 start vector dma3v5 dma3v4 dma3v3 dma3v2 dma3v1 dma3v0 r/w dma3v dma3 start vector 83h 0 0 0 0 0 0 (5) micro dma burst specification specifying the micro dma burst continues the micro dma transfer until the transfer counter register reaches zero after micro dm a start. setting a bit which corresponds to the micro dma channel of the dmab registers mentioned below to 1 specifies a burst. symbol name address 7 6 5 4 3 2 1 0 dmar3 dmar2 dmar1 dmar0 r/w r/w r/w r/w 0 0 0 0 dmar dma software request register 89h (prohibit rmw) 1: dma software request dmab3 dmab2 dmab1 dmab0 r/w 0 0 0 0 dmab dma burst register 8ah 1: dma burst request tmp91c820a 2008-02-20 91c820a-55 (6) notes the instruction execution unit and the bus interface unit of this cpu operate independently. therefore, immediately before an interrupt is generated, if the cpu fetches an instruction that clears the corresponding interrupt request flag, the cpu may execute the instruction that clears the interrupt request flag between accepting and reading the interrupt vector. in this case, the cpu reads the default vector 0008h and reads the interrupt vector address ffff08h. to avoid the above problem, place instructions that clear interrupt request flags after a di instruction. and in the case of setting an interrupt enable again by ei instruction after the execution of clearing instruction, execute ei instruction after clearing and more than 1 instructions (ex. ?nop? 1 time). if placed ei instruction without waiting nop instruction after execution of clearing instruction, interrupt will be enable before request flag is cleared. in the case of changing the value of the interrupt mask register tmp91c820a 2008-02-20 91c820a-56 3.5 port functions the tmp91c820a features 126-bit settings which relate to the various i/o ports. as well as general-purpose i/o port functionality, the port pins also have i/o functions which relate to the built-in cpu and internal i/os. table 3.5.1 and table 3.5.2 list the functions of each port pin. table 3.5.3, table 3.5.4 and table 3.5.5 list i/o registers and their specifications. table 3.5.1 port functions (1/2) (r: pu = with programmable pull-up resistor) (u = with pull-up resistor) port name pin name number of pins direction r direction setting unit pin name for built-in function port 0 p00 to p07 8 i/o ? bit d0 to d7 port 1 p10 to p17 8 i/o ? bit d8 to d15 port 2 p20 to p27 8 i/o ? bit a16 to a23 port 3 p30 to p37 8 i/o ? bit a8 to a15 port 4 p40 to p47 8 i/o ? bit a0 to a7 port z pz0 1 output ? bit rd pz1 1 output ? bit wr pz2 1 i/o pu bit hwr pz3 1 i/o pu bit w / r , srwe port 5 p56 1 i/o pu bit wait port 6 p60 1 output ? (fixed) cs0 p61 1 output ? (fixed) cs1 , sdcs p62 1 output ? (fixed) cs2 , cs2a p63 1 output ? (fixed) cs3 p64 1 output ? (fixed) ea24, cs2b p65 1 output ? (fixed) ea25, cs2c p66 1 output ? (fixed) cs2c , srlb p67 1 output ? (fixed) cs2e , srub port 7 p70 1 i/o ? bit sck, optrx0 p71 1 i/o ? bit so, sda , opttx0 p72 1 i/o ? bit si/scl p73 1 i/o ? bit cs2f p74 1 i/o ? bit cs2g p75 1 i/o ? bit csexa p76 1 i/o ? bit msk p77 1 i/o ? bit veeclk port 8 p80 to p87 8 input ? (fixed) an0 to an7, adtrg (p83) port 9 p90 to p97 8 input u (fixed) ki0 to ki7 port a pa0 to pa7 8 output ? (fixed) ko0 to ko7 port b pb0 1 i/o ? bit ta0in, txd2 pb1 1 i/o ? bit ta1out, rxd2 pb3 1 i/o ? bit int0 pb4 1 i/o ? bit int1 pb5 1 i/o ? bit int2, ta3out pb6 1 i/o ? bit int3, tb0out0 port c pc0 1 i/o ? bit txd0 pc1 1 i/o ? bit rxd0 pc2 1 i/o ? bit sclk0, cts0 pc3 1 i/o ? bit txd1 pc4 1 i/o ? bit rxd1 pc5 1 i/o ? bit sclk1, cts1 tmp91c820a 2008-02-20 91c820a-57 table 3.5.2 port functions (2/2) (r: pu = with programmable pull-up resistor) (u = with pull-up resistor) port name pin name number of pins direction r direction setting unit pin name for built-in function port d pd0 1 output ? (fixed) d1bscp pd1 1 output ? (fixed) d2blp pd2 1 output ? (fixed) d3bfr pd3 1 output ? (fixed) dlebcd pd4 1 output ? (fixed) doffb pd6 1 output ? (fixed) alarm , mldalm pd7 1 output ? (fixed) mldalm port e pd0 to pd7 8 i/o ? bit ld0 to ld7 port f pf0 1 output ? (fixed) sdras pf1 1 output ? (fixed) sdcas pf2 1 output ? (fixed) sdwe pf3 1 output ? (fixed) sdldqm pf4 1 output ? (fixed) sdudqm pf5 1 output ? (fixed) sdcke pf6 1 output ? (fixed) sdclk pf7 1 output ? (fixed) tmp91c820a 2008-02-20 91c820a-58 table 3.5.3 i/o registers and specifications (1/3) i/o register port pin name specification pn pncr pnfc pnfc2 input port x 0 output port x 1 port 0 p00 to p07 d0 to d7 bus x x none none input port x 0 0 output port x 1 0 port 1 p10 to p17 d8 to d15 bus x 0 1 none input port x 0 x output port x 1 0 port 2 p20 to p27 a16 to a23 output x 1 1 none input port x 0 x output port x 1 0 port 3 p30 to p47 a8 to a15 output x 1 1 none input port x 0 x output port x 1 0 port 4 p30 to p47 a0 to a7 output x 1 1 none output port x 0 pz0 rd output x 1 output port x 0 pz1 wr output x none 1 input port (without pu) 0 0 0 input port (with pu) 1 0 0 pz2, pz3 output port x 1 0 pz2 hwr output x 1 1 r/w output x 0 1 port z pz3 srwe output x 1 1 input port (without pu) 0 0 input port (with pu) 1 0 output port x 1 wait input (without pu) 0 0 port 5 p56 wait input (with pu) 1 0 none none p60 to p67 output port x 0 0 p60 cs0 output x 1 0 cs1 output x 1 0 p61 sdcs output x x 1 cs2 output x 1 0 p62 cs2a output x x 1 p63 cs3 output x 1 0 ea24 output x 1 0 p64 cs2b output x x 1 ea25 output x 1 0 p65 cs2c output x x 1 srlb output x 1 0 p66 cs2d output x x 1 srub output x 1 0 port 6 p67 cs2e output x none x 1 x: don?t care tmp91c820a 2008-02-20 91c820a-59 table 3.5.4 i/o registers and specifications (2/3) i/o register port pin name specification pn pncr pnfc pnfc2 input port x 0 0 0 p70 to p77 output port x 1 0 0 sck input x 0 0 0 sck output x 1 1 0 p70 optrx0 input (note 1) 1 0 x 1 sda input x 0 0 0 sda output (note 2) x 1 1 0 so output x 1 1 0 p71 opttx0 output (note 1) 1 1 x 1 si input x 0 0 scl input x 0 0 p72 scl output (note 2) x 1 1 none p73 cs2f output x 1 x 1 p74 cs2g output x 1 x 1 p75 csexa output x 1 x 1 p76 msk input (note 3) x 0 0 0 port 7 p77 veeclk output x 1 1 0 input port x p80 to p87 an0 to an7 input (note 4) x port 8 p83 adtrg input (note 5) x none input port x 0 port 9 p90 to p97 ki0 to ki7 input x none 1 output port x 0 ko0 to ko7 output (cmos) x 0 port a pa0 to pa7 ko0 to ko7 output (open drain) x none 1 none input port x 0 0 pb0 to pb6 output port x 1 0 ta0in input x 0 0 pb0 txd2 output (note 1) x 1 1 ta1out output x 1 1 pb1 rxd2 input (note 1) x 0 0 pb3 int0 input x 0 1 pb4 int1 input x 0 1 int2 input 0 0 1 pb5 ta3out 1 1 1 int3 input 0 0 1 port b pb6 tb0out0 1 1 1 none x: don?t care tmp91c820a 2008-02-20 91c820a-60 table 3.5.5 i/o registers and specifications (3/3) i/o register port pin name specification pn pncr pnfc pnfc2 input port x 0 0 pc0 to pc5 output port x 1 0 pc0 txd0 output (note 1) 1 1 1 pc1 rxd0 input (note 1, 6) 1 0 none sclk0 input (note 1) 1 0 0 sclk0 output (note 1) 1 1 1 pc2 cts0 input (note 1) 1 0 0 pc3 txd1 output (note 1) 1 1 1 pc4 rxd1 input (note 1) 1 0 none sclk1 input (note 1) 1 0 0 sclk1 output (note 1) 1 1 1 port c pc5 cts1 input (note 1) 1 0 0 pd0 to pd7 output port x 0 pd0 d1bscp output x 1 pd1 d2blp output x 1 pd2 d3bfr output x 1 pd3 dlebcd output x 1 pd4 doffb output x 1 alarm output 1 1 pd6 mldalm output 0 1 port d pd7 mldalm output x none 1 input port x 0 0 output port x 1 0 port e pe0 to pe7 ld0 to ld7 output x 1 1 pf0 to pf7 output port x 0 pf0 sdras output x 1 pf1 sdcas output x 1 pf2 sdwe output x 1 pf3 sdldqm output x 1 pf4 sdudqm output x 1 pf5 sdcke output x 1 port f pf6 sdclk output x none 1 none x: don?t care note 1: as for input ports of sio1 to sio3: (opttx0, optrx0, txd0, rxd0, sclk0, cts0 , txd1, rxd1, sclk1, cts1 , txd2, rxd2), logical selection for output data or input data is determined by the output latch register pn of each port. note 2: when p71/p72 are used as sda/scl open-drain outputs, p70de tmp91c820a 2008-02-20 91c820a-61 3.5.1 port 0 (p00 to p07) port 0 is an 8-bit general-purpose i/o port. each bit can be set individually for input or output using the control register p0cr. resetting resets all bits of the output latch p0, the control register p0cr to 0 and sets port 0 to input mode. in addition to functioning as a general-purpose i/o port, port 0 can also function as an data bus (d0 to d7). when external memory is accesed, the port automatically functions as the data bus (d0 to d7) and all bits of p0cr are cleared to 0. internal data bus direction control (on bit basis) p0cr write p00 to p07 (d0 to d7) output buffer reset p0 read p0 write output latch selector a b s d0 to d7 external access (data read) external access (data write) external access figure 3.5.1 port 0 port 0 register 7 6 5 4 3 2 1 0 bit symbol p07 p06 p05 p04 p03 p02 p01 p00 read/write r/w after reset data from external port (output latch register is cleared to 0.) port 0 control register 7 6 5 4 3 2 1 0 bit symbol p07c p06c p05c p04c p03c p02c p01c p00c read/write w after reset 0 0 0 0 0 0 0 0 function port 0 input/output settings 0: input 1:output note 1: read-modify-write is prohibited for p0cr. note 2: when functionin g as a data bus ( d0 to d7 ) , p0cr is cleared to 0. p0 (0000h) p0 (0000h) p0cr (0002h) figure 3.5.2 register for port 0 tmp91c820a 2008-02-20 91c820a-62 3.5.2 port 1 (p10 to p17) port 1 is an 8-bit general-purpose i/o port. each bit can be set individually for input or output using the control register p1cr and the function register p1fc. resetting resets all bits of the output latch p1, the control register p1cr and the function register p1fc to 0 and sets port 1 to input mode. in addition to functioning as a general-purpose i/o port, port 1 can also function as an data bus (d8 to d15). am1 am0 p1xf function setting after reset is released 0 0 1 1 0 1 0 1 0 1 ? 0 input port data bus (d8 to d15) don?t use this setting input port internal data bus direction control (on bit basis) function control (on bit basis) p1cr write p1fc write p10 to p17 (d8 to d15) output buffer reset p1 read p1 write port 1 output latch selector a b s d8 to d15 external access (data read) external access (data write) figure 3.5.3 port 1 tmp91c820a 2008-02-20 91c820a-63 port 1 register 7 6 5 4 3 2 1 0 bit symbol p17 p16 p15 p14 p13 p12 p11 p10 read/write r/w after reset data from external port (output latch register is cleared to 0.) port 1 control register 7 6 5 4 3 2 1 0 bit symbol p17c p16c p15c p14c p13c p12c p11c p10c read/write w after reset 0 0 0 0 0 0 0 0 function port 1 function settings port 1 function register 7 6 5 4 3 2 1 0 bit symbol p17f p16f p15f p14f p13f p12f p11f p10f read/write w after reset (note3) 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 function port 1 function settings port 1 function settings note 1: read-modify-write is prohibited for p1cr and p1fc. note 2: tmp91c820a 2008-02-20 91c820a-64 3.5.3 port 2 (p20 to p27) port 2 is an 8-bit general-purpose i/o port. each bit can be set individually for input or output using the control register p2cr and the function register p2fc. in addition to functioning as a general-purpose i/o port, port 2 can also function as an address bus (a16 to a23). setting the am1 and am0 pins as shown below and resetting the device initialize port 2 to the following function pins. am1 am0 p2xc p2xf function setting after reset is released 0 0 1 1 0 1 0 1 1 1 ? 0 1 1 ? 0 address bus (a16 to a23) address bus (a16 to a23) don?t use this setting input port a b internal data bus function control (on bits basis) p2fc write p20 to p27 (a16 to a23) output buffer reset output latch p2 write selector s direction control (on bit basis) p2cr write internal address bus p2 read a16 to a23 figure 3.5.5 port 2 tmp91c820a 2008-02-20 91c820a-65 port 2 register 7 6 5 4 3 2 1 0 bit symbol p27 p26 p25 p24 p23 p22 p21 p20 read/write r/w after reset data from external port (output latch register is cleared to 0.) port 2 control register 7 6 5 4 3 2 1 0 bit symbol p27c p26c p25c p24c p23c p22c p21c p20c read/write w after reset (note3) 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 function port 2 function settings port 2 function register 7 6 5 4 3 2 1 0 bit symbol p27f p26f p25f p24f p23f p22f p21f p20f read/write w after reset (note3) 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 function port 2 function settings port 2 function settings note 1: read-modify-write is prohibited for p2cr and p2fc. note 2: tmp91c820a 2008-02-20 91c820a-66 3.5.4 port 3 (p30 to p37) port 3 is an 8-bit general-purpose i/o port. each bit can be set individually for input or output using the control register p3cr and the function register p3fc. in addition to functioning as a general-purpose i/o port, port 3 can also function as an address bus (a8 to a15). setting the am1 and am0 pins as shown below and resetting the device initialize port 3 to the following function pins. am1 am0 p3xc p3xf function setting after reset is released 0 0 1 1 0 0 0 1 1 1 ? 0 1 1 ? 0 address bus (a8 to a15) address bus (a8 to a15) don?t use this setting input port a b internal data bus function control (on bit basis) p3fc write p30 to p37 (a8 to a15) output buffer reset output latch p3 write selector s internal address bus direction control (on bit basis) p3cr write p3 read a8 to a15 figure 3.5.7 port 3 tmp91c820a 2008-02-20 91c820a-67 port 3 register 7 6 5 4 3 2 1 0 bit symbol p37 p36 p35 p34 p33 p32 p31 p30 read/write r/w after reset data from external port (output latch register is cleared to 0.) port 3 control register 7 6 5 4 3 2 1 0 bit symbol p37c p36c p35c p34c p33c p32c p31c p30c read/write w after reset (note3) 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 function port 3 function settings port 3 function register 7 6 5 4 3 2 1 0 bit symbol p37f p36f p35f p34f p33f p32f p31f p30f read/write w after reset (note3) 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 function port 3 function settings port 3 function settings note 1: read-modify-write is prohibited for p3cr and p3fc. note 2: tmp91c820a 2008-02-20 91c820a-68 3.5.5 port 4 (p40 to p47) port 4 is an 8-bit general-purpose i/o port. each bit can be set individually for input or output using the control register p4cr and the function register p4fc. in addition to functioning as a general-purpose i/o port, port 4 can also function as an address bus (a0 to a7). setting the am1 and am0 pins as shown below and resetting the device initialize port 4 to the following function pins. am1 am0 p4xc p4xf function setting after reset is released 0 0 1 1 0 1 0 1 1 1 ? 0 1 1 ? 0 address bus (a0 to a7) address bus (a0 to a7) don?t use this setting input port a b internal data bus function control (on bit basis) p4fc write p40 to p47 (a0 to a7) output buffer reset output latch p4 write selector s internal address bus direction control (on bit basis) p4cr write p4 read a0 to a7 figure 3.5.9 port 4 tmp91c820a 2008-02-20 91c820a-69 port 4 register 7 6 5 4 3 2 1 0 bit symbol p47 p46 p45 p44 p43 p42 p41 p40 read/write r/w after reset data from external port (output latch register is cleared to 0.) port 4 control register 7 6 5 4 3 2 1 0 bit symbol p47c p46c p45c p44c p43c p42c p41c p40c read/write w after reset (note3) 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 function port 4 function settings port 4 function register 7 6 5 4 3 2 1 0 bit symbol p47f p46f p45f p44f p43f p42f p41f p40f read/write w after reset (note3) 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 function port 4 function settings port 4 function settings note 1: read-modify-write is prohibited for p4cr and p4fc. note 2: tmp91c820a 2008-02-20 91c820a-70 3.5.6 port z (pz0 to pz3) port z is an 4-bit general-purpose i/o port (p50 and p51 are used for output only). i/o is set using control register pzcr and pzfc. resetting resets all bits of the output latch pz to 1. in addition to functioning as a general-purpose i/o port, port z also functions as i/o for the cpu?s control/status signal. when pz0 pin is defined as rd strobe signal output mode ( tmp91c820a 2008-02-20 91c820a-71 internal data bus function control (on bit basis) pzfc write output buffer reset pz read output latch pz write pz1 ( wr ) selector s a b wr internal address area function conrtol (on bit basis) s output latch pz2 ( hwr ) selector internal data bus direction control (on bit basis) pzcr write p-ch (programmable pull up) reset pzfc write pz write output buffer pz read s a b hwr figure 3.5.12 port z (pz1, pz2) tmp91c820a 2008-02-20 91c820a-72 function conrtol (on bit basis) s output latch pz3 ( w / r , srwe ) selector internal data bus direction control (on bit basis) pzcr write p-ch ( pro g rammable pull up) reset pzfc write pz write output buffer p5 read s a b srwe c w / r figure 3.5.13 port z (pz3) tmp91c820a 2008-02-20 91c820a-73 port z register 7 6 5 4 3 2 1 0 bit symbol pz3 pz2 pz1 pz0 read/write r/w after reset data form external port (note 1) 1 1 function 0(output latch register): pull-up resistor off 1(output latch register): pull-up resistor on ? ? port z control register 7 6 5 4 3 2 1 0 bit symbol pz3c pz2c read/write w after reset 0 0 function 0: input 1: output port z function register 7 6 5 4 3 2 1 0 bit symbol pz3f pz2f pz1f pz0f read/write w after reset 0 0 0 0 function 0: port 1: w / r , srwe 0: port 1: hwr 0: port 1: wr 0: port 1: rd pzfc (007fh) pz (007dh) note 1: output latch register is set to 1. note 2: read-modify-write is prohibited for registers pzcr and pzfc. note 3: when port z is used in input mode, the pz register controls the built-in pull-up resistor. read-modify-write is prohibited in input mode or i/o mode. setting the built-in pull-up resistor may be depended on the states of the input pin. tmp91c820a 2008-02-20 91c820a-74 3.5.7 port 5 (p56) port 5 is an 1-bit general-purpose i/o port. i/o is set using control register p5cr and p5fc. resetting resets all bits of the output latch p5 to p1. in addition to functioning as a general-purpose i/o port, port 5 also functions as i/o for the cpu?s control/status signal. resetting initializes p56 pins to input mode with pull-up resistor. internal wait s output latch p5 write p5 read internal data bus direction control (on bit basis) p5cr write p-ch (programmable pull up) reset p56 ( wait ) output buffer figure 3.5.15 port 5 (p56) tmp91c820a 2008-02-20 91c820a-75 port 5 register 7 6 5 4 3 2 1 0 bit symbol p56 read/write r/w after reset data from external port (output latch register is set to 1.) function 0(output latch register): pull-up resistor off 1(output latch register): pull-up resistor on port 5 control register 7 6 5 4 3 2 1 0 bit symbol p56c read/write w after reset 0 function 0: input 1: output p5 (000dh) p5cr (0010h) note: when the p53/wait pin is to be use as the wait pin, p5cr tmp91c820a 2008-02-20 91c820a-76 3.5.8 port 6 (p60 to p67) port 60 to 67 are 8-bit output ports. resetting sets output latch of p62 to 0 and output latches of p60 to p61 and p63 to p67 are set to 1. port 6 also function as chip-select output ( cs0 to cs3 ), extend address output (ea24, ea25), extend chip-select output ( cs2a , cs2b , cs2c , cs2d , cs2e ), sram byte control output ( srub , srlb ), and sdram chip-select output ( sdcs ). writing 1 in the corresponding bit of p6fc, p6fc2 enables the respective functions. resetting reset the p6fc and p6fc2 to 0, and sets all bits to output ports. internal data bus function control ( on bit basis ) output lacth p6 read reset p60 ( cs0 ) p61 ( cs1 , sdcs ) p62 ( cs2 , cs2a ) p63 ( cs3 ) p64 (ea24, cs2b ) p65 (ea25, cs2c ) p66 ( srlb , cs2d ) p67 ( srub , cs2e ) cs0 , cs1 , cs2 , cs3 , ea24, ea25, srlb , srub selector p6fc write p6 write s a b function control 2 (on bit basis) p6fc2 write sdcs , cs2a , cs2b , cs2c , cs2d , cs2e c figure 3.5.17 port 6 port 6 register 7 6 5 4 3 2 1 0 bit symbol p67 p66 p65 p64 p63 p62 p61 p60 read/write r/w after reset 1 1 1 1 1 0 1 1 port 6 function register 7 6 5 4 3 2 1 0 bit symbol p67f p66f p65f p64f p63f p62f p61f p60f read/write w after reset 0 function 0: port 1: srub 0: port 1: srlb 0: port 1: ea25 0: port 1: ea24 0: port 1: cs3 0: port 1: cs2 0: port 1: cs1 0: port 1: cs0 port 6 function register 2 7 6 5 4 3 2 1 0 bit symbol p67f2 p66f2 p65f2 p64f2 ? p62f2 p61f2 ? read/write w after reset 0 function 0: tmp91c820a 2008-02-20 91c820a-77 3.5.9 port 7 (p70 to p77) port 7 is an 8-bit general-purpose i/o port. i/o can be set on bit basis using the control register. resetting sets port 7 to input port and all bits of output latch to 1. in addition to functioning as a general-purpose i/o port, port 7 also functions as follows. 1. input/output function for serial bus interface (sck, so/sda, si/scl) 2. input/output function for irda (optrx0, opttx0) 3. extend chip-select output ( cs2f , cs2g , csexa ) 4. clock control function for voltage boos ter of external lcd driver (msk, veeclk) writing 1 in the corresponding bit of p7fc, p7fc2 enables the respective functions. resetting resets the p7fc, p7fc2 to 0, and sets all bits to input ports. (1) port 70 (sck, optrx0) port 70 is a general-purpose i/o port. it is also used as sck (clock signal for sio mode) and optrx0 (receive input for irda mode of sio0). used as optrx0, it is possible to logical invert by p7 tmp91c820a 2008-02-20 91c820a-78 (2) port 71 (so/sda/opttx0) port 71 is a general-purpose i/o port. it is also used as sda (data input for i 2 c bus mode), so (data output for sio mode) for serial bus interface and opttx0 (transmit output for irda mode of sio0). used as opttx0, it is possible to logical invert by p7 tmp91c820a 2008-02-20 91c820a-79 (3) port 72 (si/scl) port 72 is a general-purpose i/o port. it is also used as si (data input for sio mode), scl (clock input/output for i 2 c bus mode) for serial bus interface. open-drain possible: p7ode tmp91c820a 2008-02-20 91c820a-80 (4) port 73 ( cs2f ), 74 ( cs2g ), 75 ( csexa ) port 73 to 75 are general-purpose i/o ports. these are also used as control signal for sequential mask rom and extend chip-select output. internal data bus selector a s selector a b s p73 ( cs2f ), p74 ( cs2g ), p75 ( csexa ) p7 read direction control ( on bit basis ) p7cr write funtcion control (on bit basis) p7fc write s output latch p7 write reset function control 2 ( on bit basis ) p7fc2 write b cs2f , cs2g , csexa figure 3.5.22 port 73, 74, 75 tmp91c820a 2008-02-20 91c820a-81 (5) port 76 (msk), 77 (veeclk) port 76 and 77 are general-purpose i/o ports. these are also used as clock control function for voltage booster of external lcd driver. msk pin (p76) is an input pin from external lcd driver, clock output from veeclk pin is controlled by state of this pin. logic of this pin is controlled with p7fc tmp91c820a 2008-02-20 91c820a-82 port 7 register 7 6 5 4 3 2 1 0 bit symbol p77 p76 p75 p74 p73 p72 p71 p70 read/write r/w after reset data from external port (output latch register is set to 1.) port 7 control register 7 6 5 4 3 2 1 0 bit symbol p77c p76c p75c p74c p73c p72c p71c p70c read/write w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port 7 function register 7 6 5 4 3 2 1 0 bit symbol p77f p76f p75f p74f p73f p72f p71f p70f read/write w after reset 0 function 0:port 1:veeclk msk select 0: enable 1: enable 0: port 0: port 0: port 0: port 1: scl/si 0: port 1: sda/so 0: port 1: sck port 7 function register 2 7 6 5 4 3 2 1 0 bit symbol ? ? p75f2 p74f2 p73f2 ? p71f2 p70f2 read/write w after reset 0 function always write ?0?. always write ?0?. 0: tmp91c820a 2008-02-20 91c820a-83 3.5.10 port 8 (p80 to p87) port 8 is an 8-bit input port and can also be used as the analog input pins for the internal ad converter. p83 can also be used as adtrg pin for the ad converter. figure 3.5.25 port 8 port 8 register 7 6 5 4 3 2 1 0 bit symbol p87 p86 p85 p84 p83 p82 p81 p80 read/write r after reset data from external port note: the input channel selection of ad converter and the permission of adtrg input are set by ad converter mode register admod1. p8 (0018h) figure 3.5.26 register for port 8 internal data bus ad read conversion result register ad converter channel selector port 8 read port 8 p80 to p87 (an0 to an7) adtrg (for p83 only) tmp91c820a 2008-02-20 91c820a-84 3.5.11 port 9 (p90 to p97) port 90 to 97 are 8-bit input ports with pull-up resistor. in addition to functioning as general-purpose i/o port, port 90 to 97 can also key-on wakeup function as keyboard interface. the various functions can each be enabled by writing a 1 to the corresponding bit of the port 9 function register (p9fc). resetting resets all bits of the register p9fc to 0 and sets all pins to be input port. figure 3.5.27 port 9 when p9fc = 1, if either of input of ki0 to ki7 pins falls down, intkey interrupt is generated. intkey interrupt can be used to release all halt mode. port 9 register 7 6 5 4 3 2 1 0 bit symbol p97 p96 p95 p94 p93 p92 p91 p90 read/write r after reset data from external port port 9 function register 7 6 5 4 3 2 1 0 bit symbol p97f p96f p95f p94f p93f p92f p91f p90f read/write w after reset 0 0 0 0 0 0 0 0 function 0: key-in disable 1: key-in enable p9fc (001dh) p9 (0019h) note: read-modify-write is prohibited for the registers p9fc. key-in of port 9 disable 0 enable 1 figure 3.5.28 register for port 9 internal data bus p90 to p97 (ki0 to ki7) pull-up resistor p9fc write key-on enable ( on bit basis ) rising edge detection intkey p90 to p97 8-or reset p9 read tmp91c820a 2008-02-20 91c820a-85 3.5.12 port a (pa0 to pa7) port pa0 to pa7 are 8-bit output ports, and also used key board interface pin ko0 to ko7 which can set open-drain output buffer. writing 1 in the corresponding bit of the po rt a function register (pafc) enable the open-drain output. resetting reset bits of the registers pa to 1 and pafc to 0, and all pin outputs 1. figure 3.5.29 port a port a register 7 6 5 4 3 2 1 0 bit symbol pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 read/write r/w after reset 1 1 1 1 1 1 1 1 port a function register 7 6 5 4 3 2 1 0 bit symbol pa7f pa6f pa5f pa4f pa3f pa2f pa1f pa0f read/write w after reset 0 0 0 0 0 0 0 0 function 0: cmos output 1: open drain note: read-modify-write is prohibited for pafc. pa (001eh) pafc (0021h) figure 3.5.30 register for port a internal data bus p a read pa0 to pa7 (ko0 to ko7) output buffer set p a fc write reset s output latch p a write programmable open drain tmp91c820a 2008-02-20 91c820a-86 3.5.13 port b (pb0 to pb6) port b is a 6-bit general-purpose i/o port. each bit can be set individually for input or output. resetting sets port b to be an input port. in addition to functioning as a general-purpose i/o port, port b can also function as i/o pin for timers (ta0in, ta1out, ta3out, tb0out0), input pin for external interruption (int0 to int3), and i/o for serial channels 2 (txd2, rxd2). above setting is used the function register pbfc and pbfc2. edge select of external interruption establishes it with iimc register, which there is in interruption controller. (1) pb0 (ta0in, txd2) as well as functioning as i/o port pins, port b0 can also function as serial channel txd output pins. in case of use txd2, it is possible to logical invert by setting the register pb tmp91c820a 2008-02-20 91c820a-87 (2) pb1 (ta1out, rxd2) port b1 is i/o port pins and can also is used as rxd input for the serial channels. in case of use rxd2, it is possible to logical invert by setting the register pb tmp91c820a 2008-02-20 91c820a-88 (4) pb4 (int1), pb5 (int2, ta3out), pb6 (int3, tb0out0) pb read internal data bus selector a b s pb4 (int1) direction control (on bits basis) s output latch pbcr write pb write reset function control ( on bit basis ) pbfc write rising/falling edge detection iimc tmp91c820a 2008-02-20 91c820a-89 port b register 7 6 5 4 3 2 1 0 bit symbol pb6 pb5 pb4 pb3 pb1 pb0 read/write r/w r/w after reset data from external port (output latch register is set to 1.) data from external port (output latch register is set to 1.) function ? ? ? ? (note 3) ? port b control register 7 6 5 4 3 2 1 0 bit symbol pb6c pb5c pb4c pb3c pb1c pb0c read/write w w after reset 0 0 0 0 0 0 function 0: input 1: output 0: input 1: output port b function register 7 6 5 4 3 2 1 0 bit symbol pb6f pb5f pb4f pb3f pb1f pb0f read/write w w after reset 0 0 0 0 0 0 function 0: port 1: int3 tb0out0 0: port 1: int2 ta3out 0: port 1: int1 0: port 1: int0 0: port 1: ta1out 0:port 1:txd2 port b ode register 7 6 5 4 3 2 1 0 bit symbol odepb0 read/write w after reset 0 function txd2 0: cmos 1: open drain pbfc (0025h) pb (0022h) pbcr (0024h) note 1: read-modify-write is prohibited for the registers pbcr, pbfc and pbode. note 2: pb0/ta0in pin does not have a register changing port/function. for example, when it is used as an input port, the input signal is inputted to 8-bit timer. note 3: pb1/rxd1 pin does not have a register changing port/function. for example, when it is used as an input port, the input signal is inputted to sio as the serial receive data. pbode (002bh) tmp91c820a 2008-02-20 91c820a-90 3.5.14 port c (pc0 to pc5) port c0 to c5 are 6-bit general-purpose i/o ports. each bit can be set individually for input or output. resetting sets pc0 to pc5 to be an input ports. it also sets all bits of the output latch register to 1. in addition to functioning as general-purpose i/o port pins, pc0 to pc5 can also function as the i/o for serial channels 0 and 1. a pin can be enabled for i/o by writing a 1 to the corresponding bit of the port c function register (pcfc). resetting resets all bits of the registers pccr and pcfc to 0 and sets all pins to be input ports. (1) port c0, c3 (txd0/txd1) as well as functioning as i/o port pins, port c0 and c3 can also function as serial channel txd output pins. in case of use txd0/txd1, it is possible to logical invert by setting the register pc tmp91c820a 2008-02-20 91c820a-91 (2) port c1, c4 (rxd0, 1) port c1 and c4 are i/o port pins and can also be used as rxd input for the serial channels. in case of use rxd0/rxd1, it is possible to logical invert by setting the register pc tmp91c820a 2008-02-20 91c820a-92 port c register 7 6 5 4 3 2 1 0 bit symbol pc5 pc4 pc3 pc2 pc1 pc0 read/write r/w after reset data from external port (output latch register is set to 1.) port c control register 7 6 5 4 3 2 1 0 bit symbol pc5c pc4c pc3c pc2c pc1c pc0c read/write w after reset 0 0 0 0 0 0 function 0: input 1: output port c functon register 7 6 5 4 3 2 1 0 bit symbol pc5f pc3f pc2f pc0f read/write w w w w after reset 0 0 0 0 function 0: port 1: sclk1 output 0: port 1: txd1 0: port 1: sclk0 output 0: port 1: txd0 port c ode register 7 6 5 4 3 2 1 0 bit symbol odepc3 odepc0 read/write w w after reset 0 0 function txd1 0: cmos 1: open drain txd0 0: cmos 1: open drain pcfc (0027h) pc (0023h) pccr (0026h) pcode (0028h) note 1: read-modify-write is prohibited for the registers pccr, pcfc and pcode. note 2: pc1/rxd0, pc4/rxd1 pins do not have a register changing port/function. for example, when it is used as an input port, the input signal is inputted to sio as the serial receive data. figure 3.5.39 register for port c tmp91c820a 2008-02-20 91c820a-93 3.5.15 port d (pd0 to pd7) port d is an 8-bit output port. resetting sets the output latch pd to 1, and pd0 to pd7 pin output 1. in addition to functioning as output port, port d also function as output pin for lcd controller (dibscp, d2blp, d3bfr, dlebcd and doffb), output pin for rtc alarm ( alarm ) and output pin for melody/alarm generator (mldalm, mldalm ). above setting is used the function register pdfc. only pd6 has two output function which are alarm and mldalm . this selection is used pd tmp91c820a 2008-02-20 91c820a-94 port d register 7 6 5 4 3 2 1 0 bit symbol pd7 pd6 pd4 pd3 pd2 pd1 pd0 read/write r/w r/w after reset 1 1 1 1 1 1 1 port d function register 7 6 5 4 3 2 1 0 bit symbol pd7f pd6f pd4f pd3f pd2f pd1f pd0f read/write w w after reset 0 0 function 0: port 1: mldalm 0: port 1: alarm at tmp91c820a 2008-02-20 91c820a-95 3.5.16 port e (pe0 to pe7) port e is an 8-bit general-purpose i/o ports. each bit can be set individually for input or output using the control register pecr. resetting, the control register pecr to 0 and sets port e to input ports. it also sets all bits of the output latch register to 1. in addition to functioning as a general-purpose i/o port, port e can also function as an data bus for lcd controller (ld0 to ld7). ab ove setting is used the function register pefc. internal data bus selector a b s selector a b s pe0 to pe7 (ld0 to ld7) pe read direction control (on bit basis) pecr write function control ( on bit basis ) pefc write s output latch pe write reset ld7 to ld0 figure 3.5.43 port e port e register 7 6 5 4 3 2 1 0 bit symbol pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 read/write r/w after reset data from external port (output latch register is set to 1.) port e control register 7 6 5 4 3 2 1 0 bit symbol pe7c pe6c pe5c pe4c pe3c pe2c pe1c pe0c read/write w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port e function register 7 6 5 4 3 2 1 0 bit symbol pe7f pe6f pe5f pe4f pe3f pe2f pe1f pe0f read/write w after reset 0 0 0 0 0 0 0 0 function 0: port 1: data bus for lcdc (ld7 to ld0) pe (002ch) note: read-modify-write is prohibited for pecr and pefc. pefc (002eh) pecr (002dh) figure 3.5.44 register for port e tmp91c820a 2008-02-20 91c820a-96 3.5.17 port f (pf0 to pf7) port f is an 8-bit output port. resetting sets the output latch pf to 1, and pf0 to pf7 pin output 1. in addition to functioning as output port, port f also function as output pin for sdram controller (sdcke, sdclk, sdldqm, sdudqm, sdwe ), and output pin for ssio (ssclk). above setting is used the function register pffc. function control (on bit basis) output latch pf read reset pf0 ( sdras ) pf1 ( sdcas ) pf2 ( sdwe ) pf3 (sdldqm) pf4 (sdudqm) pf5 (sdcke) pf6 (sdclk) pf7 sdras , sdcas , sdwe , sdldqm, sdudqm, sdcke, sdclk output buffer selector pffc write pf write s a b internal data bus figure 3.5.45 port f port f register 7 6 5 4 3 2 1 0 bit symbol pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 read/write r/w after reset 1 1 1 1 1 1 1 1 port f function register 7 6 5 4 3 2 1 0 bit symbol ? pf6f pf5f pf4f pf3f pf2f pf1f pf0f read/write w after reset 0 1 0 0 0 0 0 0 function always write ?0?. 0: port 1: sdclk 0: port 1: sdcke 0: port 1: sdudqm 0: port 1: sdldqm 0: port 1: sdwe 0: port 1: sdcas 0: port 1: sdras pf (0030h) pffc (0032h) note: read-modify-write is prohibited for the registers pffc. figure 3.5.46 register for port f tmp91c820a 2008-02-20 91c820a-97 3.6 chip select/wait controller on the tmp91c820a, four user-specifiable address areas ( cs0 to cs3 ) can be set. the data bus width and the number of waits can be set independently for each address area ( cs0 to cs3 and others). the pins cs0 to cs3 (which can also function as port pins p60 to p63) are the respective output pins for the areas cs0 to cs3. when the cpu specifies an address in one of these areas, the corresponding cs0 to cs3 pin outputs the chip select signal for the specified address area (in rom or sram). however, in order for the chip select signal to be output, the port 6 function register (p6fc) must be set. cs2a to cs2g and csexa (cs pin except cs0 to cs3 ) are made by mmu. these pins are cs pin that area and bank value is fixed without concern in setting of cs/wait controller. the areas cs0 to cs3 are defined by the valu es in the memory start address registers msar0 to msar3 and the memory address mask registers mamr0 to mamr3. the chip select/wait control registers b0cs to b3cs and bexcs should be used to specify the master enable/disable status the data bus width and the number of waits for each address area. the input pin controlling these states is the bus wait request pin ( wait ). 3.6.1 specifying an address area the cs0 to cs3 address areas are specified using the start address registers (msar0 to msar3) and memory address mask registers (mamr0 to mamr3). at each bus cycle, a compare operation is performed to determine if the address on the specified a location in the cs0 to cs3 area. if the result of the comparison is a match, this indicates an access to the corresponding cs area. in this case, the cs0 to cs3 pin outputs the chip select signal and the bus cycle operates in accordance with the settings in chip select/wait control register b0cs to b3cs. (see 3.6.2 ?chip select/wait control registers?.) tmp91c820a 2008-02-20 91c820a-98 (1) memory start address registers figure 3.6.1 shows the memory start address registers. the memory start address registers msar0 to msar3 set the start addresses for the cs0 to cs3 areas. set the upper eight bits (a23 to a16) of the start address in tmp91c820a 2008-02-20 91c820a-99 (2) memory address mask registers figure 3.6.3 shows the memory address mask registers. memory address mask registers mamr0 to mamr3 are used to set the size of the cs0 to cs3 areas by specifying a mask for each bit of the start address set in memory start address registers mamr0 to mamr3. the compare oper ation used to determine if an address is in the cs0 to cs3 areas is only performe d for bus address bits corresponding to bits set to 0 in these registers. also, the address bits that can be masked by mamr0 to mamr3 differ between cs0 to cs3 areas. accordingly, the size that can be each area is different. memory address mask register (for cs0 area) 7 6 5 4 3 2 1 0 bit symbol v20 v19 v18 v17 v16 v15 v14 to v9 v8 read/write r/w after reset 1 1 1 1 1 1 1 1 function sets size of cs0 area 0: used for address compare range of possible settings for cs0 area size: 256 bytes to 2 mbytes memory address mask register (cs1) 7 6 5 4 3 2 1 0 bit symbol v21 v20 v19 v18 v17 v16 v15 to v9 v8 read/write r/w after reset 1 1 1 1 1 1 1 1 function sets size of cs1 area 0: used for address compare range of possible settings for cs1 area size: 256 bytes to 4 mbytes. memory address mask register (cs2, cs3) 7 6 5 4 3 2 1 0 bit symbol v22 v21 v20 v19 v18 v17 v16 v15 read/write r/w after reset 1 1 1 1 1 1 1 1 function sets size of cs2 or cs3 area 0: used for address compare range of possible settings for cs2 and cs3 area sizes: 32 kbytes to 8 mbytes. mamr0 (00c9h) mamr1 (00cbh) mamr2 (00cdh) mamr3 (00cfh) figure 3.6.3 memory address mask registers tmp91c820a 2008-02-20 91c820a-100 (3) setting memory start addresses and address areas figure 3.6.4 shows an example of specifying a 64-kbyte address area starting from 010000h using the cs0 areas. set 01h in memory start address register msar0 tmp91c820a 2008-02-20 91c820a-101 (4) address area size specification table 3.6.1 shows the relationship between cs area and area size. ? ? ? indicates areas that cannot be set by memory start address register and address mask register combinations. when setting an area size using a combination indicated by ? ? ?, set the start address mask register in the desired steps starting from 000000h. if the cs2 area is set to 16 mbytes or if two or more areas overlap, the smaller cs area number has the higher priority. example: to set the area size for cs0 to 128 kbytes: a. valid start addresses 000000h 020000h 040000h 060000h 128 kbytes 128 kbytes 128 kbytes any of these addresses may be set as the start address. : b. invalid start addresses 000000h 010000h 030000h 050000h 64 kbytes 128 kbytes 128 kbytes this is not an integer multiple of the desired area size setting. hence, none of these addresses can be set as the start address. : table 3.6.1 valid area sizes for each cs area size (bytes) cs area 256 512 32 k 64 k 128 k 256 k 512 k 1 m 2 m 4 m 8 m cs0 ? ? ? ? ? cs1 ? ? ? ? ? ? cs2 ? ? ? ? ? ? ? cs3 ? ? ? ? ? ? ? note: ? ? ? indicates areas that cannot be set by memory start address register and address mask register combinations. 3.6.2 chip select/wait control registers figure 3.6.5 lists the chip select/wait control registers. the master enable/disable, chip select output waveform, data bus width and number of wait states for each address area (cs0 to cs3 and others) are set in their respective chip select/wait control registers, b0cs to b3cs and bexcs. tmp91c820a 2008-02-20 91c820a-102 chip select/wait control registers 7 6 5 4 3 2 1 0 bit symbol b0e b0om1 b0om0 b0bus b0w2 b0w1 b0w0 read/write w w after reset 0 0 0 0 0 0 0 function 0: disable 1: enable chip select output waveform selection 00: for rom/sram 01: 10: don?t care 11: data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 waits 100: reserved 001: 1 wait 101: 3 waits 010: (1 + n) waits 110: 4 waits 011: 0 waits 111: 8 waits bit symbol b1e b1om1 b1om0 b1bus b1w2 b1w1 b1w0 read/write w w after reset 0 0 0 0 0 0 0 function 0: disable 1: enable chip select output waveform selection 00: for rom/sram 01: 10: don?t care 11: data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 waits 100: reserved 001: 1 wait 101: 3 waits 010: (1 + n) waits 110: 4 waits 011: 0 waits 111: 8 waits bit symbol b2e b2m b2om1 b2om0 b2bus b2w2 b2w1 b2w0 read/write w after reset 1 0 0 0 0 0 0 0 function 0: disable 1: enable cs2 area selection 0: 16-mbyte area 1: cs area chip select output waveform selection 00: for rom/sram 01: 10: don?t care 11: data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 waits 100: reserved 001: 1 wait 101: 3 waits 010: (1 + n) waits 110: 4 waits 011: 0 waits 111: 8 waits bit symbol b3e b3om1 b3om0 b3bus b3w2 b3w1 b3w0 read/write w w after reset 0 0 0 0 0 0 0 function 0: disable 1: enable chip select output waveform selection 00: for rom/sram 01: 10: don?t care 11: data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 waits 100: reserved 001: 1 wait 101: 3 waits 010: (1 + n) waits 110: 4 waits 011: 0 waits 111: 8 waits bit symbol bexbus bexw2 bexw1 bexw0 read/write 0 after reset 0 0 0 0 function data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 waits 100: reserved 001: 1 wait 101: 3 waits 010: (1 + n) waits 110: 4 waits 011: 0 waits 111: 8 waits chip select output waveform selection 00 for rom/sram 01 10 11 don?t care master enable bit 0 disable 1 enable b0cs (00c0h) read- modify- write instructions are prohibited. b1cs (00c1h) read- modify- write instructions are prohibited. b2cs (00c2h) read- modify- write instructions are prohibited. b3cs (00c3h) read- modify- write instructions are prohibited. bexcs (00c7h) read- modify- write instructions are prohibited. cs2 area selection 0 16-mbyte area 1 specified address area data bus width selection 0 16-bit data bus 1 8-bit data bus number of address area waits (see 3.6.2 (3) ?wait control?.) figure 3.6.5 chip select/wait control registers tmp91c820a 2008-02-20 91c820a-103 (1) master enable bits bit 7 ( tmp91c820a 2008-02-20 91c820a-104 table 3.6.2 dynamic bus sizing l h h l h l h l h h l h l l h l l h l l l h l l l l h l l h h l h l h l h h l h l l h l l h l l l h l l l l h l l h control for write cycle r/w l h h h l h l h l h h l h l l h l l h l l l h l l l l h l l h h l control for read cycle r/w h d7 to d0 b7 to b0 b7 to b0 b7 to b0 xxxx b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 xxxx b15 to b8 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxx b15 to b8 b31 to b24 cpu data d15 to d8 xxxx xxxx xxxx b7 to b0 xxxx xxxx b15 to b8 xxxx xxxx b7 to b0 xxxx xxxx xxxx xxxx xxxx b15 to b8 b31 to b24 xxxx xxxx xxxx xxxx b7 to b0 b23 to b16 xxxx cpu address 2n + 0 2n + 0 2n + 1 2n + 1 2n + 0 2n + 1 2n + 0 2n + 1 2n + 2 2n + 1 2n + 2 2n + 0 2n + 1 2n + 2 2n + 3 2n + 0 2n + 2 2n + 1 2n + 2 2n + 3 2n + 4 2n + 1 2n + 2 2n + 4 memory data bus width 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits operand start address 2n + 0 (even number) 2n + 1 (odd number) 2n + 0 (even number) 2n + 1 (odd number) 2n + 0 (even number) 2n + 1 (odd number) operand data bus width 8 bits 16 bits 32 bits xxxx: indicates that the input data from these bits are ignored during a read. during a write, indicates that the bus for these bits goes to high impedance; also, that the write strobe signal for the bus remains inactive. rd w r hw r srlb srub srwr rd w r hw r srlb srub srwr tmp91c820a 2008-02-20 91c820a-105 (3) wait control bits 0 to 2 ( tmp91c820a 2008-02-20 91c820a-106 if a cs0 to s3 address is specified which is actually an internal i/o and ram area address, the cpu accesses the internal address area and no chip select signal is output on any of the cs0 to cs3 pins. example: in this example cs0 is set to be the 64-kbyte area 010000h to 01ffffh. the bus width is set to 16 bits and the number of waits is set to 0. msar0 = 01h .......... start address: 010000h mamr0 = 07h ......... address area: 64 kbytes b0cs = 83h.............. rom/sram, 16-bit data bus, 0 waits, cs0 area settings enabled 3.6.3 connecting external memory figure 3.6.6 shows an example of how to connect external memory to the tmp91c820a. in this example the rom is connected using a 16-bit bus. the ram and i/o are connected using an 8-bit bus. address bus c s 8-bit ram oe we tmp91c820a cs upper byte rom oe c s lower byte rom oe c s 8-bit i/o oe we a0-a23 cs0 cs1 cs2 a0 to a23 d8 to d15 d0 to d7 rd wr figure 3.6.6 example of external memory connection (rom uses 16-bit bus; ram and i/o use 8-bit bus.) a reset clears all bits of the port 6 control register (p6cr) and the port 6 function register (p6fc) to 0 and disables output of the cs si gnal. to output the cs signal, the appropriate bit must be set to 1. tmp91c820a 2008-02-20 91c820a-107 figure 3.6.7 how to connect to 16-bit sram for tmp91c820a oe lds uds r/w ce i/o [16:1] a0 a1 a2 rd srlb srub srwr cs0 d [15:0] a0 a1 a2 a3 tmp91c820a 16-bit sram not connect ... ... ... tmp91c820a 2008-02-20 91c820a-108 3.7 8-bit timers (tmra) the tmp91c820a features 4 built-in 8-bit timers. these timers are paired into four modules: tmra01 and tmra23. each module consists of two channels and can operate in any of the following four operating modes. ? 8-bit interval timer mode ? 16-bit interval timer mode ? 8-bit programmable square wave pulse generation output mode (ppg: variable duty cycle with variable period) ? 8-bit pulse width modulation output mode (pwm: variable duty cycle with constant period) figure 3.7.1 and 3.7.2 show block diagrams for tmra01 and tmra23. each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register. in addition, a timer flip-flop and a prescale r are provided for each pair of channels. the operation mode and timer flip-flops are controlled by five controls sfrs (special function registers). each of the two modules (tmra01 and tmra23) can be operated independently. all modules operate in the same manner; hence only the operation of tmra01 is explained here. the contents of this chapter are as follows. 3.7.1 block diagrams 3.7.2 operation of each circuit 3.7.3 sfrs 3.7.4 operation in each mode (1) 8-bit timer mode (2) 16-bit timer mode (3) 8-bit ppg (programmable pulse generation) output mode (4) 8-bit pwm (pulse width modulation) output mode (5) settings for each mode (6) lcdc and melody/alarm circuit supply mode table 3.7.1 registers and pins for each module module tmra01 tmra23 input pin for external clock ta0in (shared with pb0) no external pin output pin for timer flip-flop ta1out (shared with pb1) ta3out (shared with pb5) timer run register ta01 run (0100h) ta23run (0108h) timer register ta0reg (0102h) ta1reg (0103h) ta2reg (010ah) ta3reg (010bh) timer mode register ta01mod (0104h) ta23mod (010ch) sfr (address) timer flip-flop control register ta1ffcr (0105h) ta3ffcr (010dh) tmp91c820a 2008-02-20 91c820a-109 3.7.1 block diagrams run/clear prescaler clock: t0 ta0trg external input clock: ta0in ta01mod tmp91c820a 2008-02-20 91c820a-110 run/clear prescaler clock: t0 ta2tr ta23mod tmp91c820a 2008-02-20 91c820a-111 3.7.2 operation of each circuit (1) prescaler a 9-bit prescaler generates the input clock to tmra01. the clock t0 is divided by 4 and input to this prescaler. t0 can be either f fph or fc/16 and is selected using the prescaler clock selection register syscr0 tmp91c820a 2008-02-20 91c820a-112 (3) timer registers (ta0reg and ta1reg) these are 8-bit registers, which can be used to set a time interval. when the value set in the timer register ta0reg or ta1reg matches the value in the corresponding up counter, the comparator match detect signal goes active. if the value set in the timer register is 00h, the signal goes ac tive when the up counter overflows. the ta0reg are double buffer structure, ea ch of which makes a pair with register buffer. the setting of the bit ta01run tmp91c820a 2008-02-20 91c820a-113 (4) comparator (cp0) the comparator compares the value in an up counter with the value set in a timer register. if they match, the up counter is cleared to 0 and an interrupt signal (intta0 or intta1) is generated. if timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. (5) timer flip-flop (ta1ff) t he timer flip-flop (ta1ff) is a flip-flop inverted by the match detects signal (8-bit comparator output) of each interval timer. whether inversion is enabled or disabled is determined by the setting of the bit ta1ffcr tmp91c820a 2008-02-20 91c820a-114 3.7.3 sfrs tmra01 run register 7 6 5 4 3 2 1 0 bit symbol ta0rde i2ta01 ta01prun ta1run ta0run read/write r/w r/w after reset 0 0 0 0 0 function double buffer 0: disable 1: enable idle2 0: stop 1: operate 8-bit timer run/stop control 0: stop and clear 1: run (count up) ta01run (0100h) timer run/stop control 0 stop and clear 1 run (count up) ta0reg double buffer control 0 disable 1 enable i2ta01: operation in idle2 mode ta01prun: run prescaler ta1run: run tmra1 ta0run: run tmra0 note: the values of bits 4 to 6 of ta01run are undefined when read. tmra23 run register 7 6 5 4 3 2 1 0 bit symbol ta2rde i2ta23 ta23prun ta3run ta2run read/write r/w r/w after reset 0 0 0 0 0 function double buffer 0: disable 1: enable idle2 0: stop 1: operate 8-bit timer run/stop control 0: stop and clear 1: run (count up) ta23run (0108h) timer run/stop control 0 stop and clear 1 run (count up) ta2reg double buffer control 0 disable 1 enable i2ta23: operation in idle2 mode ta23prun: run prescaler ta3run: run tmra3 ta2run: run tmra2 note: the values of bits 4 to 6 of ta23run are undefined when read. figure 3.7.4 register for tmra tmp91c820a 2008-02-20 91c820a-115 tmra01 mode register 7 6 5 4 3 2 1 0 bit symbol ta01m1 ta01m0 pwm01 pwm00 ta1clk1 ta1clk0 ta0clk1 ta0clk0 read/write r/w after reset 0 0 0 0 0 0 0 0 function operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit ppg mode 11: 8-bit pwm mode pwm cycle 00: reserved 01: 2 6 10: 2 7 11: 2 8 source clock for tmra1 00: ta0trg 01: t1 10: t16 11: t256 source clock for tmra0 00: ta0in pin 01: t1 10: t4 11: t16 00 ta0in (external input) 01 t1 (prescaler) 10 t4 (prescaler) 11 t16 (prescaler) ta01mod tmp91c820a 2008-02-20 91c820a-116 tmra23 mode register 7 6 5 4 3 2 1 0 bit symbol ta23m1 ta23m0 pwm21 pwm20 ta3clk1 ta3clk0 ta2clk1 ta2clk0 read/write r/w after reset 0 0 0 0 0 0 0 0 function operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit ppg mode 11: 8-bit pwm mode pwm cycle 00: reserved 01: 2 6 10: 2 7 11: 2 8 tmra3 clock for tmra3 00: ta2trg 01: t1 10: t16 11: t256 tmra2 clock for tmra2 00: reserved 01: t1 10: t4 11: t16 00 do not set 01 t1 (prescaler) 10 t4 (prescaler) 11 t16 (prescaler) ta23mod tmp91c820a 2008-02-20 91c820a-117 tmra1 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ta1ffc1 ta1ffc0 ta1ffie ta1ffis read/write r/w r/w after reset 1 1 0 0 function 00: invert ta1ff 01: set ta1ff 10: clear ta1ff 11: don?t care ta1ff control for inversion 0: disable 1: enable ta1ff inversion select 0: tmra0 1: tmra1 0 inversion by tmra0 1 inversion by tmra1 0 disabled 1 enabled 00 inverts the value of ta1ff 01 sets ta1ff to 1 10 clears ta1ff to 0 11 don?t care ta1ffcr (0105h) control of ta1ff inverse signal for timer flip-flop 1 (ta1ff) (don?t care except in 8-bit timer mode) inversion of ta1ff read- modify- write instructions are prohibited. figure 3.7.7 register for tmra tmp91c820a 2008-02-20 91c820a-118 tmra3 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ta3ffc1 ta3ffc0 ta3ffie ta3ffis read/write r/w r/w after reset 1 1 0 0 function 00: invert ta3ff 01: set ta3ff 10: clear ta3ff 11: don?t care ta3ff control for inversion 0: disable 1: enable ta3ff inversion select 0: tmra2 1: tmra3 0 inversion by tmra2 1 inversion by tmra3 0 disabled 1 enabled 00 inverts the value of ta3ff 01 sets ta3ff to 1 10 clears ta3ff to 0 11 don?t care ta3ffcr (010dh) control of ta3ff inverse signal for timer flip-flop 3 (ta3ff) (don?t care except in 8-bit timer mode) inversion of ta3ff read- modify- write instructions are prohibited. figure 3.7.8 register for tmra tmp91c820a 2008-02-20 91c820a-119 tmra register 7 6 5 4 3 2 1 0 bit symbol ? read/write w ta0reg (0102h) after reset undefined bit symbol ? read/write w ta1reg (0103h) after reset undefined bit symbol ? read/write w ta2reg (010ah) after reset undefined bit symbol ? read/write w ta3reg (010bh) after reset undefined note: the above registers are prohibited read-modify-write instruction. figure 3.7.9 register for tmra tmp91c820a 2008-02-20 91c820a-120 3.7.4 operation in each mode (1) 8-bit timer mode both tmra0 and tmra1 can be used independently as 8-bit interval timers. a. generating interrupts at a fixed interval (using tmra1) to generate interrupts at constant intervals using tmra1 (intta1), first stop tmra1 then set the operation mode, input clock and a cycle to ta01mod and ta1reg register respectively. then, enable the interrupt intta1 and start tmra1 counting. example: to generate an intta1 interrupt every 8.0 s at fc = 36 mhz, set each register as follows: * clock state system clock: high frequency (fc) prescaler clock: f fph msb lsb 7 6 5 4 3 2 1 0 ta01run ? ? x x ? ? 0 ? stop tmra1 and clear it to 0. ta01mod 0 0 x x 1 0 ? ? select 8-bit timer mode and select t1 (0.2 s at fc = 36 mhz) as the input clock. ta1reg 0 0 1 0 1 0 0 0 set ta1reg to 8.0 s t1 = 40 = 28h. inteta01 x 1 0 1 ? ? ? ? enable intta1 and set it to level 5. ta01run ? x x x ? 1 1 ? start tmra1 counting. x: don?t care, ? : no change select the input clock using table 3.7.2. note: the input clocks for tmra0 and tmra1 are different from as follows. tmra0: ta0in input, t1, t4 or t16. tmra1: match output of tmra0, t1, t16, t256. tmp91c820a 2008-02-20 91c820a-121 b. generating a 50% duty ratio square wave pulse the state of the timer flip-flop (ta1ff) is inverted at constant intervals and its status output via the timer output pin (ta1out). example: to output a 1.2 s square wave pulse from the ta1out pin at fc = 36mhz, use the following procedure to make the appropriate register settings. this example uses tmra1; however, either tmra0 or tmra1 may be used. * clock state system clock: high frequency (fc) clock gear: 1 (fc) prescaler clock: f fph 7 6 5 4 3 2 1 0 ta01run ? x x x ? ? 0 ? stop tmra1 and clear it to 0. ta01mod 0 0 x x 0 1 ? ? select 8-bit timer mode and select t1 (0.2 s at fc = 36 mhz) as the input clock. ta1reg 0 0 0 0 0 0 1 1 set the timer register to 1.2 s t1 2 = 3. ta1ffcr x x x x 1 0 1 1 clear ta1ff to 0 and set it to invert on the match detects signal from tmra1. pbcr x ? ? ? ? x 1 ? pbfc x ? ? ? ? x 1 ? set pb1 to function as the ta1out pin. ta01run ? x x x ? 1 1 ? start tmra1 counting. x: don?t care, ? : no change 0.6 s at fc = 36 mhz bit7 to 2 t1 intta1 uc1 clea r ta1ff bit0 bit1 ta01run tmp91c820a 2008-02-20 91c820a-122 c. making tmra1 count up on the match signal from the tmra0 comparator select 8-bit timer mode and set the comp arator output from tmra0 to be the input clock to tmra1. tmra1 up counter (when ta1reg = 2) tmra0 up counter (when ta0reg = 5) 1 2 3 4 5 1 1 22 33 45 12 1 comparaot output (tmra0 match) tmra1 match output figure 3.7.11 tmra1 count up on signal from tmra0 tmp91c820a 2008-02-20 91c820a-123 (2) 16-bit timer mode pairing the two 8-bit timers tmra0 and tmra1 configures a 16-bit interval timer. to make a 16-bit interval timer in which tmra0 and tmra1 are cascaded together, set ta01mod tmp91c820a 2008-02-20 91c820a-124 (3) 8-bit ppg (programmable pu lse generation) output mode square wave pulses can be generated at any frequency and duty ratio by tmra0. the output pulses may be active-low or active-high. in this mode tmra1 cannot be used. tmra0 outputs pulses on the ta1out pin. figure 3.7.13 8-bit ppg output waveforms t ta0reg and uc0 match (interrupt intta0) t h t l ta0reg ta1reg ta1reg and uc0 match ( interru p ut intta1 ) ta1out t t l t h when tmp91c820a 2008-02-20 91c820a-125 in this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (uc0) matches the value in one of the timer registers ta0reg or ta1reg. the value set in ta0reg must be smaller than the value set in ta1reg. although the up counter for tmra1 (uc1) is not used in this mode, ta01run |