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as4lc1m16e5 3v 1m16 cmos dram (edo) alliance semiconductor

alliance semiconductor p. . selection guide symbol -50 -60 unit maximum ras access time t rac 50 60 ns maximum column address access time t aa 25 30 ns maximum cas access time t cac 12 15 ns maximum output enable (oe ) access time t oea 13 15 ns minimum read or write cycle time t rc 80 100 ns minimum hyper page mode cycle time t hpc 20 25 ns maximum operating current i cc1 140 130 ma maximum cmos standby current i cc5 1.0 1.0 ma pin designation pin(s) description a0 to a9 address inputs ras row address strobe dq1 to dq16 input/output oe output enable we write enable ucas column address strobe, upper byte lcas column address strobe, lower byte v cc power v ss ground pin arrangement 42 41 40 39 38 37 36 35 34 33 v dq16 dq15 dq14 dq13 v dq12 dq11 dq10 dq9 ! 32 31 30 29 28 27 26 25 24 23 nc lcas ucas oe a9 a8 a6 a5 a4 v 1 2 3 4 5 6 7 8 9 10 vcc dq1 dq2 dq3 "#$ vcc dq5 dq6 dq7 dq8 11 12 13 14 15 16 17 18 19 20 nc nc we ras nc nc a0 a1 a2 a3 22 21 vcc a7 v dq1 dq2 dq dq4 v dq5 dq6 dq7 dq8 nc nc v dq16 dq15 dq14 dq13 v dq12 dq11 dq10 dq9 nc nc lcas ucas oe 50 49 48 47 46 45 44 43 42 41 40 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 % &
23 24 25 28 27 26 nc we ras nc nc a0 a1 a2 a3 v a9 a8 a7 a6 a5 a4 v features ? organization: 1,048,576 words 16 bits high speed - 50/60 ns ras access time - 20/25 ns hyper page cycle time - 12/15 ns cas access time low power consumption - active: 500 mw max (-60) - standby: 3.6 mw max, cmos dq extended data out 1024 refresh cycles, 16 ms refresh interval -ras -only or cas -before-ras refresh or self-refresh read-modify-write ttl-compatible, three-state dq jedec standard package and pinout - 400 mil, 42-pin soj - 400 mil, 44/50-pin tsop 2 3v power supply (as4lc1m16e5) 5v tolerant i/os; 5.5v maximum v ih industrial and commercial temperature available

alliance semiconductor p. functional description the as4lc1m16e5 is a high performance 16 -megabit cmos dynamic random access me mory (dram) organized as 1,048,576 words 16 bits. the device is fabricated using advanced cmos technology an d innovative design techniques resulting in high speed, extreme ly low power and wide operating margins at component and system levels. the alliance 16mb dram family is optimized for use as main memory in personal and portable pcs, workstations, and multimedia and router switch applications. the as4lc1m16e5 features hyper page mode operation where read an d write operations within a single row (or page) can be execute d at very high speed by toggling column addresses wi thin that row. row and column addresses are alternately latched into input buffers us ing the falling edge of ras and xcas inputs, respectively. also, ras is used to make the column address latch transparent, enabling application of column addresses prior to xcas assertion. the as4lc1m16e5 provides dual ucas and lcas for independent byte control of read and write access. extended data out (edo), also known as 'hyp er-page mode,' enables high speed operation. in contrast to 'fast-page mode' devices , data remains active on outputs after xcas is de-asserted high, giving system lo gic more time to latch the data. use oe and we to control output impedance and prevent bus contention during read-modify-write and shared bus applications. outputs also go to high impedance at the last occurrance of ras and xcas going high. refresh on the 1024 address combinations of a0 to a9 must be performed every 16 ms using: ras -only refresh: ras is asserted while xcas is held high. each of the 1024 rows must be strobed. outputs remain high impedence. hidden refresh: xcas is held low while ras is toggled. outputs remain low impedence with previous valid data. cas -before-ras refresh (cbr): at least one xcas is asserted prior to ras . refresh address is generated internally. outputs are high-impedence (oe and we are don't care). normal read or write cycles refresh the row being accessed. self-refresh cycles the as4lc1m16e5 is available in the standard 42-pin plastic soj and 44/50-pin tsop 2 packages, respectively. the as4lc1m16e5 de vice operates with a single power supply of 3v 0.3v and provides ttl compatible inputs and outputs. logic block diagram recommended operating conditions 1 1 recommended operating conditions apply throughout this document unless otherwise specified. parameter symbol min nominal max unit supply voltage v cc 3.0 3.3 3.6 v gnd 0.0 0.0 0.0 v input voltage v ih 2.0 ? 5.5 v v il ?0.5 2 2 v il min -3.0v for pulse widths less than 5 ns. ?0.8v ambient operating temperature commercial t a 0?70 c industrial -40 ? 85 ras clock generator refresh controller 1024 1024 16 array (16,777,216) sense amp a0 a1 a2 a3 a4 a5 a6 a7 v cc gnd address buffers a8 row decoder column decoder substrate bias generator data dq buffers oe ras ucas we clock generator we lcas dq1 to dq16 cas clock generator a9

alliance semiconductor p. absolute maximum ratings parameter symbol min max unit input voltage v dq -1.0 +5.5 v power supply voltage v cc -1.0 +4.0 v storage temperature (plastic) t stg -65 +150 c soldering temperature time t solder ?260 10 o c sec power dissipation p d ?0.6w short circuit output current i out ?50ma truth table operation ras lcas ucas we oe addresses dq0 to dq15 notes t r t c standby h h to x h to x x x x x high-z word read l l l h l row col data out lower byte read llhhlrowcol lower byte, upper byte, data out upper byte read l h l h l row col lower byte, data out, upper byte word (early) write l l l l x row col data in lower byte (early) write l l h l x row col lower byte, data in, upper byte, high-z upper byte(early) write l h l l x row col lower byte, high-z, upper byte, data in read write l l l h to l l to h row col data out, data in 1,2 edo read 1st cycle l h to l h to l h l row col data out 2 2nd cycle l h to l h to l h l n/a col data out 2 any cycle l l to h l to h h l n/a n/a data out 2 edo write 1st cycle l h to l h to l l x row col data in 1 2nd cycle l h to l h to l l x n/a col data in 1 edo read write 1st cycle l h to l h to l h to l l to h row col data out, data in 1,2 2nd cycle l h to l h to l h to l l to h n/a col data out, data in 1,2 ras only refresh l h h x x row n/a high z cbr refresh h to l l l h x x x high z 3 self refresh h to l l l h x x x high z 3

alliance semiconductor p. dc electrical characteristics parameter symbol test conditions -50 -60 unit notes min max min max input leakag e c urrent i il 0v v in v cc (max) pins not under test = 0v -2 +2 -2 +2 a output leakage current i ol d out disabled, 0v v out v cc (max) -2+2-2+2 a operating power supply current i cc1 ras , ucas , lcas , address cycling; t rc =min ? 140 ? 130 ma 4,5 ttl standby power supply current i cc2 ras = ucas = lcas v ih , all other inputs at v ih or v il ?2.0?2.0ma average power supply current, ras refresh mode or cbr i cc3 ras cycling, ucas = lcas v ih , t rc = min of ras low after xcas low. ? 130 ? 120 ma 4 edo page mode average power supply current i cc4 ras = v il , ucas or lcas, address cycling: t hpc = min ? 100 ? 90 ma 4, 5 cmos standby power supply current i cc5 ras = ucas = lcas = v cc - 0.2v, f = 0 ?1?1ma output voltage v oh i out = -2.0 ma 2.4 ? 2.4 ? v v ol i out = 2.0 ma ?0.4?0.4v cas before ras refresh current i cc6 ras , ucas or lcas cycling, t rc = min ? 130 ? 120 ma self refresh current i cc7 ras = ucas = lcas 0.2v, we = oe v cc - 0.2v, all other inputs at 0.2v or v cc - 0.2v ?0.5?0.5 ma

alliance semiconductor p. ac parameters common to all waveforms symbol parameter -50 -60 unit notes min max min max t rc random read or write cycle time 80 ? 100 ? ns t rp ras precharge time 30 ? 40 ? ns t ras ras pulse width 50 10k 60 10k ns t cas cas pulse width 8 10k 10 10k ns t rcd ras to cas delay time 15 35 15 43 ns 9 t rad ras to column address delay time 9 25 10 30 ns 10 t rsh cas to ras hold time 10 ? 10 ? ns t csh ras to cas hold time 40 ? 50 ? ns t crp cas to ras precharge time 5 ? 5 ? ns t asr row address setup time 0 ? 0 ? ns t rah row address hold time 8 ? 10 ? ns t t transition time (rise and fall) 1 50 1 50 ns 7,8 t ref refresh period ? 16 ? 16 ms 6 t cp cas precharge time 8 ? 10 ? ns t ral column address to ras lead time 25 ? 30 ? ns t asc column address setup time 0 ? 0 ? ns t cah column address hold time 8 ? 10 ? ns read cycle symbol parameter -50 -60 unit notes min max min max t rac access time from ras ? 50 ? 60 ns 9 t cac access time from cas ? 12 ? 15 ns 9,16 t aa access time from address ? 25 ? 30 ns 10,16 t rcs read command setup time 0 ? 0 ? ns t rch read command hold time to cas 0 ? 0 ? ns 12 t rrh read command hold time to ras 0 ? 0 ? ns 12

alliance semiconductor p. write cycle symbol parameter -50 -60 unit notes min max min max t wcs write command setup time 0 ? 0 ? ns 14 t wch write command hold time 10 ? 10 ? ns 14 t wp write command pulse width 10 ? 10 ? ns t rw l write command to ras lead time 13 ? 15 ? ns t cwl write command to cas lead time 8 ? 10 ? ns t ds data-in setup time 0 ? 0 ? ns 15 t dh data-in hold time 8 ? 10 ? ns 15 read-modify-write cycle symbol parameter -50 -60 unit notes min max min max t rw c read-write cycle time 113 ? 135 ? ns t rw d ras to we delay time 67 ? 77 ? ns 14 t cwd cas to we delay time 32 ? 35 ? ns 14 t awd column address to we delay time 42 ? 47 ? ns 14 refresh cycle symbol parameter -50 -60 unit notes min max min max t csr cas setup time (cas -before-ras ) 5 ? 5 ? ns 6 t chr cas hold time (cas -before-ras ) 8 ? 10 ? ns 6 t rpc ras precharge to cas hold time 0 ? 0 ? ns t cpt cas precharge time (cbr counter test) 10 ? 10 ? ns

alliance semiconductor p. 1 hyper page mode cycle symbol parameter -50 -60 unit notes min max min max t cpwd cas precharge to we delay time 45 ? 52 ? ns t cpa access time from cas precharge ? 28 ? 35 ns 16 t rasp ras pulse width 50 100k 60 100k ns t doh previous data hold time from cas 5?5?ns t rez output buffer turn off delay from ras 013015ns t wez output buffer turn off delay from we 013015ns t oez output buffer turn off delay from oe 013015ns t hpc hyper page mode cycle time 20 ? 25 ? ns t hprwc hyper page mode rmw cycle 47 ? 56 ? ns t rhcp ras hold time from cas 30 ? 35 ? ns output enable symbol parameter -50 -60 unit notes min max min max t clz cas to output in low z 0 ? 0 ? ns 11 t roh ras hold time referenced to oe 8 ? 10 ? ns t oea oe access time ? 13 ? 15 ns t oed oe to data delay 13 ? 15 ? ns t oez output buffer turnoff delay from oe 013015ns11 t oeh oe command hold time 10 ? 10 ? ns t olz oe to output in low z 0 ? 0 ? ns t off output buffer turn-off time 0 13 0 15 ns 11,13 self refresh cycle std symbol parameter -50 -60 unit notes min max min max t rass ras pulse width (cbr self refresh) 100 ? 100 ? s t rps ras precharge time (cbr self refresh) 90 ? 105 ? ns t chs cas hold time (cbr self refresh) 8?10?ns

alliance semiconductor p. ac test conditions notes 1 write cycles may be byte write cycles (either lcas or ucas active). 2 read cycles may be byte read cycles (either lcas or ucas active). 3one cas must be active (either lcas or ucas ). 4i cc1 , i cc3 , i cc4 , and i cc6 are dependent on frequency. 5i cc1 and i cc4 depend on output loading. specified values are obtained with the output open. 6 an initial pause of 200 s is required after power-up followed by any 8 ras cycles before proper device operation is achieved. in the case of an internal refresh counter, a minimum of 8 cas -before-ras initialization cycles instead of 8 ras cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). 7 ac characteristics assume t t = 2 ns. all ac parameters are measured with a load as described in ac test conditions below. 8v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il . 9 operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the speci- fied t rcd (max) limit, then access time is controlled exclusively by t cac . 10 operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as a reference point only. if t rad is greater than the spec- ified t rad (max) limit, then access time is controlled exclusively by t aa . 11 assumes three state test load (5 pf and a 380 ? thevenin equivalent). 12 either t rch or t rrh must be satisfied for a read cycle. 13 t off (max) defines the time at which the output achieves the open circ uit condition; it is not referenced to output voltage levels. t off is referenced from ris- ing edge of ras or cas , whichever occurs last. 14 t wcs , t wch , t rwd , t cwd and t awd are not restrictive operating parameters. they are includ ed in the datasheet as electrical characteristics only. if t ws t ws (min) and t wh t wh (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. if t rwd t rwd (min), t cwd t cwd (min) and t awd t awd (min), the cycle is a read-write cycle and the da ta out will contain data read from the selected cell. if neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 15 these parameters are referenced to cas leading edge in early write cycles and to we leading edge in read-write cycles. 16 access time is determined by the longest of t caa or t cac or t cpa 17 t asc t cp to achieve t pc (min) and t cpa (max) values. 18 these parameters are sampled and not 100% tested. - access times are measured with output reference levels of v oh = 2.0v and v ol = 0.8v, v ih = 2.0v and v il = 0.8v - input rise and fall times: 2 ns *including scope and jig capacitance 50 pf* r2 = 295 ? r1 = 828 ? d out gnd +3.3v equivalent output load

alliance semiconductor p. key to switc hing waveforms read waveform undefined output/don?t care falling input rising input t ras t rc t rp t rsh t rad t rch t roh t cac t oea t off (see note 11) t oez ras ucas address we oe dq column address t crp t csh t rcd t asc t cah t cas t ral t rah t rcs t aa t clz t rrh data out t rac t asr lcas row address t roh t wez t olz t rez

alliance semiconductor p. upper byte read waveform lower byte read waveform t ras t rc t rp t crp t rcd t rsh t csh t crp t crp t asr t rah t rad t ral t cah t rcs t rrh t rch t clz t cac t off row data out ras ucas lcas address we oe upper dq lower dq t roh t asc t rac t oea taa t cas t oez column t rez t wez t olz t rpc t ras t rc t rp t rcd t rsh t crp t asr t rah t rad t ral t cah t rrh t rch t clz t cac t rac t off data out ras lcas ucas address we oe upper dq lower dq t csh t asc t rcs t roh t oea t aa t cas t crp t crp row t oez column t olz t rez t wez t rpc

alliance semiconductor p. early write waveform upper byte early write waveform t ras t rc t rp t crp t rsh t rcd t csh t cas t rad t asc t cah t wcs t cwl t rwl t wch t wp t ds t dh data in ras ucas , address we oe dq row address t ral column address t rah t asr lcas t ras t rc t rp t rah t rad t asc t cah t rsh t rcd t csh t crp t rpc t rwl t wcs t wp t ds t dh column address data in ras address ucas lcas we oe upper dq lower dq t asr t ral t cwl row address t crp t crp t wch t cas

alliance semiconductor p. lower byte early write waveform write waveform oe controlled t rc t ras t rp t rad t crp t rpc t crp t asc t cah t rsh t rcd t csh t rwl t wp t wcs t wch t ds t dh row address column address data in ras address ucas lcas we oe upper dq lower dq t cwl t rah t cas t asr t ral t crp row address t ras t rc t rp t crp t rsh t rcd t csh t cas t rah t ral t rad t cah t cwl tr wl t oeh t ds t dh data in ras ucas , address we oe dq column address t wp t asc t asr lcas t oed

alliance semiconductor p. upper byte write waveform oe controlled lower byte write waveform oe controlled t ras t rc t rp t ral t rad t asc t cah t csh t crp t crp t rpc t rwl t wp t oeh t ds t dh t oed row address column address data in ras address ucas lcas we oe upper dq lower dq t crp t rah t rcd t cas t rsh t cwl t asr t rc t ras t rp t rah t rad t acs t cah t rsh t csh t crp t crp t rpc t rwl t wp t oeh t ds t dh row address column address data in ras address lcas ucas we oe upper dq lower dq t crp t rcd t cas t cwl t ral t asr

alliance semiconductor p. read-modify-write waveform upper byte read-modify-write waveform t ras t rwc t rp t crp t rsh t rcd t csh t cas t rad t ral t ar t cah t cwl t cwd t rwl t awd t wp t oea t clz t cac t aa t ds t dh row address column address data in data out ras ucas address we oe dq t rah t rwd t rcs t rac t oez t oed t asc t asr lcas t olz t rwc t ras t rp t crp t rsh t rcd t csh t cas t crp t crp t rpc t ral t rad t cah t rwl t awd t wp t cwd t oea t ds t clz t aa t rac t cac t oez t oed data in data out ras ucas lcas address we oe upper input upper output lower input t acs t rwd t cwl t oed t rcs t rah t asr row column address t olz t dh lower output

alliance semiconductor p. lower byte read-modify-write waveform hyper page mode read waveform t rwc t ras t rp t crp t rpc t crp t rsh t rcd t csh t cas t crp t ral t rad t rcs t oea t oed t ds t clz t oez row column address data in data out ras ucas lcas address we oe upper input upper output lower input lower output t rah t awd t cwl t cwd t cac t rwd t asr t aa t rac t acs t cah t rwl t wp t dh t olz t oed row t rasp t rp t crp t rcd t cas t csh t rsh t hpc t asr t rad t rrh t oea t oea t aa t rac t cac t oez data out data out data out col address col address ras ucas , address we oe dq t ar t rah t asc t cah t ral t rcs t clz t cp lcas t off t oez col address t rch t cpa t rhcp t clz t clz t olz t cpa

alliance semiconductor p. hyper page mode by te write waveform hyper page mode ea rly write waveform t rasp t rp t cas t csh t rsh t cas t crp t crp t cp t cas t cp t rpc t rah t rad t asc t cah t asc t oea t cac t rac t oez t clz t aa t cac t cpa t off t oez row column 1 column 2 column n data out 1 data out n data out 2 ras ucas lcas address we oe lower dq upper dq t clz t cpa t aa t clz t cac t oea t rcs t oea t cah t ral t hpc t hpc t cah t asc t rcd t asr t crp t aa t oez t olz t olz t olz t rch t rrh t rah t rasp t rwl t asc t wcs t cp t ral t wch t cwl t wp t ds t dh t oed t cas col address col address col address data in data in data in ras ucas , address we oe dq t pc t cah t csh t rcd t oeh t hdr t ar t rad t asr t crp lcas t rsh row address

alliance semiconductor p. hyper page mode byte early writ e waveform hyper page mode read -modify-write waveform t rasp t rp t cas t csh t crp t cp t cp t rad t asc t ral t wcs t wcs t wcs t ds t ds t dh t ds t dh row column 1 column 2 column n data in 1 data in n data in 2 ras ucas lcas address we oe lower dq upper dq t pc t rah t wch t wp t wp t cwl t wp t cah t rcd t pc t asr t crp t asc t asc t cas t rsh t cas t cah t wch t cah t rpc t crp t rwl t cwl t wch t cwl t dh t rasp t rp t rcd t csh t cas t cp t crp t asr t cah t cah t ral t cah t cwd t awd t cwd t cwl t cwd t awd t rwl t wp t oez t oea t rac t ds t clz t cac t cpa row ad col ad col address col ad data out data in data in data out data out data in ras ucas , address we oe dq t rad t rah t rwd t rcs t cwl t oea t aa t dh t ds t clz t cac t clz t cac t oed t hprwc lcas t cpwd t asc t asc t asc

alliance semiconductor p. cas before ras refresh waveform we = v ih ras only refresh waveform we = oe = v ih or v il t rp t rc t ras t rpc t cp t csr t chr ras ucas , dq lcas open t ras t rp t rc t crp t rpc t asr t rah row address ras address ucas , lcas

alliance semiconductor p. hyper page mode byte re ad-modify-write waveform t rasp t rcd t csh t cp t cah t asc t cah t asc t ral t cwl t cwl t wp t rwl t oea t dh t oez t dh t clz t cac t aa t cpa t oez data out 1 data in n data out n data out 2 data in 2 rc 1 c 2 c n ras ucas lcas address we oe upper input upper output lower input lower output t cas t rsh t cas t cah t awd t asc t wp t cwl t wp t oea t oea t oed t ds t cpa t ds t oed t dh t oez t clz t oed t ds t aa t cac t clz t crp t rad t rah t asr t rac data in 1 t aa t cac t cas t cp t crp t rp t awd t awd t rwd t cwd t cwd t cwd t cpwd t cpwd t awd t awd t cah

alliance semiconductor p. hidden refresh waveform (read) hidden refresh wa veform (write) t ras t rc t rp t ras t rc t rp t crp t rcd t rsh t crp t chr t asr t rad t asc t rrh t oea t clz t cac t oez col address row data out ras cas address we oe dq t ar t rah t rac t aa t rcs t cah t off t ras t rc t rp t crp t rcd t rsh t asr t rah t rad t ar t cah t wcs t wch t ds t dh data in col address row address ras ucas , address we dq oe t asc t rwl t wcr t wp t dhr t ral lcas t chr

alliance semiconductor p. cas before ras refresh counter test waveform t ras t rsh t rp t csr t chr t cpt t cas t cah t clz t cac t rch t rrh t roh t oea t rwl t cwl t wcs t wp t wch t ds t dh t rcs t oea t ds t dh col address data out data in data out data in ras ucas , address dq we oe we dq oe we oe dq t oed t aa t clz t cac t oez t wp t cwl t rcs t aa t oez t awd t cwd t ral read cycle write cycle read-write cycle lcas t asc t off t rwl

alliance semiconductor p. cas -before- ras self refresh cycle '& ' '& & ( )* ' + ,
"# - '& ' '&

alliance semiconductor p. package dimensions
seating plane 42-pin soj min max a 0.128 0.148 a1 0.025 - a2 0.105 0.115 b 0.026 0.032 b 0.015 0.020 c 0.007 0.013 d 1.070 1.080 e 0.370 nom e1 0.395 0.405 e2 0.435 0.445 e 0.050 nom soj 50-pin tsop 2 min (mm) max (mm) a1.2 a 1 0.05 a 2 0.95 1.05 b 0.30 0.45 c 0.12 0.21 d 20.85 21.05 e 10.03 10.29 h e 11.56 11.96 e 0.80 (typical) l 0.40 0.60 d h e 1234567891011 50 49 48 47 46 45 44 43 42 41 40 15 16 36 35 17 18 19 20 34 33 32 31 c l a 1 a 2 e tsop 2 0?5 21 30 22 23 24 25 29 28 27 26 e a b

? copyright alliance semiconductor corporation. all rights rese rved. our three-point logo, our name and intelliwatt are trademark s or registered trademarks of alliance. all o ther brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time withou t notice. alliance assumes no responsibility for an y errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to chang e or correct this data at any time, without notice. if the product described herein is under development, significant changes to the se specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herei n, and disclaims any express or implied warranties related to the sale and/or use of alliance products including li ability or warranties related to fitness for a particular purpo se, merchantability, or infringement of any intellectua l property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusivel y according to alliance's terms and conditions of sa le. the purchase of products from alliance does not convey a license under any patent rights, copyrights, mask wo rks rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authori ze its products for use as critical components in life- supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and t he inclusion of alliance products in such life-suppo rting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alli ance against all claims arising from such use.

alliance semiconductor p. capacitance parameter symbol signals test conditions max unit input capacitance c in1 a0 to a9 v in = 0v 5 pf c in2 ras , ucas , lcas , we , oe v in = 0v 7 pf dq capacitance c dq dq0 to dq15 v in = v out = 0v 7 pf as4lc1m16e5 ordering information package \ ras access time 50 ns 60 ns plastic soj, 400 mil, 42-pin AS4LC1M16E5-50JC as4lc1m16e5-50ji as4lc1m16e5-60jc as4lc1m16e5-60ji tsop 2, 400 mil, 44/50-pin as4lc1m16e5-50tc as4lc1m16e5-50ti as4lc1m16e5-60tc as4lc1m16e5-60ti as4lc1m16e5 part numbering system as4 lc 1m16e5 ?xx x x dram prefix c = 5v cmos lc = 3.3v cmos device number ras access time package: j = 42-pin soj 400 mil t = 44/50-pin tsop 2 400 mil temperature range c=commercial, 0c to 70c i=industrial, -40c to 85c ? = 1 mhz, t a = room temperature

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