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| hys72t64000hr?[3.7/5]?b hys72t1280x0hr?[3.7/5]?b hys72t256220hr?[3.7/5]?b 240-pin registered ddr2 sdram modules rdimm sdram ddr2 sdram rohs compliant data sheet, rev. 1.10, mar. 2006 memory products
edition 2006-03 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2006. all rights reserved. attention please! the information herein is given to describe certain co mponents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology , delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. template: mp_a4_s_rev321 / 3 / 2005-10-05 hys72t64000hr?[3.7/5]?b, hys72t1280x0hr? [3.7/5]?b, hys72t256220hr?[3.7/5]?b, revision history: 2006-03 , 1.10 page subjects (major cha nges since last revision) previous revision: 2005-07,1.00 5 removed product types for ddr800,drr667 thes e are to be found in a separate data sheet 8 removed ddr800, ddr667 raw card figures 23 , 25 , 35 , 36 removed ddr800, ddr667 tables 45 removed ddr800, ddr667 package outlines we listen to your comments any information within this do cument that you feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send us your proposal (including a reference to this document) to: techdoc.mp@infineon.com hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram data sheet 4 rev. 1.10, 2006-03 05112005-ymix-kuoq 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin configuration and block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.1 speed grade definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.2 ac timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.3 odt ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4 i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.1 i dd test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.4.2 on die termination (odt) cu rrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6 product type nomenclature (ddr2 drams and dimms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table of contents data sheet 5 rev. 1.10, 2006-03 05112005-ymix-kuoq 240-pin registered ddr2 sdram modules rdimm sdram hys72t64000hr?[3.7/5]?b hys72t1280x0hr?[3.7/5]?b hys72t256220hr?[3.7/5]?b 1 overview this chapter gives an overview of the 1.8 v 24 0-pin registered ddr2 sdram modules product family and describes its main characteristics. 1.1 features ? 240-pin pc2?6400, pc2?5300pc2?4200 and pc2?3200 ddr2 sdram memory modules for pc, workstation and server main memory applications. ? one rank 64m 72, 128m 72, and two ranks 128m 72, 256m x72 module organization, and 512m 8, 512m 4 chip organization ? standard double-data-rate-two synchronous drams (ddr2 sdram) with a single + 1.8 v ( 0.1 v) power supply ? built with 512 mbit ddr2 sdrams in p-tfbga-60 chipsize packages. ? programmable cas latencies (3, 4, 5, 6), burst length (4 & 8) and burst type ? auto refresh (cbr) and self refresh ? programmable self refresh rate via emrs2 setting ? programmable partial array refresh via emrs2 settings ? dcc enabling via emrs2 setting ? all inputs and outputs sstl_18 compatible ? off-chip driver impedance adjustment (ocd) and on-die termination (odt) ? serial presence detect with e 2 prom ? rdimm dimensions (nominal): 30,00 mm high, 133.35 mm wide ? based on standard reference card layouts raw card ?a?, ?b?, ?c?, ?j? ? all speed grades faster than ddr400 comply with ddr400 timing specifications. ? rohs compliant products 1) 1) rohs compliant product: restriction of the use of certain hazardous substances (rohs) in electrical and electronic equipment as defined in the directive 2 002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include mercury, lead, cadmiu m, hexavalent chromium, po lybrominated biphenyls and polybrominated biphenyl ethers. table 1 performance for pc2?4200?444 product type speed code ?3.7 unit speed grade pc2?4200 4?4?4 ? max. clock frequency @cl5 f ck5 266 mhz @cl4 f ck4 266 mhz @cl3 f ck3 200 mhz min. ras-cas-delay t rcd 15 ns min. row precharge time t rp 15 ns min. row active time t ras 45 ns min. row cycle time t rc 60 ns hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram overview data sheet 6 rev. 1.10, 2006-03 05112005-ymix-kuoq 1.2 description the infineon hys72t[64/128/256]xxxhr?[3.7/5]?b module family are registered dimm modules with 30,0 mm height based on ddr2 technology. dimms are available as ecc modules in 64m 72 (512 mb), 128m 72 (1 gb), 256m x72 (2gb) organization and density, intende d for mounting into 240-pin connector sockets. the memory array is designed with 512-mbit double-dat a-rate-two (ddr2) synchronous drams. all control and address signals are re-driven on the dimm using register devices and a pll for the clock distribution. this reduces capacitive loading to the system bus, but adds one cycle to the sdram timing. decoupling capacitors are mounted on the pcb board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. table 2 high performance for pc2-3200 product type speed code ?5 unit speed grade pc2-3200 3?3?3 ? max. clock frequency @cl5 f ck5 200 mhz @cl4 f ck4 200 mhz @cl3 f ck3 200 mhz min. ras-cas-delay t rcd 15 ns min. row precharge time t rp 15 ns min. row active time t ras 40 ns min. row cycle time t rc 55 ns table 3 ordering information for rohs compliant products product type 1) 1) all part numbers end with a place code, designating the si licon die revision. example: hys72t64000hr?3.7?b, indicating rev. ?b? dies are used for ddr2 sdram components. for a ll infineon ddr2 module and component nomenclature see chapter 6 of this data sheet. compliance code 2) 2) the compliance code is printed on the module label and describes the speed grade, for example ? pc2?4200r?444? 12?a0 ?, where 4200r means registered dimm modules with 4.26 gb /sec module bandwidth and ?444-12? means column address strobe (cas) latency = 4, row column delay (rcd) latency = 4 and row precharge (rp) latency = 4 using the latest jedec spd revision 1.2 and produced on the raw card ?a? description sdram technology pc2 ? 4200 hys72t64000hr?3.7?b 512 mb 1rx8 pc2-4200r-444-12-a0 1 rank ecc 512 mbit ( 8) hys72t128000hr?3.7?b 1 gb 1rx4 pc2-4200r-444-12-c0 1 rank ecc 512 mbit ( 4) hys72t128020hr?3.7?b 1 gb 2rx8 pc2-4200r-444-12-b0 2 ranks, ecc 512 mbit ( 8) hys72t256220hr?3.7?b 2 gb 2rx4 pc2-4200r-444-12-j1 2 ranks, ecc 512 mbit ( 4) pc2 ? 3200 hys72t64000hr?5?b 512 mb 1rx8 pc2-3200r-333-12-a0 1 rank ecc 512 mbit ( 8) hys72t128000hr?5?b 1 gb 1rx4 pc2-3200r-333-12-c0 1 rank ecc 512 mbit ( 4) hys72t128020hr?5?b 1 gb 2rx8 pc2-3200r-333-12-b0 2 ranks, ecc 512 mbit ( 8) hys72t256220hr?5?b 2 gb 2rx4 pc2-3200r-333-12-j1 2 ranks, ecc 512 mbit ( 4) data sheet 7 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram overview table 4 address format dimm density module organization memory ranks ecc/ non-ecc # of sdrams # of row/bank/column bits raw card 512 mb 64m 72 1 ecc 9 14/2/10 f 1gb 128m 72 1 ecc 18 14/2/11 h 1gb 128m 72 2 ecc 18 14/2/10 g 2gb 256m 72 2 ecc 36 14/2/11 j table 5 components on modules 1) 1) for a detailed description of all functionalities of the dra m components on these modules see the component data sheet. product type 2) 2) green product dram components 2) dram density dram organisation hys72t64000hr hyb18t512800bf 512 mbit 512m 8 hys72t128000hr hyb18t512400bf 512 mbit 512m 4 hys72t128020hr hyb18t512800bf 512 mbit 512m 8 hys72t256220hr hyb18t512400bf 512 mbit 512m 4 hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram pin configuration and block diagrams data sheet 8 rev. 1.10, 2006-03 05112005-ymix-kuoq 2 pin configuration and block diagrams 2.1 pin configuration the pin configuration of the registered ddr2 sdram dimm is listed by function in table 6 (240 pins). the abbreviations used in columns pin and buffer type are explained in table 7 and table 8 respectively. the pin numbering is depicted in figure 1 . table 6 pin configuration of rdimm pin or ball no. name pin type buffer type function clock signals 185 ck0 i sstl clock signal ck0, complementary clock signal ck0 the system clock inputs. all address and command lines are sampled on the cross point of the rising edge of ck and the falling edge of ck . a delay locked loop (dll) circuit is driven from the clock inputs and output timing fo r read operations is synchronized to the input clock. 186 ck0 isstl 52 cke0 i sstl clock enables 1:0 activates the ddr2 sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke0 initiates the power down mo de or the self refresh mode. note: 2-ranks module 171 cke1 i sstl nc nc ? not connected note: 1-rank module control signals 193 s0 isstl chip select rank 1:0 enables the associated ddr2 sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. rank 0 is selected by s0 ; rank 1 is selected by s1 . the input signals also disable all outputs (except cke and odt) of the register(s) on the dimm when both inputs are high. when s is high, all register outputs (except ck, odt and chip select) remain in the previous state. note: 2-ranks module 76 s1 isstl nc nc ? not connected note: 1-rank module 192 ras isstl row address strobe (ras), co lumn address strobe (cas), write enable (we) when sampled at the cross point of the rising edge of ck, and falling edge of ck , ras , cas and we define the operation to be executed by the sdram. 74 cas isstl 73 we isstl data sheet 9 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram pin configuration and block diagrams 18 reset icmos register reset the reset pin is connected to the rst pin on the register and to the oe pin on the pll. when low, all register outputs will be driven low and the pll clocks to the drams and the register(s) will be set to low-level. the pl l will remain synchronized with the input clock. address signals 71 ba0 i sstl bank address bus 1:0 selects internal sdram memory bank 190 ba1 i sstl 54 ba2 i sstl bank address bus 2 greater than 512mb ddr2 sdrams nc i sstl not connected less than 1gb ddr2 sdrams 188 a0 i sstl address bus 12:0, address signal 10/autoprecharge during a bank activate command cycle, defines the row address when sampled at the cro sspoint of the rising edge of ck and falling edge of ck . during a read or write command cycle, defines the column address when sampled at the cross point of the rising edge of ck and falling edge of ck . in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba[ 1 :0] defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba[ 1 :0] to control which bank(s) to precharge. if ap is high, all ban ks will be precharged regardless of the state of ba[ 1 :0] inputs. if ap is low, then ba[ 1 :0] are used to define which bank to precharge. 183 a1 i sstl 63 a2 i sstl 182 a3 i sstl 61 a4 i sstl 60 a5 i sstl 180 a6 i sstl 58 a7 i sstl 179 a8 i sstl 177 a9 i sstl 70 a10 i sstl ap i sstl 57 a11 i sstl 176 a12 i sstl 196 a13 i sstl address signal 13 note: modules based on 4, 8 nc nc ? not connected note: modules based on 16 174 a14 i sstl address signal 14 note: 2 gbit based module nc nc ? not connected note: 1 gbit based module or smaller table 6 pin configuration of rdimm (cont?d) pin or ball no. name pin type buffer type function hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram pin configuration and block diagrams data sheet 10 rev. 1.10, 2006-03 05112005-ymix-kuoq data signals 3 dq0 i/o sstl data bus 63:0 data input/ output pins 4 dq1 i/o sstl 9 dq2 i/o sstl 10 dq3 i/o sstl 122 dq4 i/o sstl 123 dq5 i/o sstl 128 dq6 i/o sstl 129 dq7 i/o sstl 12 dq8 i/o sstl 13 dq9 i/o sstl 21 dq10 i/o sstl 22 dq11 i/o sstl 131 dq12 i/o sstl 132 dq13 i/o sstl 140 dq14 i/o sstl 141 dq15 i/o sstl 24 dq16 i/o sstl 25 dq17 i/o sstl 30 dq18 i/o sstl 31 dq19 i/o sstl 143 dq20 i/o sstl 144 dq21 i/o sstl 149 dq22 i/o sstl 150 dq23 i/o sstl 33 dq24 i/o sstl 34 dq25 i/o sstl 39 dq26 i/o sstl 40 dq27 i/o sstl 152 dq28 i/o sstl 153 dq29 i/o sstl 158 dq30 i/o sstl 159 dq31 i/o sstl 80 dq32 i/o sstl 81 dq33 i/o sstl 86 dq34 i/o sstl 87 dq35 i/o sstl 199 dq36 i/o sstl 200 dq37 i/o sstl 205 dq38 i/o sstl table 6 pin configuration of rdimm (cont?d) pin or ball no. name pin type buffer type function data sheet 11 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram pin configuration and block diagrams 206 dq39 i/o sstl data bus 63:0 89 dq40 i/o sstl 90 dq41 i/o sstl 95 dq42 i/o sstl 96 dq43 i/o sstl 208 dq44 i/o sstl 209 dq45 i/o sstl 214 dq46 i/o sstl 215 dq47 i/o sstl 98 dq48 i/o sstl 99 dq49 i/o sstl 107 dq50 i/o sstl 108 dq51 i/o sstl 217 dq52 i/o sstl 218 dq53 i/o sstl 226 dq54 i/o sstl 227 dq55 i/o sstl 110 dq56 i/o sstl 111 dq57 i/o sstl 116 dq58 i/o sstl 117 dq59 i/o sstl 229 dq60 i/o sstl 230 dq61 i/o sstl 235 dq62 i/o sstl 236 dq63 i/o sstl check bits 42 cb0 i/o sstl check bits 7:0 check bit input / output pins note: nc on non-ecc module 43 cb1 i/o sstl 48 cb2 i/o sstl 49 cb3 i/o sstl 161 cb4 i/o sstl 162 cb5 i/o sstl 167 cb6 i/o sstl 168 cb7 i/o sstl table 6 pin configuration of rdimm (cont?d) pin or ball no. name pin type buffer type function hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram pin configuration and block diagrams data sheet 12 rev. 1.10, 2006-03 05112005-ymix-kuoq data strobe bus 7dqs0i/osstl data strobes 17:0 the data strobes, associated with one data byte, sourced with data transfers. in write mode, the da ta strobe is sourced by the controller and is centered in the data window. in read mode the data strobe is sourced by the ddr2 sdram and is sent at the leading edge of the data window. dqs signals are complements, and timing is relative to the crossp oint of respective dqs and dqs. if the module is to be operated in single ended strobe mode, all dqs signals must be tied on the system board to v ss through a 20 ohm to 10 kohm resistor and ddr2 sdram mode registers programmed appropriately. note: see block diagram for corresponding dq signals 6dqs0 i/o sstl 16 dqs1 i/o sstl 15 dqs1 i/o sstl 28 dqs2 i/o sstl 27 dqs2 i/o sstl 37 dqs3 i/o sstl 36 dqs3 i/o sstl 84 dqs4 i/o sstl 83 dqs4 i/o sstl 93 dqs5 i/o sstl 92 dqs5 i/o sstl 105 dqs6 i/o sstl 104 dqs6 i/o sstl 114 dqs7 i/o sstl 113 dqs7 i/o sstl 46 dqs8 i/o sstl 45 dqs8 i/o sstl 126 dqs9 i/o sstl not connected note: 8 based dimms only nc nc ? not connected note: 4 based dimms 135 dqs10 i/o sstl not connected note: 8 based dimms only nc nc ? not connected note: 4 based dimms 147 dqs11 i/o sstl not connected note: 8 based dimms only nc nc ? not connected note: 4 based dimms 156 dqs12 i/o sstl not connected note: 8 based dimms only nc nc ? not connected note: 4 based dimms 203 dqs13 i/o sstl not connected note: 8 based dimms only nc nc ? not connected note: 4 based dimms table 6 pin configuration of rdimm (cont?d) pin or ball no. name pin type buffer type function data sheet 13 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram pin configuration and block diagrams 212 dqs14 i/o sstl not connected note: 8 based dimms only nc nc ? not connected note: 4 based dimms 224 dqs15 i/o sstl not connected note: 8 based dimms only nc nc ? not connected note: 4 based dimms 233 dqs16 i/o sstl not connected note: 8 based dimms only nc nc ? not connected note: 4 based dimms 165 dqs17 i/o sstl not connected note: 8 based dimms only nc nc ? not connected note: 4 based dimms 125 dqs9 i/o sstl data strobes 17:9 note: 4 based module 134 dqs10 i/o sstl 146 dqs11 i/o sstl 155 dqs12 i/o sstl 202 dqs13 i/o sstl 211 dqs14 i/o sstl 223 dqs15 i/o sstl 232 dqs16 i/o sstl 164 dqs17 i/o sstl 125 dm0 i sstl data masks 7:0 the data write masks, associated with one data byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. note: 8 based module 134 dm1 i sstl 146 dm2 i sstl 155 dm3 i sstl 202 dm4 i sstl 211 dm5 i sstl 223 dm6 i sstl 232 dm7 i sstl 164 dm8 i sstl table 6 pin configuration of rdimm (cont?d) pin or ball no. name pin type buffer type function hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram pin configuration and block diagrams data sheet 14 rev. 1.10, 2006-03 05112005-ymix-kuoq eeprom 120 scl i cmos serial bus clock this signal is used to clock data into and out of the spd eeprom. 119 sda i/o od serial bus data this is a bidirectional pin used to transfer data into or out of the spd eeprom. a resistor must be connected from sda to v ddspd on the motherboard to act as a pull-up. 239 sa0 i cmos serial address select bus 2:0 these signals are tied at the system planar to either v ss or v ddspd to configure the serial spd eeprom address range 240 sa1 i cmos 101 sa2 i cmos power supplies 1 v ref ai ? i/o reference voltage reference voltage for the sstl-18 inputs. 238 v ddspd pwr ? eeprom power supply serial eeprom positive power suppl y, wired to a separated power pin at the connector which suppor ts from 1.7 volt to 3.6 volt. 51, 56, 62, 72, 75, 78, 170, 175,, 181, 191, 194 v ddq pwr ? i/o driver power supply power and ground for the ddr sdram 53, 59, 64, 67, 69, 172, 178, 184,, 187, 189, 197 v dd pwr ? power supply power and ground for the ddr sdram 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 65, 66, 79, 82, 85, 88, 91, 94, 97, 100, 103, 106, 109, 112, 115, 118, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 169, 198, 201, 204, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237 v ss gnd ? ground plane power and ground for the ddr sdram table 6 pin configuration of rdimm (cont?d) pin or ball no. name pin type buffer type function data sheet 15 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram pin configuration and block diagrams other pins 19, 55, 68, 102, 137, 138, 173, 220, 221 nc nc ? not connected pins not connected on infineon rdimm?s 195 odt0 i sstl on-die termination control 1:0 asserts on-die termination for dq, dm, dqs, and dqs signals if enabled via the ddr2 sdram mode register. note: 2-ranks module 77 odt1 i sstl nc nc ? note: 1-rank modules table 7 abbreviations for buffer type abbreviation description sstl serial stub terminated logic (sstl_18) cmos cmos levels od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or. table 8 abbreviations for pin type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nu not usable nc not connected table 6 pin configuration of rdimm (cont?d) pin or ball no. name pin type buffer type function hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram pin configuration and block diagrams data sheet 16 rev. 1.10, 2006-03 05112005-ymix-kuoq figure 1 pin configuration for rdimm (240 pins) - 0 0 4 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 6 2 % & $ 1 6 3 3 $ 1 3 $ 1 6 3 3 $ 1 $ 1 3 6 3 3 . # 6 3 3 $ 1 $ 1 3 6 3 3 $ 1 $ 1 6 3 3 $ 1 3 2 % 3 % 4 6 3 3 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n $ 1 $ 1 6 3 3 $ 1 3 $ 1 6 3 3 $ 1 $ 1 3 6 3 3 $ 1 # " 6 3 3 $ 1 3 # " 6 3 3 # + % . # " ! 6 $ $ 1 ! ! 6 $ $ 1 6 $ $ 6 3 3 . # ! ! 0 6 $ $ 1 # ! 3 . # 3 6 $ $ 1 $ 1 6 3 3 $ 1 3 $ 1 6 3 3 $ 1 $ 1 3 6 3 3 $ 1 $ 1 6 3 3 . # $ 1 3 6 3 3 $ 1 $ 1 6 3 3 $ 1 3 $ 1 6 3 3 3 # , 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n $ 1 6 3 3 $ 1 $ 1 3 6 3 3 $ 1 $ 1 6 3 3 $ 1 3 $ 1 6 3 3 # " $ 1 3 6 3 3 # " 6 $ $ 1 6 $ $ . # ! 6 $ $ ! ! 6 3 3 6 $ $ 6 $ $ " ! 7 % 6 $ $ 1 . # / $ 4 6 3 3 $ 1 $ 1 3 6 3 3 $ 1 $ 1 6 3 3 $ 1 3 $ 1 6 3 3 $ 1 3 ! 6 3 3 $ 1 3 $ 1 6 3 3 $ 1 $ 1 3 6 3 3 $ 1 3 $ ! 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 6 3 3 $ 1 $ - $ 1 3 6 3 3 $ 1 $ 1 6 3 3 . # $ 1 3 . # 6 3 3 $ 1 6 3 3 . # $ 1 3 $ 1 6 3 3 $ 1 $ - $ 1 3 6 3 3 . # $ 1 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 6 3 3 $ 1 $ - $ 1 3 6 3 3 $ 1 $ 1 6 3 3 . # $ 1 3 $ 1 6 3 3 # " $ - $ 1 3 6 3 3 # " 6 $ $ 1 6 $ $ . # ! ! 6 $ $ ! ! 6 $ $ # + ! " ! 2 ! 3 6 $ $ 1 . # ! 6 3 3 $ 1 $ - $ 1 3 6 3 3 $ 1 $ 1 6 3 3 . # $ 1 3 $ 1 6 3 3 $ 1 . # 6 3 3 . # $ 1 3 $ 1 6 3 3 $ 1 $ - $ 1 3 6 3 3 $ 1 6 $ $ 3 0 $ 3 ! 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n $ 1 $ 1 6 3 3 . # $ 1 3 $ 1 6 3 3 $ 1 $ - $ 1 3 6 3 3 $ 1 # " 6 3 3 . # $ 1 3 # " 6 3 3 . # # + % . # 6 $ $ 1 ! ! 6 $ $ 1 ! # + 6 $ $ 6 $ $ 6 $ $ 1 3 / $ 4 6 $ $ $ 1 6 3 3 . # $ 1 3 $ 1 6 3 3 $ 1 $ - $ 1 3 6 3 3 $ 1 $ 1 6 3 3 . # $ - $ 1 3 6 3 3 $ 1 $ 1 6 3 3 . # $ 1 3 $ 1 6 3 3 3 ! & 2 / . 4 3 ) $ % " ! # + 3 ) $ % data sheet 17 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram pin configuration and block diagrams 2.2 block diagrams figure 2 block diagram raw card a rdimm (x72, 1 rank, x8) notes 1. unless otherwise noted, resistors are 22 ? 5% 2. s0 connects to dcs and v dd connects to csr on the register. - 0 " 4 $ $ $ $ $ $ $ $ $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 # " # " # " # " # " # " # " # " $ 0 , , / % 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + # + # + 2 % 3 % 4 6 $ $ 3 0 $ % % 0 2 / - % 6 $ $ 6 $ $ 1 3 $ 2 ! - s $ $ 6 2 % & 3 $ 2 ! - s $ $ 6 3 3 3 $ 2 ! - s $ $ 6 $ $ 3 0 $ 6 $ $ 6 $ $ 1 6 2 % & 6 3 3 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 # + 3 $ 2 ! - s $ $ # + 3 $ 2 ! - s $ $ # + 2 e g i s t e r # + 2 e g i s t e r 2 3 # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / 3 # , 3 $ ! 3 ! 3 ! 3 ! 6 3 3 % 3 # , 3 $ ! ! ! ! 7 0 2 % ' ) 3 4 % 2 2 3 2 " ! 2 " ! n 2 ! 2 ! n 2 2 ! 3 2 # ! 3 2 7 % 2 # + % 2 / $ 4 # 3 3 $ 2 ! - s $ $ " ! " ! n 3 $ 2 ! - s $ $ ! ! n 3 $ 2 ! - s $ $ 2 ! 3 3 $ 2 ! - s $ $ # ! 3 3 $ 2 ! - s $ $ 7 % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ / $ 4 3 $ 2 ! - s $ $ 3 " ! " ! n ! ! n 2 ! 3 # ! 3 7 % # + % / $ 4 0 # + 0 # + 2 % 3 % 4 hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram pin configuration and block diagrams data sheet 18 rev. 1.10, 2006-03 05112005-ymix-kuoq figure 3 block diagram raw card c rdimm (x72, 1 rank, x4) notes 1. unless otherwise noted, resistors are 22 ? 5% 2. s0 connects to dcs of register1 and csr of register2. 3. csr of register1 and dcs of register2 connects to v dd . 4. reset , pck7 and pck7 connect to both registers. - 0 " 4 $ $ $ $ $ $ $ $ $ 1 3 $ 1 3 # " # " # " # " 6 3 3 $ 0 , , / % 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + # + # + 2 % 3 % 4 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 # + 3 $ 2 ! - s $ $ # + 3 $ 2 ! - s $ $ # + 2 e g i s t e r # + 2 e g i s t e r 2 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 3 # , 3 $ ! 3 ! 3 ! 3 ! 6 3 3 % 3 # , 3 $ ! ! ! ! 7 0 2 % ' ) 3 4 % 2 2 3 2 " ! 2 " ! n 2 ! 2 ! n 2 2 ! 3 2 # ! 3 2 7 % 2 # + % 2 / $ 4 # 3 3 $ 2 ! - s $ $ " ! " ! n 3 $ 2 ! - s $ $ ! ! n 3 $ 2 ! - s $ $ 2 ! 3 3 $ 2 ! - s $ $ # ! 3 3 $ 2 ! - s $ $ 7 % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ / $ 4 3 $ 2 ! - s $ $ 3 " ! " ! n ! ! n 2 ! 3 # ! 3 7 % # + % / $ 4 0 # + 0 # + 2 % 3 % 4 # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - $ 1 3 $ 1 3 # " # " # " # " 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - $ $ $ # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - $ $ $ $ $ $ 6 $ $ 3 0 $ % % 0 2 / - % 6 $ $ 6 $ $ 1 3 $ 2 ! - s $ $ 6 2 % & 3 $ 2 ! - s $ $ 6 3 3 3 $ 2 ! - s $ $ 6 $ $ 3 0 $ 6 $ $ 6 $ $ 1 6 2 % & 6 3 3 data sheet 19 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram pin configuration and block diagrams figure 4 block diagram raw card b rdimm (x72, 2 ranks, x8) notes 1. unless otherwise noted, resistors are 22 ? 5% 2. rs0 and rs1 alternate between the back and front sides of the dimm. - 0 " 4 $ $ $ $ $ $ $ $ $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 # " # " # " # " # " # " # " # " $ $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 2 % ' ) 3 4 % 2 2 3 2 3 2 " ! 2 " ! n 2 ! 2 ! n 2 2 ! 3 2 # ! 3 2 7 % 2 # + % 2 # + % 2 / $ 4 2 / $ 4 # 3 3 $ 2 ! - s $ $ # 3 3 $ 2 ! - s $ $ " ! " ! n 3 $ 2 ! - s $ $ ! ! n 3 $ 2 ! - s $ $ 2 ! 3 3 $ 2 ! - s $ $ # ! 3 3 $ 2 ! - s $ $ 7 % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ / $ 4 3 $ 2 ! - s $ $ / $ 4 3 $ 2 ! - s $ $ 3 3 " ! " ! n ! ! n 2 ! 3 # ! 3 7 % # + % # + % / $ 4 / $ 4 0 # + 0 # + 2 % 3 % 4 2 3 # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / 3 # , 3 $ ! 3 ! 3 ! 3 ! 6 3 3 % 3 # , 3 $ ! ! ! ! 7 0 2 3 0 , , / % 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + # + # + 2 % 3 % 4 # + 3 $ 2 ! - s $ $ # + 3 $ 2 ! - s $ $ # + 2 e g i s t e r # + 2 e g i s t e r 6 $ $ 3 0 $ % % 0 2 / - % 6 $ $ 6 $ $ 1 3 $ 2 ! - s $ $ 6 2 % & 3 $ 2 ! - s $ $ 6 3 3 3 $ 2 ! - s $ $ 6 $ $ 3 0 $ 6 $ $ 6 $ $ 1 6 2 % & 6 3 3 # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram pin configuration and block diagrams data sheet 20 rev. 1.10, 2006-03 05112005-ymix-kuoq figure 5 block diagram raw card j rdimm (x72, 2ranks, x4) notes 1. unless otherwise noted, resistors are 22 ? 5% 2. rs0 and rs1 alternate between the bottom and surface sides of the dimm. 3. s0 connects to dcs and s1 connects to csr on a pair of registers. s1 connects to dcs and s0 connects to csr on another pair of registers. 4. reset , pck7 and pck7 connect to all registers. - 0 " 4 2 3 6 3 3 2 3 $ $ $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 # " # " # " # " $ $ $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ $ $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ $ $ $ $ $ $ $ $ $ $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 # " # " # " # " 0 , , / % 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + # + 3 $ 2 ! - s $ $ # + 3 $ 2 ! - s $ $ # + 2 e g i s t e r # + 2 e g i s t e r # + # + 2 % 3 % 4 3 # , 3 $ ! 3 ! 3 ! 3 ! 6 3 3 % 3 # , 3 $ ! ! ! ! 7 0 2 % ' ) 3 4 % 2 2 3 2 3 2 " ! 2 " ! n 2 ! 2 ! n 2 2 ! 3 2 # ! 3 2 7 % 2 # + % 2 # + % 2 / $ 4 2 / $ 4 # 3 3 $ 2 ! - s $ $ # 3 3 $ 2 ! - s $ $ " ! " ! n 3 $ 2 ! - s $ $ ! ! n 3 $ 2 ! - s $ $ 2 ! 3 3 $ 2 ! - s $ $ # ! 3 3 $ 2 ! - s $ $ 7 % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ / $ 4 3 $ 2 ! - s $ $ / $ 4 3 $ 2 ! - s $ $ 3 3 " ! " ! n ! ! n 2 ! 3 # ! 3 7 % # + % # + % / $ 4 / $ 4 0 # + 0 # + 2 % 3 % 4 6 $ $ 3 0 $ 6 $ $ 6 $ $ 1 6 2 % & 6 3 3 6 $ $ 3 0 $ % % 0 2 / - % 6 $ $ 6 $ $ 1 3 $ 2 ! - s $ $ 6 2 % & 3 $ 2 ! - s $ $ 6 3 3 3 $ 2 ! - s $ $ data sheet 21 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram electrical characteristics 3 electrical characteristics 3.1 absolute maximum ratings caution is needed not to exceed abolute maxi mum ratings of the dram device listed in table 9 at any time. 3.2 dc characteristics table 9 absolute maximum ratings symbol parameter rating unit notes v dd voltage on v dd pin relative to v ss ?1.0 to +2.3 v 1)2) 1) stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional o peration of the device at these or any ot her conditions above those indicated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2) when v dd and v ddq and v ddl are less than 500 mv; v ref may be equal to or less than 300 mv. v ddq voltage on v ddq pin relative to v ss ?0.5 to +2.3 v 2)3) v ddl voltage on v ddl pin relative to v ss ?0.5 to +2.3 v 2)3) v in , v out voltage on any pin relative to v ss ?0.5 to +2.3 v 2) t stg storage temperature ?55 to +100 c 2)3) 3) storage temperature is the case surface te mperature on the center/top side of the dram. table 10 dram component operating temperature range symbol parameter rating unit notes t oper operating temperature 0 to 95 c 1)2)3) 1) operating temperature is the case surface tem perature on the center / top side of the dram. 2) the operating temperature range are the temperatures where all dram specification will be supported. during operation, the dram case temperature must be maintained between 0 - 95 c under all other specification parameters. 3) self-refresh period is hard-coded in th e chip and therefore it is imperative t hat the system ensures the dram is below 85 c case temperature before in itiating self-refresh operation. table 11 recommended dc operating conditions (sstl_18) symbol parameter rating unit notes min. typ. max. v dd supply voltage 1.7 1.8 1.9 v 1) 1) v ddq tracks with v dd , v dddl tracks with v dd . ac parameters are measured with v dd , v ddq and v dddl tied together. v dddl supply voltage for dll 1.7 1.8 1.9 v 1) v ddq supply voltage for output 1.7 1.8 1.9 v 1) v ref input reference voltage 0.49 v ddq 0.5 v ddq 0.51 v ddq v 2)3) 2) the value of v ref may be selected by the user to provide optimum noi se margin in the system. typically the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . 3) peak to peak ac noise on v ref may not exceed 2% v ref (dc) v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v 4) 4) v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in die dc level of v ref . hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram electrical characteristics data sheet 22 rev. 1.10, 2006-03 05112005-ymix-kuoq table 12 odt dc electrical characteristics parameter / condition symbol min. nom. max. unit notes termination resistor impedance value for emrs(1)[a6,a2] = [0,1]; 75 ohm rtt1(eff) 60 75 90 ? 1) 1) measurement definition for rtt(eff): apply v ih(ac) and v il(ac) to test pin separately, then measure current i ( v ihac ) and i ( v ilac ) respectively. rtt(eff) = ( v ih(ac) ? v il(ac) ) /( i ( v ihac ) ? i ( v ilac )). termination resistor impedance value for emrs(1)[a6,a2] =[1,0]; 150 ohm rtt2(eff) 120 150 180 ? 1) termination resistor impedance value for emrs(1)(a6,a2)=[1,1]; 50 ohm rtt3(eff) 40 50 60 ? 1) deviation of v m with respect to v ddq / 2 delta v m ?6.00 ? + 6.00 % 2) 2) measurement definition for v m : turn odt on and measure voltage ( v m ) at test pin (midpoint) with no load: delta v m = ((2 x v m / v ddq ) ? 1) x 100% table 13 input and output leakage currents symbol parameter / condition min. max. unit notes iil input leakage current; any input 0 v < v in < v dd ?2 +2 a 1) 1) all other pins not under test = 0 v iol output leakage current; 0 v < v out < v ddq ?5 +5 a 2) 2) dq?s, ldqs, ldqs , udqs, udqs , dqs, dqs , rdqs, rdqs are disabled and odt is turned off table 14 input / output capacitance symbol parameter min. max. unit cck input capacitance, ck and ck pf cdck input capacitance delta, ck and ck ?pf ci input capacitance, all other input-only pins pf cdi input capacitance delta, all other input-only pins ? pf cio input/output capacitance, dq, dm, dqs , dqs , rdqs, rdqs pf cdio input/output capacitance delta, dq, dm, dqs, dqs , rdqs, rdqs ?pf data sheet 23 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram electrical characteristics 3.3 ac characteristics 3.3.1 speed grade definitions all speed grades faster than ddr2-ddr400b co mply with ddr2-ddr400b timing specifications( t ck = 5ns with t ras = 40ns). list of speed grade definition tables: ? table 15 ?speed grade definition speed bins for ddr2?533c? on page 23 ? table 16 ?speed grade definition speed bins for ddr2?400b? on page 24 table 15 speed grade definition speed bins for ddr2?533c speed grade ddr2?533c unit note ifx sort name ?3.7 cas-rcd-rp latencies 4?4?4 t ck parameter symbol min. max. ? clock frequency @ cl = 3 t ck 58 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) only. 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the cross point when in differential strobe mode 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 3.75 8 ns 1)1)1)1) @ cl = 5 t ck 3.75 8 ns 1)1)1)1) row active time t ras 45 70000 ns 1)1)1)1)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 device can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 60 ? ns 1)1)1)1) ras-cas-delay t rcd 15 ? ns 1)1)1)1) row precharge time t rp 15 ? ns 1)1)1)1) hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram electrical characteristics data sheet 24 rev. 1.10, 2006-03 05112005-ymix-kuoq table 16 speed grade definition speed bins for ddr2?400b speed grade ddr2?400b unit note ifx sort name ?5 cas-rcd-rp latencies 3?3?3 t ck parameter symbol min. max. ? clock frequency @ cl = 3 t ck 58 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) only. 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the cross point when in differential strobe mode 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 58 ns 1)2)3)4) @ cl = 5 t ck 58 ns 1)2)3)4) row active time t ras 40 70000 ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 device can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 55 ? ns 1)2)3)4) ras-cas-delay t rcd 15 ? ns 1)2)3)4) row precharge time t rp 15 ? ns 1)2)3)4) data sheet 25 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram electrical characteristics 3.3.2 ac timing parameters list of ac timing parameter tables. ? table 17 ?timing parameter by speed grade - ddr2-533? on page 25 ? table 18 ?timing parameter by speed grade - ddr2-400? on page 27 table 17 timing parameter by speed grade - ddr2-533 parameter symbol ddr2?533 unit notes 1)2)3)4) 5)6)7) min. max. dq output access time from ck / ck t ac ps cas a to cas b command period t ccd 2? t ck ck, ck high-level width t ch 0.45 0.55 t ck cke minimum high and low pulse width t cke 3? t ck ck, ck low-level width t cl 0.45 0.55 t ck auto-precharge wr ite recovery + precharge time t dal wr + t rp ? t ck minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? ns dq and dm input hold time (differential data strobe) t dh (base) 225 ?? ps dq and dm input hold time (single ended data strobe) t dh1 (base) ?25 ? ps dq and dm input pulse width (each input) t dipw 0.35 ? t ck dqs output access time from ck / ck t dqsck ps dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 300 ps write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck dq and dm input setu p time (differential data strobe) t ds (base) 100 ? ps dq and dm input setup time (single ended data strobe) t ds1 (base) ?25 ? ps dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck clock half period t hp min. ( t cl, t ch ) data-out high-impedance time from ck / ck t hz ? t ac.max ps address and control input hold time t ih (base) 375 ? ps address and control input pulse width (each input) t ipw 0.6 ? t ck address and control input setup time t is (base) 250 ? ps hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram electrical characteristics data sheet 26 rev. 1.10, 2006-03 05112005-ymix-kuoq dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max ps dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps mode register set command cycle time t mrd 2? t ck ocd drive mode output delay t oit 012ns data output hold time from dqs t qh t hp ? t qhs ? data hold skew factor t qhs ? 400 ps average periodic refresh interval t refi ?7.8 s 8) ?3.9 s 9) precharge-all (4 banks) command period t rp t rp ?ns read preamble t rpre 0.9 1.1 t ck read postamble t rpst 0.40 0.60 t ck active bank a to active bank b command period t rrd 7.5 ? ns 10 ? ns internal read to precharge command delay t rtp 7.5 ? ns write preamble t wpre 0.25 x t ck ? t ck write postamble t wpst 0.40 0.60 t ck write recovery time for write without auto- precharge t wr 15 ? ns write recovery time for write with auto- precharge wr t wr / t ck t ck internal write to read command delay t wtr 7.5 ? ns exit power down to any valid command (other than nop or deselect) t xard 2? t ck exit active power-down mode to read command (slow exit, lower power) t xards 6 ? al ? t ck exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? t ck 1) for details and notes see the relevant infineon component data sheet 2) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v. see notes 4)5)6)7) 3) timing that is not specified is illegal and after such an ev ent, in order to guarantee pro per operation, the dram must be powered down and then restarted through the specified init ialization sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential st robe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs/dqs , rdqs/rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . 8) 0 c t case 85 c table 17 timing parameter by speed grade - ddr2-533 (cont?d) parameter symbol ddr2?533 unit notes 1)2)3)4) 5)6)7) min. max. data sheet 27 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram electrical characteristics 9) 85 c < t case 95 c table 18 timing parameter by speed grade - ddr2-400 parameter symbol ddr2?400 unit notes 1)2)3)4) 5)6)7) min. max. dq output access time from ck / ck t ac ps cas a to cas b command period t ccd 2? t ck ck, ck high-level width t ch 0.45 0.55 t ck cke minimum high and low pulse width t cke 3? t ck ck, ck low-level width t cl 0.45 0.55 t ck auto-precharge wr ite recovery + precharge time t dal wr + t rp ? t ck minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? ns dq and dm input hold time (differential data strobe) t dh (base) 275 ?? ps dq and dm input hold time (single ended data strobe) t dh1 (base) ?25 ? ps dq and dm input pulse width (each input) t dipw 0.35 ? t ck dqs output access time from ck / ck t dqsck ps dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 350 ps write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck dq and dm input setu p time (differential data strobe) t ds (base) 150 ? ps dq and dm input setup time (single ended data strobe) t ds1 (base) ?25 ? ps dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck clock half period t hp min. ( t cl, t ch ) data-out high-impedance time from ck / ck t hz ? t ac.max ps address and control input hold time t ih (base) 475 ? ps address and control input pulse width (each input) t ipw 0.6 ? t ck address and control input setup time t is (base) 350 ? ps dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max ps dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps mode register set command cycle time t mrd 2? t ck hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram electrical characteristics data sheet 28 rev. 1.10, 2006-03 05112005-ymix-kuoq ocd drive mode output delay t oit 012ns data output hold time from dqs t qh t hp ? t qhs ? data hold skew factor t qhs ? 450 ps average periodic refresh interval t refi ?7.8 s 8) ?3.9 s 9) precharge-all (4 banks) command period t rp t rp ?ns read preamble t rpre 0.9 1.1 t ck read postamble t rpst 0.40 0.60 t ck active bank a to active bank b command period t rrd 7.5 ? ns 10 ? ns internal read to precharge command delay t rtp 7.5 ? ns write preamble t wpre 0.25 x t ck ? t ck write postamble t wpst 0.40 0.60 t ck write recovery time for write without auto- precharge t wr 15 ? ns write recovery time for write with auto- precharge wr t wr / t ck t ck internal write to read command delay t wtr 10 ? ns exit power down to any valid command (other than nop or deselect) t xard 2? t ck exit active power-down mode to read command (slow exit, lower power) t xards 6 ? al ? t ck exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? t ck 1) for details and notes see the relevant infineon component data sheet 2) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v. see notes 4)5)6)7) 3) timing that is not specified is illegal and after such an ev ent, in order to guarantee pro per operation, the dram must be powered down and then restarted through the specified init ialization sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential st robe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs/dqs , rdqs/rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . 8) 0 c t case 85 c 9) 85 c < t case 95 c table 18 timing parameter by speed grade - ddr2-400 parameter symbol ddr2?400 unit notes 1)2)3)4) 5)6)7) min. max. data sheet 29 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram electrical characteristics 3.3.3 odt ac electri cal characteristics table 19 odt ac characteristics and operating conditions for ddr2-533 and ddr2-400 symbol parameter / condition values unit note min. max. t aond odt turn-on delay 2 2 t ck t aon odt turn-on t ac.min t ac.max + 1 ns ns 1) 1) odt turn on time min. is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measure from t aond . t aonpd odt turn-on (power-down modes) t ac.min + 2 ns 2 t ck + t ac.max + 1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off t ac.min t ac.max + 0.6 ns ns 2) 2) odt turn off time min. is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns t anpd odt to power down mo de entry latency 3 ? t ck t axpd odt power down exit latency 8 ? t ck hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram electrical characteristics data sheet 30 rev. 1.10, 2006-03 05112005-ymix-kuoq 3.4 i dd specifications and conditions list of tables defining i dd specifications and conditions. ? table 20 ?idd measurement conditions? on page 30 ? table 22 ?idd specification for hys72t[64/128/256]xxxhr?3.7?b? on page 32 ? table 23 ?idd specification for hys72t[64/128/256]xxxhr?5?b? on page 33 table 20 i dd measurement conditions 1)2)3)4)5)6) parameter symbol operating current 0 one bank active - precharge; t ck = t ck.min , t rc = t rc.min , t ras = t ras.min , cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd0 operating current 1 one bank active - read - precharge; i out = 0 ma, bl = 4, t ck = t ck.min , t rc = t rc.min , t ras = t ras.min , t rcd = t rcd.min , al = 0, cl = cl min ; cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd1 precharge standby current all banks idle; cs is high; cke is high; t ck = t ck.min ; other control and address inputs are switching, data bus in puts are switching. i dd2n precharge power-down current other control and address inputs are st able, data bus inputs are floating. i dd2p precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ck.min ; other control and address inputs are stable, data bus inputs are floating. i dd2q active standby current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl min ; t ck = t ck.min ; t ras = t ras.max , t rp = t rp.min ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd3n active power-down current all banks open; t ck = t ck.min , cke is low; other control and ad dress inputs are stable, data bus inputs are floating. mrs a12 bit is set to low (fast power-down exit); i dd3p(0) active power-down current all banks open; t ck = t ck.min , cke is low; other control and ad dress inputs are stable, data bus inputs are floating. mrs a12 bit is set to high (slow power-down exit); i dd3p(1) operating current urst write: all banks open; continuous burst writes; bl = 4; al = 0, cl = cl min ; t ck = t ck.min ; t ras = t ras.max. , t rp = t rp.max ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd4w burst refresh current t ck = t ck.min ., refresh command every t rfc = t rfc.min interval, cke is high, cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5b distributed refresh current t ck = t ck.min. , refresh command every t rfc = t refi interval, cke is low and cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5d data sheet 31 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram electrical characteristics self-refresh current cke 0.2 v; external clock off, ck and ck at 0 v; other control and address inputs are floating, data bus inputs are floating. i dd6 current values are guaranteed up to t case of 85 c max. i dd6 all bank interleave read current all banks are being interleaved at minimum t rc without violating t rrd using a burst length of 4. control and address bus inputs are stable during deselects. i out = 0 ma. i dd7 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v 2) i dd specifications are tested after th e device is properly initialized and i dd parameter are specif ied with odt disabled. 3) definitions for i dd see table 21 4) i dd1 , i dd4r and i dd7 current measurements are de fined with the outputs disabled ( i out = 0 ma). to achieve this on module level the output buffers can be disabl ed using an emrs(1) (extended mode register command) by setting a12 bit to high. 5) for two rank modules: for all active current measur ements the other rank is in precharge power-down mode i dd2p 6) for details and notes see the relevant infineon component data sheet table 21 definitions for i dd parameter description low v in v il(ac).max , high is defined as v in v ih(ac).min stable inputs are stable at a high or low level floating inputs are v ref = v ddq /2 switching inputs are changing between high and low every other clock (once per 2 cycles) for address and control signals, and inputs changing between high and low every othe r data transfer (once per cycle) for dq signals no t including mask or strobes table 20 i dd measurement conditions (cont?d) 1)2)3)4)5)6) parameter symbol hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram electrical characteristics data sheet 32 rev. 1.10, 2006-03 05112005-ymix-kuoq table 22 i dd specification for hys72t[64/128/256]xxxhr?3.7?b product type hys72t64000hr?3.7?b hys72t128000hr?3.7?b hys72t128020hr?3.7?b hys72t256220hr?3.7?b unit note 1) 1) module i dd is calculated on the basis of component i dd and includes currents of registers and pll. odt disabled. i dd1, i dd4r, and i dd7, are defined with the outputs disabled. organization 512 mb 1 gb 1 gb 2 gb 1 rank 1 rank 2 ranks 2 ranks 72 72 72 72 -3.7 -3.7 -3.7 -3.7 symbol max. max. max. max. i dd0 920 1670 980 1800 ma 2) 2) the other rank is in i dd2p precharge power-down current mode i dd1 1010 1850 1070 1980 ma 2) i dd2p 390 630 460 750 ma 3) 3) both ranks are in the same i dd current mode i dd2n 670 1180 1010 1870 ma 3) i dd2q 650 1130 960 1760 ma 3) i dd3p( mrs = 0) 580 1000 830 1510 ma 3) i dd3p( mrs = 1) 410 660 490 820 ma 3) i dd3n 720 1270 1100 2050 ma 3) i dd4r 1320 2480 1380 2610 ma 2) i dd4w 1320 2480 1380 2610 ma 2) i dd5b 1500 2840 1560 2970 ma 2) i dd5d 410 660 490 820 ma 3)4) 4) i dd5d and i dd6 values are for 0 c t case 85 c i dd6 63 126 126 252 ma 3)4) i dd7 1640 3110 1700 3240 ma 2) data sheet 33 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram electrical characteristics table 23 i dd specification for hys72t[64/128/256]xxxhr?5?b product type hys72t64000hr?5?b hys72t128000hr?5?b hys72t128020hr?5?b hys72t256220hr?5?b unit note 1) 1) module i dd is calculated on the basis of component i dd and includes currents of regi sters and pll. odt disabled. i dd1, i dd4r, and i dd7, are defined with the outputs disabled. organization 512 mb 1 gb 1gb 2 gb 1 rank 1 rank 2 ranks 2 ranks 72 72 72 72 -5 -5 -5 -5 symbol max. max. max. max. i dd0 820 1500 890 1630 ma 2) 2) the other rank is in i dd2p precharge power-down current mode i dd1 910 1670 970 1790 ma 2) i dd2p 340 530 400 660 ma 3) 3) both ranks are in the same i dd current mode i dd2n 580 1020 890 1630 ma 3) i dd2q 560 980 850 1560 ma 3) i dd3p( mrs = 0) 490 840 710 1270 ma 3) i dd3p( mrs = 1) 360 570 440 730 ma 3) i dd3n 630 1110 980 1810 ma 3) i dd4r 1130 2120 1190 2240 ma 2) i dd4w 1130 2120 1190 2240 ma 2) i dd5b 1400 2660 1460 2780 ma 2) i dd5d 360 570 440 730 ma 3)4) 4) i dd5d and i dd6 values are for 0 c t case 85 c. i dd6 63 126 126 252 ma 3)4) i dd7 1540 2940 1610 3070 ma 2) hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram electrical characteristics data sheet 34 rev. 1.10, 2006-03 05112005-ymix-kuoq 3.4.1 i dd test conditions for testing the i dd parameters, the timing parameters as shown in the tables below are used. ? table 24 ?idd measurement test condition for ddr2?533c? on page 34 ? table 25 ?idd measurement test condition for ddr2?400b? on page 34 table 24 i dd measurement test condition for ddr2?533c parameter symbol ?3.7 unit notes ddr2?533c cas latency cl idd 3t ck clock cycle time t ck.idd 3.75 ns active to read or write delay t rcd.idd 15 ns active to active / auto -refresh command period t rc.idd 60 ns active bank a to active bank b command delay t rrd.idd 7.5 ns 1) 1) 4 & 8 (1 kb page size) 10 ns 2) 2) 16 (2 kb page size) active to precharge command t ras.min.idd 45 ns t ras.max.idd 7000 ns precharge command period t rp.idd 15 ns auto-refresh to ac tive / auto-refresh command period t rfc.idd ns average periodic refresh interval 0 c t case 85 ct refi 7.8 s 85 c t case 95 ct refi 3.9 s table 25 i dd measurement test condition for ddr2?400b parameter symbol ?5 unit notes ddr2?400b cas latency cl idd 3t ck clock cycle time t ck.idd 5ns active to read or write delay t rcd.idd 15 ns active to active / auto -refresh command period t rc.idd 55 ns active bank a to active bank b command delay t rrd.idd 7.5 ns 1) 1) 4 & 8 (1 kb page size) 10 ns 2) 2) 16 (2 kb page size) active to precharge command t ras.min.idd 40 ns t ras.max.idd 7000 ns precharge command period t rp.idd 15 ns auto-refresh to ac tive / auto-refresh command period t rfc.idd ns average periodic refresh interval 0 c t case 85 ct refi 7.8 s 85 c t case 95 ct refi 3.9 s data sheet 35 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram electrical characteristics 3.4.2 on die termina tion (odt) current the odt function adds addi tional current consumption to the ddr2 sdram when enabled by the emrs(1). depending on address bits a[6,2] in the emrs(1) a ?weak? or ?strong? termination can be selected. the current consumption for any terminated input pin, depends on the input pin is in tri-state or driving 0 or 1, as long a odt is enabled during a given period of time. note: for power consumption calculations the odt duty cycle has to be taken into account table 26 odt current per terminated pin parameter symbol min. typ. m ax. unit emrs(1) state enabled odt current per dq odt is high; data bus inputs are floating i odto 5 6 7.5 ma/dq a6 = 0, a2 = 1 2.5 3 3.75 ma/dq a6 = 1, a2 = 0 active odt current per dq odt is high; worst case of data bus inputs are stable or switching. i odtt 10 12 15 ma/dq a6 = 0, a2 = 1 5 6 7.5 ma/dq a6 = 1, a2 = 0 hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram spd codes data sheet 36 rev. 1.10, 2006-03 05112005-ymix-kuoq 4spdcodes this chapter lists all hexadecimal byte values stored in the eeprom of the products described in this data sheet. spd stands for serial presence detect . all values with xx in the table are module specific byte s which are defined during production. list of spd code tables ? table 27 ?hys72t[64/128/256]xxxhr?3.7?b? on page 36 ? table 28 ?hys72t[64/128/256]xxxhr?5?b? on page 41 table 27 hys72t[64/128/256]xxxhr?3.7?b product type hys72t64000hr?3.7?b hys72t128000hr?3.7?b hys72t128020hr?3.7?b hys72t256220hr?3.7?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) label code pc2? 4200r?444 pc2? 4200r?444 pc2? 4200r?444 pc2? 4200r?444 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex 0 programmed spd byte s in eeprom 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 2 memory type (ddr2) 08 08 08 08 3 number of row addresses 0e 0e 0e 0e 4 number of column addresses 0a 0b 0a 0b 5 dimm rank and stacking information 60 60 61 61 6 data width 48 48 48 48 7 not used 00 00 00 00 8 interface voltage level 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 3d 3d 3d 3d 10 t ac sdram @ cl max (byte 18) [ns] 50 50 50 50 11 error correction support (non-ecc, ecc) 02 02 02 02 12 refresh rate and type 82 82 82 82 13 primary sdram width 08 04 08 04 14 error checking sdram width 08 04 08 04 15 not used 00 00 00 00 16 burst length supported 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 data sheet 37 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram spd codes 18 supported cas latencies 38 38 38 38 19 dimm mechanical characteristics 01 01 01 01 20 dimm type information 01 01 01 01 21 dimm attributes 04 05 05 07 22 component attributes 07 07 07 07 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 3d 3d 24 t ac sdram @ cl max -1 [ns] 50 50 50 50 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 60 27 t rp.min [ns] 3c 3c 3c 3c 28 t rrd.min [ns] 1e 1e 1e 1e 29 t rcd.min [ns] 3c 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 2d 31 module density per rank 80 01 80 01 32 t as.min and t cs.min [ns] 25 25 25 25 33 t ah.min and t ch.min [ns] 37 37 37 37 34 t ds.min [ns] 10 10 10 10 35 t dh.min [ns] 22 22 22 22 36 t wr.min [ns] 3c 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 40 t rc and t rfc extension 00000000 41 t rc.min [ns] 3c 3c 3c 3c 42 t rfc.min [ns] 69 69 69 69 43 t ck.max [ns] 80 80 80 80 table 27 hys72t[64/128/256]xxxhr?3.7?b (cont?d) product type hys72t64000hr?3.7?b hys72t128000hr?3.7?b hys72t128020hr?3.7?b hys72t256220hr?3.7?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) label code pc2? 4200r?444 pc2? 4200r?444 pc2? 4200r?444 pc2? 4200r?444 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram spd codes data sheet 38 rev. 1.10, 2006-03 05112005-ymix-kuoq 44 t dqsq.max [ns] 1e 1e 1e 1e 45 t qhs.max [ns] 28 28 28 28 46 pll relock time 0f 0f 0f 0f 47 t case.max delta / ? t 4r4w delta 50 50 50 50 48 psi(t-a) dram 7a 7a 7a 7a 49 ? t 0 (dt0) 43434343 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm)29292929 51 ? t 2p (dt2p) 36 36 36 36 52 ? t 3n (dt3n) 21 21 21 21 53 ? t 3p.fast (dt3p fast) 41414141 54 ? t 3p.slow (dt3p slow) 2a 2a 2a 2a 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 40 40 40 40 56 ? t 5b (dt5b) 1e 1e 1e 1e 57 ? t 7 (dt7) 22222222 58psi(ca) pll c4c4c4c4 59 psi(ca) reg 8c 8c 8c 8c 60 ? t pll (dtpll) 61616161 61 ? t reg (dtreg) / toggle rate 78 78 78 78 62 spd revision 12 12 12 12 63 checksum of bytes 0-62 7e f9 80 fc 64 jedec id code of infineon (1) c1 c1 c1 c1 65 jedec id code of infineon (2) 00 00 00 00 66 jedec id code of infineon (3) 00 00 00 00 67 jedec id code of infineon (4) 00 00 00 00 68 jedec id code of infineon (5) 00 00 00 00 69 jedec id code of infineon (6) 00 00 00 00 table 27 hys72t[64/128/256]xxxhr?3.7?b (cont?d) product type hys72t64000hr?3.7?b hys72t128000hr?3.7?b hys72t128020hr?3.7?b hys72t256220hr?3.7?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) label code pc2? 4200r?444 pc2? 4200r?444 pc2? 4200r?444 pc2? 4200r?444 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex data sheet 39 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram spd codes 70 jedec id code of infineon (7) 00 00 00 00 71 jedec id code of infineon (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 product type, char 1 37 37 37 37 74 product type, char 2 32 32 32 32 75 product type, char 3 54 54 54 54 76 product type, char 4 36 31 31 32 77 product type, char 5 34 32 32 35 78 product type, char 6 30 38 38 36 79 product type, char 7 30 30 30 32 80 product type, char 8 30 30 32 32 81 product type, char 9 48 30 30 30 82 product type, char 10 52 48 48 48 83 product type, char 11 33 52 52 52 84 product type, char 12 2e 33 33 33 85 product type, char 13 37 2e 2e 2e 86 product type, char 14 42 37 37 37 87 product type, char 15 20 42 42 42 88 product type, char 16 20 20 20 20 89 product type, char 17 20 20 20 20 90 product type, char 18 20 20 20 20 91 module revision code 2x 2x 2x 0x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx table 27 hys72t[64/128/256]xxxhr?3.7?b (cont?d) product type hys72t64000hr?3.7?b hys72t128000hr?3.7?b hys72t128020hr?3.7?b hys72t256220hr?3.7?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) label code pc2? 4200r?444 pc2? 4200r?444 pc2? 4200r?444 pc2? 4200r?444 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram spd codes data sheet 40 rev. 1.10, 2006-03 05112005-ymix-kuoq 95 - 98 module serial number xx xx xx xx 99 - 127 not used 00 00 00 00 table 27 hys72t[64/128/256]xxxhr?3.7?b (cont?d) product type hys72t64000hr?3.7?b hys72t128000hr?3.7?b hys72t128020hr?3.7?b hys72t256220hr?3.7?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) label code pc2? 4200r?444 pc2? 4200r?444 pc2? 4200r?444 pc2? 4200r?444 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex data sheet 41 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram spd codes table 28 hys72t[64/128/256]xxxhr?5?b product type hys72t64000hr?5?b hys72t128000hr?5?b hys72t128020hr?5?b hys72t256220hr?5?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) label code pc2? 3200r?333 pc2? 3200r?333 pc2? 3200r?333 pc2? 3200r?333 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex 0 programmed spd byte s in eeprom 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 2 memory type (ddr2) 08 08 08 08 3 number of row addresses 0e 0e 0e 0e 4 number of column addresses 0a 0b 0a 0b 5 dimm rank and stacking information 60 60 61 61 6 data width 48 48 48 48 7 not used 00 00 00 00 8 interface voltage level 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 50 50 50 50 10 t ac sdram @ cl max (byte 18) [ns] 60 60 60 60 11 error correction support (non-ecc, ecc) 02 02 02 02 12 refresh rate and type 82 82 82 82 13 primary sdram width 08 04 08 04 14 error checking sdram width 08 04 08 04 15 not used 00 00 00 00 16 burst length supported 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 18 supported cas latencies 38 38 38 38 19 dimm mechanical characteristics 01 01 01 01 20 dimm type information 01 01 01 01 21 dimm attributes 04 05 05 07 22 component attributes 07 07 07 07 23 t ck @ cl max -1 (byte 18) [ns] 50 50 50 50 24 t ac sdram @ cl max -1 [ns] 60 60 60 60 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 50 hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram spd codes data sheet 42 rev. 1.10, 2006-03 05112005-ymix-kuoq 26 t ac sdram @ cl max -2 [ns] 60 60 60 60 27 t rp.min [ns] 3c 3c 3c 3c 28 t rrd.min [ns] 1e 1e 1e 1e 29 t rcd.min [ns] 3c 3c 3c 3c 30 t ras.min [ns] 28 28 28 28 31 module density per rank 80 01 80 01 32 t as.min and t cs.min [ns] 35 35 35 35 33 t ah.min and t ch.min [ns] 47 47 47 47 34 t ds.min [ns] 15 15 15 15 35 t dh.min [ns] 27 27 27 27 36 t wr.min [ns] 3c 3c 3c 3c 37 t wtr.min [ns] 28 28 28 28 38 t rtp.min [ns] 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 40 t rc and t rfc extension 00000000 41 t rc.min [ns] 37 37 37 37 42 t rfc.min [ns] 69 69 69 69 43 t ck.max [ns] 80 80 80 80 44 t dqsq.max [ns] 23 23 23 23 45 t qhs.max [ns] 2d 2d 2d 2d 46 pll relock time 0f 0f 0f 0f 47 t case.max delta / ? t 4r4w delta 50 50 50 50 48 psi(t-a) dram 7a 7a 7a 7a 49 ? t 0 (dt0) 3b 3b 3b 3b 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm)25252525 51 ? t 2p (dt2p) 36 36 36 36 52 ? t 3n (dt3n) 1e 1e 1e 1e table 28 hys72t[64/128/256]xxxhr?5?b (cont?d) product type hys72t64000hr?5?b hys72t128000hr?5?b hys72t128020hr?5?b hys72t256220hr?5?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) label code pc2? 3200r?333 pc2? 3200r?333 pc2? 3200r?333 pc2? 3200r?333 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex data sheet 43 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram spd codes 53 ? t 3p.fast (dt3p fast) 38383838 54 ? t 3p.slow (dt3p slow) 2a 2a 2a 2a 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 38 38 38 38 56 ? t 5b (dt5b) 1d 1d 1d 1d 57 ? t 7 (dt7) 21212121 58psi(ca) pll c4c4c4c4 59 psi(ca) reg 8c 8c 8c 8c 60 ? t pll (dtpll) 59595959 61 ? t reg (dtreg) / toggle rate 5c 5c 5c 5c 62 spd revision 12 12 12 12 63 checksum of bytes 0-62 b2 2d b4 30 64 jedec id code of infineon (1) c1 c1 c1 c1 65 jedec id code of infineon (2) 00 00 00 00 66 jedec id code of infineon (3) 00 00 00 00 67 jedec id code of infineon (4) 00 00 00 00 68 jedec id code of infineon (5) 00 00 00 00 69 jedec id code of infineon (6) 00 00 00 00 70 jedec id code of infineon (7) 00 00 00 00 71 jedec id code of infineon (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 product type, char 1 37 37 37 37 74 product type, char 2 32 32 32 32 75 product type, char 3 54 54 54 54 76 product type, char 4 36 31 31 32 77 product type, char 5 34 32 32 35 78 product type, char 6 30 38 38 36 79 product type, char 7 30 30 30 32 table 28 hys72t[64/128/256]xxxhr?5?b (cont?d) product type hys72t64000hr?5?b hys72t128000hr?5?b hys72t128020hr?5?b hys72t256220hr?5?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) label code pc2? 3200r?333 pc2? 3200r?333 pc2? 3200r?333 pc2? 3200r?333 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram spd codes data sheet 44 rev. 1.10, 2006-03 05112005-ymix-kuoq 80 product type, char 8 30 30 32 32 81 product type, char 9 48 30 30 30 82 product type, char 10 52 48 48 48 83 product type, char 11 35 52 52 52 84 product type, char 12 42 35 35 35 85 product type, char 13 20 42 42 42 86 product type, char 14 20 20 20 20 87 product type, char 15 20 20 20 20 88 product type, char 16 20 20 20 20 89 product type, char 17 20 20 20 20 90 product type, char 18 20 20 20 20 91 module revision code 2x 2x 2x 0x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number xx xx xx xx 99 - 127 not used 00 00 00 00 table 28 hys72t[64/128/256]xxxhr?5?b (cont?d) product type hys72t64000hr?5?b hys72t128000hr?5?b hys72t128020hr?5?b hys72t256220hr?5?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) label code pc2? 3200r?333 pc2? 3200r?333 pc2? 3200r?333 pc2? 3200r?333 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex data sheet 45 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram package outlines 5 package outlines figure 6 package outline raw card a l-dim-240-11 gld09655 1 128.95 133.35 4 0.1 bc a 1.27 0.4 c 0.1 2.7 max. 30 120 2.5 4 5 63 b 55 0.1 1.5 3.8 121 240 10 17.8 (3) burr max. 0.4 allowed 2.5 0.2 0.05 0.8 0.1 a bc detail of contacts 0.2 a 1 0.1 2.3 4x hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram package outlines data sheet 46 rev. 1.10, 2006-03 05112005-ymix-kuoq figure 7 package outline raw card c l-dim-240-13 gld09657 1 128.95 133.35 4 0.1 bc a 1.27 0.4 c 0.1 4 max. 30 120 2.5 4 5 63 b 55 0.1 1.5 3.8 121 240 10 17.8 (3) burr max. 0.4 allowed 2.5 0.2 0.05 0.8 0.1 a bc detail of contacts 0.2 a 1 0.1 2.3 4x data sheet 47 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram package outlines figure 8 package outline raw card b l-dim-240-12 gld09656 1 128.95 133.35 4 0.1 bc a 1.27 0.4 c 0.1 4 max. 30 120 2.5 4 5 63 b 55 0.1 1.5 3.8 121 240 10 17.8 (3) burr max. 0.4 allowed 2.5 0.2 0.05 0.8 0.1 a bc detail of contacts 0.2 a 1 0.1 2.3 4x hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram package outlines data sheet 48 rev. 1.10, 2006-03 05112005-ymix-kuoq figure 9 package outline raw card j l-dim-240-20 gld09659 1 128.95 133.35 4 0.1 bc a 1.27 0.4 c 0.1 4 max. 30 120 2.5 4 5 63 b 55 0.1 1.5 3.8 121 240 10 17.8 3 min. burr max. 0.4 allowed 2.5 0.2 0.05 0.8 0.1 a bc detail of contacts 0.2 a 1 0.1 2.3 4x data sheet 49 rev. 1.10, 2006-03 05112005-ymix-kuoq hys72t[64/128/256]xxxhr?[3.7/5]?b 240-pin registered ddr2 sdram product type nomenclature (ddr2 drams and dimms) 6 product type nomenclature (ddr2 drams and dimms) infineon?s nomenclature uses simple coding combined with some propriatory coding. table 29 provides examples for module and component product type number as well as the field number. the detailed field description together with possible values and coding explanation is listed for modules in table 30 and for components in table 31 . table 29 nomenclature fields and examples example for field number 1234567891011 micro-dimm hys64t64020km?5?a ddr2 dram hyb 18 t 512 16 0 a c ?5 table 30 ddr2 dimm nomenclature field description values coding 1infineon modul prefix hys constant 2 module data width [bit] 64 non-ecc 72 ecc 3dram technology t ddr2 4 memory density per i/o [mbit]; module density 1) 32 256 mbyte 64 512 mbyte 128 1 gbyte 256 2 gbyte 512 4 gbyte 5raw card generation 0 .. 9 look up table 6 number of module ranks 0, 2, 4 1, 2, 4 7 product variations 0 .. 9 look up table 8 package, lead-free status a .. z look up table 9 module type d so- d imm m m icro-dimm r r egistered u u nbuffered 10 speed grade ?2.5 pc2?6400 6?6?6 ?3 pc2?5300 4?4?4 ?3s pc2?5300 5?5?5 ?3.7 pc2?4200 4?4?4 ?3.7f pc2?4200 cl3 ?5 pc2?3200 3?3?3 11 die revision ?a first ?b second 1) multiplying ?memory density per i/o? with ?module data width? and dividing by 8 for non-ecc and 9 for ecc modules gives the overall module memory density in mbytes as listed in column ?coding?. table 31 ddr2 dram nomenclature field description values coding 1 infineon component prefix hyb constant 2 interface voltage [v] 18 sstl1.8 3dram technology t ddr2 4 component density [mbit] 256 256 mbit 512 512 mbit 1g 1 gbit 2g 2 gbit 5+6 number of i/os 40 4 80 8 16 16 7 product variations 0 .. 9 look up table 8 die revision a first b second 9 package, lead-free status cfbga, lead-containing f fbga, lead-free 10 speed grade ?2.5 ddr2-800e 6-6-6 ?3 ddr2-667c 4-4-4 ?3s ddr2-667d 5-5-5 ?3.7 ddr2-533c 4-4-4 ?3.7f ddr2-533c cl3 ?5 ddr2-400b 3-3-3 published by infineon technologies ag www.infineon.com |
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