micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2004-11 preliminary specifications 1 micro netw orks an integrated circuit systems compan y iso 9001 registered iso 9001 registered m2004-11 frequency synthesizer description the m2004-11 integrates a high performance phase locked loop (pll) with a voltage controlled saw oscillator (vcso) to provide a low jitter frequency t ranslator in a 9mm x 9mm surface mount package. the m2004-11 is pin and function compatible with the m2004-01 and in addition includes a phase slope limiting circuit. this provides phase build-out protection when reselecting the input clock. the internal high ??saw filter provides low jitter signal performance and determines the maximum output frequency of the vcso. a programmable output divider can divide the vcso frequency to achieve an output as low as 38.88mhz. the input to the frequency translator is provided by selecting between one of two output reference clocks. the output frequency is an integer multiple of the input reference frequency. parallel and serial control of the output and feedback dividers is provided via the configuration logic. an external loop filter sets the pll bandwidth which can be optimized to provide jitter attenuation of the input reference clock. the m2004-11 is available at sonet/sdh and 10gbe frequencies up to 700mhz. pin compatible with the m2004-01 build-in phase slope limiter for phase build-out protection meets bellcore gr-253-core mtie output clock frequency up to 700mhz differential lvpecl outputs internal low-jitter saw-based oscillator intrinsic jitter <1ps rms (12khz - 20mhz) jitter attenuation of input reference clock dual input mux parallel programming t unable loop filter response 3.3v operation small 9mm x 9mm smt package inputs, v i : ................................................. -0.5 to v cc +0.5v output, v o : ................................................. -0.5 to v cc +0.5v supply voltage, v dd : ......................................................... 4.6 v storage temperature, t sto : ............................ -45 c to +100 c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended peri- ods may affect product reliability. absolute max ratings features applications sonet / sdh / 10gbe system synchronization add / drop muxes, access and edge switches line card system clock cleaner / t ranslator optical module clock cleaner / translator
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2004-11 preliminary specifications 2 micro netw orks an integrated circuit systems compan y the internal pll will adjust the vcso output frequency to be m times the selected input r eference clock frequency. note that the product of m x input frequency must be such that it falls within the ?ock?range of the vcso. the n output divider can be programmed to divide the vcso output frequency by 1, 2, 4, or 8 and provide a 50% output duty cycle. the m2004-01 supports both parallel and serial operating modes for programming the m divider and n output divider. figure 1 shows the timing diagram for each mode. in the parallel mode the np_load input is initially low. the data on inputs m0 through m5 and n0 and n1 is passed directly to the m divider. on the low-to-high transition of the np_load input, the data is latched and the m divider remains loaded until the next low transition on np_load or until a serial event occurs. as a r esult, the m and n bits can be hardwired to set the m divider and n output divider to a specific default state that will automatically occur during power-up. the relationship between the vcso frequency, the input ref_clk , and the m divider is defined as follows: f vcso = f ref_clk x m when the n output divider is included, the complete relationship for the output frequency is defined as: fout= f vcso =f ref_clk x m nn the m value and the required logic states of m0 through m5 are shown in table 5b, programmable vcso frequency function table. (i.e. for an output frequency of 622.08mhz and an input frequency of 19.44mhz the m value would be 32 and the n value would be 1. similarly, for an output frequency of 311.04 mhz and an input frequency of 19.44mhz the m value would be 32 and the n value would be 2.) serial operation occurs when np_load is high and s_load is low. the shift register is loaded by sampling the s_data bits with the rising edge of s_clock. the contents of the shift register are loaded into the m divider and n output divider when s_load transitions from low-to-high. the m divider and n output divide values are latched on the high-to- low transition of s_load. if s_load is held high, data at the s_data input is passed directly to the m divider and n output divider on each rising edge of s_clock. functional block diagram figure 1 low low null null null null n1 n0 m5 m4 m3 m2 m1 m0 s_data s_clk s_load m 2004-11 saw delay line phase shifter vcso c post c post vc nvc r post nop_out op_out r post r loop c loop r loop c loop r in r in op_in nop_in m divider m = 3-1023 mux 0 1 n divider n = 1,2,4,8 serial / parallel configuration register 6 m5:0 n1:0 phase detector loop filter amplifier external loop filter co m ponents ref_sel ref_clk0 ref_clk1 fout nfout mr s_data s_clk s_load np_load 2
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2004-11 preliminary specifications 3 micro netw orks an integrated circuit systems compan y functional description loop filter figure 2 table 1. recommended loop filter values the m2004-01 requires the use of an external loop filter via the provided filter pins. due to the differential design, the implementation requires two identical rc filters as shown in figure 2. ref clk vcso m n fout rloop cloop rpost cpost frequency frequency 19.44mhz 622.0800mhz 32 1 622.0800mhz 5k ? 1mf 50k ? 100pf vc nvc op_out nop_out op_in nop_in rloop rloop cloop cloop rpost rpost cpost cpost
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2004-11 preliminary specifications 4 micro netw orks an integrated circuit systems compan y pin descriptions table 2 pin number name i/o configuration description 1, 2, 3 gnd gnd power supply ground 4, 9 op_in, nop_in analog i/o used for external loop filter. see figure 2. 5, 8 nop_out, op_out analog i/o used for external loop filter. see figure 2 6, 7 nvc, vc input vcso differential control voltage input pair 10, 14, 26 gnd gnd power supply ground 11, 19, 33 vdd power positive supply pins 12, 13 n0, n1 input pull - down determines the output divider value as defined in table 3c. lvcmos / lvttl interface levels. 15, 16 fout, nfout output unterminated differential output, 3.3v lvpecl levels. 17 mr input pull - down logic high resets the reference frequency and n output dividers. logic low enables the outputs. l vcmos / lvttl interface levels. 18 s_clock input pull - down clocks in serial data present at s_data input into the shift register on the rising edge of s_clock. 20 s_data input pull - down shift register serial input. data is sampled on the rising edge of s_clock. 21 s_load input pull - down controls transition of data from shift register into the dividers. lvcmos / lvttl interface levels 22 np_load input pull - down parallel load input. determines when data present at m5:m0 is loaded into mdivider, and when data present at n1:n0 sets the n output divider value. lvcmos / lvttl interface levels. 23 ref_clk1 input pull - down input reference clock. lvcmos / lvttl interface levels. 24 ref_clk0 input pull - down input reference clock. lvcmos / lvttl interface levels. 25 ref_sel input pull - down selects between the different reference clock inputs as the pll reference source. see table 3d. l vcmos / lvttl interface levels. 27, 28, 29, 30, 31 m0, m1, m2, m3, m4 input pull - down m divider inputs. data is latched on low-to-high transition of np_load input. lvcmos/ lvttl interface levels. 32 m5 input pull - down 34, 35, 36 dnc do not connect. internal test pins must be left floating.
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2004-11 preliminary specifications 5 micro netw orks an integrated circuit systems compan y table 4 pin characteristics symbol parameter test conditions min typical max units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? table 5b programmable vcso frequency function vcso frequency 32 16 8421 (mhz) m divide m5 m4 m3 m2 m1 m0 325 13 001101 350 14 001110 375 15 001111 400 16 0 1 0 0 0 0 600 24 011000 625 25 011001 650 26 011010 note 1: these m divide values and the resulting frequencies correspond to a reference frequency of 25mhz. table 5a parallel & serial modes function inputs mr np load m n s_load s_clock s_data conditions hx xx xx x reset, forces outputs low. ll data data x x x data on m and n inputs passed directly to the m divider and n output divider. test output forced low. l data data l x x data is latched into input registers and remains loaded until next low transition or until a serial event occurs. lh xx l data serial input mode. shift register is loaded with data on s_data on each rising edge of s_clock lh xx ld at a contents of the shift register are passed to the m divider and n output divider. lh xx ld at am divider and n output divider values are latched. lh xx lx xp arallel or serial input do not affect shift registers. lh xx h data s_data passed directly to m divider as it is clocked. note: l = low; h = high; x = don? care; = rising edge transition; = falling edge transition
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2004-11 preliminary specifications 6 micro netw orks an integrated circuit systems compan y table 5c parallel mode function serial mode function table 5d inputs n divider output frequency (mhz) n1 n0 value min max 00 1 311 700 01 2 155.5 350 10 4 77.75 175 11 83 8.875 87.5 inputs ref sel reference 0 diff_ref 1 ref_clk symbol parameter test conditions min typ max units v dd po wer supply voltage 3.135 3.3 3.465 v i dd po wer supply current 162 ma v cc = 3.3v 5%, t a = 0 c to 70 c symbol parameter test conditions min max units v ih input high ref_sel, s_load, s_ data, s_clock 2 vcc + 0.3 v v oltage np_load, n0:n1, m0:m5, mr ref_clk0, ref_clk1 2 vcc + 0.3 v v il input low ref_sel, s_load, s_data, s_clock -0.3 0.8 v v oltage np_load, n0:n1, m0:m5, mr ref_clk0, ref_clk1 -0.3 1.3 v i ih input high m5 v dd = v in = 3.465v 5 a current n0, n1, mr, m0:m4, s_clock, v dd = v in = 3.465v 150 a s_data, s_load, np_load, ref_sel, ref_clk0, ref_clk1 i il input low m5 v dd = 3.465, v in = 0v -150 a current n0, n1, mr, m0:m4, s_clock, v dd = 3.465, v in = 0v -5 a s_data, s_load, np_load, ref_sel, ref_clk0, ref_clk1 v oh output high voltage; note 1 2.6 v v ol output low voltage; note 1 0.5 v note 1: outputs terminated with 50 ? to v cc /2. see parameter measurement section, 3.3v output load test circuit. l vcmos/lvttl dc characteristics power supply dc characteristics
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2004-11 preliminary specifications 7 micro netw orks an integrated circuit systems compan y symbol parameter signal min max units v oh output high voltage: note 1 fout, nfout v dd ?1.4 vcc ?1.0 v v ol output low voltage: note 1 fout, nfout v dd ?2.0 vcc ?1.7 v v swing p eak-to-peak output voltage swing fout, nfout 0.6 0.85 v note 1: output terminated with 50 ? to v dd ?.v symbol parameter test conditions min max units f in input frequency ref_clk0, ref_clk1 10 166 mhz s_clock 50 mhz v cc = 3.3v 5%, t a = 0 c to 70 c symbol parameter test conditions min typ max units f out output frequency 38.88 700 mhz noise single side band 1khz offset -72 dbc/hz phase noise 10khz offset -94 dbc/hz 100khz offset -123 dbc/hz j (t) jitter (rms) 12khz to 20 mhz 0.69 ps odc output duty cycle 50 % t r output rise time fout = 155mhz 20% to 80%, each 350 450 550 ps (note 1) for output pairs fout = 311mhz output of pair measured 325 425 500 ps fout0, nfout0 & fout = 622mhz is terminated into 50 ? 200 275 350 ps fout1, nfout1 load biased at vcc-2v t f output fall time fout = 155mhz 20% to 80%, each 350 450 550 ps (note 1) for output pairs fout = 311mhz output of pair measured 325 425 500 ps fout0, nfout0 & fout = 622mhz is terminated into 50 ? 200 275 350 ps fout1, nfout1 load biased at vcc-2v t s setup time m, n, to np_load 5 ns s_data to s_clk 5 ns s_clk to s_load 5 ns t h hold time m,n, to np_load 5 ns s_data to s_clk 5 ns s_clk to s_load 5 ns t lock pll lock time 1 ms t pw output pulse tbd ns width tbd ns note: the output frequencies of 155mhz, 311mhz and 622mhz were chosen for device characterization as these are common optical n etwork clock frequencies. ac characteristics input frequency characteristics l vpecl dc characteristics
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2004-11 preliminary specifications 8 micro netw orks an integrated circuit systems compan y parameter measurement information odc & t period pulse width t period t pw t period odc = clock inputs and outputs 20% 80% 80% 20% t r t f v swing input and output rise and fall time thold thold tset-up tset-up tset-up s_data s_clock s_load m[5:0] n[1:0] np_load setup and hold time
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2004-11 preliminary specifications 9 micro netw orks an integrated circuit systems compan y test evaluation board j3 9-pin d connector pin signal 1mr 3 s_clock 5 s_data 7 s_load 9 np_load sw1 1 2345678 p osition ref select m5 m4 m3 m2 m1 m0 n/c off ref_clk0 ? ? ? ? ? ? n/c on ref_clk1 ? ? ? ? ? ? n/c jp1: n0 logic ? when installed jp2: n1 logic ? when installed
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2004-11 preliminary specifications 10 micro netw orks an integrated circuit systems compan y mechanical dimensions & pin configuration pin# designation 1 gnd 2 gnd 3 gnd 4 op_in 5 nop_out 6 nvc 7vc 8 op_out 9 nop_in 10 gnd 11 vdd 12 no 13 n1 14 gnd 15 fout 16 nfout 17 mr pin# designation 18 s_clock 19 vdd 20 s_data 21 s_load 22 np_load 23 ref_clk1 24 ref_clk0 25 ref_sel 26 gnd 27 m0 28 m1 29 m2 30 m3 31 m4 32 m5 33 vdd 34, 35, 36 n/c ordering information o rientati o n ta b [] .354 [ 9.0 ] .200 [ 5.1 ] r .006 [r 0.2 ] .025 [ 0.6 ] pin #1 c # 36 l .041 [ 1.0 ] .007 [ 0.2 ] c c l l #1 0 .354 [ 9.0 ] #2 8 #27 #1 9 #1 8 .110 [ 2.8 ] dimensions are in inches, (dimensions) are in mm. part number m2004-11-622.0800 series model vcso center frequency (i.e. 622.0800mhz) a vailable vcso frequencies 622.0800 669.1281 625.0000 669.3266 627.3296 672.1600 644.5313 690.5692 666.5143 693.4830 micro networks an integrated circuit systems company 32 4 clark street worcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 european sales headquarters hertogsingel 20 6214 ad maastricht t he netherlands tel: +31-43-32-70912 fax: +31-43-32-70715 www.micronetworks.com rev. 7.0 micro networks makes no assertion or warranty that the circuitry and the uses thereof disclosed herein are non-infringing on any valid us or foreign patents. micro networks assumes no liability as a result of the use of said specifications and reserves the right to make changes to specifications without notice. contact your nearest micro networks sales representative office for the latest specifications.
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