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WFP6462 november 12, 1999 1 rev. 0.03 i advanced product information signal driver 300-channel, 6-bit dot inversion driver for tft-lcd applications 1. product description the WFP6462 is a 6-bit, 300-channel signal driver designed for low power svga tft-lcd panel applications. the WFP6462 accepts 2 sets of ref- erence voltages ev0..ev8 and ov0..ov8. chan- nels v s2n use ev0..ev8, and channels v s2n-1 use ov0..ov8 (n = 1..150). this allows column or dot inversion to be easily implemented in single bank applications. the WFP6462s internal architecture provides separate resistor-string dacs for both the odd and even channels. the value of the individual resistor segments is weighted to reduce signal driver power dissipation by as much as 20% to 60% when compared to non-weighted resistor string dac architectures. 300 gate driver 300 300 800x600 gate driver data ... ....... reference amplifier circuit lcd control asic WFP6462 WFP6462 signal driver WFP6462 signal driver WFP6462 signal driver 262,144-color lcd from graphics controller control
2 november 12, 1999 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver 2. features & benefits features benefits ? weighted r-string: see figure 2-1 & table 2-1 ? reduces power dissipation 20-60% or more. ? reduces dc current drive requirements of external reference amplifiers ? low-power operation ? logic supply: 2.5 or 3.3 volts ? analog supply: 3.30.3 to 5.00.5 volts ? extends battery-based operation ? low power and emi from 3.3 v operation ? minimum dynamic-power dissipation ? high speed operation ? 65 mhz (3.3 volt logic supply) ? 45 mhz (2.5 volt logic supply) ? support for wide range of color lcd resolutions ? reduce emi & power dissipation in svga systems ? data inversion feature ? data inversion capability enables a complete internal solution for vcom modulation by data inversion. ? can reduce data transitions for lower emi & power ? full color display ? 64 gray scales per primary color ? 262,144 (256k) color palette ? excellent output uniformity ? output error = 0.15 lsb (12 mv @5v, 8 mv @3v) . . . ov 0 ov 8 . . ovr 00 ovr 01 ovr 62 . ovr 63 . . . ev 0 ev 8 . . evr 00 evr 01 evr 62 . evr 63 decoder vs 3 decoder vs 1 decoder vs 299 .... decoder vs 4 decoder vs 2 decoder vs 300 figure 2-1: block diagram d 00 -d 25 lp dclk ld300_1 eio1# eio300# data_inv 2xclk
november 12, 1999 3 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver ? internal weighted r-string for low power operation (see table 2-1 and figure 2-1). table 2-1: weighted r seg values for WFP6462 (ignoring bus resistance) r-segment value ev 7 ~ev 8 , ov 7 ~ov 8 51 w ,51 w ,51 w, 51 w ,51 w ,51 w ,102 w ,204 w ev 6 ~ev 7 , ov 6 ~ov 7 38 w x 8 ev 5 ~ev 6 , ov 5 ~ov 6 32 w x 8 ev 4 ~ev 5 , ov 4 ~ov 5 32 w x 8 ev 3 ~ev 4 , ov 3 ~ov 4 32 w x 8 ev 2 ~ev 3 , ov 2 ~ov 3 32 w x 8 ev 1 ~ev 2 , ov 1 ~ov 2 38 w x 8 ev 0 ~ev 1 , ov 0 ~ov 1 204 w ,102 w, 51 w ,51 w ,51 w, 51 w ,51 w . . . . . . ev 7 , ov 7 102 w 51 w 51 w 51 w 51 w 51 w 51 w vs 62 vs 61 vs 60 vs 59 vs 58 vs 57 vs 56 vs 55 . . . . . . . . 51 w 51 w 51 w 51 w 102 w 204 w vs 06 vs 05 vs 04 vs 03 vs 02 vs 01 vs 00 . . . . . . . . ev 8 , ov 8 ev 8 , ov 8 304 w 612 w 256 w 256 w 256 w 256 w 304 w 561 w figure 2-2: r-string detail vs 63 . 204 w ev 7 , ov 7 ev 6 , ov 6 ev 5 , ov 5 ev 4 , ov 4 ev 3 , ov 3 ev 2 , ov 2 ev 1 , ov 1 ev 0 , ov 0 ev 1 , ov 1 ev 0 , ov 0 . vs 07 51 w
4 november 12, 1999 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver 2.1. low svga power dissipation the WFP6462 provides a very low power dissipation solution of < 300 mw for module electronics (not including backlight power) for an all black image. table 2-2 shows the power dissipation for a typical svga system consisting of 8 WFP6462s and 2 cl- fp6131s (to provide 18 voltage references). 60 hz polarity inversion is assumed, resulting in negligible power dissipation for charging and discharging the panel capacitance. table 2C2. dissipation term mw due to amplifier idda: 18 x 400 ua x 5.0v 36 due to amplifier headrooms x load currents 37 due to WFP6462 r-string 28 due to WFP6462 iddd (active + standby) 30 charge digital lines & dclk 43 tcon asic: 30 ma x 3.3v 100 total 274
november 12, 1999 5 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver 3. die diagram & pad coordinates 3.1. die diagram x y (0,0) inputs outputs eio300 d25 d00 eio1 vs 1 vs 45 vs 56 vs 300 vs 256 vs 245 outputs outputs vs 255 vs 246 vs 46 vs 55
6 november 12, 1999 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver 3.2. input bond pad coordinates pad # signal x (um) y (um) 1 eio300# 2649.0 583.30 2 d25 2529.2 583.30 3 d24 2429.2 583.30 4 d23 2329.2 583.30 5 2xclk 2229.2 583.30 6 dclk 2129.2 583.30 7 ld300_1 2029.2 583.30 8 ov0 1909.4 583.30 9 ov8 1809.4 583.30 10 ev8 1709.4 583.30 11 ev0 1609.4 583.30 12 d22 1489.6 583.30 13 d21 1389.6 583.30 14 d20 1289.6 583.30 15 d15 1189.6 583.30 16 d14 1089.6 583.30 17 d13 989.6 583.30 18 vddd 869.8 583.30 19 vdda 769.8 583.30 20 ev1 650.0 583.30 21 ev7 550.0 583.30 22 ev3 450.0 583.30 23 ev5 350.0 583.30 24 ev6 250.0 583.30 25 ev4 150.0 583.30 26 ev2 50.0 583.30 27 ov2 -50.0 583.30 28 ov4 -150.0 583.30 29 ov6 -250.0 583.30 30 ov5 -350.0 583.30 31 ov3 -450.0 583.30 32 ov7 -550.0 583.30 33 ov1 -650.0 583.30 34 agnd -769.8 583.30 35 dgnd -869.8 583.30 36 d12 -989.6 583.30 37 d11 -1089.6 583.30 38 d10 -1189.6 583.30 39 d05 -1289.6 583.30 40 d04 -1389.6 583.30 41 data_inv -1489.6 583.30 42 ev0 -1609.4 583.30 43 ev8 -1709.4 583.30 44 ov8 -1809.4 583.30 45 ov0 -1909.4 583.30 46 lp -2029.2 583.30 47 d03 -2129.2 583.30 48 d02 -2229.2 583.30 49 d01 -2329.2 583.30 50 d00 -2429.2 583.30 51 eio1# -2549.0 583.30 table 3C1. input bond pad coordinates
november 12, 1999 7 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver 3.3. output bond pad coordinates table 3C2. output bond pad coordinates pad # signal x (um) y (um) 52 vs1 -3030.0 594.1 53 vs2 -3090.0 594.1 54 vs3 -3150.0 594.1 55 vs4 -3210.0 594.1 56 vs5 -3270.0 594.1 57 vs6 -3330.0 594.1 58 vs7 -3390.0 594.1 59 vs8 -3450.0 594.1 60 vs9 -3510.0 594.1 61 vs10 -3570.0 594.1 62 vs11 -3630.0 594.1 63 vs12 -3690.0 594.1 64 vs13 -3750.0 594.1 65 vs14 -3810.0 594.1 66 vs15 -3870.0 594.1 67 vs16 -3930.0 594.1 68 vs17 -3990.0 594.1 69 vs18 -4050.0 594.1 70 vs19 -4110.0 594.1 71 vs20 -4170.0 594.1 72 vs21 -4230.0 594.1 73 vs22 -4290.0 594.1 74 vs23 -4350.0 594.1 75 vs24 -4410.0 594.1 76 vs25 -4470.0 594.1 77 vs26 -4530.0 594.1 78 vs27 -4590.0 594.1 79 vs28 -4650.0 594.1 80 vs29 -4710.0 594.1 81 vs30 -4770.0 594.1 82 vs31 -4830.0 594.1 83 vs32 -4890.0 594.1 84 vs33 -4950.0 594.1 85 vs34 -5010.0 594.1 86 vs35 -5070.0 594.1 87 vs36 -5130.0 594.1 88 vs37 -5190.0 594.1 89 vs38 -5250.0 594.1 90 vs39 -5310.0 594.1 91 vs40 -5370.0 594.1 92 vs41 -5430.0 594.1 93 vs42 -5490.0 594.1 94 vs43 -5550.0 594.1 95 vs44 -5610.0 594.1 96 vs45 -5670.0 594.1 97 dummy -5743.0 598.1 98 vs46 -5739.1 409.5 99 vs47 -5739.1 318.5 100 vs48 -5739.1 227.5 101 vs49 -5739.1 136.5 102 vs50 -5739.1 45.5 103 vs51 -5739.1 -45.5 104 vs52 -5739.1 -136.5 105 vs53 -5739.1 -227.5 106 vs54 -5739.1 -318.5 107 vs55 -5739.1 -409.5 108 dummy -5743.0 -598.1 109 vs56 -5670.0 -594.1 110 vs57 -5610.0 -594.1 111 vs58 -5550.0 -594.1 112 vs59 -5490.0 -594.1 113 vs60 -5430.0 -594.1 114 vs61 -5370.0 -594.1 115 vs62 -5310.0 -594.1 116 vs63 -5250.0 -594.1 117 vs64 -5190.0 -594.1 118 vs65 -5130.0 -594.1 119 vs66 -5070.0 -594.1 120 vs67 -5010.0 -594.1 121 vs68 -4950.0 -594.1 122 vs69 -4890.0 -594.1 123 vs70 -4830.0 -594.1 124 vs71 -4770.0 -594.1 125 vs72 -4710.0 -594.1 126 vs73 -4650.0 -594.1 127 vs74 -4590.0 -594.1 128 vs75 -4530.0 -594.1 129 vs76 -4470.0 -594.1 130 vs77 -4410.0 -594.1 131 vs78 -4350.0 -594.1 132 vs79 -4290.0 -594.1 133 vs80 -4230.0 -594.1 134 vs81 -4170.0 -594.1 135 vs82 -4110.0 -594.1 136 vs83 -4050.0 -594.1 137 vs84 -3990.0 -594.1 138 vs85 -3930.0 -594.1 139 vs86 -3870.0 -594.1 140 vs87 -3810.0 -594.1 141 vs88 -3750.0 -594.1 142 vs89 -3690.0 -594.1 143 vs90 -3630.0 -594.1 144 vs91 -3570.0 -594.1 145 vs92 -3510.0 -594.1 146 vs93 -3450.0 -594.1 147 vs94 -3390.0 -594.1 148 vs95 -3330.0 -594.1 149 vs96 -3270.0 -594.1 150 vs97 -3210.0 -594.1 151 vs98 -3150.0 -594.1 152 vs99 -3090.0 -594.1 153 vs100 -3030.0 -594.1 154 vs101 -2970.0 -594.1 155 vs102 -2910.0 -594.1 156 vs103 -2850.0 -594.1 157 vs104 -2790.0 -594.1 158 vs105 -2730.0 -594.1 table 3C2. output bond pad coordinates pad # signal x (um) y (um)
8 november 12, 1999 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver 159 vs106 -2670.0 -594.1 160 vs107 -2610.0 -594.1 161 vs108 -2550.0 -594.1 162 vs109 -2490.0 -594.1 163 vs110 -2430.0 -594.1 164 vs111 -2370.0 -594.1 165 vs112 -2310.0 -594.1 166 vs113 -2250.0 -594.1 167 vs114 -2190.0 -594.1 168 vs115 -2130.0 -594.1 169 vs116 -2070.0 -594.1 170 vs117 -2010.0 -594.1 171 vs118 -1950.0 -594.1 172 vs119 -1890.0 -594.1 173 vs120 -1830.0 -594.1 174 vs121 -1770.0 -594.1 175 vs122 -1710.0 -594.1 176 vs123 -1650.0 -594.1 177 vs124 -1590.0 -594.1 178 vs125 -1530.0 -594.1 179 vs126 -1470.0 -594.1 180 vs127 -1410.0 -594.1 181 vs128 -1350.0 -594.1 182 vs129 -1290.0 -594.1 183 vs130 -1230.0 -594.1 184 vs131 -1170.0 -594.1 185 vs132 -1110.0 -594.1 186 vs133 -1050.0 -594.1 187 vs134 -990.0 -594.1 188 vs135 -930.0 -594.1 189 vs136 -870.0 -594.1 190 vs137 -810.0 -594.1 191 vs138 -750.0 -594.1 192 vs139 -690.0 -594.1 193 vs140 -630.0 -594.1 194 vs141 -570.0 -594.1 195 vs142 -510.0 -594.1 196 vs143 -450.0 -594.1 197 vs144 -390.0 -594.1 198 vs145 -330.0 -594.1 199 vs146 -270.0 -594.1 200 vs147 -210.0 -594.1 201 vs148 -150.0 -594.1 202 vs149 -90.0 -594.1 203 vs150 -30.0 -594.1 204 vs151 30.0 -594.1 205 vs152 90.0 -594.1 206 vs153 150.0 -594.1 207 vs154 210.0 -594.1 208 vs155 270.0 -594.1 209 vs156 330.0 -594.1 210 vs157 390.0 -594.1 211 vs158 450.0 -594.1 212 vs159 510.0 -594.1 213 vs160 570.0 -594.1 table 3C2. output bond pad coordinates pad # signal x (um) y (um) 214 vs161 630.0 -594.1 215 vs162 690.0 -594.1 216 vs163 750.0 -594.1 217 vs164 810.0 -594.1 218 vs165 870.0 -594.1 219 vs166 930.0 -594.1 220 vs167 990.0 -594.1 221 vs168 1050.0 -594.1 222 vs169 1110.0 -594.1 223 vs170 1170.0 -594.1 224 vs171 1230.0 -594.1 225 vs172 1290.0 -594.1 226 vs173 1350.0 -594.1 227 vs174 1410.0 -594.1 228 vs175 1470.0 -594.1 229 vs176 1530.0 -594.1 230 vs177 1590.0 -594.1 231 vs178 1650.0 -594.1 232 vs179 1710.0 -594.1 233 vs180 1770.0 -594.1 234 vs181 1830.0 -594.1 235 vs182 1890.0 -594.1 236 vs183 1950.0 -594.1 237 vs184 2010.0 -594.1 238 vs185 2070.0 -594.1 239 vs186 2130.0 -594.1 240 vs187 2190.0 -594.1 241 vs188 2250.0 -594.1 242 vs189 2310.0 -594.1 243 vs190 2370.0 -594.1 244 vs191 2430.0 -594.1 245 vs192 2490.0 -594.1 246 vs193 2550.0 -594.1 247 vs194 2610.0 -594.1 248 vs195 2670.0 -594.1 249 vs196 2730.0 -594.1 250 vs197 2790.0 -594.1 251 vs198 2850.0 -594.1 252 vs199 2910.0 -594.1 253 vs200 2970.0 -594.1 254 vs201 3030.0 -594.1 255 vs202 3090.0 -594.1 256 vs203 3150.0 -594.1 257 vs204 3210.0 -594.1 258 vs205 3270.0 -594.1 259 vs206 3330.0 -594.1 260 vs207 3390.0 -594.1 261 vs208 3450.0 -594.1 262 vs209 3510.0 -594.1 263 vs210 3570.0 -594.1 264 vs211 3630.0 -594.1 265 vs212 3690.0 -594.1 266 vs213 3750.0 -594.1 267 vs214 3810.0 -594.1 268 vs215 3870.0 -594.1 table 3C2. output bond pad coordinates pad # signal x (um) y (um)
november 12, 1999 9 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver 269 vs216 3930.0 -594.1 270 vs217 3990.0 -594.1 271 vs218 4050.0 -594.1 272 vs219 4110.0 -594.1 273 vs220 4170.0 -594.1 274 vs221 4230.0 -594.1 275 vs222 4290.0 -594.1 276 vs223 4350.0 -594.1 277 vs224 4410.0 -594.1 278 vs225 4470.0 -594.1 279 vs226 4530.0 -594.1 280 vs227 4590.0 -594.1 281 vs228 4650.0 -594.1 282 vs229 4710.0 -594.1 283 vs230 4770.0 -594.1 284 vs231 4830.0 -594.1 285 vs232 4890.0 -594.1 286 vs233 4950.0 -594.1 287 vs234 5010.0 -594.1 288 vs235 5070.0 -594.1 289 vs236 5130.0 -594.1 290 vs237 5190.0 -594.1 291 vs238 5250.0 -594.1 292 vs239 5310.0 -594.1 293 vs240 5370.0 -594.1 294 vs241 5430.0 -594.1 295 vs242 5490.0 -594.1 296 vs243 5550.0 -594.1 297 vs244 5610.0 -594.1 298 vs245 5670.0 -594.1 299 dummy 5743.0 -598.1 300 vs246 5739.1 -409.5 301 vs247 5739.1 -318.5 302 vs248 5739.1 -227.5 303 vs249 5739.1 -136.5 304 vs250 5739.1 -45.5 305 vs251 5739.1 45.5 306 vs252 5739.1 136.5 307 vs253 5739.1 227.5 308 vs254 5739.1 318.5 309 vs255 5739.1 409.5 310 dummy 5743.0 598.1 311 vs256 5670.0 594.1 312 vs257 5610.0 594.1 313 vs258 5550.0 594.1 314 vs259 5490.0 594.1 315 vs260 5430.0 594.1 316 vs261 5370.0 594.1 317 vs262 5310.0 594.1 318 vs263 5250.0 594.1 319 vs264 5190.0 594.1 320 vs265 5130.0 594.1 321 vs266 5070.0 594.1 322 vs267 5010.0 594.1 323 vs268 4950.0 594.1 table 3C2. output bond pad coordinates pad # signal x (um) y (um) 324 vs269 4890.0 594.1 325 vs270 4830.0 594.1 326 vs271 4770.0 594.1 327 vs272 4710.0 594.1 328 vs273 4650.0 594.1 329 vs274 4590.0 594.1 330 vs275 4530.0 594.1 331 vs276 4470.0 594.1 332 vs277 4410.0 594.1 333 vs278 4350.0 594.1 334 vs279 4290.0 594.1 335 vs280 4230.0 594.1 336 vs281 4170.0 594.1 337 vs282 4110.0 594.1 338 vs283 4050.0 594.1 339 vs284 3990.0 594.1 340 vs285 3930.0 594.1 341 vs286 3870.0 594.1 342 vs287 3810.0 594.1 343 vs288 3750.0 594.1 344 vs289 3690.0 594.1 345 vs290 3630.0 594.1 346 vs291 3570.0 594.1 347 vs292 3510.0 594.1 348 vs293 3450.0 594.1 349 vs294 3390.0 594.1 350 vs295 3330.0 594.1 351 vs296 3270.0 594.1 352 vs297 3210.0 594.1 353 vs298 3150.0 594.1 354 vs299 3090.0 594.1 355 vs300 3030.0 594.1 table 3C2. output bond pad coordinates pad # signal x (um) y (um)
10 november 12, 1999 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver 4. detailed pad descriptions the following abbreviations are used for pad types in the following sections: (i) input; (o) output; (i/o) input/output, (#) active low signal. name pad # type description ld300_1 7 i load direction: controls the direction in which the data is loaded into the input register: when ld300_1 = 0, data is loaded from channel v s1 to v s300 . when ld300_1 = 1, data is loaded from channel v s300 to v s1 . eio1#, eio300# 51,1 i/o enable in/out : the eio1# and eio300# active low sig- nals initiate the loading of data into the input register of the WFP6462. when one of the eiox# s is configured as an input, the other is configured as an output, with the direction determined by the ld300_1 input (see table 4-1). the eiox# outputs are designed to be connected to the eiox# inputs of adjacent devices to allow a series of drivers to operate sequentially. when a low is applied to the eiox# pin configured as an input on the first device in the series, data is loaded from the three sets of 6-bit data inputs into the first three 6-bit input-register locations. on subsequent transitions of the dclk, data continues to be loaded into the remaining 6-bit input-register locations. when the register is full (300 words), the eiox# pin configured as an output goes low, enabling the next driver. the data load sequence is summarized in table 4-1, figure 4-1 and figure 4-2. table 4-1: input/output selection for eio1# and eio300# ld300_1 input eio1#, eio300# functionality data loading sequence eio1# eio300# 0 input output channel 1 to 300 1 output input channel 300 to 1
november 12, 1999 11 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver figure 4C2. display data channel assignment and output sequence last first first last data loaded from channel v s1 to v s300 (ld300_1 = 0) data loaded from channel v s300 to v s1 (ld300_1 = 1) d 25 -d 20 d 15 -d 10 d 05 -d 00 d 25 -d 20 d 15 -d 10 d 05 -d 00 v s300 v s299 v s298 v s3 v s2 v s1 v s300 v s299 v s298 v s3 v s2 v s1 d 25 -d 20 d 15 -d 10 d 05 -d 00 d 25 -d 20 d 15 -d 10 d 05 -d 00 d 25 -d 20 d 15 -d 10 d 05 -d 00 d 25 -d 20 d 15 -d 10 d 05 -d 00 ..... ..... dclk d 05 -d 00 d 25 -d 20 d 15 -d 10 d 25 -d 20 d 15 -d 10 d 05 -d 00 v s4 vs 300 v s1 v s5 v s2 v s6 v s3 v s297 v s299 v s296 v s298 v s295 ld300_1 = 0 ld300_1 = 1 upper bank lower bank figure 4C1. display data sampling and output direction d 25 -d 20 d 15 -d 10 d 05 -d 00 d 25 -d 20 d 15 -d 10 d 05 -d 00 ..... lp dclk d 25 -d 20 d 15 -d 10 d 05 -d 00 d 25 -d 20 d 15 -d 10 d 05 -d 00 ..... lp dclk input reg. input reg. storage reg. storage reg. input bus input bus
12 november 12, 1999 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver name pad # type description ( cont. ) v s1 -v s300 see table 3-2 o voltage outputs : these outputs drive all 300 pixel inputs of the lcd simultaneously after the high-to-low tran- sition of lp. outputs are high impedance while lp is high . d 05 -d 00 39,40,47-50 i data : the data inputs consist of 6-bit words for each of d 15 -d 10 15-17,36-38 three channels. at the falling edge of dclk, three 6-bit d 25 -d 20 2-4,12-14 words for three adjacent channels are loaded in parallel. each data bit is represented as dij where: i = 2-0 indicates the channel j = 5-0 indicates the significance of the bit in each word. d i5 indicates the msb and d i0 indicates the lsb of the input word. lp 46 i latch pulse : when lp is driven high, the data is transferred from the input register into the storage register, and the selected analog voltages drive the lcd. also, the eiox# output is reset to the high level. dclk 6 i data clock : data is loaded into the input registers on the high-to-low transition of dclk for 2xclk= low and on both rising and falling edges of the dclk input for 2xclk = high. ov 8 9,44 i odd reference voltage inputs: these 9 inputs ov 7 32 supply the reference voltage inputs to the r-string dac ov 6 29 for the odd channels vs 1 , vs 3 , ..vs 299 ov 5 30 ov 4 28 note: both ov 8 inputs must be connected to each other ov 3 31 and to the same potential; also, both ov 0 inputs must be . ov 2 27 connected to each other and to the same potential ov 1 33 ov 0 8,45 ev 8 10,43 i even reference voltage inputs: these 9 inputs ev 7 21 supply the reference voltage inputs to the r-string dac ev 6 24 for the even channels vs 2 , vs 4 , ..vs 300 ev 5 23 ev 4 25 note: both ev 8 inputs must be connected to each other ev 3 22 and to the same potential; also, both ev 0 inputs must be . ev 2 26 connected to each other and to the same potential ev 1 20 ev 0 11,42 v ddd 18 i digital supply voltage : 2.5 v 0.2 or 3.3 v 0.3 should be provided on this pin to supply digital power to the device. v dda 19 i analog supply voltage : up to 5.5 v should be pro- vided on this pin to supply analog power to the device. also, must have v dda >= v ddd .
november 12, 1999 13 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver name pad# type description ( cont. ) agnd 34 i analog ground dgnd 35 i digital ground data_inv 41 i data inversion : the data inversion input signal, when logic high, enables inversion of the input display data (d ij ). this pad should be tied low or allowed to float if data inver- sion is not used. this signal may also be used in coordina- tion with the control asic to reduce data transitions. 2xclk 5 i 2xclk : when logic high, the 2xclk input enables sampling of input display data (d ij ) on both rising and falling edges of the dclk input (see figure 5-2). when logic low, input dis- play data is sampled on the falling edge of dclk only (see figure 5-1).
14 november 12, 1999 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver table 4-2: input data vs. output voltage msb display data lsb output voltage v n = ev n or ov n d 5 d 4 d 3 d 2 d 1 d 0 000000 v 0 000001v 0 + 204/561 x (v 1 - v 0 ) 000010v 0 + 306/561 x (v 1 - v 0 ) 000011v 0 + 357/561 x (v 1 - v 0 ) 000100v 0 + 408/561 x (v 1 - v 0 ) 000101v 0 + 459/561 x (v 1 - v 0 ) 000110v 0 + 510/561 x (v 1 - v 0 ) 000111 v 1 001000v 1 + 1/8 x (v 2 - v 1 ) 001001v 1 + 2/8 x (v 2 - v 1 ) 001010v 1 + 3/8 x (v 2 - v 1 ) 001011v 1 + 4/8 x (v 2 - v 1 ) 001100v 1 + 5/8 x (v 2 - v 1 ) 001101v 1 + 6/8 x (v 2 - v 1 ) 001110v 1 + 7/8 x (v 2 - v 1 ) 001111 v 2 010000v 2 + 1/8 x (v 3 - v 2 ) 010001v 2 + 2/8 x (v 3 - v 2 ) 010010v 2 + 3/8 x (v 3 - v 2 ) 010011v 2 + 4/8 x (v 3 - v 2 ) 010100v 2 + 5/8 x (v 3 - v 2 ) 010101v 2 + 6/8 x (v 3 - v 2 ) 010110v 2 + 7/8 x (v 3 - v 2 ) 010111 v 3 011000v 3 + 1/8 x (v 4 - v 3 ) 011001v 3 + 2/8 x (v 4 - v 3 ) 011010v 3 + 3/8 x (v 4 - v 3 ) 011011v 3 + 4/8 x (v 4 - v 3 ) 011100v 3 + 5/8 x (v 4 - v 3 ) 011101v 3 + 6/8 x (v 4 - v 3 ) 011110v 3 + 7/8 x (v 4 - v 3 ) 011111 v 4 100000v 4 + 1/8 x (v 5 - v 4 ) 100001v 4 + 2/8 x (v 5 - v 4 ) 100010v 4 + 3/8 x (v 5 - v 4 ) 100011v 4 + 4/8 x (v 5 - v 4 ) 100100v 4 + 5/8 x (v 5 - v 4 ) 100101v 4 + 6/8 x (v 5 - v 4 ) 100110v 4 + 7/8 x (v 5 - v 4 ) 100111 v 5 101000v 5 + 1/8 x (v 6 - v 5 ) 101001v 5 + 2/8 x (v 6 - v 5 ) 101010v 5 + 3/8 x (v 6 - v 5 ) 101011v 5 + 4/8 x (v 6 - v 5 ) 101100v 5 + 5/8 x (v 6 - v 5 ) 101101v 5 + 6/8 x (v 6 - v 5 ) 101110v 5 + 7/8 x (v 6 - v 5 ) 101111 v 6 110000v 6 + 1/8 x (v 7 - v 6 ) 110001 v 6 x 2/8 x (v 7 - v 6 ) 110010v 6 + 3/8 x (v 7 - v 6 ) 110011v 6 + 4/8 x (v 7 - v 6 ) 110100v 6 + 5/8 x (v 7 - v 6 ) 110101v 6 + 6/8 x (v 7 - v 6 ) 110110v 6 + 7/8 x (v 7 - v 6 ) 110111 v 7 111000v 7 + 51/612 x (v 8 - v 7 ) 111001v 7 + 102/612 x (v 8 - v 7 ) 111010v 7 + 153/612 x (v 8 - v 7 ) 111011v 7 +204/612 x (v 8 - v 7 ) 111100v 7 + 255/612 x (v 8 - v 7 ) 111101v 7 + 306/612 x (v 8 - v 7 ) 111110v 7 + 408/612 x (v 8 - v 7 ) 111111 v 8
november 12, 1999 15 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver 5. electrical specifications 5.1 absolute maximum ratings symbol parameter min max units notes v ddd digital power supply voltage -0.3 smaller of 6.0 volts 1,2,4 or v dda v dda analog power supply voltage -0.3 6.0 volts 1,2,4 ev 8 - ev 0 analog reference voltage inputs -0.3 v dda + 0.3 volts 1,2 ov 8 - ov 0 v s300 -v s1 output voltage -0.3 v dda + 0.3 volts 1,2 v in voltage on any digital input -0.3 v ddd + 0.3 volts 1,2,3 p d operating power dissipation 300 mw t a operating temperature -20 85 c 1 (ambient temperature under bias) t str storage temperature -30 85 c 1 notes: 1) stresses above those listed may cause permanent damage to system components. these are stress ratings only. functional operation at these or any conditions above those indicated in the operational ratings of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect system re liability. 2) all voltages are with respect to ground (dgnd) unless otherwise noted. 3) for d 25 -d 20 , d 15 -d 10 , d 05 -d 00 , dclk, data_inv, 2xclk, lp, eio1#, eio300# and ld300_1 input pads. 4) v dda must be greater than or equal to v ddd for proper circuit operation . for this rea- son, v dda should be powered on first (or at the same time as v ddd ). also, v ddd should be powered off first, or at same time as v dda .
16 november 12, 1999 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver 5.2 recommended operating conditions symbol parameter min typical max units notes v ddd digital supply voltage 2.3 2.5 2.7 volts 1 3.0 3.3 3.6 volts 1 v dda analog supply voltage 4.5 5.0 5.5 volts 1 t a ambient temperature 0 25 70 c ev 8 - ev 0 analog reference voltage 0 v dda volts 1, 2 ov 8 - ov 0 i ref analog reference current 20 ma notes: 1) all voltages are with respect to ground (dgnd) unless otherwise noted. 2) case i: v dda 3 v 8 3 v 7 3 v 6 3 v 5 3 v 4 3 v 3 3 v 2 3 v 1 3 v 0 for ev n or ov n case ii: v dda 3 v 0 3 v 1 3 v 2 3 v 3 3 v 4 3 v 5 3 v 6 3 v 7 3 v 8 for ev n or ov n
november 12, 1999 17 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver 5.3 dc characteristics (preliminary data C subject to change) v dda = 5 v 0.5 v, t a = 25 c, unless otherwise specified symbol parameter min typ max units test conditions note v s analog output voltage vdda-0.03 volts 1 v st analog output transition band |e/ov 8 -e/ov 0 | volts v err analog output error voltage -0.15 +0.15 lsb 2 v ih logic input high voltage 0.7v ddd volts 3 v il logic input low voltage 0.3v ddd volts 3 v oh logic output high voltage v ddd - 0.4 volts i oh = - 0.4 ma 4 v ol logic output low voltage 0.4 volts i ol = 0.4 ma 4 i qr reference quiescent current 0.53 0.9 1.27 ma 5 i dda analog supply current 400 a v dda = 5.0 v 6 i ddd digital-supply current (active) 3.5 5.0 ma v ddd = 2.5 v 6 5.0 7.0 ma v ddd = 3.3 v 6 i ddd digital-supply current (stand-by) 80 400 a v ddd = 2.5 v 7 100 400 a v ddd = 3.3 v 7 i in input leakage current -5 +5 a 0 < v in < v ddd c in input capacitance 5 pf 4 r string string resistance e/ov0-e/ov1 380 561 723 w e/ov1-e/ov2 219 304 389 e/ov2-e/ov3 185 256 327 e/ov3-e/ov4 185 256 327 e/ov4-e/ov5 185 256 327 e/ov5-e/ov6 185 256 327 e/ov6-e/ov7 219 304 389 e/ov7-e/ov8 434 612 790 r out output resistance e/ov 0 -e/ov 1 ( at code 2) 23.8 k w e/ov 1 -e/ov 2 ( at code 11) 14.4 e/ov 2 -e/ov 3 ( at code 19) 12.5 e/ov 3 -e/ov 4 ( at code 27) 12.5 e/ov 4 -e/ov 5 ( at code 35) 12.5 e/ov 5 -e/ov 6 ( at code 43) 12.5 e/ov 6 -e/ov 7 ( at code 51) 14.4 e/ov 7 -e/ov 8 ( at code 61) 25.9 notes : 1) see table 4-2 for digital code-voltage relationship. 2) for all codes 3) dclk, lp, data_inv, 2xclk, d 25 -d 20 , d 15 -d 10 , d 05 -d 00 , eio1#, eio300#, and ld300_1 inputs
18 november 12, 1999 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver 4) eio1# and eio300# outputs 5) quiescent current into e/ov 0 and out of e/ov 8 with |e/ov 0 -e/ov 8 | = 2.5v and all other references floating. 6) f dclk =12.5 mhz, f lp = 30 khz, device is loading,100% of data lines toggle each dclk cycle 7) f dclk =12.5 mhz, f lp = 30 khz, device is not loading,100% of data lines toggle each dclk cycle
november 12, 1999 19 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver 5.4 ac characteristics ( v ddd = 3.3 v 0.3 v ) C (preliminary data C subject to change) see figures 5-1 to 5-4 for waveforms. conditions: v dda = 5.0 v 0.5 v, t a = 25 c symbol parameter min max units note 2xclk /2xclk 2xclk /2xclk f max maximum dclk frequency 65/32.5 mhz t clk dclk period 15.4/30.8 ns t 1 dclk high pulse width 6/6 ns t 2 dclk low pulse width 6/6 ns t 3 dclk, lp rise time 6/6 ns t 4 dclk, lp fall time 6/6 ns t 5 data setup to dclk 0/0 ns t 6 data hold from dclk 5/7 ns t 7 data_inv setup to dclk 2/2 ns t 8 data_inv hold from dclk 3/5 ns t 9 dclk low to lp high 50/50 ns t 10 lp low to dclk high 50/50 ns t 11 lp high pulse width 50/50 ns 1 t 12 enable-in setup to dclk 3/-2 ns t 13 dclk to enable-out low 10/14 ns 2 notes: 1) lp width should not be wider than necessary since outputs dont drive to the next value until lp goes low. 2) c load = 15 pf (see figure 5-5)
20 november 12, 1999 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver 5.5 ac characteristics ( v ddd = 2.5 v 0.2 v ) C (preliminary data C subject to change) see figures 5-1 to 5-4 for waveforms. conditions: v dda = 5.0 v 0.5 v, t a = 25 c symbol parameter min max units note 2xclk /2xclk 2xclk /2xclk f max maximum dclk frequency 45/22.5 mhz t clk dclk period 22.2/44.4 ns t 1 dclk high pulse width 8/8 ns t 2 dclk low pulse width 8/8 ns t 3 dclk, lp rise time 6/6 ns t 4 dclk, lp fall time 6/6 ns t 5 data setup to dclk 1/1 ns t 6 data hold from dclk 6/12 ns t 7 data_inv setup to dclk 3/3 ns t 8 data_inv hold from dclk 4/10 ns t 9 dclk low to lp high 50/50 ns t 10 lp low to dclk high 50/50 ns t 11 lp high pulse width 50/50 ns 1 t 12 enable-in setup to dclk 6/-2 ns t 13 dclk to enable-out low 14/18 ns 2 notes: 1) lp width should not be wider than necessary since outputs dont drive to the next value until lp goes low. 2) c load = 15 pf (see figure 5-5)
november 12, 1999 21 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver figure 5-1: dclk and data input timing relationship (2xclk = low) figure 5-2: dclk and data input timing relationship (2xclk = high) note: when 2xclk = high, the first rising edge of dclk after lp falling edge clocks in the first display data word. dclk d ij 0.3v ddd 0.3v ddd 0.7v ddd 0.3v ddd t 3 t 1 t 4 t 2 t clk t 5 t 6 data_inv 0.7v ddd 0.3v ddd 0.3v ddd 0.7v ddd t 7 t 8 dclk d ij 0.3v ddd 0.3v ddd 0.7v ddd 0.3v ddd t 3 t 1 t 4 t 2 t clk t 5 t 5 t 6 0.7v ddd t 6 data_inv 0.7v ddd 0.3v ddd t 7 t 7 t 8 t 8 data n+1 data n
22 november 12, 1999 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver figure 5-3: lp, dclk, eio1#and eio300# timing relationship (2xclk low) figure 5-4: lp, dclk, eio1#and eio300# timing relationship (2xclk high) dclk lp enable output enable input 0.7v ddd 0.3v ddd 0.3v ddd t 11 t 9 t 10 t 12 0.7v ddd dclk[1] dclk[100] t 13 0.3v ddd t 3 t 4 0.3v ddd 0.3v ddd dclk lp enable output enable input 0.7v ddd 0.3v ddd 0.3v ddd t 11 t 9 t 10 t 12 0.3v ddd dclk[1] t 13 0.3v ddd t 3 t 4 0.3v ddd dclk[50] 0.3v ddd
november 12, 1999 23 rev. 0.03 WFP6462 300-channel 6-bit dot inversion driver changes from cl-fp6462 version 0.02 changes from cl-fp6462 version 0.01 date of issue page description timing specs t 1 to t 13 change as follows: feb. 14, 1997 19-22 separate setup & hold times for dij & data_inv inputs. 19-22 change definition & value of enable-in setup to dclk & dclk to enable-out. 19-22 show dependence of timing specs on 2xclk mode 22-23 eliminate old figure 5-5; add new figure 5-4 showing 2xclk eio timing. date of issue page description september 26,1996 10,12,13 add pad numbers to pad description table 19,20 change t 5 ,t 6 ,t 12 ,t 13 c l = 15pf eio1#, eio300# enable out figure 5-5: capacitive load test circuit

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