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1 features ? data retention for at least 10 years without power ? automatic write-protection during power-up/power-down cycles ? conventional sram operation, including unlimited write cycles ? internal isolation of battery be - fore power application ? industry standard 32-pin dip pinout ? 34-pin lifetime lithium? module - module completely surface-mounted - snap-on power-source for lithium battery backup - replaceable power-source (part number: bq40ms) general description the cmos bq4015/y is a nonvola - tile 4,194,304-bit static ram organ - ized as 524,288 words by 8 bits. the integral control circuitry and lith - ium energy source provide reliable nonvolatility coupled with the un - limited write cycles of standard sram. the control circuitry constantly monitors the single 5v supply for an out-of-tolerance condition. when v cc falls out of tolerance, the sram is unconditionally write-protected to prevent an inadvertent write opera - tion. at this time the integral energy source is switched on to sustain the memory until after v cc returns valid. the bq4015/y uses extremely low standby current cmos srams, cou - pled with small lithium coin cells to provide nonvolatility without long write-cycle times and the write-cycle limitations associated with ee - prom. the bq4015/y requires no external circuitry and is compatible with the industry-standard 4mb sram pin - out. 1 pn401501.eps 32-pin dip module 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 9 10 24 23 11 12 22 21 13 14 20 19 15 16 18 17 v cc a 15 a 17 we a 13 a 8 a 9 a 11 oe a 10 ce dq 7 dq 6 dq 5 dq 4 dq 3 a 18 a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 0 dq 1 dq 2 v ss pin names a0?a18 address inputs dq0?dq7 data input/output ce chip enable input oe output enable input we write enable input nc no connect v cc supply voltage input v ss ground bq4015/y 5/99 e pin connections 512kx8 nonvolatile sram pn4015yncm.eps 34-pin lifetime lithium module 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 34 33 32 31 30 29 28 27 26 25 nc a15 a16 nc v cc we oe ce dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 v ss a18 a17 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 selection guide part number maximum access time (ns) negative supply tolerance part number maximum access time (ns) negative supply tolerance bq4015x -70 70 -5% bq4015yx -70 70 -10% bq4015x -85 85 -5% bq4015yx -85 85 -10% note: x = ma for pdip or ms for lifetime lithium module.
functional description when power is valid, the bq4015/y operates as a stan - dard cmos sram. during power-down and power-up cycles, the bq4015/y acts as a nonvolatile memory, auto - matically protecting and preserving the memory con - tents. power-down/power-up control circuitry constantly moni - tors the v cc supply for a power-fail-detect threshold v pfd . the bq4015 monitors for v pfd = 4.62v typical for use in systems with 5% supply tolerance. the bq4015y monitors for v pfd = 4.37v typical for use in systems with 10% supply tolerance. when v cc falls below the v pfd threshold, the sram automatically write-protects the data. all outputs be - come high impedance, and all inputs are treated as ?don?t care.? if a valid access is in process at the time of power-fail detection, the memory cycle continues to com - pletion. if the memory cycle fails to terminate within time t wpt , write-protection takes place. as v cc falls past v pfd and approaches 3v, the control circuitry switches to the internal lithium backup supply, which provides data retention until valid v cc is applied. when v cc returns to a level above the internal backup cell voltage, the supply is switched back to v cc . after v cc ramps above the v pfd threshold, write-protection continues for a time t cer (120ms maximum) to allow for processor stabilization. normal memory operation may resume after this time. the internal coin cells used by the bq4015/y have an ex - tremely long shelf life and provide data retention for more than 10 years in the absence of system power. as shipped from unitrode, the integral lithium cells of the mt-type module are electrically isolated from the memory. (self-discharge in this condition is approxi - mately 0.5% per year.) following the first application of v cc , this isolation is broken, and the lithium backup provides data retention on subsequent power-downs. the lifetime lithium package option is shipped as two parts. 2 bq4015/y block diagram oe a 0 ?a 18 dq 0 ?dq 7 we ce lithium cell ce con v cc 1024k x 8 sram block power-fail control power bd4015.eps
3 bq4015/y truth table mode ce we oe i/o operation power not selected h x x high z standby output disable l h h high z active read l h l d out active write l l x d in active absolute maximum ratings symbol parameter value unit conditions v cc dc voltage applied on v cc relative to v ss -0.3 to 7.0 v v t dc voltage applied on any pin excluding v cc relative to v ss -0.3 to 7.0 v v t v cc + 0.3 t opr operating temperature 0 to +70 c commercial -40 to +85 c industrial ?n? t stg storage temperature -40 to +70 c commercial -40 to +85 c industrial ?n? t bias temperature under bias -10 to +70 c commercial -40 to +85 c industrial ?n? t solder soldering temperature +260 c for 10 seconds note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be limited to the recommended dc operating conditions detailed in this data sheet. exposure to con - ditions beyond the operational limits for extended periods of time may affect device reliability.
4 bq4015/y recommended dc operating conditions (t a = t opr ) symbol parameter minimum typical maximum unit notes v cc supply voltage 4.5 5.0 5.5 v bq4015y 4.75 5.0 5.5 v bq4015 v ss supply voltage 0 0 0 v v il input low voltage -0.3 - 0.8 v v ih input high voltage 2.2 - v cc + 0.3 v note: typical values indicate operation at t a = 25c. dc electrical characteristics (t a = t opr , v ccmin v cc v ccmax ) symbol parameter minimum typical maximum unit conditions/notes i li input leakage current - - 1 av in = v ss to v cc i lo output leakage current - - 1 a ce = v ih or oe = v ih or we = v il v oh output high voltage 2.4 - - v i oh = -1.0 ma v ol output low voltage - - 0.4 v i ol = 2.1 ma i sb1 standby supply current - 3 5 ma ce = v ih i sb2 standby supply current - 0.1 1 ma ce v cc - 0.2v, 0v v in 0.2v, or v in v cc - 0.2 i cc operating supply current - - 90 ma min. cycle, duty = 100%, ce = v il , i i/o = 0ma, a17 < v il or a17 > v ih , a18 < v il or a18 > v ih v pfd power-fail-detect voltage 4.55 4.62 4.75 v bq4015 4.30 4.37 4.50 v bq4015y v so supply switch-over voltage - 3 - v note: typical values indicate operation at t a = 25c, v cc = 5v. capacitance (t a = 25c, f = 1mhz, v cc = 5.0v) symbol parameter minimum typical maximum unit conditions c i/o input/output capacitance - - 8 pf output voltage = 0v c in input capacitance - - 10 pf input voltage = 0v note: these parameters are sampled and not 100% tested.
5 bq4015/y ac test conditions parameter test conditions input pulse levels 0v to 3.0v input rise and fall times 5 ns input and output timing reference levels 1.5 v (unless otherwise specified) output load (including scope and jig) see figures 1 and 2 figure 2. output load b figure 1. output load a read cycle (t a = t opr , v ccmin v cc v ccmax ) symbol parameter -70 -85/-85n -120/-120n unit conditions min. max. min. max. min. max. t rc read cycle time 70 - 85 - 120 - ns t aa address access time - 70 - 85 - 120 ns output load a t ace chip enable access time - 70 - 85 - 120 ns output load a t oe output enable to output valid - 35 - 45 - 60 ns output load a t clz chip enable to output in low z 5 - 5 - 5 - ns output load b t olz output enable to output in low z 5 - 0 - 0 - ns output load b t chz chip disable to output in high z 0 25 0 35 0 45 ns output load b t ohz output disable to output in high z 0 25 0 25 0 35 ns output load b t oh output hold from address change 10 - 10 - 10 - ns output load a
6 bq4015/y notes: 1. we is held high for a read cycle. 2. device is continuously selected: ce =oe = v il . 3. address is valid prior to or coincident with ce transition low. 4. oe = v il . 5. device is continuously selected: ce = v il . read cycle no. 3 (oe access) 1,5 read cycle no. 1 (address access) 1, 2 read cycle no. 2 (ce access) 1, 2, 3
7 bq4015/y write cycle (t a = t opr ,v ccmin v cc v ccmax ) symbol parameter -70 -85/-85n -120/-120n units conditions/notes min. max. min. max. min. max. t wc write cycle time 70 - 85 - 120 - ns t cw chip enable to end of write 65 - 75 - 100 - ns (1) t aw address valid to end of write 65 - 75 - 100 - ns (1) t as address setup time 0 - 0 - 0 - ns measured from address valid to beginning of write. (2) t wp write pulse width 55 - 65 - 85 - ns measured from begin - ning of write to end of write. (1) t wr1 write recovery time (write cycle 1) 5-5-5-ns measured from we go - ing high to end of write cycle. (3) t wr2 write recovery time (write cycle 2) 15-15-15- ns measured from ce going high to end of write cy- cle. (3) t dw data valid to end of write 30 - 35 - 45 - ns measured to first low- to-high transition of ei- ther ce or we . t dh1 data hold time (write cycle 1) 0-0-0-ns measured from we go- ing high to end of write cycle. (4) t dh2 data hold time (write cycle 2) 10-10-10- ns measured from ce going high to end of write cy - cle. (4) t wz write enabled to output in high z 025030040ns i/o pins are in output state. (5) t ow output active from end of write 5-0-0-ns i/o pins are in output state. (5) notes: 1. a write ends at the earlier transition of ce going high and we going high. 2. a write occurs during the overlap of a low ce and a low we . a write begins at the later transition of ce going low and we going low. 3. either t wr1 or t wr2 must be met. 4. either t dh1 or t dh2 must be met. 5. if ce goes low simultaneously with we going low or after we going low, the outputs remain in high-impedance state.
8 bq4015/y write cycle no. 1 (we-controlled) 1,2,3 write cycle no. 2 (ce-controlled) 1,2,3,4,5 notes: 1. ce or we must be high during address transition. 2. because i/o may be active (oe low) during this period, data input signals of opposite polarity to the outputs must not be applied. 3. if oe is high, the i/o pins remain in a state of high impedance. 4. either t wr1 or t wr2 must be met. 5. either t dh1 or t dh2 must be met.
9 bq4015/y power-down/power-up cycle (t a = t opr ) symbol parameter minimum typical maximum unit conditions t pf v cc slew, 4.75 to 4.25 v 300 - - s t fs v cc slew, 4.25 to v so 10 - - s t pu v cc slew, v so to v pfd (max.) 0 - - s t cer chip enable recovery time 40 80 120 ms time during which sram is write-protected after v cc passes v pfd on power-up. t dr data-retention time in absence of v cc 10 - - years t a = 25c. (2) t wpt write-protect time 40 100 150 s delay after v cc slews down past v pfd before sram is write- protected. notes: 1. typical values indicate operation at t a = 25c, v cc = 5v. 2. batteries are disconnected from circuit until after v cc is applied for the first time. t dr is the accumulated time in absence of power beginning when power is first applied to the device. caution: negative undershoots below the absolute maximum rating of -0.3v in battery-backup mode may affect data integrity. power-down/power-up timing
10 bq4015/y ma: 32-pin a-type module 32-pin ma ( a-type module ) dimension minimum maximum a 0.365 0.375 a1 0.015 - b 0.017 0.023 c 0.008 0.013 d 1.670 1.700 e 0.710 0.740 e 0.590 0.630 g 0.090 0.110 l 0.120 0.150 s 0.075 0.110 all dimensions are in inches. 34-pin lcr lifetime lithium module dimension minimum maximum a 0.920 0.930 b 0.980 0.995 c - 0.080 d 0.052 0.060 e 0.045 0.055 f 0.015 0.025 g 0.020 0.030 h - 0.090 j 0.053 0.073 all dimensions are in inches. ms: 34-pin leaded chip carrier for lifetime lithium m odule 1 centerline of lead within 0.005 of true position. 2 leads coplanar within 0.004 at seating plane. 3 components and location may vary.
11 bq4015/y ms: lifetime lithium module with lcr attached lifetime lithium module dimension minimum maximum a 0.955 0.965 b 0.980 0.995 c 0.240 0.250 d 0.052 0.060 e 0.045 0.055 f 0.015 0.025 all dimensions are in inches. 1 leads coplanar within 0.004 at seating plane. 2 components and location may vary. ms: lifetime lithium module housing lifetime lithium module housing dimension minimum maximum a 0.845 0.855 b 0.955 0.965 c 0.210 0.220 d 0.065 0.075 e 0.065 0.075 all dimensions are in inches. 1 edges coplanar within 0.025.
12 bq4015/y data sheet revision history change no. page no. description nature of change 13i cc test conditions clarification 2 1, 2, 3, 4, 7, 8, 10 bq4015ma part addition 32,10 added industrial temperature range addition 4 1, 3, 10 removed mb package selection deletion 5 1, 10 added ms package addition notes: change 1 = sept. 1992 b changes from sept. 1990 a. change 2 = nov. 1993 c changes from sept. 1992 b. change 3 = june 1995 c changes from nov. 1993 c. change 4 = nov. 1997 d changes from june 1995 c. change 5 = may 1999 e changes from nov. 1997 d. ordering information bq4015 xx - speed options: 70 = 70 ns 85 = 85 ns 120 = 120 ns package option: ma = a-type module ms = lifetime lithium lcr34 (preliminary package option) 2 supply tolerance: no mark = 5% negative supply tolerance y = 10% negative supply tolerance device: bq4013 128 k x 8 nvsram temperature: blank = commercial (0 to +70c) n = industrial (-40 to +85c) 1 notes: 1. only 10% supply (?y-ma?) version is available in industrial temperature range; contact factory for speed grade availability. 2. the lifetime lithium module is ordered seperately under part number bq40ms.

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