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gennum corporation p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 e-mail: info@gennum.com www.gennum.com revision date: july 2001 document no. 18303 - 0 preliminary data sheet gf9331 gennum proprietary and confidential features features features features ? seamless interface to gennum?s gf9330 edge adaptive and vertical motion adaptive control bus (4-bits) seamlessly interfaces to the gf9330 support for multiple input data formats with multiplexed and separate y/c channels ability to extract hvf information from embedded trs edge detection along nine directions vertical motion detection support for both 8-bit and 10-bit video signals flexibility to handle generic input data formats that have less than 2046 active samples per line user configuration through a dedicated host interface, supporting parallel and serial interfaces seamless interface to gennum?s gs1500/gs1510/ gs9020 seamless interface to popular ntsc/pal decoders default power-up mode dedicated reset pin 5v tolerant inputs 3.3v supply for device i/o and 2.5v for core logic ieee 1149.1 compliant jtag test port device overview device overview device overview device overview the gf9331 is a high performance motion co-processor that is used in conjunction with gennum?s gf9330 sdtv/ hdtv de-interlacer. together, the gf9331 and the gf9330 implement a motion adaptive de-interlacer for both sdtv and hdtv digital television signals. the gf9331 contains pixel-based adaptive edge detectors that cover nine different edge directions and a vertical motion detector that covers special motions in the vertical direction. edge sensitive and motion adaptive control signals are generated by the gf9331 and fed to the gf9330. the gf9331 integrates all the necessary line delays for the motion/edge detectors. the gf9331 also provides seamless interfaces to off-chip sdrams that form the required field delays. applications applications applications applications hdtv upconverters/downconverters projection systems plasma displays/lcd displays video walls home theater systems hd dvd players block diagram block diagram block diagram block diagram ordering information ordering information ordering information ordering information part number package temp. range GF9331-CBP 328 pin bga 0c to 70c pre-filter encoder edge detection vertical motion detection y/c control bus to gf9330 (fil.sel[3:0]) external memory interface delay y'/c' to gf9330 gen ? gf9331 gf9331 gf9331 gf9331 sdtv/hdtv motion co-processor sdtv/hdtv motion co-processor sdtv/hdtv motion co-processor sdtv/hdtv motion co-processor
gennum corporation 18303 - 0 2 gf9331 gennum proprietary and confidential fig. 1 top view pin out 328 bga a b c d j k e f g h l m n p w y r t u v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 reset y_in9 nc nc y_in8 y_in5 y_in7 y_in4 s2_dat0 s2_dat1 s2_dat2 s2_dat3 y_in6 y_in3 nc nc s2_dat4 s2_dat5 s2_dat7 s2_dat8 s2_dat6 nc s2_dat9 nc s2_dat10 s2_dat11 s2_dat13 s2_dat14 s2_dat12 nc s2_dat15 nc s2_clk s2_addr0 s2_addr2 s2_addr3 s2_addr1 nc s2_addr4 nc s2_addr7 s2_addr6 s2_addr10 s2_addr9 s2_addr5 nc s2_addr8 nc s2_addr13 s2_addr12 s2_cs s2_cas s2_addr11 nc nc nc s2_we s2_ras nc nc nc nc nc nc nc nc nc nc nc nc nc y_out3 nc nc y_out9 y_out8 y_out6 y_out4 y_out7 y_out5 y_in2 vclk_in y_in1 nc ser_md memclk_in std4 std1 y_in0 mode host_en nc std3 std0 std2 xvoclk_sl gnd vdd_clkd vdd_int vdd_int vss_clkd gnd vdd_int gnd vdd_io vdd_io nc gnd vdd_io gnd vdd_int nc gnd gnd vdd_io vdd_io gnd vdd_int gnd vdd_int gnd nc nc nc nc nc nc nc y_out1 nc y_out2 nc nc nc nc c_out9 xvoclk_in c_in7 nc c_in6 c_in0 ed_mode c_in1 vm_mode c_in9 c_in5 c_in8 c_in4 c_in2 nc c_in3 nc vdd_io gnd vdd_int gnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd vdd_io gnd gnd vdd_io nc nc c_out6 c_out3 nc nc c_out2 nc c_out7 c_out4 c_out8 c_out5 c_out1 fil_sel3 c_out0 fil_sel2 fvh_en a_d f_in cs dat_io4 dat_io0 dat_io5 dat_io1 v_in r_w h_in nc dat_io6 dat_io2 dat_io7 dat_io3 vdd_io gnd gnd nc gnd vdd_int vdd_int vdd_io vdd_io nc gnd vdd_io gnd vdd_int nc gnd gnd gnd vdd_int vdd_io vdd_io vdd_int gnd nc nc nc nc nc nc nc nc fil_sel1 nc fil_sel0 h_out nc nc v_out f_out tclk gnd tms gnd tdo nc nc nc tdi nc gnd nc nc nc s1_ras s1_we nc nc nc s1_addr11 s1_cas s1_cs s1_addr12 s1_addr13 nc s1_addr8 nc s1_addr5 s1_addr9 s1_addr10 s1_addr6 s1_addr7 nc s1_addr2 nc s1_addr0 s1_addr3 s1_addr4 s1_addr1 s1_clk nc s1_dat15 nc s1_dat12 s1_dat14 s1_dat13 s1_dat11 s1_dat10 nc s1_dat9 nc s1_dat6 s1_dat8 s1_dat7 s1_dat5 s1_dat4 nc s1_dat3 nc nc s1_dat2 s1_dat1 nc s1_dat0 nc nc gnd nc nc nc nc nc gnd nc gnd nc nc nc nc nc y_out0 top view gf9331 pin out 328 bga gnd: 0v nc: no connection vdd_io: +3.3v vdd_int: +2.5v
gennum corporation 18303 - 0 3 gf9331 gennum proprietary and confidential pin descriptions pin descriptions pin descriptions pin descriptions symbol pin grid type description reset a1 i active low, asynchronous reset , resets all internal state machines to their default conditions. vclk_in f1 i input clock. when the input is sdtv the input clock will be 27, 36, 54 or 72mhz. when the input format is hdtv, the input clock will be 74.25 or 74.25/1.001mhz. memclk_in h1 i input clock for sdram operation to support hd modes, 90mhz input (supplied by an off-chip crystal oscillator). xvoclk_in j1 i input clock. this input may be used instead of the internal clock doubler for vclk_in to supply the internal voclk. sd only applications may use voclk to supply s1_clk and s2_clk rather than memclk_in. xvoclk_sl h4 i control signal input. when high, selects external voclk source; when low, selects the internal vclk_in clock doubler for generation of the internal voclk signal (required only for sd only applications where voclk is used to supply s1_clk and s2_clk). y_in[9:0] b1,c1,c2,c3,d1,d2, d3,e1,e2,e3 i 8/10-bit input data bus for separate luminance or multiplexed luminance and colour difference video data. when supplying 8-bit data to the gf9331, y_in[1:0] will be set low and the 8-bit data supplied to y_in[9:2]. c_in[9:0] j3,j4,k1,k2,k3,k4,l4, l3,l2,l1 i 8/10-bit input data bus for colour difference video data. when supplying 8- bit data to the gf9331, c_in[1:0] will be set low and the 8-bit data supplied to c_in[9:2]. f_in n2 i video timing control. f_in identifies the odd and even fields in the incoming video signal. f_in will be low in field 1 and high in field 2. v_in n3 i video timing control. v_in represents the vertical blanking signal associated with the incoming video signal. v_in is high during the vertical blanking interval and low during active video. h_in n4 i video timing control. h_in represents the horizontal blanking signal associated with the incoming video signal. h_in is high during horizontal blanking and low during active video. fvh_en n1 i control signal input. when high, the f_in, v_in, and h_in input pins will be used for video data signaling. when low, embedded trs ? s will be detected for video data signaling. vm_mode m2 i control signal input. when high, the vertical motion detection is enabled. ed_mode m1 i control signal input. when high, the edge direction detection is enabled. std[4:0] g2,g3,g4,h2,h3 i video format definition. defines the video standard when operating without the host interface. see table 1. mode f3 i operation mode selection. when high, the gf9331 motion co-processing is enabled. when low, the gf9331 motion co-processing is bypassed. see section 7.0 host_en e4 i host interface enable. when set high, the gf9330 is then configured through the host interface. when set low, the gf9330 is manually configured via input pins. ser_md g1 i host interface mode selection. enables serial mode operation when high. enables parallel mode operation when low. cs p2 i functions as an active low chip select input for host interface parallel mode operation. functions as a serial clock input for host interface serial mode operation. dat_io[7:0] r4,r3,r2,r1,t4,t3, t2,t1 i/o host interface bi-directional data bus for parallel mode. in serial mode, dat_io[7] serves as the serial data output pin and dat_io[0] serves as the serial data input pin.
gennum corporation 18303 - 0 4 gf9331 gennum proprietary and confidential r_w p3 i host interface read/write control for parallel mode. a read cycle is defined when high, a write cycle is defined when low. a_d p1 i host interface address/data control for parallel mode. the data bus contains an address when high, a data word when low. in serial mode, this pin serves as the chip select (active low). y_out[9:0] a20,b20,c20,c19,d20, d19,d18,e20,e19,e18 o output data bus for separate luminance or multiplexed luminance and colour difference video data. c_out[9:0] h20,j20,j19,j18,k20,k 19,k18,l18,l19,l20 o output data bus for colour difference video data. fil_sel[3:0] m19,m20,n19,n20 o filter selection control bus output to the gf9330. the fil_sel[3:0] bus is used to switch the gf9330 ? s internal directional filters on a pixel by pixel basis. h_out p20 o output control signal. h_out is a horizontal blanking output. f_out t20 o output control signal. f_out is an odd/even field indicator. v_out r20 o output control signal. v_out is a vertical blanking output. s1_clk y10 o sdram bank 1 clock. s1_cs y5 o active low sdram chip select for field buffer 1. s1_ras w4 o active low sdram row address strobe for field buffer 1. s1_cas w5 o active low sdram column address strobe for field buffer 1. s1_we y4 o active low sdram write enable for field buffer 1. s1_addr[13:0] y6,w6,v6,y7,w7,v7, y8,w8,v8,y9,w9,v9, w10,v10 o sdram address for field buffer 1. s1_dat[15:0] v11,w11,y11,v12,w12, y12,v13,w13,y13,v14, w14,y14,v15,w15, y15,y16 i/o sdram data for field buffer 1. s2_clk a9 o sdram bank 2 clock. s2_cs a14 o active low sdram chip select for field buffer 2. s2_ras b15 o active low sdram row address strobe for field buffer 2. s2_cas b14 o active low sdram column address strobe for field buffer 2. s2_we a15 o active low sdram write enable for field buffer 2. s2_addr[13:0] a13,b13,c13,a12,b12, c12,a11,b11,c11,c10, b10,a10,c9,b9 o sdram address for field buffer 2. s2_dat[15:0] c8,b8,a8,c7,b7,a7, c6,b6,a6,c5,b5,a5, b4,a4,b3,a3 i/o sdram data for field buffer 2. tdi u3 i jtag data input. tms u2 i jtag mode select. pin descriptions pin descriptions pin descriptions pin descriptions (continued) (continued) (continued) (continued) symbol pin grid type description
gennum corporation 18303 - 0 5 gf9331 gennum proprietary and confidential tclk u1 i jtag test clock. tdo w1 o jtag data output. vdd_clkd f5 na 2.5 v supply for the internal clock doubler. vss_clkd g5 na ground connection for the internal clock doubler. vdd_io e7,e10,e15,f7,f15,j5, j16,m16,n5,r7,r15,t7, t10,t15 na 3.3 v supply. vdd_int e6,e12,f6,f16,g6,g16, l5,p16,r6,r16,t6,t12 na 2.5 v supply. gnd / tgnd e5,e9,e11,e14,e16, f14,g15,h5,h6, h16,j9,j10,j11,j12,k5, k9,k10,k11,k12,k16, l9,l10,l11,l12,l16, m5,m9,m10,m11,m12, n16,p5,p6,p15,t5,t9, t11,t14,t16,u4,u18, u19,u20,v1,v2 na device ground / thermal ground (electrically equivalent). nc a2,a16,a17,a18,a19, b2,b16,b17,b18,b19, c4,c14,c15,c16,c17, c18,d4,d5,d6,d7,d8, d9,d10,d11,d12,d13, d14,d15,d16,d17,e8, e13,e17,f2,f4,f17, f18,f19,f20,g17,g18, g19,g20,h17,h18, h19,j2,j17,k17,l17, m3,m4,m17,m18,n17, n18,p4,p17,p18,p19, r5,r17,r18,r19,t8, t13,t17,t18,t19,u5, u6,u7,u8,u9,u10,u11, u12,u13,u14,u15,u16, u16,u17,v3,v4,v5,v16, v17,v18,v19,v20,w2, w3,w16,w17,w18, w19,w20,y1,y2,y3, y17,y18,y19,y20 na no connection. pin descriptions pin descriptions pin descriptions pin descriptions (continued) (continued) (continued) (continued) symbol pin grid type description
gennum corporation 18303 - 0 6 gf9331 gennum proprietary and confidential electrical characteristics electrical characteristics electrical characteristics electrical characteristics 5v tolerant inputs input cells used in the design are able to withstand a 5 v cmos input signal without degrading performance or long- term reliability. the gf9331 supports ttl compatible inputs as well as 3/5v cmos inputs. esd tolerance gf9331 has 2 kv esd protection. esd testing is done in accordance with gennum ? s standard esd testing procedure. 3.3v supply for device i/0 and 2.5v for core logic t he gf9331 operates from a single +3.3v supply for device i/o. the gf9331 operates off a single +2.5v supply for core logic. absolute maximum ratings absolute maximum ratings absolute maximum ratings absolute maximum ratings parameter symbol value device i/o supply voltage v ddio -0.5 to tbd v device core supply voltage v ddcore -0.5 to tbd v input voltage range (any input) v in -0.5 < v in < +4.6v operating temperature range t a 0 c < t a < 70 c storage temperature range t s -40 c < t s < 125 c lead temperature (soldering 10 seconds) 260 c dc electrical characteristics dc electrical characteristics dc electrical characteristics dc electrical characteristics v ddio = 3.0 to 3.6v, v ddcore = 2.25 to 2.75v, t a = 0 c to 70 c, unless otherwise shown parameter conditions symbol min typ max units notes device i/o supply voltage v ddio +3.0 +3.3 +3.6 v 1 device core supply voltage v ddcore +2.25 +2.5 +2.75 v 1 device i/o supply current v ddio =3.6v ddio tbd ma 1 device core supply current v ddcore =2.75v ddcore tbd ma 1 input leakage current in =0v or i in =v dd leak 10 ? 1 input logic low voltage v il -- -- 0.8 v 1 input logic high voltage v ih 2.1 -- -- v 1 output logic low voltage ol = 4ma v ol -- 0.2 0.4 v 1 output logic high voltage oh = -4ma v oh 2.7 -- -- v 1 notes: 1. production, test and qa are performed at room tempature.
gennum corporation 18303 - 0 7 gf9331 gennum proprietary and confidential ac electrical characteristics - video interfaces ac electrical characteristics - video interfaces ac electrical characteristics - video interfaces ac electrical characteristics - video interfaces the video interface signals include vclk, y_in, c_in, fil_sel[3:0], f_in, v_in, h_in, fvh_en, ff_en, y_out, c_out, h_out, f_ou t and v_out. v ddio = 3.0 to 3.6v, v ddcore = 2.25 to 2.75v, t a = 0 c to 70 c, unless otherwise shown parameter conditions symbol min typ max units notes clock input frequency f hsci -- 74.25 83 mhz 1, 2 input data setup time t su 2.5 -- -- ns 1, 3 input data hold time t ih 1.5 -- -- ns 1, 3 input clock duty cycle 40 -- 60 % 1 output data delay time v ddio =3.6v, c l =15pf load t od -- -- 10.0 ns 1 output data hold time v ddio =3.6v, c l =15pf load t oh 2.0 -- -- ns 1 output enable time v ddio =3.6v, c l =15pf load t oen -- -- 10 ns 1 output disable time v ddio =3.6v, c l =15pf load t odis -- -- 10 ns 1 output data rise/fall time v ddio =3.6v, c l =15pf load t odrf -- -- 2.0 ns 1, 4 notes: 1. based on simulation results, verified during device characterization process. 2. also supports 74.25/1.001mhz. 3. 50% levels. 4. 20% to 80% levels.
gennum corporation 18303 - 0 8 gf9331 gennum proprietary and confidential ac electrical characteristics - sdram interfaces ac electrical characteristics - sdram interfaces ac electrical characteristics - sdram interfaces ac electrical characteristics - sdram interfaces the sdram 1 interface signals include s1_clk, s1_cs , s1_ras , s1_cas , s1_we , s1_addr[13:0] and s1_dat[15:0]. the sdram 2 interface signals include s2_clk, s2_cs , s2_ras, s2_cas , s2_we , s2_addr[13:0] and s2_dat[15:0]. v ddio = 3.0 to 3.6v, v ddcore = 2.25 to 2.75v, t a = 0 c to 70 c, unless otherwise shown parameter conditions symbol min typ max units notes clock input frequency f hsci_sd -- 85 90 mhz 1 input data setup time t su_sd 2.0 -- -- ns 1, 2 input data hold time t ih_sd 2.5 -- -- ns 1, 2 input clock duty cycle 40 -- 60 % 1 output data delay time v ddio =3.6v, c l =15pf load t od_sd -- -- 9.1 ns 1 output data hold time v ddio =3.6v, c l =15pf load t oh_sd 2.0 -- -- ns 1 output enable time v ddio =3.6v, c l =15pf load t oen_sd -- -- 20 ns 1, 4 output disable time v ddio =3.6v, c l =15pf load t odis_sd -- -- 20 ns 1, 4 output data rise/fall time v ddio =3.6v, c l =15pf load t odrf_sd -- -- 2.0 ns 1, 3 notes: 1. based on simulation results, verified during device characterization process. 2. 50% levels. 3. 20% to 80% levels. 4. two clock cycles allocated for data bus turnaround. ac electrical characteristics - host interface ac electrical characteristics - host interface ac electrical characteristics - host interface ac electrical characteristics - host interface the host interface signals include host_en, ser_md, cs , dat_io[7:0], r_w and a_d. v ddio = 3.0 to 3.6v, v ddcore = 2.25 to 2.75v, t a = 0 c to 70 c, unless otherwise shown parameter conditions symbol min typ max units notes clock input frequency f hsci_hi -- -- 20 mhz 1 input data setup time t su_hi 5----ns 1, 2 input data hold time t ih_hi 1.5 -- -- ns 1, 2 input clock duty cycle 40 -- 60 % 1 output data delay time v ddio =3.6v, c l =15pf load t od_hi -- -- 10.0 ns 1 output data hold time v ddio =3.6v, c l =15pf load t oh_hi 2.0 -- -- ns 1 output enable time v ddio =3.6v, c l =15pf load t oen_hi -- -- 15 ns 1 output disable time v ddio =3.6v, c l =15pf load t odis_hi -- -- 15 ns 1 output data rise/fall time v ddio =3.6v, c l =15pf load t odrf_hi -- -- 2.0 ns 1, 3 notes: 1. based on simulation results, verified during device characterization process. 2. 50% levels. 3. 20% to 80% levels.
gennum corporation 18303 - 0 9 gf9331 gennum proprietary and confidential detailed device description detailed device description detailed device description detailed device description 1. input data formats the gf9331 supports multiple input data formats with multiplexed or separate y/c channels. data is supplied to the gf9331 through the y_in[9:0] and the c_in[9:0] busses. table 1 outlines the data formats that the gf9331 supports according to the setting of std[4:0] pins or host interface bits, std[4:0]. table 1: encoding of stnd[4:0] for selecting input data format std std[4:0] description 0 00000 525i (30/1.001) component smpte 125m. . . . multiplexed y cb cr data applied to y_in. c_in should be set low. note: input clock is 27mhz. 1 00001 reserved. 2 00010 525i (30/1.001) component 16x9 smpte 267m. multiplexed y cb cr data applied to y_in. c_in should be set low. note: input clock is 36mhz. 3 00011 reserved 4 00100 625i (25hz) component ebu tech. 3267e. .. . multiplexed y cb cr data applied to y_in. c_in should be set low. note: input clock is 27mhz. 5 00101 reserved 6 00110 625i (25hz) component 16x9 itu-r bt.601-5 part b. multiplexed y cb cr data applied to y_in. c_in should be set low. note: input clock is 36mhz. 7 00111 reserved 8 01000 525p (60/1.001hz) smpte 293m. y cb cr data stream applied to y_in. c_in should be set low. timing information is extracted from embedded trs sequences. note: input clock is 54mhz. 9 01001 reserved 10 01010 reserved 11 01011 reserved 12 01100 625p (50hz) itu-r bt.1358. y cb cr data stream applied to y_in. c_in should be set low. timing information is extracted from embedded trs sequences. note: input clock is 54mhz. 13 01101 625p (50hz) 16 x 9 with 18mhz sampling. y cb cr data stream applied to y_in. c_in should be set low. timing information is extracted from embedded trs sequences. note: input clock is 72mhz. 14 01110 generic sd input data format with 4:1:1 sampling. y cb cr data is applied to both y_in and c_in. the externally supplied f, v and h signals are used to synchronize the input data stream. note: input clock is 27mhz. 15 01111 generic sd input data format with 4:2:2 sampling and single multiplexed y cb cr input format. y cb cr data applied to y_in. c_in should be set low. the externally supplied f, v and h signals are used to synchronize the input data stream. note: input clock is 27 or 36mhz. 16 10000 720p (60 & 60/1.001hz) smpte 296m january 1999 draft (system #1 and #2). y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz or 74.25/1.001mhz. 17 10001 720p (30 & 30/1.001hz) smpte 296m january 1999 draft (system #4 and #5). .. . y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz or 74.25/1.001mhz. 18 10010 1080p (30 & 30/1.001hz) smpte 274m (system #7 and #8). y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz or 74.25/1.001mhz. 19 10011 720p (50hz) smpte 296m january 1999 draft (system #3). y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz. 20 10100 1080p (25hz) smpte 274m (system #9). y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz.
gennum corporation 18303 - 0 10 gf9331 gennum proprietary and confidential 2. input synchronization the gf9331 obtains relevant timing information from either embedded trs information or externally supplied h_in, v_in, and f_in signals. when the fvh_en pin or the fvh_en bit within the host interface are high, the gf9331 relies on the externally supplied h_in , v_in and f_in signals for timing information. when both the fvh_en pin and the fvh_en bit are low, the gf9331 extracts the embedded trs timing information from the video data stream and ignores any timing information present of the f_in , v_in and h_in pins. 2.1 support for both 8-bit and 10-bit input data the gf9331 supports 8-bit and 10-bit input data. when operating with 8-bit input data, the two lsbs of the gf9331 ? s 10-bit input bus should be set low and the input data applied to the 8 msbs of the input bus. 2.2 generic input format signaling t he gf9331 supports generic input data formats with either 4:1:1 or 4:2:2 sampling structures that require up to 2046 active samples per line and have maximum total line width of 4096 (active + blanking) samples. in addition, there is a limit of 2048 lines per interlaced frame. the following host interface parameters are programmable to describe the generic input data format relative to the f_in , v_in and h_in signals. 2.2.1 h_blank_size this parameter defines the number of samples that comprise the horizontal blanking region. this parameter has a maximum value of 4095 and is to be less than the total line width (active + blanking) sample size. twelve bits within the host interface are dedicated to this parameter. the gf9331 stores and processes active video samples only (i.e. h_in =0). 2.2.2 v_blank_size_odd this parameter defines the number of lines that comprise the vertical blanking interval that follows the odd field. this parameter has a maximum value of 255. eight bits within the host interface are dedicated to this parameter. the gf9331 stores and processes active video samples only (i.e. v_in =0) 21 10101 720p (25hz) smpte 296m january 1999 draft (system #6). y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz. 22 10110 1080p (24 & 24/1.001hz) smpte 274m (system # 10 and #11). y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz or 74.25/1.001mhz. 23 10111 720p (24 & 24/1.001hz) smpte 296m january 1999 draft (system #7 and #8). .. . y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz or 74.25/1.001mhz. 24 11000 1080i (30 & 30/1.001hz) smpte 274m (system #4 and #5). y data applied to y_in. cb/cr data applied to c_in. note: input clock is 74.25 mhz or 74.25/1.001mhz. 25 11001 1080p (30 & 30/1.001hz in segmented frame format) smpte draft rp may 99 (system #12 and #13). y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz or 74.25/1.001mhz. 26 11010 1080i (25hz) smpte 274 (system # 6). y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz. 27 11011 1080p (25hz in segmented frame format) smpte draft rp may 99 (system #14). y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz. 28 11100 1080i (25hz) smpte 295m (system #2). y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz. 29 11101 1080p ( 24 & 24/1.001hz in segmented frame format) draft rp may 99 (system #15 & #16). .. . y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz or 74.25/1.001mhz. 30 11110 1035i (30hz) smpte 260m. y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz. 31 11111 generic hd input data format with 4:2:2 sampling and a separate y/c format. y data applied to y_in. cb cr data applied to c_in. the externally supplied f_in, v_in and h_in signals are used to synchronize the input data stream. note: input clock is 74.25mhz or 74.25/1.001mhz. table 1: encoding of stnd[4:0] for selecting input data format std std[4:0] description
gennum corporation 18303 - 0 11 gf9331 gennum proprietary and confidential 2.2.3 v_blank_size_even this parameter defines the number of lines that comprise the vertical blanking interval that follows the even field. this parameter has a maximum value of 255. eight bits within the host interface are dedicated to this parameter. the gf9331 stores and processes active video samples only (i.e. v_in =0). see figure 2. 2.2.4 v_offset_odd this parameter defines the number of lines from the v_in pin eav transition to the end of the odd active video field region. this parameter has a maximum value of 255. eight bits within the host interface are dedicated to this parameter. this parameter has been added to accommodate all video decoders which output non- standard timing for the v _in signal. see figure 2. 2.2.8 h_polarity this parameter defines the polarity of the h_in pin. with h_polarity set low, a high-to-low transition on the h_in pin indicates the end of active video. with h_polarity set high, a low-to-high transition on the h _in pin indicates the end of active video. one bit within the host interface is dedicated to this parameter. 2.2.9 f_polarity this parameter defines the polarity of the f _in pin. refer to table 2 for f_polarity encoding. one bit within the host interface is dedicated to this parameter. fig. 2. v_offset definition 2.2.5 v_offset_even this parameter defines the number of lines from the v _in pin eav transition to the end of the even active video field region. this parameter has a maximum value of 255. eight bits within the host interface are dedicated to this parameter. this parameter has been added to accommodate all video decoders which output non- standard timing for the v _in signal. 2.2.6 f_offset_odd this parameter defines the number of lines from the f_in pin eav transition to the desired position within the vertical blanking interval following the odd field. this parameter has a maximum value of 255. eight bits within the host interface are dedicated to this parameter. this parameter has been added to accommodate all video decoders which output non-standard timing for the f_in signal. 2.2.7 f_offset_even this parameter defines the number of lines from the f_in pin eav transition to the desired position within the vertical blanking interval following the even field. this parameter has a maximum value of 255. eight bits within the host interface are dedicated to this parameter. this parameter has been added to accommodate all video decoders which output non-standard timing for the f_in signal. 2.2.10 v_polarity this parameter defines the polarity of the v _in pin. with v_polarity set low, a high-to-low transition on the v _in pin indicates the end of active video. with v_polarity set high, a low-to-high transition on the v _in pin indicates the end of active video. one bit within the host interface is dedicated to this parameter h vertical blanking region v v_offset_odd/even last active line table 2: f_polarity table 2: f_polarity table 2: f_polarity table 2: f_polarity f_polarity f_in pin f_in pin function 0 0 even field 0 1 odd field 1 0 odd field 1 1 even field
gennum corporation 18303 - 0 12 gf9331 gennum proprietary and confidential 3. seamless interface to the gf9330 high performance de-interlacer for directional filter control the gf9330 can operate as a stand-alone de-interlacer or can operate in conjunction with the gf9331 motion co- processor. the gf9331 contains adaptive edge detectors that cover nine different directions and a vertical motion detector. edge sensitive control signals are fed directly to the gf9330. these control signals adaptively switch the gf9330 ? s internal de-interlacing filters on a pixel by pixel basis. these control signals are fed to the gf9330 by the gf9331 over the fil_sel[3:0] control bus. note: when using the gf9331, the y_in[9:0] of the gf9330 must be connect to the y_out[9:0] of the gf9331 and the c_in[9:0] of the gf9330 must be connected to the c_out[9:0] of the gf9331. the fil_sel[3:0] output of the gf9331 must be connected to the fil_sel[3:0] input of the gf9330. refer to figure 3 for a pictorial description of connections between the gf9330 and the gf9331. fig. 3 using the gf9331 with the gf9330 for motion adaptive de-interalcing 4. seamless interface to external sdrams the gf9331 requires two independent external field buffers, each implemented with a 1 meg (min) x 16-bit sdram configuration. this configuration supports all operational modes. the following external sdram devices are supported for the external field buffer function. nec: upd4516161ag5, upd4564163g5, upd45128163g5 micron: mt48lc4m16a2, mt48lc8m16a2 samsung: k4s161622c, k4s641632c, k4s281632b 5. host interface the gf9331 provides both a serial and a parallel host interface control ports for the configuration of internal parameters. the gf9331 is also able to operate in stand- alone mode, with no host interface control. in stand-alone mode, the video standard std[4:0] and mode of operation mode must be set using dedicated pins on the device. both the serial and parallel interfaces share common pins as described in table 4. c2_out[11:0] gf9331 c_out[9:0] y_out[9:0] gf9330 y_in[9:0] c_in[9:0] c1_out[11:0] y1_out[11:0] y2_out[11:0] fil_sel[3:0] fil_sel[3:0] y_in[9:0] c_in[9:0] table 4: host interface common pins gf9331 pin name parallel mode serial mode cs chip select sclk - serial clock dat_io0 data/address (bit 0) sdi - serial data in dat_io1 data/address (bit 1) (not used) dat_io2 data/address (bit 2) (not used) dat_io3 data/address (bit 3) (not used) dat_io4 data/address (bit 4) (not used) dat_io5 data/address (bit 5) (not used) dat_io6 data/address (bit 6) (not used) dat_io7 data/address (bit 7) sdo - serial data out a_d address/data select scs - serial chip select r_w read/write select (not used) host_en host interface enable host interface enable ser_md low = parallel mode enable high = serial mode enable
gennum corporation 18303 - 0 13 gf9331 gennum proprietary and confidential 5.1 host interface serial mode the gennum serial peripheral interface (gspi) is a 4 wire interface comprised of serial data in (sdi), serial data out (sdo), an active low serial chip select (scs ), and a clock (sclk). the interface operates in a master/slave configuration, where the master provides the sclk, sdi, and scs signals to the slave or slaves. the master uc_sdo drives the slave(s) sdi input the sdo pin is a tristate output to allow multiple devices to drive the master uc_sdi. serial mode operation supports both a continuous clock and a burst clock configuration. the interface is illustrated in figure 4. 5.1.1 serial command word description the command word consists of a 16-bit word transmitted msb first and contains a read/write bit, an auto-update control bit, nine reserved bits and a 5-bit address as shown in figure 5. fig. 4 host interface serial mode fig. 5 serial command word bit representation the r/w bit indicates a read command if r/w = high, and a write command when r/w = low. the auto-update feature will be executed when the auto- update control bit is set (used during write operations only). all configuration registers will be set to their appropriate settings corresponding on the previously stored video standard and operational mode. this simplifies configuration while allowing customization of many features and format parameters. the 5-bit address is used to identify all configuration registers within the gf9331. 5.1.2 serial data word description the serial data word consists of a 16-bit word as shown in figure 6. serial data is transmitted or received msb first. fig. 6 serial data word bit representation both command and data words are clocked into the gf9331 on the rising edge of the serial clock (sclk) which may operate in either a continuous or burst fashion. the first bit (msb) of the serial output (sdo) is available following the last falling sclk edge of the "read" command word. the remaining bits are clocked out on the negative edges of sclk. uc_scs uc_sclk uc_sdo uc_sdi master (uc) scs (a_d) sclk (cs) sdi (dat_io_0) sdo (dat_io_7) slave (gf9331) r/w au rsv rsv a0 a1 a2 a3 a4 rsv rsv rsv rsv rsv rsv rsv msb lsb d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 lsb msb
gennum corporation 18303 - 0 14 gf9331 gennum proprietary and confidential 5.1.3 serial write operation all write cycles consist of a command word followed by a data word, both transmitted to the gf9331 via sdi. the first 16-bit word transmitted following a high-to-low transition of scs is a command word. several write cycles may be performed while scs is low. see figure 7. fig. 7 write cycle 5.1.4 serial read operation all read cycles consist of a command word transmitted to the gf9331 via sdi followed by a data word transmitted from the gf9331 via sdo. the first 16-bit word transmitted following a high-to-low transition of scs is a command word. several read cycles may be performed while scs is low. see figure 8. fig. 8 read cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 sclk scs r/w 0 au r a0 a1 a2 a3 a4 r r r r r rrr sdi 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d15 d14 d13 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d12 d11 d10 sdo tsu_hi tih_hi tsu_hi 01234567891011121314 15 sclk scs r/w 1 au 0 r a0 a1 a2 a3 a4 r r r r r rrr sdi 01234567891011121314 15 sdo d15 d14 d13 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d12 d11 d10 tod_hi todis_hi toen_hi
gennum corporation 18303 - 0 15 gf9331 gennum proprietary and confidential 5.2 host interface parallel mode the gennum parallel peripheral interface (gppi) consists of an 8-bit multiplexed address/data bus (data_io[7:0]), a chip select pin (cs ), a read/write pin (r_w), and an address/data pin (a_d) as shown in figure 9. fig. 9 host interface parallel mode data is strobed in/out of the parallel interface on the falling edge of cs . the gf9331 drives the data_io[7:0] bus when the r_w pin is high and the cs pin is low, otherwise this port is in a high impedance state. a write cycle to the parallel interface is shown below. first an 8-bit address word is provided to the data_io port by asserting the r_w pin to low and a_d pin to high. the msb of the address word contains an auto-update flag, which allows automatic configuration of predefined registers (used during write operations only). the 5 lsb's of the address word contain the address location for the read or write operation. the remaining address word bits dat_io[6:5] are reserved. the address word is registered on the falling edge of cs . following this, the a_d pin is driven low and two data words are sent upper byte (ub) word first and are each clocked in on the falling edge of cs . two 8-bit data words must follow each address word to occupy each 16-bit parameter which are defined in table 5. a read cycle begins with an address write by asserting the r_w pin low and a_d high. the address is clocked on the falling edge of cs. following the address, the r_w pin must be driven high and a_d driven low to allow the upper byte of data to be clocked out on the first falling edge of cs followed by the lower byte on the second negative edge of cs . see figure 10 fig. 10 write cycle to the parallel interface a_d cs addr/data (dat_io[7:0]) r_w slave (gf9331) uc_a/d uc_cs uc_addr/data uc_r/w master (uc) address (ub) data_in (lb) data_in address (ub) data_out (lb) data_out dat_io(7..0) r_w a_d cs tsu_hi tih_hi toen_hi todis_hi
gennum corporation 18303 - 0 16 gf9331 gennum proprietary and confidential table 5: host interface register allocation hex bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address 31 1f cmd_reset start_operation address 30 1e clk_x1_sel ext_memclk_sel address 29 1d address 28 1c address 27 1b address 26 1a address 25 19 address 24 18 address 23 17 address 22 16 field2_has_top_line address 21 15 progressive_input format_sd address 20 14 address 19 13 address 18 12 address 17 11 address 16 10 address 15 f address 14 e address 13 d address 12 c address 11 b address 10 a address 9 9 address 8 8 address 7 7 address 6 6 address 5 5 address 4 4 address 3 3 address 2 2 address 1 1 h_polarity v_polarity f_polarity fvh_en_bit cc_blank_en edge_ctl vm_ctl address 0 0 mode id_mode(1:0) no_line_delays ( 9:0 ) h_blank_size ( 11:0 ) v_offset_odd(7:0) v_offeset_even(7:0) cc_blank_start_line(7:0) active_pixel_line ( 10:0 ) cc_blank_end_line(7:0) std(4:0) v_blank_size_odd(7:0) v_blank_size_even ( 7:0 ) f_offset_odd(7:0) f_offeset_even(7:0) even_lines_per_frame[1:0]
gennum corporation 18303 - 0 17 gf9331 gennum proprietary and confidential 5.3 control register definition the host interface internal registers are divided into two classes: user configurable (uc) and auto-configurable (ac). address locations 0 through 6 contain parameters which may be configured by the user. locations 7 through 31 are automatically configured based on the std[4:0] and mode registers, but can be user configured if desired. std[4:0] std[4:0] std[4:0] std[4:0] address [0][4:0], uc, default value = 00000, defines the video standard as described in section 1.0. mode mode mode mode address [0][5], uc, default value = 0, enables (mode=1) or bypasses (mode=0) the gf9331 processing. vm_ctl vm_ctl vm_ctl vm_ctl - address[1][0], uc, default value = 0, enables (vm_ctl=1) or bypasses (vm_ctl=0) vertical motion detection of the video input stream. edge_ctl edge_ctl edge_ctl edge_ctl address[1][1], uc, default value = 0, enables (edge_ctl=1) or bypasses (edge_ctl=0) edge detection of the video input stream. cc_blank_en cc_blank_en cc_blank_en cc_blank_en - address[1][6], uc, default value = 0, enables (cc_blank_en=1) or bypasses (cc_blank_en=0) blanking in the close captioned video region. fvh_en_bit fvh_en_bit fvh_en_bit fvh_en_bit address[1][12], uc, default value = 0, enables the gf9331 to use external f_in, v_in, h_in controls (fvh_en=1) in place of embedded trs (fvh_en=0). f_polarity f_polarity f_polarity f_polarity address[1][13], uc, default value = 1, defines the polarity of the f_in pin. when set to '1', f_in follows normal convention where f_in is '0' for field 1(odd) and '1' for field 2 (even). v_polarity v_polarity v_polarity v_polarity address[1][14], uc, default value = 1, defines the polarity of the v_in pin. when set to '1', v_in follows normal convention where v_in is high in the vertical blanking region. h_polarity h_polarity h_polarity h_polarity address[1][15], uc, default value = 1, defines the polarity of the h_in pin. when set to '1', h_in follows normal convention where h_in is high in the horizontal blanking region. f_offset_even[7:0] f_offset_even[7:0] f_offset_even[7:0] f_offset_even[7:0] address[2][7:0], uc, default value = 00000000, defines the number of lines from the f_in pin eav transition to the desired position within the vertical blanking interval following the even field. this parameter has a maximum value of 255. f_offset_odd[7:0] f_offset_odd[7:0] f_offset_odd[7:0] f_offset_odd[7:0] address[2][15:8], uc, default value = 00000000, defines the number of lines from the f _in pin eav transition to the desired position within the vertical blanking interval following the odd field. this parameter has a maximum value of 255. v_offset_even[7:0] v_offset_even[7:0] v_offset_even[7:0] v_offset_even[7:0] address[3][7:0], uc, default value = 00000000, defines the number of lines from the v _in pin eav transition to the end of the even active video field region. this parameter has a maximum value of 255. v_offset_odd[7:0] v_offset_odd[7:0] v_offset_odd[7:0] v_offset_odd[7:0] address[3][15:8], uc, default value = 00000000, defines the number of lines from the v _in pin eav transition to the end of the odd active video field region. this parameter has a maximum value of 255. cc_blank_end_line[7:0] cc_blank_end_line[7:0] cc_blank_end_line[7:0] cc_blank_end_line[7:0] address[6][7:0], uc, default value = 00000000, defines the last line number at which to end closed captioned blanking. for this parameter, line 0 is defined as the first active line of the field/frame. cc_blank_start_line[7:0] cc_blank_start_line[7:0] cc_blank_start_line[7:0] cc_blank_start_line[7:0] a ddress[6][15:8], uc, default vaue = 00000000, defines the first line number at which to start closed captioned blanking. for this parameter, line 0 is defined as the first active line of the field/frame. v_blank_size_even[7:0] v_blank_size_even[7:0] v_blank_size_even[7:0] v_blank_size_even[7:0] address[19][7:0], ac, default value = auto, defines the number of lines that comprise the vertical blanking interval that follows the even input field. this parameter has a maximum value of 255. v_blank_size_odd[7:0] v_blank_size_odd[7:0] v_blank_size_odd[7:0] v_blank_size_odd[7:0] address[19][15:8], ac, default value = auto, defines the number of lines that comprise the vertical blanking interval that follows the odd input field. this parameter has a maximum value of 255. active_pixel_line[10:0] active_pixel_line[10:0] active_pixel_line[10:0] active_pixel_line[10:0] address[21][10:0], ac, default value = auto, defines the number of active pixels per video input line (2046 maximum). format_sd format_sd format_sd format_sd address[21][12], ac, default value = auto, used to configure the gf9331 sdram controller into 8-bit mode for sd video formats. this bit is auto-configured based on standard and mode selection. progressive_input progressive_input progressive_input progressive_input address[21][13], ac, default value = auto, configures the gf9331 to accept a progressive video format. this bit is auto-configured based on standard and mode selection. id_mode[1:0] id_mode[1:0] id_mode[1:0] id_mode[1:0] address[21][15:14], uc, default value = auto, defines the type of video sequence for input video de- multiplexing. when set to "00" the input represents a 4:2:2 sequence, "01" represents a 4:1:1 sequence, and "10" represents an hd format. this word can be auto- configured based on video standard and mode. h_blank_size[11:0] h_blank_size[11:0] h_blank_size[11:0] h_blank_size[11:0] address[22][11:0], ac, default value = auto, defines the number of horizontal blanked input words per line which corresponds to 2 times the number of blanking pixels per line for 4:2:2 sd modes and is equal to the number of pixels per line for hd formats (maximum 4095). this value can be auto-configured. field2_has_top_line field2_has_top_line field2_has_top_line field2_has_top_line address[22][13], ac, default value = auto, set high when field 2, line one is the first line in the video frame (smpte 260m).
gennum corporation 18303 - 0 18 gf9331 gennum proprietary and confidential even_lines_per_frame[1:0] even_lines_per_frame[1:0] even_lines_per_frame[1:0] even_lines_per_frame[1:0] address [22][15:14], ac, default value = auto, set to 11 for video standards that have an even number of lines per frame such as smpte 295m, otherwise set to 00. no_line_delays[9:0] no_line_delays[9:0] no_line_delays[9:0] no_line_delays[9:0] address[23][9:0], ac, default value = auto, defines the number of line delays to implement within the external field delay. this value is auto- configured based on standard and mode. the calculation is: no_line_delays = (total number of lines per frame -3) / 2. ext_memclk_sel ext_memclk_sel ext_memclk_sel ext_memclk_sel address[30][0], ac, default value = auto, controls the selection of the sdram clock source. for vclk_in frequencies less than 36mhz, the internal clock doubler can be used. in all other modes an external source is required (memclk_in). clk_x1_sel clk_x1_sel clk_x1_sel clk_x1_sel address[30][2], ac, default value = auto , this parameter is normally set for all hd modes and is '0' for all other cases. cmd_reset cmd_reset cmd_reset cmd_reset address[31][15], uc, default value = 0, this parameter forces the gf9331 to enter a reset state. the reset remains in effect until this parameter is cleared with a subsequent command. s s s s tart_operation tart_operation tart_operation tart_operation address[31][0], uc, default value = 0, if using external f_in, v_in and h_in signals, this parameter must be set following the completion of programming the f_in, v_in and h_in offsets. 6. reset pin this resets all internal state machines and configuration registers to their default power-up states. reset is active low. 7. modes of operation the device supports enabled and disabled modes of operation. the basic operating mode for the gf9331 is selected using the mode control bit or the mode register within the host interface. see table 6. 7.1 motion processing mode (mode=1) when set to operate as a motion co-processor the gf9331 per- forms vertical motion detection, edge direction determination and provides control of the gf9330 filters through the fil_sel[3:0] bus on a pixel by pixel basis. 7.2 disabled mode (mode=0) the gf9331 may also be set to disabled mode of operation. in the disabled mode, no motion co-processing operations are performed and the fil_sel[3:0} output bus is set to ? 0000 ? . in this mode, the input video is still routed to the y_out and c_out pins of the gf9330 (note: only the active portion of the input video signal is passed through the device to the gf9330, all other data will be lost from the input data stream). see table 6. table 6: modes of operation mode description 0 bypass mode 1 motion processing of input video signal
gennum corporation 18303 - 0 19 gf9331 gennum proprietary and confidential 8. processing of input formats the gf9331 provides motion processing for the formats identified in table 7. table 7: processing of input formats std[4:0] input format motion processing mode disabled mode 00000 525i (30/1.001) smpte 125m supported supported 00001 reserved na na 00010 525i (30/1.001) smpte 267m - 16x9 supported supported 00011 reserved na na 00100 625i (25) ebu tech 3267 supported supported 00101 reserved na na 00110 625i (25) 16 x9 itu-r bt.601 part b supported supported 00111 reserved na na 01000 525p (60/1.001) smpte 293m na supported 01001 reserved na na 01010 reserved na na 01011 reserved na na 01100 625p (50) itu-r bt-1358 na supported 01101 625p (50) 16x9 na supported 01110 generic sd 4:1:1 supported supported 01111 generic sd 4:2:2 supported supported 10000 720p (60 & 60/1.001) smpte 296m jan ? 99 draft (system #1 and #2) na supported 10001 720p (30 & 30/1.001) smpte 296m jan ? 99 draft (system #4 and #5) na supported 10010 1080p (30 & 30/1.001) smpte 274m (system #7 and #8) na supported 10011 720p (50) smpte 296m jan ? 99 draft (system #3) na supported 10100 1080p (25) smpte 274m (system #9) na supported
gennum corporation 18303 - 0 20 gf9331 gennum proprietary and confidential 10101 720p (25) smpte 296m jan ? 99 draft (system #6) na supported 10110 1080p (24 & 24/1.001) smpte 274m (system #10 and #11) na supported 10111 720p (24 & 24/1.001) smpte 296m jan ? 99 draft (system #7 and #8) na supported 11000 1080i (30 & 30/1.001) smpte 274m (system #4 and #5) supported supported 11001 1080psf (30 & 30/1.001) draft rp may 99 (system #12 and #13) na supported 11010 1080i (25) smpte 274m (system #6) supported supported 11011 1080psf (25) draft rp may 99(system #14) na supported 11100 1080i (25) smpte 295m (system #2) supported supported 11101 1080psf (24 & 24/1.001) draft rp may 99 (system #15 & #16) na supported 11110 1035i (30 & 30/1.001) smpte 260m supported supported 11111 generic hd 4:2:2 supported supported table 7: processing of input formats (continued) std[4:0] input format motion processing mode disabled mode
gennum corporation 18303 - 0 21 gf9331 gennum proprietary and confidential 9. vertical motion detection the gf9331 detects objects moving in the vertical direction (e.g. edit text in film). by performing motion detection, a special vertical filter may be enabled within the gf9331 for interpolating the pixels with vertical motion, thereby greatly reducing de-interlacing artifacts. this vertical motion detection signal is provided to the gf9330 through the control bus (fil_sel[3:0]). 9.1 vertical motion feature control the gf9331 is able to operate in automatic or disabled mode for vertical motion detection of the video input stream. when set to operate in disabled mode (vm_mode=0), the internal vertic al motion detection circuitry is disabled. when set to operate in automatic mode (vm_mode=1) the gf9331 internally detects vertical motion . see table 8. 10. edge direction detection in order to reduce the artifacts caused by the de-interlacing process, interpolated pixels are calculated along different edge directions. when the gf9331 is used in conjunction with the gf9330, nine edge directions are analyzed and the appropriate filter for use within the gf9330 is selected using the control bus fil_sel[3:0]. based on several complex techniques including vertical-temporal filtering, gradient and morphological operations, the gf9331 detects edge directions so that temporal flickers are minimized. 10.1 edge direction detection feature control the gf9331 is able to operate in automatic or disabled mode for edge direction detection of the video input stream. when set to operate in disabled mode (ed_mode=0), the internal edge direction detection circuitry is disabled. when set to operate in automatic mode (ed_mode=1) the gf9331 internally detects edge directions. see table 9. 11. video output the gf9331 supports all input formats defined in section 1. routing of video data to the gf9330 is done via the y_out[9:0] and c_out[9:0] busses. note that only the active portion of the input video signal is passed through the device to the gf9330 unchanged. all other ancillary data is discarded from the input data stream. 12. processing latency for all modes of operation, the gf9331 video information processing latency is constant at 2 lines, 16 pixels. table 8: vm_mode external vm_mode pin host infterface vm_mode bit description 0 0 vertical motion detection disabled 0 1 vertical motion detection enabled 10 11 table 9: ed_mode external ed_mode pin host interface ed_mode bit description 0 0 edge direction detection disabled 0 1 edge direction detection enabled 10 11
18303 - 0 22 gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 gennum japan corporation c-101, miyamae village, 2-10-42 miyamae, suginami-ku tokyo 168-0081, japan tel. +81 (03) 3334-7700 fax. +81 (03) 3247-8839 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no responsibility for the use of any circuits described herein and makes no representations that th ey are free from patent infringement. ?copyright june 2001 gennum corporation. all rights reserved. printed in canada. gf9331 gennum proprietary and confidential package dimensions package dimensions package dimensions package dimensions 12 34 56 7 8 91011121314151617181920 y w v u t r p n m l k j h g f e d c b a 24.00 ref. 4.00, 45? (4x) 24.00 ref. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 y w v u t r p n m l k j h g f e d c b a pin #1 27.00 ?0.20 24.13 1.27 27.00 ?0.20 24.13 1.27 1.00 (3x) ref. 0.75 ?0.15 (x328) 0.60 ?0.10 2.33 ?0.13 1.17 ref. 0.56 ref. revision notes: new document document identification preliminary data sheet the product is in a preproduction phase and specifications are subject to change without notice.

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