ics727 mds 727 b 1 revision 121404 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com l ow c ost 27 mh z 3.3 v olt vcxo description the ics727 combines the functions of a vcxo (voltage controlled crystal oscillator) and pll (phase locked loop) frequency doubler onto a single chip. used in conjunction with an external pullable quartz crystal, this monolithic integrated circuit replaces more costly hybrid (canned) vcxo devices. the ics727 is designed primarily for data and clock recovery applications within end products such as set-top box receivers. the ics727 exhibits a moderate vcxo gain of 110 ppm/v typical, when used with a high quality external pullable quartz crystal. the frequency of the on-chip vcxo is adjusted by an external control voltage input into pin vin. because vin is a high impedance input, it can be driven directly from an pwm rc integrator circuit. frequency output increases with vin voltage input. the usable range of vin is 0 to 3 v. features ? ideal for set-top box applications using 13.5 mhz external pullable crystal to generate lock 27 mhz clock transport video clock ? on-chip vcxo with guaranteed pull range of 110 ppm minimum ? vcxo input tuning voltage 0 to 3.3 v ? packaged in 8-pin soic (150 mil wide) block diagram 27 mhz (2x crystal frequency) x1 x2 voltage controlled crystal oscillator pll frequency doubler vin 13.5 mhz pullable crystal
l ow c ost 27 mh z 3.3 v olt vcxo mds 727 b 2 revision 121404 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com ics727 pin assignment pin descriptions x1 vdd vin gnd gnd clk gnd x2 1 2 3 4 8 7 6 5 8-pin (150 mil) soic pin number pin name pin type pin description 1 xi input crystal connection. connect to the external pullable crystal. 2 vdd power connect to +3.3 v (0.01uf decoupling capacitor recommended). 3 vin input voltage input to vcxo. zero to 3.3 v analog input which controls the oscillation frequency of the vcxo. 4 gnd power connect to ground. 5 gnd power connect to ground. 6 clk output clock output. 7 gnd power connect to ground. 8 x2 input crystal connection. connect to the external pullable crystal.
l ow c ost 27 mh z 3.3 v olt vcxo mds 727 b 3 revision 121404 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com ics727 external component selection the ics727 requires a minimum number of external components for proper operation. decoupling capacitor a decoupling capacitor of 0.01f must be connected between vdd (pin 2) and gnd (pin 4), as close to these pins as possible. for optimum device performance, the decoupling capacitor should be mounted on the component side of the pcb. avoid the use of vias in the decoupling circuit. series termination resistor when the pcb trace between the clock output (clk, pin 5) and the load is over 1 inch, series termination should be used. to series terminate a 50 ? trace (a commonly used trace impedance) place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . quartz crystal the ics727 vcxo function consists of the external crystal and the integrated vcxo oscillator circuit. to assure the best system performance (frequency pull range) and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the following section shown must be followed. the frequency of oscillation of a quartz crystal is determined by its ?cut? and by the load capacitors connected to it. the ics727 incorporates on-chip variable load capacitors that ?pull? (change) the frequency of the crystal. the crystal specified for use with the ics727 is designed to have zero frequency error when the total of on-chip + stray capacitance is 14pf. recommended crystal parameters: initial accuracy at 25 c 20 ppm temperature stability 30 ppm aging 20 ppm load capacitance 14 pf shunt capacitance, c0 7 pf max c0/c1 ratio 250 max equivalent series resistance 35 ? max the third overtone mode of the crystal and all spurs must be >100 ppm distant from 3x the fundamental resonance measured with a physical load of 14 pf. the external crystal must be connected as close to the chip as possible and should be on the same side of the pcb as the ics727. there should be no vias between the crystal pins and the x1 and x2 device pins. there should be no signal traces underneath or close to the crystal. crystals can be made to resonate either at the fundamental frequency, or on the third, fifth, or even higher overtone. vcxo crystals are always fundamental mode, because overtone modes are much less pullable and require addi tional oscillator circuitry for proper operation. the third overtone mode is not necessarily at exactly three times the fundamental frequency. the mechanical properties of the quartz element dictate the position of the overtones relative to the fundamental, and in a vcxo circuit, the third overtone is not typically exactly three times the fundamental, or the oscillator circuit may excite both the fundamental and overtone modes simultaneously. this will cause a nonlinearity in the transfer curve such as the one in figure 3. this potential problem is why vcxo crystals are required to be tested for absence of any activity inside a +/-100 ppm window at three times the fundamental frequency. crystal tuning load capacitors the crystal traces should include pads for small fixed capacitors, one between x1 and ground, and another between x2 and ground. stuffing of these capacitors on the pcb is optional. the need for these capacitors is determined at system prototype evaluation, and is influenced by the particular crystal used (manufacture and frequency) and by pcb layout. the typical required capacitor value is 1 to 4 pf. to determine the need for and value of the crystal adjustment capacitors, you will need a pc board of your final layout, a frequency counter capable of about 1 ppm resolution and accuracy, two power supplies, and some samples of the crystals which you plan to use in production, along with measured initial accuracy for each crystal at the specified crystal load capacitance, cl.
l ow c ost 27 mh z 3.3 v olt vcxo mds 727 b 4 revision 121404 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com ics727 to determine the value of the crystal capacitors: 1. connect vdd of the ics727 to 3.3 v. connect pin 3 of the ics727 to the second power supply. adjust the voltage on pin 3 to 0v. measure and record the frequency of the clk output. 2. adjust the voltage on pin 3 to 3.3 v. measure and record the frequency of the same output. to calculate the centering error: where: f target = nominal crystal frequency error xtal =actual initial accuracy (in ppm) of the crystal being measured if the centering error is less than 25 ppm, no adjustment is needed. if the centering error is more than 25ppm negative, the pc board has excessive stray capacitance and a new pcb layout should be considered to reduce stray capacitance. (alternately, the crystal may be re-specified to a higher load capacitance. contact ics microclock for details.) if the centering error is more than 25 ppm positive, add identical fixed centering capacitors from each crystal pin to ground. the value for each of these caps (in pf) is given by: external capacitor = 2 x (centering error)/(trim sensitivity) trim sensitivity is a parame ter which can be supplied by your crystal vendor. if you do not know the value, assume it is 30 ppm/pf. after any changes, repeat the measurement to verify that the remaining error is acceptably low (typically less than 25 ppm). absolute maximum ratings stresses above the ratings listed below can cause perma nent damage to the ics727. these ratings, which are standard values for ics commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions error 10 6 x f 3.0v f tet arg ? () f 0v f tet arg ? () + f tet arg ------------------------------------------------------------------------------ error xtal ? = item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v storage temperature -65 to +150 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature 0 +70 c power supply voltage (measured in respect to gnd) +3.15 +3.45 v reference crystal parameters refer to page 3
l ow c ost 27 mh z 3.3 v olt vcxo mds 727 b 5 revision 121404 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com ics727 dc electrical characteristics vdd=3.3 v 5% , ambient temperature 0 to +70 c, unless stated otherwise ac electrical characteristics vdd = 3.3 v 5% , ambient temperature 0 to +70 c, unless stated otherwise note 1: external crystal device must conform with pullable crystal specifications listed on page 3. thermal characteristics parameter symbol conditions min. typ. max. units operating voltage vdd 3.15 3.45 v output high voltage v oh i oh = -12 ma 2.4 v output low voltage v ol i ol = 12 ma 0.4 v output high voltage (cmos level) v oh i oh = -4 ma vdd-0.4 v operating supply current idd output = 27 mhz, no load 12 ma short circuit current i os 50 ma vin, vcxo control voltage v ia 03.3v parameter symbol conditions min. typ. max. units output frequency f o 27 mhz crystal pullability f p 0v< vin < 3.3 v, note 1 + 110 ppm vcxo gain vin = vdd/2 + 1 v, note 1 120 ppm/v output rise time t or 0.8 to 2.0 v, c l =15 pf 1.5 ns output fall time t of 2.0 to 0.8 v, c l =15 pf 1.5 ns output clock duty cycle t d measured at 1.4 v, c l =15 pf 40 50 60 % maximum output jitter, short term t j c l =15 pf 100 ps parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 150 c/w ja 1 m/s air flow 140 c/w ja 3 m/s air flow 120 c/w thermal resistance junction to case jc 40 c/w
l ow c ost 27 mh z 3.3 v olt vcxo mds 727 b 6 revision 121404 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com ics727 package outline and package dimensions (8-pin soic, 150 mil. narrow body) package dimensions are kept current with jedec publication no. 95 ordering information while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringemen t of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high re liability, or other extraordina ry environmental requirements are not recomm ended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. part / order number marking shipping packaging package temperature ics727m ics727m tubes 8-pin soic 0 to +70 c ICS727MT ics727m tape and reel 8-pin soic 0 to +70 c d eh c h x 45 0 b e q a pin 1 index area millimeters inches symbol min max min max a 1.35 1.75 0.0532 0.0688 a1 1.10 0.25 0.0040 0.0098 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.0075 0.0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 0.1497 0.1574 e 1.27 basic 0.050 basic h 5.80 6.20 0.2284 0.2440 h 0.25 0.50 0.010 0.020 l 0.40 1.27 0.016 0.050 a0 8 0 8
l ow c ost 27 mh z 3.3 v olt vcxo mds 727 b 7 revision 121404 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com ics727 revision history rev. originator date description of change a p.griffith 10/06/04 new devi ce/datasheet for thomson. b j. sarma 12/14/04 release from prelim to final; release as general purpose device.
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