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ltc3577-3/ltc3577-4 1 357734fb typical application features applications description highly integrated portable product pmic n full featured li-ion/polymer charger/powerpath? controller with instant-on operation n triple adjustable high ef? ciency step-down switching regulators (800ma, 500ma, 500ma i out ) n i 2 c adjustable sw slew rates for emi reduction n high temperature battery voltage reduction improves safety and reliability n overvoltage protection controller for usb (v bus )/wall inputs provide protection to 30v n integrated 40v series led back light driver with 60db brightness control and gradation via i 2 c n 1.5a maximum charge current with thermal limiting n battery float voltage: 4.2v (ltc3577-3) 4.1v (ltc3577-4) n pushbutton on/off control with system reset n dual 150ma current limited ldos n start-up timing compatible with sirf atlas iv processor n small 4mm 7mm 44-pin qfn package n pnds, dmb/dvb-h, digital/satellite radio, media players n portable industrial/medical products n other usb-based handheld products the ltc ? 3577-3/ltc3577-4 are highly integrated power management ics for single cell li-ion/polymer battery ap- plications. it includes a powerpath manager with automatic load prioritization, a battery charger, an ideal diode, input overvoltage protection and numerous other internal pro- tection features. the ltc3577-3/ltc3577-4 are designed to accurately charge from current limited supplies such as usb by automatically reducing charge current such that the sum of the load current and the charge current does not exceed the programmed input current limit (100ma or 500ma modes). the ltc3577-3/ltc3577-4 reduce the bat- tery voltage at elevated temperatures to improve safety and reliability. the three step-down switching regulators and two ldos provide a wide range of available supplies. the ltc3577-3/ltc3577-4 also include a pushbutton input to control power sequencing and system reset. the onboard led backlight boost circuitry can drive up to 10 series leds and includes versatile digital dimming via the i 2 c input. the ltc3577-3/ltc3577-4 are designed to support the sirf atlas iv processor and has pushbutton timing and sequencing different from other ltc3577 versions. the ltc3577-3/ltc3577-4 are available in a low pro? le 4mm 7mm 0.75mm 44-pin qfn package. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and powerpath is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 6522118, 6700364, 7511390, 5481178, 6580258. other patents pending. led driver ef? ciency (10 leds) + 100ma/500ma 1000ma 5v adapter charge usb optional overvoltage protection pb 2 cc/cv charger led backlight with digitally controlled dimming dual ldo regulators ltc3577-3/ltc3577-4 triple high efficiency step-down switching regulators pushbutton control 0v single cell li-ion 4 to 10 led boost v out 0.8v to 3.6v/800ma 0.8v to 3.6v/150ma 0.8v to 3.6v/150ma 0.8v to 3.6v/500ma 0.8v to 3.6v/500ma ntc i 2 c port 357734 ta01a led current (ma) 20 efficiency (%) 30 50 60 80 90 1000 100 10 1 0.1 0.01 357734 ta01b 10 70 40 0 max pwm constant current
ltc3577-3/ltc3577-4 2 357734fb features ...................................................................................................................... ...... 1 applications .................................................................................................................. ..... 1 typical application ........................................................................................................... .... 1 description.................................................................................................................... ..... 1 absolute maximum ratings ..................................................................................................... 3 order information ............................................................................................................. .... 3 pin con? guration ............................................................................................................. .... 3 electrical characteristics .................................................................................................... .... 4 typical performance characteristics .........................................................................................10 pin functions ................................................................................................................. ....16 block diagram ................................................................................................................. ...19 operation...................................................................................................................... ....20 powerpath operation ........................................................................................................... ............................. 20 low dropout linear regulator operation ........................................................................................ ..................... 28 step-down switching regulator operation ....................................................................................... .................... 29 led backlight/boost operation ................................................................................................. ............................ 33 i 2 c operation ................................................................................................................... ..................................... 37 pushbutton interface operation ................................................................................................ ............................ 42 layout and thermal considerations ............................................................................................. ........................ 46 typical applications .......................................................................................................... ...48 package description ........................................................................................................... .50 related parts ................................................................................................................. ....51 table of contents
ltc3577-3/ltc3577-4 3 357734fb pin configuration absolute maximum ratings v sw ............................................................ C0.3v to 45v v bus , v out , v in12 , v in3 , v inldo1 , v inldo2 , wall t < 1ms and duty cycle < 1% ................... C0.3v to 7v steady state ............................................ C0.3v to 6v chrg , bat, led_fs, led_ov, pwr_on, extpwr , pbstat, pgood, fb1, fb2, fb3, ldo1, ldo1_fb, ldo2, ldo2_fb, dv cc , scl, sda, en3 ................. C0.3v to 6v ntc, prog, clprog, on , i lim0 , i lim1 (note 4) ........................................... C0.3v to v cc + 0.3v i vbus , i vout , i bat , continuous (note 16) .....................2a i sw3 , continuous (note 16) ................................. 850ma i sw2 , i sw1 , continuous (note 16) ........................ 600ma i ldo1 , i ldo2 , continuous (note 16) ..................... 200ma i chrg , i acpr , i extpwr , i pbstat , i pgood ...................75ma i ovsens ..................................................................10ma i clprog , i prog , i led_fs , i led_ov ..............................2ma maximum junction temperature ...........................110c operating temperature range .................C40c to 85c storage temperature range .................. C65c to 125c (notes 1, 2, 3) top view 45 gnd uff package 44-lead (7mm s 4mm) plastic qfn i lim0 1 i lim1 2 led_fs 3 wall 4 sw3 5 v in3 6 fb3 7 ovsens 8 led_ov 9 dv cc 10 sda 11 scl 12 ovgate 13 pwr_on 14 on 15 37 idgate 36 prog 35 ntc 34 ntcbias 33 sw1 32 v in12 31 sw2 30 v inld02 29 ldo2 28 ldo1 27 v inldo1 26 fb1 25 fb2 24 ldo2_fb 23 ldo1_fb pbstat 16 en3 17 sw 18 sw 19 sw 20 pgood 21 i led 22 44 chrg 43 clprog 42 extpwr 41 acpr 40 v bus 39 v out 38 bat t jmax = 110c, ja = 45c/w exposed pad (pin 45) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking package description temperature range ltc3577euff-3#pbf ltc3577euff-3#trpbf 35773 44-lead (4mm 7mm) plastic qfn C40c to 85c ltc3577euff-4#pbf ltc3577euff-4#trpbf 35774 44-lead (4mm 7mm) plastic qfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
ltc3577-3/ltc3577-4 4 357734fb electrical characteristics power manager . the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v bus = 5v, v bat = 3.8v, i lim0 = i lim1 = 5v, wall = 0v, v inldo2 = v inlod1 = v in12 = v in3 = v out , r prog = 2k, r clprog = 2.1k, unless otherwise noted. symbol parameter conditions min typ max units input power supply v bus input supply voltage 4.35 5.5 v i bus_lim total input current (note 5) i lim0 = 5v, i lim1 = 5v (1x mode) i lim0 = 0v, i lim1 = 0v (5x mode) i lim0 = 0v, i lim1 = 5v (10x mode) l l l 80 450 900 90 475 950 100 500 1000 ma ma ma i busq input quiescent current, poff state 1x, 5x, 10x modes i lim0 = 5v, i lim1 = 0v (suspend mode) 0.42 0.05 0.1 ma ma h clprog ratio of measured v bus current to clprog program current 1000 ma/ma v clprog clprog servo voltage in current limit 1x mode 5x mode 10x mode 0.2 1.0 2.0 v v v v uvlo v bus undervoltage lockout rising threshold falling threshold 3.5 3.8 3.7 3.9 v v v duvlo v bus to v out differential undervoltage lockout rising threshold falling threshold 50 C50 100 mv mv r on_ilim input current limit power fet on- resistance (between v bus and v out ) 200 m battery charger v float v bat regulated output voltage ltc3577-3 ltc3577-3, 0 t a 85c 4.179 4.165 4.200 4.200 4.221 4.235 v v ltc3577-4 ltc3577-4, 0 t a 85c 4.079 4.065 4.1 4.1 4.121 4.135 v v i chg constant-current mode charge current ic not in thermal limit r prog = 1k, input current limit = 2a r prog = 2k, input current limit = 1a r prog = 5k, input current limit = 0.4a l l l 950 465 180 1000 500 200 1050 535 220 ma ma ma i batq_off battery drain current, poff state, buck3 disabled, no load (note 15) v bat = 4.3v, charger time out v bus = 0v 6 55 27 100 a a i batq_on battery drain current, pon state, buck3 enabled (notes 10, 15) v bus = 0v, i out = 0a, no load on supplies, burst mode operation 130 200 a v prog,chg prog pin servo voltage v bat > v trkl 1.000 v v prog,trkl prog pin servo voltage in trickle charge v bat < v trkl 0.100 v h prog ratio of i bat to prog pin current 1000 ma/ma i trkl trickle charge current v bat < v trkl 40 50 60 ma v trkl trickle charge rising threshold trickle charge falling threshold v bat rising v bat falling 2.5 2.9 2.75 3.0 v v v rechrg recharge battery threshold voltage threshold voltage relative to v float C75 C100 C125 mv t term safety timer termination period timer starts when v bat = v float C 50mv 3.2 4 4.8 hour t badbat bad battery termination time v bat < v trkl 0.4 0.5 0.6 hour h c/10 end-of-charge indication current ratio (note 6) 0.085 0.1 0.11 ma/ma r on_chg battery charger power fet on- resistance (between v out and bat) 200 m t lim junction temperature in constant temperature mode 110 c
ltc3577-3/ltc3577-4 5 357734fb power manager . the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v bus = 5v, v bat = 3.8v, i lim0 = i lim1 = 5v, wall = 0v, v inldo2 = v inlod1 = v in12 = v in3 = v out , r prog = 2k, r clprog = 2.1k, unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units ntc, battery discharge protection v cold cold temperature fault threshold voltage rising ntc voltage hysteresis 75 76 1.3 77 %v ntcbias %v ntcbias v hot hot temperature fault threshold voltage falling ntc voltage hysteresis 34 35 1.3 36 %v ntcbias %v ntcbias v too _ hot ntc discharge threshold voltage falling ntc voltage hysteresis 24.5 25.5 50 26.5 %v ntcbias mv i ntc ntc leakage current v ntc = v bus = 5v C50 50 na i bat2hot bat discharge current v bat = 4.1v, ntc < v too_hot 170 ma v bat2hot bat discharge threshold i bat < 0.1ma, ntc < v too_hot 3.9 v ideal diode v fwd forward voltage detection i out = 10ma 5 15 25 mv r dropout diode on-resistance, dropout i out = 200ma 200 m i max diode current limit (note 7) 3.6 a overvoltage protection v ovcutoff overvoltage protection threshold rising threshold, r ovsens = 6.2k 6.10 6.35 6.70 v v ovgate ovgate output voltage input below v ovcutoff input above v ovcutoff 1.88 ? v ovsens 12 0 v v i ovsensq ovsens quiescent current v ovsens = 5v 40 a t rise ovgate time to reach regulation c ovgate = 1nf 2.5 ms wall adapter and high voltage buck output control v acpr acpr pin output high voltage acpr pin output low voltage i acpr = 0.1ma i acpr = 1ma v out C 0.3 v out 0 0.3 v v v w absolute wall input threshold voltage v wall rising v wall falling 3.1 4.3 3.2 4.45 v v v w differential wall input threshold voltage v wall C v bat falling v wall C v bat rising 025 75 100 mv mv i qwall wall operating quiescent current i wall + i vout , i bat = 0ma, wall = v out = 5v 440 a logic (i lim0 , i lim1 and chrg ) v il input low voltage i lim0 , i lim1 0.4 v v ih input high voltage i lim0 , i lim1 1.2 v i pd static pull-down current i lim0 , i lim1 ; v pin = 1v 2 a v chrg chrg pin output low voltage i chrg = 10ma 0.15 0.4 v i chrg chrg pin input current v bat = 4.5v, v chrg = 5v 0 1 a
ltc3577-3/ltc3577-4 6 357734fb electrical characteristics i 2 c interface. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. dv cc = 3.3v, v out = 3.8v, unless otherwise noted. symbol parameter conditions min typ max units dv cc input supply voltage 1.6 5.5 v i dvcc dv cc supply current scl = 400khz scl = sda = 0khz 10 1 a a v dvcc,uvlo dv cc uvlo 1.0 v v ih input high voltage 50 70 %dv cc v il input low voltage 30 50 %dv cc i ih input high leakage current sda = scl = dv cc = 5.5v C1 1 a i il input low leakage current sda = scl = 0v, dv cc = 5.5v C1 1 a v ol sda output low voltage i sda = 3ma 0.4 v timing characteristics (note 8) (all values are referenced to v ih and v il ) f scl scl clock frequency 400 khz t low low period of the scl clock 1.3 s t high high period of the scl clock 0.6 s t buf bus free time between stop and start condition 1.3 s t hd,sta hold time after (repeated) start condition 0.6 s t su,sta setup time for a repeated start condition 0.6 s t su,sto stop condition setup time 0.6 s t hd,dato output data hold time 0 900 ns t hd,dati input data hold time 0 ns t su,dat data setup time 100 ns t sp input spike suppression pulse width 50 ns led boost switching regulator. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in3 = v out = 3.8v, r ov = 10m, r led_fs = 20k, boost regulator disabled unless otherwise noted. symbol parameter conditions min typ max units v in3 , v out operating supply range (note 9) l 2.7 5.5 v i vout_led operating quiescent current shutdown quiescent current (notes 10, 14) 560 0.01 a a v led_ov led overvoltage threshold led_ov rising led_ov falling 0.6 1.0 0.85 1.25 v v i lim peak nmos switch current 800 1000 1200 ma i led(fs) i led pin full-scale operating current 18 20 22 ma i led(dim) i led pin full-scale dimming range 64 steps 60 db r nswon r ds(on) of nmos switch 240 m i nswoff nmos switch off leakage current v sw = 5.5v 0.01 1 a f osc oscillator frequency 0.95 1.125 1.3 mhz v led_fs led_fs pin voltage l 780 800 820 mv i led_ov led_ov pin current l 3.8 4 4.2 a d boost maximum duty cycle i led = 0 97 % v boostfb boost mode feedback voltage l 775 800 825 mv
ltc3577-3/ltc3577-4 7 357734fb electrical characteristics step-down switching regulators. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v out = v in12 = v in3 = 3.8v, all regulators enabled unless otherwise noted. symbol parameter conditions min typ max units step-down switching regulators (buck1, buck2 and buck3) v in12 , v in3 input supply voltage (note 9) l 2.7 5.5 v v out uvlo v out falling v out rising v in12 and v in3 connected to v out through low impedance. switching regulators are disabled below v out uvlo 2.5 2.7 2.8 2.9 v v f osc oscillator frequency 1.91 2.25 2.59 mhz 800ma step-down switching regulator 3 (buck3-enabled via en3, disabled in pon and poff states) i vin3q pulse-skipping mode input current (note 10) 100 a burst mode operation input current (note 10) 20 35 a shutdown input current en3 = 0 0.01 1 a i lim3 peak pmos current limit (note 7) 1000 1400 1700 ma v fb3 feedback voltage pulse-skipping mode burst mode operation l l 0.78 0.78 0.8 0.8 0.82 0.824 v v i fb3 fb3 input current (note 10) C0.05 0.05 a d3 max duty cycle fb3 = 0v 100 % r p3 r ds(on) of pmos 0.3 r n3 r ds(on) of nmos 0.4 r sw3_pd sw3 pull-down in shutdown en3 = 0 10 k v il,en3 en3 input low voltage 0.4 v v ih,en3 en3 input high voltage 1.2 v 500ma step-down switching regulator 2 (buck2-pushbutton enabled, third in sequence) i vin12q pulse-skipping mode input current (note 10) 100 a burst mode operation input current (note 10) 20 a shutdown input current poff state 0.01 1 a i lim2 peak pmos current limit (note 7) 650 900 1200 ma v fb2 feedback voltage pulse-skipping mode burst mode operation l l 0.78 0.78 0.8 0.8 0.82 0.824 v v i fb2 fb2 input current (note 10) C0.05 0.05 a d2 max duty cycle fb2 = 0v 100 % r p2 r ds(on) of pmos i sw2 = 100ma 0.6 r n2 r ds(on) of nmos i sw2 = C100ma 0.6 r sw2_pd sw2 pull-down in shutdown poff state 10 k 500ma step-down switching regulator 1 (buck1-pushbutton enabled, second in sequence) i vin12q pulse-skipping mode input current (note 10) 100 a burst mode operation input current (note 10) 20 a shutdown input current 0.01 1 a i lim1 peak pmos current limit (note 7) 650 900 1200 ma v fb1 feedback voltage pulse-skipping mode burst mode operation l l 0.78 0.78 0.8 0.8 0.82 0.824 v v i fb1 fb1 input current (note 10) C0.05 0.05 a d1 max duty cycle fb1 = 0v 100 % r p1 r ds(on) of pmos i sw1 = 100ma 0.6 r n1 r ds(on) of nmos i sw1 = C100ma 0.6 r sw1_pd sw1 pull-down in shutdown poff state 10 k
ltc3577-3/ltc3577-4 8 357734fb electrical characteristics ldo regulators. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v inldo1 = v inldo2 = v out = 3.8v, ldo1 and ldo2 enabled unless otherwise noted. symbol parameter conditions min typ max units ldo regulator 1 (ldo1-always on) v inldo1 input voltage range v inldo1 v out + 0.3v l 1.65 5.5 v v out_uvlo v out falling v out rising ldo1 is disabled below v out uvlo 2.5 2.7 2.8 2.9 v v v ldo1_fb ldo1_fb regulated feedback voltage i ldo1 = 1ma l 0.78 0.8 0.82 v ldo1_fb line regulation (note 11) i ldo1 = 1ma, v in = 1.65v to 5.5v 0.4 mv/v ldo1_fb load regulation (note 11) i ldo1 = 1ma to 150ma 5 v/ma i ldo1_oc available output current l 150 ma i ldo1_sc short-circuit output current 270 ma v drop1 dropout voltage (note 12) i ldo1 = 150ma, v inldo1 = 3.6v i ldo1 = 150ma, v inldo1 = 2.5v i ldo1 = 75ma, v inldo1 = 1.8v 160 200 170 260 320 280 mv mv mv r ldo1_pd output pull-down resistance in shutdown ldo1 disabled 10 k i ldo_fb1 ldo_fb1 input current C50 50 na ldo regulator 2 (ldo2-pushbutton enabled, first in sequence) v inldo2 input voltage range v inldo2 v out + 0.3v l 1.65 5.5 v v out_uvlo v out falling v out rising ldo2 is disabled below v out uvlo 2.5 2.7 2.8 2.9 v v v ldo2_fb ldo2_fb regulated output voltage i ldo2 = 1ma l 0.78 0.8 0.82 v ldo2_fb line regulation (note 11) i ldo2 = 1ma, v in = 1.65v to 5.5v 0.4 mv/v ldo2_fb load regulation (note 11) i ldo2 = 1ma to 150ma 5 v/ma i ldo2_oc available output current l 150 ma i ldo2_sc short-circuit output current 270 ma v drop2 dropout voltage (note 12) i ldo2 = 150ma, v inldo2 = 3.6v i ldo2 = 150ma, v inldo2 = 2.5v i ldo1 = 75ma, v inldo1 = 1.8v 160 200 170 260 320 280 mv mv mv r ldo2_pd output pull-down resistance in shutdown ldo2 disabled 14 k i ldo_fb2 ldo_fb2 input current C50 50 na
ltc3577-3/ltc3577-4 9 357734fb electrical characteristics pushbutton controller. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v out = 3.8v, unless otherwise noted. symbol parameter conditions min typ max units pushbutton pin ( on ) v out pushbutton operating supply range (note 9) l 2.7 5.5 v v out uvlo v out falling v out rising pushbutton is disabled below v out uvlo 2.5 2.7 2.8 2.9 v v v on _th on threshold rising on threshold falling 0.4 0.8 0.7 1.2 v v i on on input current v on = v out v on = 0v C1 C4 C9 1 C14 a a power-on input pin (pwr_on) v pwr_on pwr_on threshold rising pwr_on threshold falling 0.4 0.8 0.7 1.2 v v i pwr_on pwr_on input current v pwr_on = 3v C1 1 a status output pins (pbstat, extpwr , pgood) i pbstat pbstat output high leakage current v pbstat = 3v C1 1 a v pbstat pbstat output low voltage i pbstat = 3ma 0.1 0.4 v i extpwr extpwr pin input current v extpwr = 3v 0 1 a v extpwr extpwr pin output low voltage i extpwr = 2ma 0.15 0.4 v i pgood pgood output high leakage current v pgood = 3v C1 1 a v pgood pgood output low voltage i pgood = 3ma 0.1 0.4 v v thpgood pgood threshold voltage (note 13) C8 % pushbutton timing parameters t on _pbstat1 on low time to pbstat low 50 ms t on _pbstat2 on high to pbstat high pbstat low > t pbstat_pw 900 s t pbstat_pw pbstat minimum pulse width 40 50 ms t on _pup on low time for power-up 50 ms t on _rst on low to pgood reset low 12 14 16.5 seconds t on _rst_pw pgood reset low pulse width 1.8 ms t pup_pdn minimum time from po wer up to down 1 seconds t pdn_pup minimum time from po wer down to up 1 s econds t pwr_onh pwr_on high to power-up 50 ms t pwr_onl pwr_on low to power-down 50 ms t pwr_onbk1 pwr_on power-up blanking pwr_on low recognized from pow er-up 1 seconds t pwr_onbk2 pwr_on power-down blanking pwr_on high recognized from po wer-down 1 seconds t pgoodh from regulation to pgood high buck1, 2 and ldo1 within pgood threshold 230 ms t pgoodl bucks disabled to pgood low bucks disabled 44 s t ldo2_bk1 ldo2 enable to buck enable 12.5 14.5 17.5 ms note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3577-3/ltc3577-4 are guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: this ic includes over temperature protection that is intended to protect the device during momentary overload conditions. junction temperatures will exceed 110c when over temperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may result in device degradation or failure. note 4: v cc is the greater of v bus , v out or bat. note 5: total input current is the sum of quiescent current, i busq , and measured current given by v clprog /r clprog ? (h clprog + 1).
ltc3577-3/ltc3577-4 10 357734fb typical performance characteristics input supply current vs temperature input supply current vs temperature (suspend mode) battery drain current vs temperature input current limit vs temperature input r on vs temperature charge current vs temperature (thermal regulation) electrical characteristics note 6: h c/10 is expressed as a fraction of measured full charge current with indicated prog resistor. note 7: the current limit features of this part are intended to protect the ic from short term or intermittent fault conditions. continuous operation above the maximum speci? ed pin current rating may result in device degradation or failure. note 8: the serial port is tested at rated operating frequency. timing parameters are tested and/or guaranteed by design. note 9: v out not in uvlo. note 10: buck fb high, not switching. note 11: measured with the ldo running unity gain with output tied to feedback pin. note 12: dropout voltage is the minimum input to output voltage differential needed for an ldo to maintain regulation at a speci? ed output current. when an ldo is in dropout, its output voltage will be equal to v in C v drop . note 13: pgood threshold is expressed as a percentage difference from the buck1, buck2 and ldo1 regulation voltages. the threshold is measured from buck1, buck2 and ldo1 output rising. note 14: i vout_led is the sum of v out and v in3 current due to led driver. note 15: the i batq speci? cations represent the total battery load assuming v inldo1 , v inldo2 , v in12 and v in3 are tied directly to v out . note 16: long-term current density rating for the part. temperature (c) C50 i vbus (ma) 0.7 25 357734 g01 0.4 0.2 C25 0 50 0.1 0 0.8 0.6 0.5 0.3 75 100 125 v bus = 5v 1x mode t a = 25c unless otherwise speci? ed temperature (c) C50 C25 0 i vbus (ma) 0.04 0.10 0 50 75 357734 g02 0.02 0.08 0.06 25 100 125 v bus = 5v temperature (c) C50 i vbus (ma) 400 1000 1100 1200 0 50 75 357734 g04 200 100 800 600 300 900 0 700 500 C25 25 100 125 v bus = 5v r clprog = 2.1k 10x mode 5x mode 1x mode temperature (c) C50 0 r on (m) 100 140 160 180 300 240 0 50 75 357734 g05 120 260 280 220 C25 25 100 125 i out = 400ma v bus = 4.5v v bus = 5.5v v bus = 5v temperature (c) C50 i bat (ma) 400 500 600 25 75 357734 g06 300 200 C25 0 50 100 125 100 0 v bus = 5v 10x mode r prog = 2k temperature (c) C50 0 i bat (a) 50 150 200 250 450 350 0 50 75 357734 g03 100 400 300 C25 25 100 125 no load on all supplies v bat = 3.8v v bus = 0v all supplies enabled (except boost) pulse-skip mode all supplies enabled (except boost) burst mode operation all supplies disabled except ldo1
ltc3577-3/ltc3577-4 11 357734fb typical performance characteristics battery current and voltage vs time battery float voltage load regulation (ltc3577-3) battery regulation (float) voltage vs temperature i bat vs v bat (ltc3577-3) forward voltage vs ideal diode current (no external fet) forward voltage vs ideal diode current (with si2333ds external fet) input connect waveform input disconnect waveform t a = 25c unless otherwise speci? ed time (hour) 0 0 i bat (ma) v bat and v chrg (v) 100 200 300 400 600 1 234 357734 g07 56 500 0 1 2 3 4 6 v bat i bat c/10 5 1450mahr cell v bus = 5v r prog = 2k r clprog = 2k chrg safety timer termination v bat (v) 2.0 0 i bat (ma) 100 200 300 400 600 2.4 2.8 3.2 3.6 357734 g10 4.0 4.4 500 falling v bat rising v bat v bus = 5v 10x mode r prog = 2k r clprog = 2k i bat (a) 0 0 v fwd (v) 0.05 0.10 0.15 0.20 0.25 0.2 0.4 0.6 0.8 357734 g12 1.0 1.2 v bat = 3.2v v bus = 0v t a = 25c v bat = 4.2v v bat = 3.6v i bat (a) 0 v fwd (mv) 15 20 25 0.6 1.0 357734 g13 10 5 0 0.2 0.4 0.8 30 35 40 v bat = 3.8v v bus = 0v t a = 25c v bus 5v/div v out 5v/div i bus 0.5a/div i bat 0.5a/div v bat = 3.75v i out = 100ma r clprog = 2k r prog = 2k 1ms/div 357734 g14 v bus 5v/div v out 5v/div i bus 0.5a/div i bat 0.5a/div v bat = 3.75v i out = 100ma r clprog = 2k r prog = 2k 1ms/div 357734 g15 i bat (ma) 0 4.20 4.22 4.24 800 357734 g08 4.18 4.16 200 400 600 1000 4.14 4.12 4.10 v float (v) v bus = 5v 10x mode temperature (c) C50 v bat (v) 4.22 25 357734 g09 4.12 4.14 4.08 C25 0 50 4.06 4.04 4.24 4.20 4.18 4.16 4.10 75 100 125 ltc3577-3 i bat = 2ma ltc3577-4 i bat vs v bat (ltc3577-4) v bat (v) 2.0 0 i bat (ma) 100 200 300 400 600 2.4 2.8 3.2 3.6 357734 g11 4.0 4.4 falling v bat 500 rising v bat r clprog = 2.1k r prog = 2k v bus = 5v 10x mode
ltc3577-3/ltc3577-4 12 357734fb typical performance characteristics switching from suspend mode to 5x mode wall connect waveform wall disconnect waveform oscillator frequency vs temperature step-down switching regulator 1 3.3v output ef? ciency vs i out1 step-down switching regulator 2 1.8v output ef? ciency vs i out2 t a = 25c unless otherwise speci? ed step-down switching regulator 3 1.2v ooutput ef? ciency vs i out3 step-down switching regulator 3 2.5v output ef? ciency i lim0 5v/div v out 5v/div i bus 0.5a/div i bat 0.5a/div v bat = 3.75v i out = 100ma r clprog = 2k r prog = 2k i lim1 = 5v 100s/div 357734 g17 wall 5v/div v out 5v/div i wall 0.5a/div i bat 0.5a/div v bat = 3.75v i out = 100ma r prog = 2k 1ms/div 357734 g18 wall 5v/div v out 5v/div i wall 0.5a/div i bat 0.5a/div v bat = 3.75v i out = 100ma r prog = 2k 1ms/div 357734 g19 temperature (c) C50 frequency (mhz) 1.8 1.9 2.0 2.5 2.6 2.7 2.8 2.2 0 50 75 357734 g20 2.3 2.4 2.1 C25 25 100 125 v out = 5v v out = 3.8v i out (ma) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 100 1000 357734 g21 30 20 10 0 90 100 v in12 = 3.8v v in12 = 5v burst mode operation pulse-skipping v out1 = 3.3v i out (ma) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 100 1000 357734 g22 30 20 10 0 90 100 v in12 = 3.8v v in12 = 5v burst mode operation pulse-skipping v out2 = 1.8v i out (ma) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 100 1000 357734 g23 30 20 10 0 90 100 v in3 = 3.8v v in3 = 5v burst mode operation pulse-skipping v out3 = 1.2v i out (ma) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 100 1000 357734 g24 30 20 10 0 90 100 v in3 = 3.8v v in3 = 5v burst mode operation pulse-skipping v out3 = 2.5v switching from 1x to 5x mode i lim0 /i lim1 5v/div i bus 0.5a/div i bat 0.5a/div v bat = 3.75v i out = 50ma r clprog = 2k r prog = 2k 1ms/div 357734 g16
ltc3577-3/ltc3577-4 13 357734fb step-down switching regulator short-circuit current vs temperature temperature (c) C50 short-circuit current (ma) 1100 25 357734 g25 800 600 C25 0 50 500 1200 1300 1400 1500 1000 900 700 75 100 125 800ma buck 500ma buck v inx = 3.8v v inx = 5v typical performance characteristics step-down switching regulator output transient (burst mode operation) step-down switching regulator output transient (pulse-skipping) 800ma step-down switching regulator feedback voltage vs output current step-down switching regulator 3 soft-start and shutdown t a = 25c unless otherwise speci? ed ovp connection waveform step-down switching regulator switch impedance vs temperature 500ma step-down switching regulator feedback voltage vs output current ovp protection waveform temperature (c) C50 0 switch impedance () 0.1 0.3 0.4 0.5 50 0.9 357734 g28 0.2 0 C25 75 100 25 125 0.6 0.7 0.8 800ma nmos 800ma pmos 500ma pmos 500ma nmos v inx = 3.2v i out (ma) 0.78 feedback (v) 0.84 0.85 0.77 0.76 0.83 0.80 0.82 0.81 0.79 0.1 10 100 1000 357732 g29 0.75 1 v in3 = 3.8v v in3 = 5v burst mode operation pulse-skipping i out (ma) 0.78 feedback (v) 0.84 0.85 0.77 0.76 0.83 0.80 0.82 0.81 0.79 0.1 10 100 1000 357734 g30 0.75 1 burst mode operation pulse-skipping v in12 = 3.8v v in12 = 5v v out1 50mv/div (ac) v out2 50mv/div (ac) v out3 100mv/div (ac) i out3 500ma 5ma 357734 g26 50s/div v out1 = 3.3v i out1 = 10ma v out2 = 1.8v i out2 = 20ma v out3 = 1.2v v out = v bat = 3.8v v out1 50mv/div (ac) v out2 50mv/div (ac) v out3 100mv/div (ac) i out3 500ma 5ma 357734 g27 50s/div v out1 = 3.3v i out1 = 30ma v out2 = 1.8v i out2 = 20ma v out3 = 1.2v v out = v bat = 3.8v v out1 100mv/div (ac) v out3 i l3 2v 1v 0v 400ma 200ma 0ma 357734 g31 50s/div v out1 = 1.8v i out1 = 100ma r out3 = 3 v bus 5v/div ovgate 5v/div 500s/div 357734 g32 ovp input voltage 0v to 5v step 5v/div v bus 5v/div ovgate 5v/div 500s/div 357734 g33 ovp input voltage 5v to 10v step 5v/div
ltc3577-3/ltc3577-4 14 357734fb typical performance characteristics ovsens quiescent current vs temperature ovgate vs ovsens led driver ef? ciency 10 leds t a = 25c unless otherwise speci? ed dac code vs led current rising overvoltage threshold vs temperature led driver ef? ciency 8 leds led driver ef? ciency 6 leds temperature (c) C40 quiescent current (a) 33 35 37 60 357734 g35 31 29 27 C15 10 35 85 v ovsens = 5v temperature (c) C40 opv threshold (v) 6.270 6.275 6.280 60 357734 g36 6.265 6.260 6.255 C15 10 35 85 input voltage (v) 0 0 ovgate (v) 2 4 6 8 10 12 24 68 357734 g37 ovsens connected to input through 6.2k resistor i led (ma) 0 efficiency (%) 90 85 80 75 70 65 60 55 50 16 357734 g38 4 8 12 20 14 2 6 10 18 3v 3.6v 4.2v 4.8v 5.5v i led (ma) 0 efficiency (%) 90 85 80 75 70 65 60 55 50 16 357734 g39 4 8 12 20 14 2 6 10 18 3v 3.6v 4.2v 4.8v 5.5v i led (ma) 0 efficiency (%) 90 85 80 75 70 65 60 55 50 16 357734 g40 4 8 12 20 14 2 6 10 18 3v 3.6v 4.2v 4.8v 5.5v led driver ef? ciency 4 leds i led (ma) 0 efficiency (%) 90 85 80 75 70 65 60 55 50 16 357734 g41 4 8 12 20 14 2 6 10 18 3v 3.6v 4.2v 4.8v 5.5v dac code 0 40 50 70 30 50 357734 g42 30 20 10 20 40 60 70 10 0 60 current (db) 0db = 20a 60db = 20ma r led_fs = 20k ovp reconnection waveform v bus 5v/div ovgate 5v/div 500s/div 357734 g34 ovp input voltage 10v to 5v step 5v/div
ltc3577-3/ltc3577-4 15 357734fb led boost start-up transient typical performance characteristics too hot bat discharge t a = 25c unless otherwise speci? ed ldo load step 10-led driver ef? ciency input and battery current vs output current i out (ma) 0 600 500 400 300 200 100 0 C100 300 500 357734 g51 100 200 400 600 current (ma) i load i in i bat (charging) i bat (discharging) wall = 0v r prog = 2k r clprog = 2k led boost switch impedance vs temperature temperature (c) C40 r ds(on) (m) 200 250 300 120 357734 g44 150 100 0 0 40 80 C20 140 20 60 100 50 400 350 3v 3.6v 4.2v 4.8v 5.5v temperature (c) C50 95.7 max duty cycle (%) 95.8 96.0 96.1 96.2 50 96.6 357734 g45 95.9 0 C25 75 100 25 125 96.3 96.4 96.5 3v 3.6v 4.2v 5.5v led boost maximum duty cycle vs temperature led boost current limit vs temperature temperature (c) C40 current limit (ma) 600 800 1000 1200 40 357734 g46 400 200 500 700 900 1100 300 100 0 C20 0 20 60 80 100 120 ldo1 50mv/div (ac) ldo2 20mv/div (ac) i out1 100ma 5ma 357734 g48 20s/div ldo1 = 1.2v ldo2 = 2.5v i ldo2 = 40ma v out = v bat = 3.8v v bat (v) 3.8 0 i bat (ma) 20 60 80 100 200 140 3.9 4.0 357734 g49 40 160 180 120 4.1 4.2 v ntc < v too_hot v bus = 0v led current (ma) 20 efficiency (%) 30 50 60 80 90 1000 100 10 1 0.1 0.01 357734 g47 10 70 40 0 max pwm constant current i led 10ma/div v boost 20v/div i l 200ma/div 2ms/div 357734 g43 battery discharge vs temperature temperature (c) 50 battery discharge current (ma) 175 80 357734 g50 100 50 60 70 90 25 0 200 150 125 75 100 110 120 v bus = 5v v bus = 0v v bat = 4.1v v ntc < v too_hot 5x mode i vout = 0ma
ltc3577-3/ltc3577-4 16 357734fb pin functions i lim0 , i lim1 (pins 1, 2): input current control pins. i lim0 and i lim1 control the input current limit. see table 1 in the usb powerpath controller section. both pins are pulled low by a weak current sink. led_fs (pin 3): a resistor between this pin and ground sets the full-scale output current of the i led pin. wall (pin 4): wall adapter present input. pulling this pin above 4.3v will disconnect the power path from v bus to v out . the acpr pin will also be pulled low to indicate that a wall adapter has been detected. sw3 (pin 5): power transmission (switch) pin for step- down switching regulator 3 (buck3). v in3 (pin 6): power input for step-down switching regu- lator 3. this pin should be connected to v out . fb3 (pin 7): feedback input for step-down switching regulator 3 (buck3). this pin servos to a ? xed voltage of 0.8v when the control loop is complete. ovsense (pin 8): overvoltage protection sense input. ovsense should be connected through a 6.2k resistor to the input power connector and the drain of an external n-channel mos pass transistor. when the voltage on this pin exceeds a preset level, the ovgate pin will be pulled to gnd to disable the pass transistor and protect downstream circuitry. led_ov (pin 9): a resistor between this pin and the boosted led backlight voltage sets the overvoltage limit on the boost output. if the boost voltage exceeds the programmed limit the led boost converter will be disabled. dv cc (pin 10): supply voltage for i 2 c lines. this pin sets the logic reference level of the ltc3577-3/ltc3577-4. a uvlo circuit on the dv cc pin forces all registers to all 0s whenever dv cc is <1v. bypass to gnd with a 0.1f capacitor. sda (pin 11): i 2 c data input. serial data is shifted one bit per clock to control the ltc3577-3/ltc3577-4. the logic level for sda is referenced to dv cc . scl (pin 12): i 2 c clock input. the logic level for scl is referenced to dv cc . ovgate (pin 13): overvoltage protection gate 0utput. connect ovgate to the gate pin of an external n-channel mos pass transistor. the source of the transistor should be connected to v bus and the drain should be connected to the products dc input connector. in the absence of an overvoltage condition, this pin is connected to an internal charge pump capable of creating suf? cient overdrive to fully enhance this transistor. if an overvoltage condition is detected, ovgate is brought rapidly to gnd to prevent damage. ovgate works in conjunction with ovsense to provide this protection. pwr_on (pin 14): logic input used to keep buck1, buck2 and ldo2 enabled after power-up. may also be used to enable regulators directly (sequence = ldo2 buck1 buck2). see the pushbutton interface operation section for more information. on (pin 15): pushbutton input. a weak internal pull-up forces on high when left ? oating. a normally open push- button is connected from on to ground to force a low state on this pin. pbstat (pin 16): open-drain output is a debounced and buffered version of on to be used for processor interrupts. en3 (pin 17): enable pin for step-down switching regulator 3 (buck3) . sw (pins 18, 19, 20): power transmission (switch) pin for led boost converter. see the led backlight/boost operation section for circuit hook-up and component selection. i 2 c is used to control led driver enable. i 2 c default is led driver off. pgood (pin 21): open-drain output. pgood indicates that buck1, buck2 and ldo1 are within 8% of ? nal regulation value. there is a 230ms delay from all regulators reaching regulation and pgood going high.
ltc3577-3/ltc3577-4 17 357734fb pin functions i led (pin 22): series led backlight current sink output. this pin is connected to the cathode end of the series led backlight string. the current drawn through the series leds is programmed via a 6-bit 60db dac and can be further dimmed via an internal pwm function. i 2 c is used to control led driver enable, brightness, gradation (soft on/soft off). i 2 c default is led driver off, current = 0ma. ldo1_fb (pin 23): feedback voltage input for low drop- out linear regulator 1 (ldo1). ldo1 output voltage is set using an external resistor divider between ldo1 and ldo1_fb. ldo2_fb (pin 24): feedback voltage input for low drop- out linear regulator 2 (ldo2). ldo2 output voltage is set using an external resistor divider between ldo2 and ldo2_fb. fb2 (pin 25): feedback input for step-down switching regulator 2 (buck2). this pin servos to a ? xed voltage of 0.8v when the control loop is complete. fb1 (pin 26): feedback input for step-down switching regulator 1 (buck1). this pin servos to a ? xed voltage of 0.8v when the control loop is complete. v inldo1 (pin 27): input supply of low dropout linear regulator 1 (ldo1). this pin should be bypassed to ground with a 1f or greater ceramic capacitor. ldo1 (pin 28): output of low dropout linear regulator 1. ldo1 is an always-on ldo and will be enabled whenever the part is not in v out uvlo. this pin must be bypassed to ground with a 1f or greater ceramic capacitor. ldo2 (pin 29): output of low dropout linear regulator 2. this pin must be bypassed to ground with a 1f or greater ceramic capacitor. v inldo2 (pin 30): input supply of low dropout linear regulator 2 (ldo2). this pin should be bypassed to ground with a 1f or greater ceramic capacitor. sw2 (pin 31): power transmission (switch) pin for step- down switching regulator 2 (buck2). v in12 (pin 32): power input for step-down switching regulators 1 and 2. this pin will generally be connected to v out . sw1 (pin 33): power transmission (switch) pin for step- down switching regulator 1 (buck1). ntcbias (pin 34): output bias voltage for ntc. a resistor from this pin to the ntc pin will bias the ntc thermistor. ntc (pin 35): the ntc pin connects to a batterys therm- istor to determine if the battery is too hot or too cold to charge. if the batterys temperature is out of range, charging is paused until it drops back into range. a low drift bias resistor is required from ntcbias to ntc and a thermistor is required from ntc to ground. prog (pin 36): charge current program and charge current monitor pin. connecting a resistor from prog to ground programs the charge current: i v r a chg prog = () 1000 ? if suf? cient input power is available in constant-current mode, this pin servos to 1v. the voltage on this pin always represents the actual charge current. idgate (pin 37): ideal diode gate connection. this pin controls the gate of an optional external p-channel mosfet transistor used to supplement the internal ideal diode. the source of the p-channel mosfet should be connected to v out and the drain should be connected to bat. it is important to maintain high impedance on this pin and minimize all leakage paths. bat (pin 38): single cell li-ion battery pin. depending on available power and load, a li-ion battery on bat will either deliver system power to v out through the ideal diode or be charged from the battery charger.
ltc3577-3/ltc3577-4 18 357734fb v out (pin 39): output voltage of the powerpath controller and input voltage of the battery charger. the majority of the portable product should be powered from v out . the ltc3577-3/ltc3577-4 will partition the available power between the external load on v out and the internal battery charger. priority is given to the external load and any extra power is used to charge the battery. an ideal diode from bat to v out ensures that v out is powered even if the load exceeds the allotted input current from v bus or if the v bus power source is removed. v out should be bypassed with a low impedance multilayer ceramic capacitor. v bus (pin 40): usb input voltage. v bus will usually be connected to the usb port of a computer or a dc output wall adapter. v bus should be bypassed with a low imped- ance multilayer ceramic capacitor. acpr (pin 41): wall adapter present output (active low). a low on this pin indicates that the wall adapter input com- parator has had its input pulled above its input threshold (typically 4.3v). this pin can be used to drive the gate of an external p-channel mosfet to provide power to v out from a power source other than a usb port. extpwr (pin 42): external power present output (active low, open-drain output). a low on this pin indicates that external power is present at either the v bus or wall input. for extpwr to signal v bus present, v bus must exceed the v bus undervoltage lockout threshold. for extpwr to signal wall present, wall must exceed the absolute and differential wall input thresholds. the extpwr signal is independent of the i lim1 and i lim0 pins. thus, it is possible to have the input current limit circuitry in suspend with extpwr showing a valid charging level on v bus . clprog (pin 43): input current program and input current monitor pin. a resistor from clprog to ground determines the upper limit of the current drawn from the v bus pin (i.e., the input current limit). a precise fraction of the input current, h clprog , is sent to the clprog pin. the input powerpath delivers current until the clprog pin reaches 2v (10x mode), 1v (5x mode) or 0.2v (1x mode). therefore, the current drawn from v bus will be limited to an amount given by h clprog and r clprog . in usb applications the resistor r clprog should be set to no less than 2.1k. chrg (pin 44): open-drain charge status output. the chrg pin indicates the status of the battery charger. if chrg is high then the charger is near the ? oat voltage (charge current less than 1/10th programmed charge cur- rent) or charging is complete and charger is disabled. a low on chrg indicates that the charger is enabled. for more information see the charge status indication section. ground (exposed pad pin 45): the exposed package pad is ground and must be soldered to pcb ground for electrical contact and rated thermal performance. pin functions
ltc3577-3/ltc3577-4 19 357734fb block diagram + C 39 + C 15mv v out uvlo ideal diode cc/cv charger external power detect 500ma, 2.25mhz buck regulator 1 input current limit overtemp battery safety discharger overvoltage protecton battery temp monitor i lim logic i 2 c logic 40v led backlight boost converter 0.8v en en pg 500ma, 2.25mhz buck regulator 2 0.8v en pg pg 800ma, 2.25mhz buck regulator 3 0.8v pgood en 0.8v 150ma ldo1 enb 37 idgate 38 bat 32 v in12 36 prog 33 sw1 26 fb1 25 fb2 5 sw3 7 fb3 31 sw2 27 v inld01 6 v in3 28 21 dv cc 10 en3 17 pbstat 16 sw 18,19,20 led_ov 9 ldo1 23 ldo1_fb 0.8v 150ma ldo2 30 v inld02 29 ldo2 24 45 ldo2_fb 357734 bd 230ms falling delay chrg 44 charge status i led 22 led_fs 3 dac 0.8v gnd sda 11 scl 12 pwr_on 14 ntc 35 ntcbias 34 clprog 43 v bus ovsens 40 i lim1 2 i lim0 1 on 15 push- button input 8 ovgate 13 extpwr 42 acpr 41 wall detect wall 4 14ms rising delay + C + C + C + C + C
ltc3577-3/ltc3577-4 20 357734fb operation powerpath operation introduction the ltc3577-3/ltc3577-4 are highly integrated power management ic that includes the following features: C powerpath controller C battery charger C ideal diode C input overvoltage protection C pushbutton controller C three step-down switching regulators C two low dropout linear regulators C 40v led backlight controller designed speci? cally for usb applications, the powerpath controller incorporates a precision input current limit which communicates with the battery charger to ensure that input current does not violate the usb average input current speci? cation. the ideal diode from bat to v out guarantees that ample power is always available to v out even if there is insuf? cient or absent power at v bus . the ltc3577-3/ltc3577-4 also have the ability to receive power from a wall adapter or other non-current-limited power source. such a power supply can be connected to the v out pin of the ltc3577-3/ltc3577-4 through an external device such as a power schottky or fet as shown in figure 1. the ltc3577-3/ltc3577-4 have the unique ability to use the output, which is powered by an external supply, to charge the battery while providing power to the load. a comparator on the wall pin is con? gured to detect the presence of the wall adapter and shut off the connection to the usb. this prevents reverse conduction from v out to v bus when a wall adapter is present. the ltc3577-3/ltc3577-4 also include a pushbutton input to control the power sequencing of two synchronous step-down switching regulators (buck1 and buck2), a low dropout regulator (ldo2) and system reset. the three + C + C + C + C 4.3v (rising) 3.2v (falling) 75mv (rising) 25mv (falling) enable usb current limit constant-current constant-voltage battery charger wall from ac adapter 4 v bus from usb 40 37 + C 15mv idgate bat 357734 f01 li-ion optional external ideal diode pmos bat ideal diode 38 39 v out v out 41 acpr + system load figure 1. simpli? ed powerpath block diagram
ltc3577-3/ltc3577-4 21 357734fb operation 2.25mhz constant frequency current mode step-down switching regulators provide 500ma, 500ma and 800ma each and support 100% duty cycle operation as well as operating in burst mode operation for high ef? ciency at light load. no external compensation components are required for the switching regulators. the two low dropout regulators can output up to 150ma. the onboard led backlight boost circuitry can drive up to 10 series leds and includes versatile digital dimming via the i 2 c input. the i 2 c input also provides additional regulator controls as well as status read-back. all regulators can be programmed for a minimum output voltage of 0.8v and can be used to power a microcon- troller core, microcontroller i/o, memory or other logic circuitry. usb powerpath controller the input current limit and charge control circuits of the ltc3577-3/ltc3577-4 are designed to limit input current as well as control battery charge current as a function of i vout . v out drives the combination of the external load, the three step-down switching regulators, two ldos, led backlight and the battery charger. if the combined load does not exceed the programmed input current limit, v out will be connected to v bus through an internal 200m p-channel mosfet. if the combined load at v out exceeds the programmed input current limit, the battery charger will reduce its charge current by the amount necessary to enable the external load to be satis? ed while maintaining the programmed input current. even if the battery charge current is set to exceed the allowable usb current, the average input current usb speci? cation will not be violated. furthermore, load current at v out will always be prioritized and only excess available cur- rent will be used to charge the battery. the current out of the clprog pin is a fraction (1/h clprog ) of the v bus current. when a programming resistor is connected from clprog to gnd, the voltage on clprog represents the input current: ii v r h vbus busq clprog clprog clprog =+ ? where i busq and h clprog are given in the electrical characteristics table. the input current limit is programmed by the i lim0 and i lim1 pins. the ltc3577-3/ltc3577-4 can be con? gured to limit input current to one of several possible settings as well as be deactivated (usb suspend). the input current limit will be set by the appropriate servo voltage and the resistor on clprog according to the following expression: ii v r h x mode i vbus busq clprog clprog v =+ () 02 1 . ??? b bus busq clprog clprog vbus i v r h x mode i =+ () 1 5 ??? = =+ () i v r h x mode busq clprog clprog 2 10 ??? under worst-case conditions, the usb speci? cation for average input current will not be violated with an r clprog resistor of 2.1k or greater. table 1 shows the available settings for the i lim0 and i lim1 pins: table 1. controlled input current limit i lim1 i lim0 i bus(lim) 1 1 100ma (1x) 1 0 1a (10x) 0 1 suspend 0 0 500ma (5x) notice that when i lim0 is low and i lim1 is high, the input current limit is set to a higher current limit for increased charging and current availability at v out . this mode is typically used when there is a higher power, non-usb source available at the v bus pin.
ltc3577-3/ltc3577-4 22 357734fb operation ideal diode from bat to v out the ltc3577-3/ltc3577-4 have an internal ideal diode as well as a controller for an optional external ideal diode. both the internal and the external ideal diodes respond quickly whenever v out drops below bat. if the load increases beyond the input current limit, additional current will be pulled from the battery via the ideal diodes. furthermore, if power to v bus (usb) or v out (external wall power or high voltage regulator) is removed, then all of the application power will be provided by the battery via the ideal diodes. the ideal diodes are fast enough to keep v out from drop- ping signi? cantly below v bat with just the recommended output capacitor (see figure 2). the ideal diode consists of a precision ampli? er that enables an on-chip p-channel mosfet whenever the voltage at v out is approximately 15mv (v fwd ) below the voltage at bat. the resistance of the internal ideal diode is approximately 200m. if this is suf? cient for the application, then no external components are necessary. however, if lower resistance is needed, an external p-channel mosfet can be added from bat to v out . the idgate pin of the ltc3577-3/ltc3577-4 drives the gate of the external p-channel mosfet for automatic ideal diode control. the source of the mosfet should be connected to v out and the drain should be connected to bat. capable of driving a 1nf load, the idgate pin can control an external p-channel mosfet having extremely low on-resistance. using the wall pin to detect the presence of an external power source the wall input pin can be used to identify the presence of an external power source (particularly one that is not subject to a ? xed current limit like the usb v bus input). typically, such a power supply would be a 5v wall adapter output or the low voltage output of a high voltage buck regulator. when the wall adapter output (or buck regulator output) is connected directly to the wall pin, and the volt- age exceeds the wall pin threshold, the usb power path (from v bus to v out ) will be disconnected. furthermore, the acpr pin will be pulled low. in order for the presence of an external power supply to be acknowledged, both of the following conditions must be satis? ed: 1. the wall pin voltage must exceed approximately 4.3v. 2. the wall pin voltage must be greater than 75mv above the bat pin voltage. the input power path (between v bus and v out ) is re- enabled and the acpr pin is pulled high when either of the following conditions is met: 1. the wall pin voltage falls to within 25mv of the bat pin voltage. 2. the wall pin voltage falls below 3.2v. each of these thresholds is suitably ? ltered in time to prevent transient glitches on the wall pin from falsely triggering an event. suspend mode when i lim0 is pulled high and i lim1 is pulled low the ltc3577-3/ltc3577-4 enters suspend mode to comply with the usb speci? cation. in this mode, the power path between v bus and v out is put in a high impedance state to reduce the v bus input current to 50a. if no other power source is available to drive wall and v out , the system load connected to v out is supplied through the ideal diodes connected to bat. 4.0v 3.8v v out 3.6v 500ma C500ma 0 i bat i vout load 1a 0a 10s/div charge discharge 357734 f02 v bat = 3.8v v bus = 5v 5x mode c out = 10f figure 2. ideal diode transient response
ltc3577-3/ltc3577-4 23 357734fb operation v bus undervoltage lockout (uvlo) and undervoltage current limit (uvcl) an internal undervoltage lockout circuit monitors v bus and keeps the input current limit circuitry off until v bus rises above the rising uvlo threshold (3.8v) and at least 50mv above v out . hysteresis on the uvlo turns off the input current limit if v bus drops below 3.7v or 50mv below v out . when this happens, system power at v out will be drawn from the battery via the ideal diode. to minimize the possibility of oscillation in and out of uvlo when using resistive input supplies, the input current limit is reduced as v bus falls below 4.45v (typ). battery charger the ltc3577-3/ltc3577-4 include a constant-current/ constant-voltage battery charger with automatic recharge, automatic termination by safety timer, low voltage trickle charging, bad cell detection and thermistor sensor input for out of temperature charge pausing. when a battery charge cycle begins, the battery charger ? rst determines if the battery is deeply discharged. if the battery voltage is below v trkl , typically 2.85v, an automatic trickle charge feature sets the battery charge current to 10% of the programmed value. if the low voltage persists for more than 1/2 hour, the battery charger automatically terminates. once the battery voltage is above 2.85v, the battery charger begins charging in full power constant-current mode. the current delivered to the battery will try to reach 1000v/r prog . depending on available input power and external load conditions, the battery charger may or may not be able to charge at the full programmed rate. the external load will always be prioritized over the battery charge current. the usb current limit programming will always be observed and only additional current will be available to charge the battery. when system loads are light, battery charge cur- rent will be maximized. charge termination the battery charger has a built-in safety timer. when the battery voltage approaches the ? oat voltage, the charge current begins to decrease as the ltc3577-3/ltc3577-4 enters constant-voltage mode. once the battery charger detects that it has entered constant voltage mode, the four hour safety timer is started. after the safety timer expires, charging of the battery will terminate and no more current will be delivered. automatic recharge after the battery charger terminates, it will remain off drawing only microamperes of current from the battery. if the portable product remains in this state long enough, the battery will eventually self discharge. to ensure that the battery is always topped off, a charge cycle will automati- cally begin when the battery voltage falls below v rechrg (typically 4.1v for ltc3577-3 and 4v for ltc3577-4). in the event that the safety timer is running when the battery voltage falls below v rechrg , the timer will reset back to zero. to prevent brief excursions below v rechrg from re- setting the safety timer, the battery voltage must be below v rechrg for more than 1.3ms. the charge cycle and safety timer will also restart if the v bus uvlo cycles low and then high (e.g., v bus , is removed and then replaced). charge current the charge current is programmed using a single resistor from prog to ground. 1/1000th of the battery charge cur- rent is delivered to prog which will attempt to servo to 1.000v. thus, the battery charge current will try to reach 1000 times the current in the prog pin. the program resistor and the charge current are calculated using the following equations: r v i i v r prog chg chg prog == 1000 1000 ,?
ltc3577-3/ltc3577-4 24 357734fb operation in either the constant-current or constant-voltage charging modes, the prog pin voltage will be proportional to the actual charge current delivered to the battery. therefore, the actual charge current can be determined at any time by monitoring the prog pin voltage and using the fol- lowing equation: i v r bat prog prog = ? 1000 in many cases, the actual battery charge current, i bat , will be lower than i chg due to limited input current available and prioritization with the system load drawn from v out . thermal regulation to prevent thermal damage to the ic or surrounding components, an internal thermal feedback loop will automatically decrease the programmed charge current if the die temperature rises to approximately 110c. thermal regulation protects the ltc3577-3/ltc3577-4 from excessive temperature due to high power operation or high ambient thermal conditions and allows the user to push the limits of the power handling capability with a given circuit board design without risk of damaging the ltc3577-3/ltc3577-4 or external components. the bene? t of the ltc3577-3/ltc3577-4 thermal regulation loop is that charge current can be set according to actual conditions rather than worst-case conditions with the assurance that the battery charger will automatically reduce the current in worst-case conditions. charge status indication the chrg pin indicates the status of the battery charger. an open-drain output, the chrg pin can drive an indica- tor led through a current limiting resistor for human interfacing or simply a pull-up resistor for microproces- sor interfacing. when charging begins, chrg is pulled low and remains low for the duration of a normal charge cycle. when charging is complete, i.e., the charger enters constant voltage mode and the charge current has dropped to one-tenth of the programmed value, the chrg pin is released (high impedance). the chrg pin does not re- spond to the c/10 threshold if the ltc3577-3/ltc3577-4 are in input current limit. this prevents false end-of-charge indications due to insuf? cient power available to the battery charger. even though charging is stopped during an ntc fault the chrg pin will stay low indicating that charging is not complete. battery charger stability considerations the ltc3577-3/ltc3577-4s battery charger contains both a constant-voltage and a constant-current control loop. the constant-voltage loop is stable without any compen- sation when a battery is connected with low impedance leads. excessive lead length, however, may add enough series inductance to require a bypass capacitor of at least 1f from bat to gnd. furthermore, a 4.7f capacitor in series with a 0.2 to 1 resistor from bat to gnd is required to keep ripple voltage low when the battery is disconnected. high value, low esr multilayer ceramic chip capacitors reduce the constant-voltage loop phase margin, possibly resulting in instability. ceramic capacitors up to 22f may be used in parallel with a battery, but larger ceramics should be decoupled with 0.2 to 1 of series resistance. in constant-current mode, the prog pin is in the feed- back loop rather than the battery voltage. because of the additional pole created by any prog pin capacitance, capacitance on this pin must be kept to a minimum. with no additional capacitance on the prog pin, the battery charger is stable with program resistor values as high as 25k. however, additional capacitance on this node reduces the maximum allowed program resistor. the pole frequency at the prog pin should be kept above 100khz. therefore, if the prog pin has a parasitic capacitance, c prog , the following equation should be used to calculate the maximum resistance value for r prog : r khz c prog prog 1 2 100 ??
ltc3577-3/ltc3577-4 25 357734fb operation ntc thermistor and battery voltage reduction the battery temperature is measured by placing a negative temperature coef? cient (ntc) thermistor close to the bat- tery pack. to use this feature connect the ntc thermistor, r ntc , between the ntc pin and ground and a bias resis- tor, r nom , from ntcbias to ntc. r nom should be a 1% resistor with a value equal to the value of the chosen ntc thermistor at 25c (r25). the ltc3577-3/ltc3577-4 will pause charging when the resistance of the ntc thermistor drops to 0.54 times the value of r25 or approximately 54k (for a vishay curve 1 thermistor, this corresponds to approximately 40c). if the battery charger is in constant voltage (? oat) mode, the safety timer also pauses until the thermistor indicates a return to a valid temperature. as the temperature drops, the resistance of the ntc therm- istor rises. the ltc3577-3/ltc3577-4 are also designed to pause charging when the value of the ntc thermistor increases to 3.25 times the value of r25. for a vishay curve 1 thermistor this resistance, 325k, corresponds to approximately 0c. the hot and cold comparators each have approximately 3c of hysteresis to prevent oscilla- tion about the trip point. the typical ntc circuit is shown in figure 3. to improve safety and reliability the battery voltage is re- duced when the battery temperature becomes excessively high. when the resistance of the ntc thermistor drops to about 0.35 times the value of r25 or approximately 35k (for a vishay curve 1 thermistor, this corresponds to approximately 50c) the ntc enables circuitry to moni- tor the battery voltage. if the battery voltage is above the battery discharge threshold (about 3.9v) then the battery discharge circuitry is enabled and draws about 140ma from the battery when v bus = 0v and about 180ma when v bus = 5v. the battery discharge current is disabled below the battery discharge threshold. when the charger is disabled an internal watchdog timer samples the ntc thermistor for about 150s every 150ms and will enable the battery monitoring circuitry if the bat- tery temperature exceeds the ntc too_hot threshold. if adding a capacitor to the ntc pin for ? ltering the time constant must be much less than 150s so that the ntc pin can settle to its ? nal value during the sampling period. a time constant less than 10s is recommended. once the battery monitoring circuitry is enabled it will remain enabled and monitoring the battery voltage until the battery temperature falls back below the discharge temperature threshold. the battery discharge circuitry is only enabled if the battery voltage is greater than the battery discharge threshold. alternate ntc thermistors and biasing the ltc3577-3/ltc3577-4 provide temperature quali? ed charging if a grounded thermistor and a bias resistor are connected to ntc. by using a bias resistor whose value is equal to the room temperature resistance of the thermis- tor (r25) the upper and lower temperatures are pre-pro- grammed to approximately 40c and 0c, respectively (assuming a vishay curve 1 thermistor). the upper and lower temperature thresholds can be ad- justed by either a modi? cation of the bias resistor value or by adding a second adjustment resistor to the circuit. if only the bias resistor is adjusted, then either the upper or the lower threshold can be modi? ed but not both. the other trip point will be determined by the characteristics of the thermistor. using the bias resistor in addition to an adjustment resistor, both the upper and the lower tempera- ture trip points can be independently programmed with the constraint that the difference between the upper and lower temperature thresholds cannot decrease. examples of each technique are given below. ntc thermistors have temperature characteristics which are indicated on resistance-temperature conversion tables. the vishay-dale thermistor nths0603n011-n1003f, used in the following examples, has a nominal value of 100k and follows the vishay curve 1 resistance-temperature characteristic.
ltc3577-3/ltc3577-4 26 357734fb figure 4. ntc thermistor circuit with additional bias resistor C + C + r nom 105k r ntc 100k r1 12.7k ntc ntcbias 34 0.26 ? ntcbias battery overtemp 357734 f04 ntc block ltc3577-3/ ltc3577-4 too_cold too_hot 0.76 ? ntcbias 0.35 ? ntcbias C + 35 figure 3. typical ntc thermistor circuit operation in the explanation below, the following notation is used. r25 = value of the thermistor at 25c r ntc|cold = value of thermistor at the cold trip point r ntc|hot = value of the thermistor at the hot trip point r cold = ratio of r ntc|cold to r25 r hot = ratio of r ntc|hot to r25 r nom = primary thermistor bias resistor (see figure 3) r1 = optional temperature range adjustment resistor (see figure 4) the trip points for the ltc3577-3/ltc3577-4s temperature quali? cation are internally programmed at 0.35 ? v ntc for the hot threshold and 0.76 ? v ntc for the cold threshold. therefore, the hot trip point is set when: r rr ntcbias ntcbias nom ntc|hot ntc|hot + = ?.? 035 and the cold trip point is set when: r rr ntcbias ntcbia nom ntc|cold ntc|cold + = ?.? 076 s s solving these equations for r ntc|cold and r ntc|hot results in the following: r ntc|hot = 0.538 ? r nom and r ntc|cold = 3.17 ? r nom by setting r nom equal to r25, the above equations result in r hot = 0.538 and r cold = 3.17. referencing these ratios to the vishay resistance-temperature curve 1 chart gives a hot trip point of about 40c and a cold trip point of about 0c. the difference between the hot and cold trip points is approximately 40c. C + C + r nom 100k r ntc 100k ntc ntcbias 34 0.26 ? ntcbias battery overtemp 357734 f03 ntc block ltc3577-3/ ltc3577-4 too_cold too_hot 0.76 ? ntcbias 0.35 ? ntcbias C + 35
ltc3577-3/ltc3577-4 27 357734fb operation by using a bias resistor, r nom , different in value from r25, the hot and cold trip points can be moved in either direc- tion. the temperature span will change somewhat due to the non-linear behavior of the thermistor. the following equations can be used to easily calculate a new value for the bias resistor: r r r r r r nom hot nom cold = = 0 538 25 317 25 . ? . ? where r hot and r cold are the resistance ratios at the desired hot and cold trip points. note that these equations are linked. therefore, only one of the two trip points can be chosen, the other is determined by the default ratios designed in the ic. consider an example where a 60c hot trip point is desired. from the vishay curve 1 r-t characteristics, r hot is 0.2488 at 60c. using the above equation, r nom should be set to 46.4k. with this value of r nom , the cold trip point is about 16c. notice that the span is now 44c rather than the previous 40c. this is due to the decrease in temperature gain of the thermistor as absolute tem- perature increases. the upper and lower temperature trip points can be inde- pendently programmed by using an additional bias resistor as shown in figure 4. the following formulas can be used to compute the values of r nom and r1: r rr r rrr nom cold hot nom hot = = C . ? .? C ? 2 714 25 1 0 536 r r25 for example, to set the trip points to 0c and 45c with a vishay curve 1 thermistor choose: rkk nom == 3 266 0 4368 2 714 100 104 2 .C. . ?. the nearest 1% value is 105k. r1 = 0.536 ? 105k C 0.4368 ? 100k = 12.6k the nearest 1% value is 12.7k. the ? nal solution is shown in figure 4 and results in an upper trip point of 45c and a lower trip point of 0c. overvoltage protection (ovp) the ltc3577-3/ltc3577-4 can protect themselves from the inadvertent application of excessive voltage to v bus or wall with just two external components: an n-channel fet and a 6.2k resistor. the maximum safe overvoltage magnitude will be determined by the choice of the external nmos and its associated drain breakdown voltage. the overvoltage protection module consists of two pins. the ? rst, ovsens, is used to measure the externally applied voltage through an external resistor. the second, ovgate, is an output used to drive the gate pin of an external fet. the voltage at ovsens will be lower than the ovp input voltage by (i ovsens ? 6.2k) due to the ovp circuits quiescent current. the ovp input will be 200mv to 400mv higher than ovsens under normal operating conditions. when ovsens is below 6v, an internal charge pump will drive ovgate to approximately 1.88 ? ovsens. this will enhance the n-channel fet and provide a low impedance connection to v bus or wall which will, in turn, power the ltc3577-3/ltc3577-4. if ovsens should rise above 6v (6.35v ovp input) due to a fault or use of an incorrect wall adapter, ovgate will be pulled to gnd, disabling the external fet to protect downstream circuitry. when the voltage drops below 6v again, the external fet will be re-enabled. in an overvoltage condition, the ovsens pin will be clamped at 6v. the external 6.2k resistor must be sized appropriately to dissipate the resultant power. for example, a 1/10w 6.2k resistor can have at most p max ? 6.2k = 24v applied across its terminals. with the 6v at ovsens, the maximum overvoltage magnitude that this resistor can withstand is 30v. a 1/4w 6.2k resistor raises this value to 45v. the charge pump output on ovgate has limited output drive capability. care must be taken to avoid leakage on this pin, as it may adversely affect operation.
ltc3577-3/ltc3577-4 28 357734fb operation dual input overvoltage protection it is possible to protect both v bus and wall from overvoltage damage with several additional components, as shown in figure 5. schottky diodes d1 and d2 pass the larger of v1 and v2 to r1 and ovsens. if either v1 or v2 exceeds 6v plus v f(schottky) , ovgate will be pulled to gnd and both the wall and usb inputs will be protected. each input is protected up to the drain-source breakdown, bvdss, of mn1 and mn2. r1 must also be rated for the power dissipated during maximum overvoltage. see the overvoltage protection section for an explanation of this calculation. table 2 shows some nmos fets that maybe suitable for overvoltage protection. table 2. recommended overvoltage fets nmos fet bvdss r on package si1472dh 30v 82m sc70-6 si2302ads 20v 60m sot-23 si2306bds 30v 65m sot-23 si2316bds 30v 80m sot-23 irlml2502 20v 35m sot-23 reverse input voltage protection the ltc3577-3/ltc3577-4 can also be easily protected against the application of reverse voltage as shown in figure 6. d1 and r1 are necessary to limit the maximum vgs seen by mp1 during positive overvoltage events. d1s breakdown voltage must be safely below mp1s bvgs. the circuit shown in figure 6 offers forward voltage protection up to mn1s bvdss and reverse voltage protection up to mp1s bvdss. low dropout linear regulator operation ldo operation and voltage programming the ltc3577-3/ltc3577-4 contain two 150ma adjustable output ldo regulators. the ? rst ldo (ldo1) is always on and will be enabled whenever v out is greater than v out uvlo. the second ldo (ldo2) is controlled by the pushbutton and is the ? rst supply to sequence up in re- sponse to pushbutton application. both ldos are disabled when v out is less than v out uvlo and ldo2 is further disabled when the pushbutton circuity is in the power down or power off states. both ldos contain a soft-start function to limit inrush current when enabled. the soft-start function works by ramping up the ldo reference over a 200s period (typical) when the ldo is enabled. figure 5. dual input overvoltage protection c1 d1 r1 mn2 mn1 d2 v1 v2 357734 f05 wall ovgate ltc3577-3/ ltc3577-4 v bus ovsens figure 6. dual polarity voltage protection d1 c1 r2 6.2k r1 500k d1: 5.6v zener mp1: si2323 ds, bvdss = 20v v bus positive protection up to bvdss of mn1 v bus negative protection up to bvdss of mp1 mn1 mp1 usb/wall adapter 357734 f06 v bus ovgate ltc3577-3/ ltc3577-4 ovsens
ltc3577-3/ltc3577-4 29 357734fb operation when disabled all ldo circuitry is powered off leaving only a few nanoamps of leakage current on the ldo sup- ply. both ldo outputs are individually pulled to ground through internal resistors when disabled. the power good status bits of ldo1 and ldo2 are avail- able in i 2 c through the read-back registers pgldo[1] and pgldo[2] for ldo1 and ldo2 respectively. the power good comparators for both ldos are sampled when the i 2 c port receives the correct i 2 c read address. figure 7 shows the ldo application circuit. the full-scale output voltage for each ldo is programmed using a resistor divider from the ldo output (ldo1 or ldo2) connected to the feedback pins (ldo1_fb or ldo2_fb) such that: vv r r ldox =+ ? ? ? ? ? ? 08 1 2 1 .? for stability, each ldo output must be bypassed to ground with a minimum 1f ceramic capacitor (c out ). step-down switching regulator operation introduction the ltc3577-3/ltc3577-4 include three 2.25mhz constant-frequency current mode step-down switching regulators providing 500ma, 500ma and 800ma each. all step-down switching regulators can be programmed for a minimum output voltage of 0.8v and can be used to power a microcontroller core, microcontroller i/o, memory or other logic circuitry. all step-down switching regulators support 100% duty cycle operation (low dropout mode) when the input voltage drops very close to the output voltage and are also capable of burst mode operation for highest ef? ciencies at light loads. burst mode operation is individually selectable for each step-down switching regulator through the i 2 c register bits bk1brst, bk2brst and bk3brst. the step-down switching regulators also include soft-start to limit inrush current when powering on, short-circuit current protection, and switch node slew limiting circuitry to reduce emi radiation. no external compensation components are required for the switch- ing regulators. switching regulators 1 and 2 (buck1 and buck2) are sequenced up and down together through the pushbutton interface (see the pushbutton interface sec- tion for more information), while buck3 has an individual enable pin (en3) that is active when the pushbutton is in the power-up or power-on states. buck3 is disabled in the power down and power off states. it is recommended that the step-down switching regulator input supplies (v in12 and v in3 ) be connected to the system supply pin (v out ). this is recommended because the undervoltage lockout circuit on the v out pin (v out uvlo) disables the step- down switching regulators when the v out voltage drops below the v out uvlo threshold. if driving the step-down switching regulator input supplies from a voltage other than v out the regulators should not be operated outside the speci? ed operating range as operation is not guaranteed beyond this range. figure 7. ldo application circuit 0.8v r1 ldox output c out r2 357734 f07 mp v inldox gnd ldox_fb 1 0 ldox ldoxen
ltc3577-3/ltc3577-4 30 357734fb operation output voltage programming figure 8 shows the step-down switching regulator ap- plication circuit. the full-scale output voltage for each step-down switching regulator is programmed using a resistor divider from the step-down switching regulator output connected to the feedback pins (fb1, fb2 and fb3) such that: vv r r outx =+ ? ? ? ? ? ? 08 1 2 1 .? typical values for r1 are in the range of 40k to 1m. the capacitor c fb cancels the pole created by feedback resis- tors and the input capacitance of the fb pin and also helps to improve transient response for output voltages much greater than 0.8v. a variety of capacitor sizes can be used for c fb but a value of 10pf is recommended for most ap- plications. experimentation with capacitor sizes between 2pf and 22pf may yield improved transient response. 2.25mhz cycle or if the current through the n-channel mosfet synchronous recti? er drops to zero. using this method of operation, the error ampli? er adjusts the peak inductor current to deliver the required output power. all necessary compensation is internal to the step-down switching regulator requiring only a single ceramic output capacitor for stability. at light loads in pulse-skipping mode, the inductor current may reach zero on each pulse which will turn off the n-channel mosfet synchronous recti? er. in this case, the switch node (sw1, sw2 or sw3) goes high impedance and the switch node voltage will ring. this is discontinuous operation, and is normal behavior for a switching regulator. at very light loads in pulse-skipping mode, the step-down switching regulators will automati- cally skip pulses as needed to maintain output regulation. at high duty cycle (v outx approaching v inx ) it is possible for the inductor current to reverse at light loads causing the stepped down switching regulator to operate continu- ously. when operating continuously, regulation and low noise output voltage are maintained, but input operating current will increase to a few milliamps. in burst mode operation, the step-down switching regula- tors automatically switch between ? xed frequency pwm operation and hysteretic control as a function of the load current. at light loads the step-down switching regulators control the inductor current directly and use a hysteretic control loop to minimize both noise and switching losses. while operating in burst mode operation, the output capacitor is charged to a voltage slightly higher than the regulation point. the step-down switching regulator then goes into sleep mode, during which the output capacitor provides the load current. in sleep mode, most of the switching regulators circuitry is powered down, helping conserve battery power. when the output voltage drops below a pre-determined value, the step-down switching regulator circuitry is powered on and another burst cycle begins. the sleep time decreases as the load current increases. beyond a certain load current point (about 1/4 rated output load current) the step-down switching regulators will switch to a low noise constant frequency pwm mode of operation, much the same as pulse-skip- ping operation at high loads. for applications that can tolerate some output ripple at low output currents, burst mode operation provides operating modes the step-down switching regulators include two possible operating modes to meet the noise/power needs of a variety of applications. in pulse-skipping mode, an internal latch is set at the start of every cycle, which turns on the main p-channel mosfet switch. during each cycle, a current comparator compares the peak inductor current to the output of an error ampli? er. the output of the current comparator resets the internal latch, which causes the main p-channel mosfet switch to turn off and the n-channel mosfet synchronous recti? er to turn on. the n-channel mosfet synchronous recti? er turns off at the end of the figure 8. step-down switching regulator application circuit 0.8v r1 l v outx c out c fb r2 357734 f08 mp mn en mode slew v in gnd fbx swx pwm control
ltc3577-3/ltc3577-4 31 357734fb operation better ef? ciency than pulse-skipping at light loads. the step-down switching regulators allow mode transition on-the-? y, providing seamless transition between modes even under load. this allows the user to switch back and forth between modes to reduce output ripple or increase low current ef? ciency as needed. burst mode operation is individually selectable for each step-down switching regulator through the i 2 c register bits bk1brst, bk2brst and bk3brst. shutdown the step-down switching regulators (buck1, buck2 and buck3) are shut down when the pushbutton circuitry is in the power-down or power-off state. step-down switching regulator 3 (buck3) can also be shut down by bringing the en3 input low. in shutdown all circuitry in the step-down switching regulator is disconnected from the switching regulator input supply leaving only a few nanoamps of leakage current. the step-down switching regulator out- puts are individually pulled to ground through internal 10k resistors on the switch pin (sw1, sw2 or sw3) when in shutdown. dropout operation it is possible for a step-down switching regulators input voltage to approach its programmed output voltage (e.g., a battery voltage of 3.4v with a programmed output voltage of 3.3v). when this happens, the pmos switch duty cycle increases until it is turned on continuously at 100%. in this dropout condition, the respective output voltage equals the regulators input voltage minus the voltage drops across the internal p-channel mosfet and the inductor. soft-start operation soft-start is accomplished by gradually increasing the peak inductor current for each step-down switching regulator over a 500s period. this allows each output to rise slowly, helping minimize inrush current required to charge up the switching regulator output capacitor. a soft-start cycle occurs whenever a given switching regulator is enabled. a soft-start cycle is not triggered by changing operating modes. this allows seamless output transition when actively changing between operating modes. slew rate control the step-down switching regulators contain new patent pending circuitry to limit the slew rate of the switch node (sw1, sw2 and sw3). this new circuitry is designed to transition the switch node over a period of a few nanosec- onds, signi? cantly reducing radiated emi and conducted supply noise while maintaining high ef? ciency. since slowing the slew rate of the switch nodes causes ef? ciency loss, the slew rate of the step-down switching regulators is adjustable via the i 2 c registers slewctl1 and slew- ctl2. this allows the user to optimize ef? ciency or emi as necessary with four different slew rate settings. the power up default is the fastest slew rate (highest ef? ciency) set- ting. figures 9 and 10 show the ef? ciency and power loss graph for buck3 programmed for 1.2v and 2.5v outputs. figure 9. v out3 (1.2v) ef? ciency and power loss vs i out3 figure 10. v out3 (2.5v) ef? ciency and power loss vs i out3 i out3 (a) 0.01 efficiency (%) power loss (mw) 60 80 100 100 357734 f09 40 20 50 70 90 30 10 0 10 100 1000 1 0.1 0.001 110 0.1 1000 burst mode operation v in = 3.8v sw[1:0] = 00 01 10 11 i out3 (a) 0.01 0.1 10 1000 efficiency (%) power loss (mw) 60 80 100 100 357734 f10 40 20 50 70 90 30 10 0 10 100 1000 1 0.1 0.01 1 burst mode operation v in = 3.8v sw[1:0] = 00 01 10 11
ltc3577-3/ltc3577-4 32 357734fb operation note that the power loss curves remain fairly constant for both graphs yet changing the slew rate has a larger effect on the 1.2v output ef? ciency. this is mainly because for a given output current the 2.5v output is delivering more than 2x the power than the 1.2v output. ef? ciency will always decrease and show more variation to slew rate as the programmed output voltage is decreased. low supply operation an undervoltage lockout circuit on v out (v out uvlo) shuts down the step-down switching regulators when v out drops below about 2.7v. it is recommended that the step- down switching regulator input supplies (v in12 , v in3 ) be connected to the power path output (v out ) directly. this uvlo prevents the step-down switching regulators from operating at low supply voltages where loss of regula- tion or other undesirable operation may occur. if driving the step-down switching regulator input supplies from a voltage other than the v out pin, the regulators should not be operated outside the speci? ed operating range as operation is not guaranteed beyond this range. inductor selection many different sizes and shapes of inductors are available from numerous manufacturers. choosing the right inductor from such a large selection of devices can be overwhelming, but following a few basic guidelines will make the selection process much simpler. the step-down switching regula- tors are designed to work with inductors in the range of 2.2h to 10h. for most applications a 4.7h inductor is suggested for step-down switching regulators providing up to 500ma of output current while a 3.3h inductor is suggested for step-down switching regulators providing up to 800ma. larger value inductors reduce ripple current, which improves output ripple voltage. lower value induc- tors result in higher ripple current and improved transient response time, but will reduce the available output current. to maximize ef? ciency, choose an inductor with a low dc resistance. for a 1.2v output, ef? ciency is reduced about 2% for 100m series resistance at 400ma load current, and about 2% for 300m series resistance at 100ma load current. choose an inductor with a dc current rating at least 1.5 times larger than the maximum load current to ensure that the inductor does not saturate during normal operation. if output short circuit is a possible condition, the inductor should be rated to handle the maximum peak current speci? ed for the step-down converters. different core materials and shapes will change the size/current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. inductors that are very thin or have a very small volume typically have much higher core and dcr losses, and will not give the best ef? ciency. the choice of which style inductor to use often depends more on the price versus size, performance, and any radiated emi requirements than on what the step-down switching regulators requires to operate. the inductor value also has an effect on burst mode operation. lower inductor values will cause burst mode switching frequency to increase. table 3 shows several inductors that work well with the step-down switching regulators. these inductors offer a good compromise in current rating, dcr and physical size. consult each manufacturer for detailed information on their entire selection of inductors. input/output capacitor selection low esr (equivalent series resistance) ceramic capacitors should be used at both step-down switching regulator outputs as well as at each step-down switching regulator input supply. only x5r or x7r ceramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. a 10f output capacitor is suf? cient for the step-down switching regulator outputs. for good transient response and stability the output capacitor for step-down switching regulators should retain at least 4f of capacitance over operating temperature and bias voltage. each switching regulator input supply should be bypassed with a 2.2f capacitor. consult with capacitor manufacturers for de- tailed information on their selection and speci? cations of ceramic capacitors. many manufacturers now offer very thin (<1mm tall) ceramic capacitors ideal for use in height-restricted designs. table 4 shows a list of several ceramic capacitor manufacturers.
ltc3577-3/ltc3577-4 33 357734fb operation table 4. ceramic capacitor manufacturers avx www.avxcorp.com murata www.murata.com taiyo yuden www.t-yuden.com vishay siliconix www.vishay.com tdk www.tdk.com led backlight/boost operation introduction the led driver uses a constant frequency, current mode boost converter to supply power for up to 10 series leds. as shown in figure 11 the series string of leds is con- nected from the output of the boost converter (boost) to the i led pin. under normal operation the boost converter boost output will be driven to a voltage where the i led pin regulates at approximately 300mv to 400mv. the i led pin is a constant current sink that is programmed via i 2 c led dac register. the led can be further controlled using i 2 c to program brightness levels and soft turn-on/ turn-off effects. see the i 2 c interface section for more information on programming the i led current. the boost converter also includes an overvoltage protection feature to limit the boost output voltage as well as variable slew rate control of the sw pin to reduce emi. led boost operation the led boost converter is designed for very high duty cycle operation and can boost from 3v to 40v out for load currents up to 20ma. the boost converter also features overvoltage protection to protect the output in case of an open circuit in the led string. the overvoltage protection threshold is set by adjusting r1 in figure 11 such that: boost max mv r r led ov () ? ? _ =+ 800 1 10 2 where led_ov is approximately 1.0v. in the case of figure 11 boost(max) is set to 40v for a 10-led string. capacitor c3 provides soft-start, limiting the inrush cur- rent when the boost converter is ? rst enabled. c3 provides feedback to the i led pin. this feedback limits the rise time of output voltage and the inrush current while the output capacitor, c2, is charging. table 3. recommended inductors for step-down switching regulators inductor type l (h) max i dc (a) max dcr () size in mm (l w h) manufacturer db318c d312c de2812c 4.7 3.3 4.7 3.3 4.7 3.3 1.07 1.20 0.79 0.90 1.15 1.37 0.1 0.07 0.24 0.20 0.13* 0.105* 3.8 3.8 1.8 3.8 3.8 1.8 3.6 3.6 1.2 3.6 3.6 1.2 3.0 2.8 1.2 3.0 2.8 1.2 toko www.toko.com cdrh3d16 cdrh2d11 cls4d09 4.7 3.3 4.7 3.3 4.7 0.9 1.1 0.5 0.6 0.75 0.11 0.085 0.17 0.123 0.19 4 4 1.8 4 4 1.8 3.2 3.2 1.2 3.2 3.2 1.2 4.9 4.9 1 sumida www.sumida.com sd3118 sd3112 sd12 sd10 4.7 3.3 4.7 3.3 4.7 3.3 4.7 3.3 1.3 1.59 0.8 0.97 1.29 1.42 1.08 1.31 0.162 0.113 0.246 0.165 0.117* 0.104* 0.153* 0.108* 3.1 3.1 1.8 3.1 3.1 1.8 3.1 3.1 1.2 3.1 3.1 1.2 5.2 5.2 1.2 5.2 5.2 1.2 5.2 5.2 1.0 5.2 5.2 1.0 cooper www.cooperet.com lps3015 4.7 3.3 1.1 1.3 0.2 0.13 3.0 3.0 1.5 3.0 3.0 1.5 coil craft www.coilcraft.com *typical dcr
ltc3577-3/ltc3577-4 34 357734fb operation the boost converter will be operated in either continuous conduction mode, discontinuous conduction mode or pulse-skipping mode depending on the inductor current required for regulation. led constant current sink the led driver uses a precision current sink to regulate the led current up to 20ma. the current sink is programmed via i 2 c led dac register and utilizes a 6-bit 60db expo- nential dac. this dac provides accurate current control from 20a to 20ma with approximately 1db per step for i led(fs) = 20ma. the led current can be approximated by the following equations: ii i led led fs dac led fs = ? ? ? ? ? ? () ??? ?C? ( ?10 3 63 63 ) ) . ? = 08 2 500 v r (1) where dac is the decimal value programmed into the i 2 c led dac register. for example with i led(fs) = 20ma and dac[5:0] = 000000 (0 decimal) i led equates to 20a, while dac[5:0] = 111111 (63 decimal) i led equates to 20ma. as a ? nal example dac[5:0] = 101010 is 42 decimal and equates to i led = 2ma for i led(fs) = 20ma. the dac approximates equation 1 using the nominal values in table 5. the differences between the approximation equation and the table are due to design of the dac using eight linear segments that approximate the exponential function. table 5. led dac codes to output current dac codes output current dac codes output current 0 20.0a 32 668a 1 23.5a 33 786a 2 27.0a 34 903a 3 30.5a 35 1.02ma 4 34.0a 36 1.14ma 5 37.6a 37 1.26ma 6 41.1a 38 1.37ma 7 44.6a 39 1.49ma 8 48.1a 40 1.61ma 9 56.5a 41 1.89ma 10 65.0a 42 2.17ma 11 73.4a 43 2.45ma 12 81.9a 44 2.74ma 13 90.3a 45 3.02ma 14 98.7a 46 3.30ma 15 107a 47 3.58ma 16 116a 48 3.86ma 17 136a 49 4.54ma 18 156a 50 5.22ma 19 177a 51 5.90ma 20 197a 52 6.58ma 21 217a 53 7.26ma 22 237a 54 7.93ma 23 258a 55 8.61ma 24 278a 56 9.29ma 25 327a 57 10.8ma 26 376a 58 12.4ma 27 424a 59 13.9ma 28 473a 60 15.4ma 29 522a 61 17.0ma 30 571a 62 18.5ma 31 620a 63 20.0ma the full-scale led current is set using a resistor (r2 in figure 11) connected between the led_fs pin and ground. typically r2 should be set to 20k to give 20ma of led current at full scale. the resistance may be increased to decrease the current or the resistance may be decreased to increase the led current. the dac has been optimized for best performance at 20ma full scale. the full-scale current may be adjusted but the accuracy of the output current will be degraded the further it is programmed from 20ma. the led_fs pin is current limited and will only source about 80a. this protects the pin and limits the i led current in a case where led_fs is shorted to ground, it is not recommended to program the led cur- rent above 25ma. figure 11. led boost application circuit c2 1f 50v d12 zlls400 c1 22f r1 10m d1 r2 20k l1 10h lps4018-103ml 39 18 boost 19 20 357734 f11 v out 9 led_ov sw sw 3 22 i led_fs i led c3 22nf 50v sw ltc3577-3/ ltc3577-4 d2 d3 d4 d5 d10 d9 d8 d7 d6
ltc3577-3/ltc3577-4 35 357734fb operation led gradation the led driver features an automatic gradation circuit. the gradation circuit ramps the led current up when the led driver is enabled and ramps the current down when the led driver is disabled. the dac is enabled and disabled with the en bit of the i 2 c led control register. the gradation function is automatic when enabling and disabling the led driver; only the gradation speed needs to be programmed to use this function. the gradation speed is set by the gr1 and gr2 bits of the i 2 c led control register which allows transitions times of approximately 15ms, one-half second, one second and two seconds. see the i 2 c interface section for more information. the gradation function allows the leds to turn on and off gradually as opposed to an abrupt step. led pwm vs constant current operation the led driver provides both linear led current mode as well as pwm led current mode. these modes are selected through the md1 and md2 bits of the i 2 c led control register. when both bits are 0 the led boost converter is in constant current (cc) mode and the i led current sink is constant whose value is set by the dac[5:0] bits of the i 2 cled dac register. setting md1 to 0 and md2 to 1 selects the led pwm mode. in this mode the led driver is pulsed using an internally generated pwm signal. the pwm mode may be used to reduce the led intensity for a given programmed current. when dimming via pwm the led driver and boost converter are both turned on and off together. this allows some degree of additional control over the led current, and in some cases may offer a more ef? cient method of dimming since the boost could be operated at an optimal ef? ciency point and pulsed for the desired led intensity. the pwm mode, if enabled, is set up using 3 values, pwmnum [3:0] and pwmden [3:0] in the i 2 c led pwm register and pwmclk, set by pwmc2 and pwmc1 in the i 2 c led control register. duty cycle pwmnum pwmden frequency pwmclk pwmd ? = = e en table 6. pwm clock frequency pwmc2 pwmc1 pwmclk 0 0 8.77khz 0 1 4.39khz 1 0 2.92khz 1 1 2.19khz using the pwm control, a 4-bit internally generated pwm is possible as additional dimming. using these control bits a number of pwm duty cycles and frequencies are available in the 100hz to 500hz range. this range was selected to be below the audio range and above the frequency where the pwm is visible. for example, given pwmc2 = 1, pwmc1 = 0, pwmnum[3:0] = 0111 and pwmden[3:0] = 1100 then the duty cycle will be 58.3% and pwm frequency will be 243hz. if pwmnum is set to 0 then the duty cycle will be 0% and the current sink will effectively be off. if pwmnum is ever programmed to a value larger than pwmden the duty cycle will be 100% and the current sink will effectively be constant. pwmden and pwmnum may both be changed to result in 73 different duty cycle possibilities and 41 dif- ferent pwm frequencies between 8.77khz and 100hz. when pwm mode is enabled a small (2a) standby current source is always enabled on the led pin. the purpose of this is to have some current ? owing in the leds at all times. this helps to reduce the magnitude of the voltage swing on the led pin as the current is pulsed on and off.
ltc3577-3/ltc3577-4 36 357734fb operation fixed boost output setting md1 to 1 and md2 to 0 selects the ? xed high voltage boost mode. this mode can be used to generate output voltages at or greater than v out . when con? gured as a boost converter the i led pin becomes the feedback pin, and the boost will regulate the output voltage such that the voltage on the i led pin is 800mv. figure 12 shows a ? xed 12v output generated using the boost converter in the ? xed high voltage boost mode. any output voltage up to 40v may be programmed by select- ing appropriate values for the r1 and r2 voltage divider from the equation: vv r r boost =+ ? ? ? ? ? ? 08 1 2 1 .? values for r2 should be kept below 24.3k to keep the pole at the i led pin beyond cross over. the boost is designed primarily as a high voltage and high duty cycle converter. when operating with a lower boost ratio, a larger output capacitor, 10f, should be used. op- erating with a very low duty cycle will cause cycle skipping which will increase ripple. to keep the average steady-state inductor current below 300ma the maximum output current is reduced as pro- grammed output voltage increases. the output current available is given by: ima v v boost max out min boost () () ? = 300 note that the maximum boost output current must be set by the minimum v out operating voltage. if the boost converter is allowed to operate down to the v out uvlo then 2.5v must be assumed as the minimum operating v out voltage. inductor selection the led boost converter is designed to work with a 10h inductor. the inductor must be able to handle a peak current of 1a and should have a low esr value for good ef? ciency. table 7 shows several inductors that work well with the led boost converter. these inductors offer a good compromise in current rating, dcr and physical size. consult each manufacturer for detailed information on their entire selection of inductors. figure 12. fixed 12v/75ma boost output application c2 10f 10v d12 zlls400 800mv v ref c1 22f r1 301k r2 21.5k l4 10h lps4018-103ml 39 18 boost 19 20 357734 f12 v out 3 i led_fs 22 i led sw sw 9 led_ov sw ltc3577-3/ ltc3577-4 table 7. recommended inductors for boost switching reguators inductor type l (h) max i dc (a) max dcr () size in mm (l w h) manufacturer lps4018-103 10 1.1 0.200 4.0 4.0 1.8 coil craft www.coilcraft.com db62lcb 10 1.22 0.118 6.2 6.2 2 toko www.toko.com cdrh4d16np-100m 10 1.05 0.155 4.8 4.8 1.8 sumida www.sumida.com sd18-100-r 10 1.28 0.158* 5.2 5.2 1.8 cooper www.cooperet.com *typical
ltc3577-3/ltc3577-4 37 357734fb operation diode selection when boosting to increasingly higher voltages, parasitic capacitance at the switch pin becomes an increasing large component of the switching loses. for this reason it is important to minimize the capacitance on the switch node. the diode selected should be sized to handle the peak inductor current and the average output current. at high boost voltages a diode with the lowest possible junction capacitance will often result in a more ef? cient solution than one with a lower forward drop. i 2 c operation i 2 c interface the ltc3577-3/ltc3577-4 may communicate with a bus master using the standard i 2 c 2-wire interface. the timing diagram shows the relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources, such as the ltc1694 smbus accelerator, are required on these lines. the ltc3577-3/ltc3577-4 are both a slave receiver and slave transmitter. the i 2 c control signals, sda and scl are scaled internally to the dv cc supply. dv cc should be connected to the same power supply as the bus pull-up resistors. the i 2 c port has an undervoltage lockout on the dv cc pin. when dv cc is below approximately 1v, the i 2 c serial port is cleared and registers are set to the default con? gura- tion of all zeros. i 2 c bus speed the i 2 c port is designed to be operated at speeds of up to 400khz. it has built-in timing delays to ensure correct operation when addressed from an i 2 c compliant master device. it also contains input ? lters designed to suppress glitches should the bus become corrupted. i 2 c start and stop conditions a bus master signals the beginning of communications by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. the master may transmit either the slave write or the slave read address. once data is written to the ltc3577-3/ltc3577-4, the master may transmit a stop condition which commands the ltc3577-3/ltc3577-4 to act upon its new command set. a stop condition is sent by the master by transitioning sda from low to high while scl is high. the bus is then free for communication with another i 2 c device. t su, dat t hd, sta t hd, dat sda scl t su, sta t hd, sta t su, sto 357734 td t buf t low t high start condition repeated start condition stop condition start condition t r t f t sp ack ack 123 address wr 456789123456789123456789 00 01 0 01 0 00010010 a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 ack stop start sda scl data byte a data byte b i 2 c timing diagram
ltc3577-3/ltc3577-4 38 357734fb operation i 2 c byte format each byte sent to or received from the ltc3577-3/ltc3577-4 must be 8 bits long followed by an extra clock cycle for the acknowledge bit. the data should be sent to the ltc3577-3/ ltc3577-4 most signi? cant bit (msb) ? rst. i 2 c acknowledge the acknowledge signal is used for handshaking between the master and the slave. when the ltc3577-3/ltc3577-4 are written to (write address), they acknowledge their write address as well as the subsequent two data bytes. when they are read from (read address), the ltc3577-3/ ltc3577-4 acknowledge their read address only. the bus master should acknowledge receipt of information from the ltc3577-3/ltc3577-4. an acknowledge (active low) generated by the ltc3577-3/ ltc3577-4 let the master know that the latest byte of information was received. the acknowledge related clock pulse is generated by the master. the master releases the sda line (high) during the acknowledge clock cycle. the ltc3577-3/ltc3577-4 pull-down the sda line during the write acknowledge clock pulse so that it is a stable low during the high period of this clock pulse. when the ltc3577-3/ltc3577-4 are read from, they re- lease the sda line so that the master may acknowledge receipt of the data. since the ltc3577-3/ltc3577-4 only transmit one byte of data, a master not acknowledging the data sent by the ltc3577-3/ltc3577-4 has no i 2 c speci? c consequence on the operation of the i 2 c port. i 2 c slave address the ltc3577-3/ltc3577-4 respond to a 7-bit address which has been factory programmed to b0001001[r/w]. the lsb of the address byte, known as the read/write bit, should be 0 when writing data to the ltc3577-3/ltc3577-4 and 1 when reading data from it. considering the address an 8-bit word, then the write address is 0x12 and the read address is 0x13. the ltc3577-3/ltc3577-4 will acknowl- edge both its read and write address. i 2 c sub-addressed writing the ltc3577-3/ltc3577-4 have four command registers for control input. they are accessed by the i 2 c port via a sub- addressed writing system. each write cycle of the ltc3577-3/ltc3577-4 consists of exactly three bytes. the ? rst byte is always the ltc3577-3/ ltc3577-4s write address. the second byte represents the ltc3577-3/ltc3577-4s sub-address. the sub address is a pointer which directs the subsequent data byte within the ltc3577-3/ltc3577-4. the third byte consists of the data to be written to the location pointed to by the sub-address. the ltc3577-3/ltc3577-4 contain control registers at only four sub-address locations: 0x00, 0x01, 0x02 and 0x03. writing to sub-addresses outside the four sub-addresses listed is not recommended as it can cause data in one of the four listed sub-addresses to be overwritten. i 2 c bus write operation the master initiates communication with the ltc3577-3/ ltc3577-4 with a start condition and the ltc3577-3/ ltc3577-4s write address. if the address matches that of the ltc3577-3/ltc3577-4, the ltc3577-3/ltc3577-4 return an acknowledge. the master should then deliver the sub-address. again the ltc3577-3/ltc3577-4 ac- knowledge and the cycle is repeated for the data byte. the data byte is transferred to an internal holding latch upon the return of its acknowledge by the ltc3577-3/ ltc3577-4. this procedure must be repeated for each sub-address that requires new data. after one or more cycles of [address][sub-address][data], the master may terminate the communication with a stop condition. alternatively, a repeat-start condition can be initiated by the master and another chip on the i 2 c bus can be addressed. this cycle can continue inde? nitely and the ltc3577-3/ltc3577-4 will remember the last input of valid data that it received. once all chips on the bus have been addressed and sent valid data, a global stop can be sent and the ltc3577-3/ltc3577-4 will update their command latches with the data that they had received.
ltc3577-3/ltc3577-4 39 357734fb operation i 2 c bus read operation the bus master reads the status of the ltc3577-3/ ltc3577-4 with a start condition followed by the ltc3577-3/ltc3577-4 read address. if the read address matches that of the ltc3577-3/ltc3577-4, the ltc3577-3/ ltc3577-4 return an acknowledge. following the acknowl- edgement of their read address, the ltc3577-3/ltc3577-4 return one bit of status information for each of the next 8 clock cycles. a stop command is not required for the bus read operation. i 2 c input data there are 4 bytes of data that can be written to on the ltc3577-3/ltc3577-4. the bytes are accessed through the sub-addresses 0x00 to 0x03. at ? rst power applica- tion (v bus , wall or bat) all bits default to 0. addition- ally all bits are cleared to 0 when dv cc drops below its undervoltage lock out or if the pushbutton enters the power down (pdn) state. table 8 shows the ? rst byte of data that can be written to at sub-address 0x00. this byte of data is referred to as the buck control register. table 8. buck control register buck control register address: 00010010 sub-address: 00000000 bit name function b0 n/a not usedno effect on operation b1 n/a not usedno effect on operation b2 bk1brst buck1 burst mode enable b3 bk2brst buck2 burst mode enable b4 bk3brst buck2 burst mode enable b5 slewctl1 buck sw slew rate: 00 = 1ns, 01 = 2ns, 10 = 4ns, 11 = 8ns b6 slewctl2 b7 n/a not usedno effect on operation bits b2, b3, and b4 set the operating modes of the step- down switching regulators (bucks). writing a 1 to any of these three registers will put that respective buck converter in the high ef? ciency burst mode operation, while a 0 will enable the low noise pulse-skipping mode of operation. the b5 and b6 bits adjust the slew rate of all sw pins together so they all slew at the same rate. it is recom- mended that the fastest slew rate (b6:b5 = 00) be used unless emi is an issue in the application as slower slew rates cause reduced ef? ciency. table 9 shows the second byte of data that can be written to at sub-address 0x01. this byte of data is referred to as the led control register. table 9. i 2 c led control register led control register address: 00010010 sub-address: 00000001 bit name function b0 en enable: 1 = enable 0 = off b1 gr2 gradation gr[2:1]: 00 = 15ms, 01 = 460ms, 10 = 930ms, 11 = 1.85 seconds b2 gr1 b3 md1 mode md[2:1]: 00 = cc boost, 10 = pwm boost; 01 = hv boost, b4 md2 b5 pwmc1 pwm clk pwmc[2:1]: 00 = 8.77khz, 01 = 4.39khz, 10 = 2.92khz, 11 = 2.19khz b6 pwmc2 b7 slewled led sw slew rate: 0/1 = fast/slow bit b0 enables and disables the led boost circuitry. writing a 1 to b0 enables the led boost circuitry, while writing a 0 disables the led boost circuitry. bits b1 and b2 are the led gradation which sets the ramp up and down time of the led current when enabled or disabled. the gradation function allows the leds to turn on/off gradually as opposed to an abrupt step. bits b3 and b4 set the operating mode of the led boost circuitry. the operating modes are: b4:b3 = 00 led con- stant current (cc) boost operation; b4:b3 = 10 led pwm boost operation; b4:b3 = 01 ? xed high voltage (hv) output boost operation; b4:b3 = 11, not supported, do not use. see the led backlight/boost operation section for more information on the operating modes. bits b5 and b6 set the pwm clock speed as shown in table 5 of the led backlight/boost operation section. bit b7 sets the slew rate of the led boost sw pin. setting b7 to 0 results in the fastest slew rate and provides the most ef? cient mode of operation. setting b7 to 1 should only be used in cases where emi due to sw slewing is an issue as the slower slew rate causes a loss in ef? ciency. see the led backlight/boost operation section for more detailed operating information.
ltc3577-3/ltc3577-4 40 357734fb operation table 10 shows the third byte of data that can be written to at sub-address 0x02. this byte of data is referred to as the led dac register. the led current source utilizes a 6-bit 60db exponential dac. this dac provides accurate current control from 20a to 20ma with approximately 1db per step with i led(fs) programmed to 20ma. the led current can be approximated by the following equation: ii led led fs = ? ? ? ? ? ? () ?10 3??? dac?C?63 63 where dac is the decimal value programmed into the i 2 c led dac register. for example with i led(fs) = 20ma and dac[5:0] = 101010 (42 decimal) i led equates to 2ma. table 10. i 2 c led dac register led dac register address: 00010010 sub-address: 00000010 bit name function b0 dac[0] 6-bit log dac code b1 dac[1] b2 dac[2] b3 dac[3] b4 dac[4] b5 dac[5] b6 n/a not usedno effect on operation b7 n/a not usedno effect on operation table 11 shows the ? nal byte of data that can be written to at sub-address 0x03. this byte of data is referred to as the led pwm register. see the led pwm vs constant current operation section for detailed information on how to set the values of this register. table 11. led pwm register led pwm register address: 00010010 sub-address: 00000011 bit name function b0 pwmden[0] pwm denominator b1 pwmden[1] b2 pwmden[2] b3 pwmden[3] b4 pwmnum[0] pwm numerator b5 pwmnum[1] b6 pwmnum[2] b7 pwmnum[3] i 2 c output data one status byte may be read from the ltc3577-3/ltc3577-4 as shown in table 12. a 1 read back in the any of the bit positions indicates that the condition is true. for example, 1 read back from bit a3 indicate that ldo1 is enabled and regulating correctly. a status read from the ltc3577-3/ ltc3577-4 captures the status information when the ltc3577-3/ltc3577-4 acknowledge its read address. table 12. i 2 c read register status register address: 00010011 sub-address: none bit name function a0 charge charge status (1 = charging) a1 stat[0] stat[1:0]; 00 = no fault 01 = too cold/hot 10 = battery overtemp 11 = battery fault a2 stat[1] a3 pgldo[1] ldo1 power good a4 pgldo[2] ldo2 power good a5 pgbck[1] buck1 power good a6 pgbck[2] buck2 power good a7 pgbck[3] buck3 power good bit a7 shows the power good status of buck3. a 1 indicates that buck3 is enabled and is regulating correctly. a 0 indi- cates that either buck3 is not enabled, or that the buck3 is enabled, but is out of regulation by more than 8%. bit a6 shows the power good status of buck2. a 1 indicates that buck2 is enabled and is regulating correctly. a 0 indi- cates that either buck2 is not enabled, or that the buck2 is enabled, but is out of regulation by more than 8%. bit a5 shows the power good status of buck1. a 1 indicates that buck1 is enabled and is regulating correctly. a 0 indi- cates that either buck1 is not enabled, or that the buck1 is enabled, but is out of regulation by more than 8%. bit a4 shows the power good status of ldo2. a 1 indicates that ldo2 is enabled and is regulating correctly. a 0 indi- cates that either ldo2 is not enabled, or that the ldo2 is enabled, but is out of regulation by more than 8%.
ltc3577-3/ltc3577-4 41 357734fb operation bit a3 shows the power good status of ldo1. a 1 indicates that ldo1 is enabled and is regulating correctly. a 0 indi- cates that either ldo1 is not enabled, or that the ldo1 is enabled, but is out of regulation by more than 8%. bits a2 and a1 indicate the fault status of the charger measurement circuit and are decoded in table 12. the too cold/hot state indicates that the thermistor temperature is out of the valid charging range (either below 0c or above 40c for a curve 1 thermistor) and that charging has paused until the battery returns to valid charging temperature. the battery overtemperature state indicates that the batterys thermistor has reached a critical temperature (about 50c for a curve 1 thermistor) and that long-term battery capacity may be seriously compromised if the condition persists. the battery fault state indicates that an attempt was made to charge a low battery (typically < 2.85v) but that the low voltage condition persisted for more than 1/2 hour. in this case charging has terminated. bit a0 indicates the status of the battery charger. a 1 indicates that the charger is enabled and is in the con- stant-current charge state. in this case the battery is being charged unless the ntc thermistor is outside its valid charge range in which case charging is temporarily suspended but not complete. charging will continue once the battery has returned to a valid charging temperature. a 0 in bit a0 indicates that charger has reached end-of- charge (h c/10 ) and is near v float or that charging has been terminated. charging can be terminated by reaching the end of the charge timer or by a battery fault as described previously. i 2 c write register map (see the i 2 c input data section for more details, all registers default to 0 when reset) buck contol register address: 00010010 sub-address: 00000000 bit name function b0 n/a not usedno effect on operation b1 n/a not usedno effect on operation b2 bk1brst buck1 burst mode enable b3 bk2brst buck2 burst mode enable b4 bk3brst buck2 burst mode enable b5 slewctl1 buck sw slew rate: 00 = 1ns, 01 = 2ns, 10 = 4ns, 11 = 8ns b6 slewctl2 b7 n/a not usedno effect on operation led control register address: 00010010 sub-address: 00000001 bit name function b0 en enable: 1= enable 0 = off b1 gr2 gradation gr[2:1]: 00 = 15ms, 01 = 460ms, 10 = 930ms, 11 = 1.85 seconds b2 gr1 b3 md1 mode md[2:1]: 00 = cc boost, 10 = pwm boost, 01 = hv boost b4 md2 b5 pwmc1 pwm clk pwmc[2:1]: 00 = 8.77khz, 01 = 4.39khz, 10 = 2.92khz, 11 = 2.19khz b6 pwmc2 b7 slewled led sw slew rate: 0/1 = fast/slow led dac register address: 00010010 sub-address: 00000010 bit name function b0 dac[0] 6-bit log dac code b1 dac[1] b2 dac[2] b3 dac[3] b4 dac[4] b5 dac[5] b6 n/a not usedno effect on 0peration b7 n/a not usedno effect on 0peration led pwm register address: 00010010 sub-address: 00000011 bit name function b0 pwmden[0] pwm denominator b1 pwmden[1] b2 pwmden[2] b3 pwmden[3] b4 pwmnum[0] pwm numerator b5 pwmnum[1] b6 pwmnum[2] b7 pwmnum[3]
ltc3577-3/ltc3577-4 42 357734fb operation pushbutton interface operation state diagram/operation figure 13 shows the ltc3577-3/ltc3577-4 pushbutton state diagram. upon ? rst application of power (v bus , wall or bat) an internal power-on reset (por) signal places the pushbutton circuitry into the power-off (poff) state. the following events cause the state machine to transition out of poff into the power-up (pup) state: 1) on input low for 50ms (pb50ms) 2) pwr_on input going high (pwr_on) upon entering the pup state, the pushbutton circuitry will sequence up ldo2, buck1 and buck2 in that order. the led backlight is enabled via i 2 c and does not take part in the power-up sequence of the pushbutton. one second after entering the pup state, the pushbutton circuitry will transition into the power-on (pon) state. note that the pwr_on input must be brought high before entering the pon state if the part is to remain in the pon state. buck3 can be enabled through the en3 input once the pushbutton is in the pup or pon states. pwr_on going low, or v out dropping to its undervoltage lockout (v out uvlo) threshold will cause the state machine to leave the pon state and enter the power-down (pdn) state. the pdn state resets the i 2 c registers effectively shutting down the led backlight as well as disabling buck1, buck2 and ldo2 together. buck3 is also disabled in the pdn and poff states. the one second delay before leaving the power-down state allows the supplies to power down completely before they can be re-enabled. pbstat operation pbstat goes low 50ms after the initial pushbutton ap- plication ( on low) and will stay low for 50ms minimum. pbstat will go high coincident with on going high unless on goes high before the 50ms minimum low time. hard reset and pgood operation the hard reset event is generated by pressing and holding the pushbutton ( on input low) for 14 seconds. for a valid hard reset event to occur the initial pushbutton application must start in the pup or pon state. this avoids causing a hard reset from occurring if the user hangs on the push- button during initial power-up. if a valid hard reset event is present then the pgood output will transition low for about 1.8ms to allow the microprocessor to reset. the hard reset event does not affect the operating state or regulator operation. the pgood pin is an open-drain output used to indicate that buck1, buck2 and ldo1 are enabled and have reached their ? nal regulation voltage. a 230ms delay is included from the time buck1, buck2 and ldo1 reach 92% of their regulation value to allow a system controller ample time to reset itself. pgood is an open-drain output and requires a pull-up resistor to an appropriate power source. optimally the pull-up resistor is connected to the output of buck1, buck2 or ldo2 so that power is not dissipated while the regulators are disabled. pushbutton operation and v out uvlo as stated earlier v out dropping to its uvlo threshold will cause the pushbutton to leave the power-on state and enter the power-down state, thus powering down buck1, buck2, buck3, ldo2 and the led backlight. additionally, ldo1 is disabled when in uvlo. thus, all ltc3577-3/ltc3577-4 supplies are disabled and remain disabled as long as the v out uvlo condition exists. it is not possible to power up any of the ltc3577-3/ltc3577-4 generated supplies while v out is below the v out uvlo threshold. figure 13. pushbutton state diagram 1sec por 35773 f13 1sec pb50ms + pwr_on pup pon poff pdn uvlo + pwr_on
ltc3577-3/ltc3577-4 43 357734fb operation power-up via pushbutton timing the timing diagram, figure 14, shows the ltc3577-3/ ltc3577-4 powering up through application of the external pushbutton. for this example the pushbutton circuitry starts in the poff state with v out not in uvlo and buck1, buck2 and ldo2 disabled. pushbutton application ( on low) for 50ms transitions the pushbutton circuitry into the pup state which sequences up ldo2, buck1 and buck2 in that order. pwr_on must be driven high before the 1 second pup period is over to keep supplies up. if pwr_on is low or goes low after the 1 second pup period buck1, buck2, and ldo2 will be shut down together. pgood is asserted once buck1, buck2 and ldo1 are within 8% of their regulation voltage for 230ms. buck3 and led backlight can be enabled and disabled at any time via en3 or i 2 c once in the pup or pon states. the pwr_on input can be driven via a p/c or by one of the sequenced outputs through a high impedance (100k typ). pbstat goes low 50ms after the initial pushbutton application and will stay low for 50ms minimum. pbstat will go high coincident with on going high unless on goes high before the 50ms minimum low time. power-up via pwr_on timing the timing diagram, figure 15, shows the ltc3577-3/ ltc3577-4 powering up by driving pwr_on high. for this example the pushbutton circuitry starts in the poff state with v out not in uvlo and buck1, buck2 and ldo2 disabled. 50ms after pwr_on goes high the pushbutton circuitry transitions into the pup state which sequences up ldo2, buck1 and buck2 in that order. pwr_on must be driven high before the 1 second pup period is over to keep supplies up. if pwr_on is low or goes low after the 1 second pup period buck1, buck2 and ldo2 will be shut down together. pgood is asserted once buck1, buck2 and ld01 are within 8% of their regulation voltage for 230ms. buck3 and led backlight can be enabled and disabled at any time via en3 or i 2 c once in the pup or pon states. powering up via pwr_on is useful for applications containing an always on microcontroller. this allows the microcontroller to power the application up and down for house keeping and other activities outside the users control. v out uvlo pbstat ldo2 buck1 buck2 pgood pwr_on state poff pup pon 35773 f14 on (pb) 50ms 230ms 14ms 1 sec figure 14. power-up via pushbutton v out uvlo pbstat ldo2 buck1 buck2 pgood pwr_on state poff pup pon 35773 f15 on (pb) 1 sec 50ms 14ms 230ms figure 15. power-up via pwr_on
ltc3577-3/ltc3577-4 44 357734fb operation power down via pushbutton timing the timing diagram, figure 16, shows the ltc3577-3/ ltc3577-4 powering down by c/p control. for this ex- ample the pushbutton circuitry starts in the pon state with v out not in uvlo and buck1, buck2 and ldo2 enabled. in this case the pushbutton is applied ( on low) for at least 50ms, which generates a low impedance on the pbstat output. after receiving the pbstat the c/p will drive the pwr_on input low. 50ms after pwr_on goes low the pushbutton circuitry will enter the pdn state. buck1, buck2 and ldo2 are disabled together upon entering the pdn state. after entering the pdn state, a 1 second wait time is initiated before entering the poff state. during this 1 second time on and pwr_on inputs are ignored to allow all ltc3577-3/ltc3577-4 generated supplies to go low. upon entering the pdn state buck3 is disabled and led backlight i 2 c registers are cleared effectively disabling the backlight. the led backlight can be disabled via i 2 c prior to entering the pdn state if desired. holding on low through the 1 second power-down period will not cause a power-up event at end of the 1 second period. the on input must be brought high following the power-down event and then go low again to establish a valid power-up event. v out uvlo power-down timing if v out drops below the v out uvlo threshold, the push- button circuitry will transition from the pon state to the pdn state. buck1, buck2 and ldo2 are disabled together upon entering the pdn state. after entering the pdn state, a 1 second wait time is initiated before entering the poff state. during this 1 second time on and pwr_on inputs are ignored to allow all ltc3577-3/ltc3577-4 generated supplies to go low. upon entering the pdn state the buck3 is disabled and led backlight i 2 c registers are cleared effectively disabling the backlight. ldo1 is also disabled by the v out uvlo and stays disabled as long as the v out uvlo condition remains. note that it is not possible to sequence any of the supplies up while the v out uvlo condition exists. ldo1 will be re-enabled when the v out uvlo condition is removed. the other supplies will remain disabled until a valid power-up pushbutton event takes place. figure 16. power-down via pushbutton v out uvlo pbstat buck1 buck2 ldo2 ldo1 pgood pwr_on state pon pdn poff 35773 f17 on (pb) 1 sec figure 17. v out uvlo power-down v out uvlo pbstat buck1 buck2 ldo2 pgood pwr_on state pon pdn poff 35773 f16 on (pb) 1 sec 50ms c/p control 50ms
ltc3577-3/ltc3577-4 45 357734fb operation hard reset timing hard reset provides a way to reset the c/p in case of a software lockup. to initiate a hard reset, the pushbutton is pressed ( on low) and held for greater than 14 seconds. once the hard reset time is exceeded the pgood input will go low for 1.8ms which resets the c/p . operation of the enabled supplies is not effected by the hard reset event. all enabled supplies should remain in regulation and operating correctly assuming speci? ed operating conditions are met (i.e., no shorted supplies, etc). there are only two methods to power down the ltc3577-3/ ltc3577-4 supplies: 1) pwr_on goes low; 2) v out drops below the v out uvlo threshold. if the c/p controls shutdown by bringing pwr_on low, it is possible that the application can hang with all supplies enabled if the c/p fails to reset correctly on hard reset. in this case the battery will continue to be drained until v out drops below the v out uvlo threshold, or the user intervenes to shut down the application manually. the application can be shut down manually by removing the battery and any external supplies, or by providing a suicide button that will bring pwr_on low when pressed. power-up sequencing figure 19 shows the actual power-up sequencing of the ltc3577-3/ltc3577-4. buck1, buck2 and ldo2 are all ini- tially disabled (0v). once the pushbutton has been applied ( on low) for 50ms pbstat goes low and ldo2 is enabled. once enabled, ldo2 slews up and enters regulation. the actual slew rate is controlled by the soft-start function of ldo2 which ramps the ldo reference up over a 200s period typically. after a 14ms delay from ldo2 being enabled, buck1 is enabled and slews up into regulation. when buck1 is within about 8% of ? nal regulation, buck2 is enabled and slews up into regulation. the bucks also have a soft-start function to limit inrush current at start- up. 230ms after buck2 is within 8% of ? nal regulation, the pgood output will go high impedance (not shown in figure 19). the regulators in figure 19 are slewing up with nominal output capacitors and no load. adding a load or increasing output capacitance on any of the outputs will reduce the slew rate and lengthen the time it takes the regulator to get into regulation. figure 19. power-up sequencing v out uvlo pbstat buck1 buck2 ldo1 pgood pwr_on state pon 35773 f18 on (pb) 50ms 1.8ms >14 sec 14 sec figure 18. hard reset timing 1 0 0v 0v 0v 2ms/div 35773 f19 pbstat buck1 1v/div buck2 2v/div ldo2 1v/div
ltc3577-3/ltc3577-4 46 357734fb operation layout and thermal considerations printed circuit board power dissipation in order to be able to deliver maximum charge current under all conditions, it is critical that the exposed ground pad on the backside of the ltc3577-3/ltc3577-4 pack- age be soldered to a ground plane on the board. correctly soldered to 2500mm 2 ground plane on a double-sided 1oz copper board the ltc3577-3/ltc3577-4 have a thermal resistance ( ja ) of approximately 45c/w. failure to make good thermal contact between the exposed pad on the backside of the package and a adequately sized ground plane will result in thermal resistances far greater than 45c/w. the conditions that cause the ltc3577-3/ltc3577-4 to reduce charge current due to the thermal protection feedback can be approximated by considering the power dissipated in the part. for high charge currents with a wall adapter applied to v out , the ltc3577-3/ltc3577-4 power dissipation is approximately: p d = (v out C bat) ? i bat + p dregs where p d is the total power dissipated, v out is the supply voltage, bat is the battery voltage and i bat is the battery charge current. p dregs is the sum of power dissipated on-chip by the step-down switching, ldo and led boost regulators. the power dissipated by a step-down switching regulator can be estimated as follows: p outx i eff d swx outx () ?? C = () 100 100 where outx is the programmed output voltage, i outx is the load current and eff is the % ef? ciency which can be measured or looked up on an ef? ciency table for the programmed output voltage. the power dissipated on chip by a ldo regulator can be estimated as follows: p dldox = (v inldox C ldox) ? i ldox where ldox is the programmed output voltage, vi nldox is the ldo supply voltage and i ldox is the ldo output load current. note that if the ldo supply is connected to one of the buck output, then its supply current must be added to the buck regulator load current for calculating the buck power loss. the power dissipated by the led boost regulator can be estimated as follows: pi vr i boost v dled led nswon led out =+ ? ? ? ? ?. ? ? C 03 1 ? ? ? 2 where boost is the output voltage driving the top of the led string, r nswon is the on-resistance of the sw n-fet (typically 330m), i led is the led programmed current sink. thus the power dissipated by all regulators is: p dregs = p dsw1 + p dsw2 + p dsw3 + p dldo1 + p dldo2 + p dled it is not necessary to perform any worst-case power dis- sipation scenarios because the ltc3577-3/ltc3577-4 will automatically reduce the charge current to maintain the die temperature at approximately 110c. however, the approximate ambient temperature at which the thermal feedback begins to protect the ic is: t a = 110c C p d ? ja example: consider the ltc3577-3/ltc3577-4 operating from a wall adapter with 5v (v out ) providing 1a (i bat ) to charge a li-ion battery at 3.3v (bat). also assume p dregs = 0.3w, so the total power dissipation is: p d = (5v C 3.3v) ? 1a + 0.3w = 2w the ambient temperature above which the ltc3577-3/ ltc3577-4 will begin to reduce the 1a charge current, is approximately t a = 110c C 2w ? 45c/w = 20c
ltc3577-3/ltc3577-4 47 357734fb operation the ltc3577-3/ltc3577-4 can be used above 20c, but the charge current will be reduced below 1a. the charge current at a given ambient temperature can be approxi- mated by: p ct v bat i p d a ja out bat d regs = = () + 110 C C? () thus: i ct p v bat bat a ja d regs out = () 110 C C C () consider the above example with an ambient temperature of 55c. the charge current will be reduced to approxi- mately: i cc cw w vv i bat bat = = 110 55 45 03 533 122 C / C. C. .C 0 03 17 542 . . w v ma = printed circuit board layout when laying out the printed circuit board, the following list should be followed to ensure proper operation of the ltc3577-3/ltc3577-4: 1. the exposed pad of the package (pin 45) should connect directly to a large ground plane to minimize thermal and electrical impedance. 2. the step-down switching regulator input supply pins (v in12 and v in3 ) and their respective decoupling ca- pacitors should be kept as short as possible. the gnd side of these capacitors should connect directly to the ground plane of the part. these capacitors provide the ac current to the internal power mosfets and their driv- ers. its important to minimizing inductance from these capacitors to the pins of the ltc3577-3/ltc3577-4. connect v in12 and v in3 to v out through a short low impedance trace. 3. the switching power traces connecting sw1, sw2, and sw3 to their respective inductors should be minimized to reduce radiated emi and parasitic coupling. due to the large voltage swing of the switching nodes, sensitive nodes such as the feedback nodes (fbx, ldox_fb and led_ov) should be kept far away or shielded from the switching nodes or poor performance could result. 4. connections between the step-down switching regu- lator inductors and their respective output capacitors should be kept as short as possible. the gnd side of the output capacitors should connect directly to the thermal ground plane of the part. 5. keep the buck feedback pin traces (fb1, fb2, and fb3) as short as possible. minimize any parasitic capacitance between the feedback traces and any switching node (i.e. sw1, sw2, sw3, and logic signals). if necessary shield the feedback nodes with a gnd trace. 6. connections between the ltc3577-3/ltc3577-4 power path pins (v bus and v out ) and their respective decou- pling capacitors should be kept as short as possible. the gnd side of these capacitors should connect directly to the ground plane of the part. 7. the boost converter switching power trace connect- ing sw to the inductor should be minimized to reduce radiated emi and parasitic coupling. due to the large voltage swing of the sw node, sensitive nodes such as the feedback nodes (fbx, ldox_fb and led_ov) should be kept far away or shielded from this switching node or poor performance could result.
ltc3577-3/ltc3577-4 48 357734fb typical applications wall 5v wall adapter acpr ovgate v inldo2 v inldo1 441 30 v out 39 27 10f 13 ovsense 8 v bus prog clprog ldo1 ldo1_fb ldo2 ldo2_fb 40 usb 36 43 dv cc 10 sda scl 11 499k 12 extpwr pbstat 42 16 pwr_on 14 i lim0 1 i lim1 2 24 29 23 28 on 15 10f ltc3577-3/ ltc3577-4 gnd v in3 6 44 2.2f v in12 chrg 37 idgate 38 bat 32 sw 18,19,20 ntcbias 34 ntc 35 2.2f 1k 100k bat 20f 1f 50v v out1 1.8v 500ma li-ion 10h zlls400 v boost 10-led backlight 100k ntc si2333ds v out system load si2333ds (opt) led_ov 9 i led 22 10m 649k led_fs 3 sw1 33 fb1 26 4.7h 20k 2k 2.1k + 806k 10pf 22nf 50v 10f v out2 3.3v 500ma 324k sw2 31 fb2 25 4.7h 1.02m 10pf 10f 1f 1f v out3 1.2v 800ma 464k 464k 100k 324k pushbutton sw3 5 fb3 pgood 7 21 45 3.3h 232k 10pf 1.02m 348k v ldo2 1.4v 150ma v ldo1 3.3v 150ma 10f 35773 ta02 499k 499k dv cc sda scl extpwr pbstat pwr_on kill i lim0 en3 17 en3 i lim1 c/p rst
ltc3577-3/ltc3577-4 49 357734fb typical applications wall 5v wall adapter optional overvoltage/ reverse voltage protection acpr ovgate v inldo1 441 30 v out 39 10f 13 6.2k d3 5.6v r1 500k si2306bds si2333ds ovsense 8 v bus prog clprog ldo1 ldo1_fb ldo2 ldo2_fb 40 usb 36 43 dv cc 10 sda scl 11 499k 12 extpwr pbstat 42 16 pwr_on 14 i lim0 1 i lim1 2 24 29 23 28 on 15 10f ltc3577-3/ ltc3577-4 gnd v in3 6 44 2.2f v in12 chrg 37 idgate 38 bat 32 sw 18,19,20 ntcbias 34 ntc 35 2.2f 1k 100k bat 20f 1f 50v v out1 3.3v 500ma li-ion 10h zlls400 v boost 6-led backlight 100k ntc si2333ds v out system load si2333ds (opt) led_ov 9 i led 22 6m 324k led_fs 3 sw1 33 fb1 26 v inldo2 30 4.7h 20k 2k 2.1k + 1.02m 10pf 22nf 50v 10f v out2 1.8v 500ma 649k sw2 31 fb2 25 4.7h 806k 10pf 10f 1f 1f v out3 1.3v 800ma 649k 464k 100k 470k pushbutton sw3 5 fb3 pgood 7 21 45 3.3h 402k 10pf 1.00m 115k v ldo2 1.0v 150ma v ldo1 2.5v 150ma 10f 35773 ta03 499k 499k dv cc sda scl extpwr pbstat pwr_on kill i lim0 en3 17 en3 i lim1 c/p rst
ltc3577-3/ltc3577-4 50 357734fb package description uff package variation: uffma 44-lead plastic qfn (4mm 7mm) (reference ltc dwg # 05-08-1762 rev ?) 4.00 p 0.10 5.60 ref 6.10 0.05 2.56 0.05 2.64 0.05 1.70 0.05 7.50 0.05 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 43 1 2 44 bottom viewexposed pad 2.40 ref 3.10 0.05 4.50 0.05 7.00 p 0.10 5.60 ref 0.75 p 0.05 0.20 p 0.05 (uff44ma) qfn ref ? 1107 0.40 bsc 0.98 0.10 0.200 ref 0.00 C 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 2.40 ref 2.64 0.10 0.40 p 0.10 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 s 45 o chamfer 2.56 0.10 1.70 0.10 2.76 0.10 0.74 0.10 r = 0.10 typ r = 0.10 typ r = 0.10 typ 0.74 0.10 0.40 bsc package outline 0.20 0.05 2.02 0.05 2.76 0.05 0.98 0.05 1.48 0.05 0.70 0.05
ltc3577-3/ltc3577-4 51 357734fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number b nov 09 changes to features change to absolute maximum ratings add note 16 text changes to pin functions 1 3 10 18 (revision history begins at rev b)
ltc3577-3/ltc3577-4 52 357734fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 1209 rev b ? printed in usa related parts part number description comments ltc3455 dual dc/dc converter with usb power manager and li-ion battery charger seamless transition between input power sources: li-ion battery, usb and 5v wall adapter. two high ef?ciency dc/dc converters: up to 96%. full featured li-ion battery charger with accurate usb current limiting (500ma/100ma). pin selectable burst mode operation. hot swap? output for sdio and memory cards. 24-lead 4mm 4mm qfn package ltc3456 2-cell, multi-output dc/dc converter with usb power manager seamless transition between 2-cell battery, usb and ac wall adapter input power sources. main output: fixed 3.3v output, core output: adjustable from 0.8v to v batt(min) . hot swap output for memory cards. power supply sequencing: main and hot swap accurate usb current limiting. high frequency operation: 1mhz. high ef?ciency: up to 92%. 24-lead 4mm 4mm qfn package ltc3555 i 2 c controlled high ef? ciency usb power manager plus triple step-down dc/dc maximizes available power from usb port, bat-track, instant-on operation, 1.5a max charge current, 180m ideal diode with <50m option, 3.3v/25ma always-on ldo, three synchronous buck regulators, one 1a buck-boost regulator, 4mm 5mm qfn28 package ltc3556 high ef? ciency usb power manager plus dual buck plus buck-boost dc/dc maximizes available power from usb port, bat-track, instant-on operation, 1.5a max charge current, 180m ideal diode with <50m option, 3.3v/25ma always-on ldo, two 400ma synchronous buck regulators, one 1a buck-boost regulator, 4mm 5mm qfn28 package ltc3557/ ltc3557-1 usb power manager with li-ion/polymer charger and triple synchronous buck converter complete multifunction assp: linear power manager and three buck regulaters charge current programmable up to 1.5a from wall adapter input, thermal regulation synchronous buck ef?ciency: >95%, adj outputs: 0.8v to 3.6v at 400ma/400ma/600ma bat-track adaptive output control, 200m ideal diode, 4mm 4mm qfn28 package, -1 version has 4.1v float voltage. ltc3566 switching usb power manager with li-ion/polymer charger, 1a buck-boost converter plus ldo multifunction pmic: switchmode power manager and 1a buck-boost regulator + ldo, charge current programmable up to 1.5a from wall adapter input, thermal regulation synchronous buck-boost converters ef? ciency: >95%, adj output: down to 0.8v at 1a, bat-track adaptive output control, 180m ideal diode, 4mm 4mm qfn24 package ltc3567 switching usb power manager with li-ion/polymer charger, 1a buck-boost converter plus ldo, i 2 c interface multifunction pmic: switchmode power manager and 1a buck-boost + ldo, i 2 c interface, charge current programmable up to 1.5a from wall adapter input, thermal regulation synchronous buck-boost converters ef? ciency: >95%, adj output: down to 0.8v at 1a, bat-track adaptive output control, 180m ideal diode, 4mm 4mm qfn24 package ltc3577/ ltc3577-1 highly integrated protable/navigation pmic complete multifunction pmic: linear power manager and three buck regulators, charge current programmable up to 1.5a from wall adapter input, thermal regulation, synchronous buck converters ef? ciency: >95%, adj outputs: 0.8v to 3.6v at 800ma/ 500ma/500ma, pushbutton control, i 2 c interface, 2 150ma ldos, overvoltage protection bat-track adaptive output control, 200m ideal diode, 4mm 7mm qfn44 package, -1 version has 4.1v float voltage. ltc4085/ ltc4085-1 usb power manager with ideal diode controller and li-ion charger charges single cell li-ion batteries directly from a usb port, thermal regulation, 200m ideal diode with <50m option, 4mm 3mm dfn14 package, -1 version has 4.1v float voltage. ltc4088 high ef?ciency usb power manager and battery charger maximizes available power from usb port, bat-track, instant-on operation, 1.5a max charge current, 180m ideal diode with <50m option, 3.3v/25ma always-on ldo, 4mm 3mm dfn14 package ltc4088-1 high ef? ciency usb power manager and battery charger with regulated output voltage maximizes available power from usb port, bat-track, instant-on operation, 1.5a max charge current, 180m ideal diode with <50m option, automatic charge current reduction maintains 3.6v minimum v out , battery charger disabled when all logic inputs are grounded, 3mm 4mm dfn14 package ltc4088-2 high ef? ciency usb power manager and battery charger with regulated output voltage maximizes available power from usb port, bat-track, instant-on operation, 1.5a max charge current, 180m ideal diode with <50m option, automatic charge current reduction maintains 3.6v minimum v out , 3mm 4mm dfn14 package ltc4098 usb-compatible switchmode power manager with ovp high v in : 38v operating, 60v transient; 66v ovp . maximizes available power from usb port, bat-track, instant-on operation, 1.5a max charge current from wall, 600ma charge current from usb, 180m ideal diode with <50m option; 3mm 4mm ultrathin qfn20 package hot swap is a trademark of linear technology corporation.

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