 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| asahi kasei [ak4642] ms0358-e-00 2004/11 - 1 - general description the ak4642 features a 16-bit stereo codec with a built-in microphone-amplifier, headphone-amplifier and speaker-amplifier. input circuits include a microphone-amplifier and an alc (auto level control) circuit that is suitable for portable application with recording/playback function. the ak4642 is available in a 32pin qfn, utilizing less board space than competitive offerings. features 1. resolution: 16bits 2. recording function ? stereo mic input (full-differential or single-ended) ? stereo line input ? mic amplifier (+32db/+26db/+20db or 0db) ? digital alc (automatic level control) (+36db ? 54db, 0.375db step, mute) ? adc performance: s/(n+d): 83db, dr, s/n: 86db (mic-amp=+20db) s/(n+d): 88db, dr, s/n: 95db (mic-amp=0db) ? wind-noise reduction filter ? stereo separation emphasis 3. playback function ? digital de-emphasis filter (tc=50/15 s, fs=32khz, 44.1khz, 48khz) ? digital volume (+12db ? 115.0db, 0.5db step, mute) ? digital alc (automatic level control) (+36db ? 54db, 0.375db step, mute) ? stereo separation emphasis ? stereo line output - performance: s/(n+d): 88db, s/n: 92db ? stereo headphone-amp - s/(n+d): 70db, s/n: 90db - output power: 15mw@16 ? (hvdd=3.3v) - pop noise free at power on/off ? mono speaker-amp - s/(n+d): 50db@240mw, s/n: 90db - btl output - availbable for both dynamic and piezo speaker - output power: 250mw@8 ? (hvdd=3.3v) 3.0vrms@50 ? (hvdd=5v) ? beep input 4. power management 5. master clock: (1) pll mode ? frequencies: 11.2896mhz, 12mhz, 12.288mhz, 13.5mhz, 24mhz, 27mhz (mcki pin) 1fs (lrck pin) 32fs or 64fs (bick pin) (2) external clock mode ? frequencies: 256fs, 512fs or 1024fs (mcki pin) 6. output master clock frequencies: 32fs/64fs/128fs/256fs 16-bit ? stereo codec with mic/hp/spk-amp ak4642
asahi kasei [ak4642] ms0358-e-00 2004/11 - 2 - 7. sampling rate: ? pll slave mode (lrck pin): 7.35khz 48khz ? pll slave mode (bick pin): 7.35khz 48khz ? pll slave mode (mcki pin): 8khz, 11.025khz, 12khz, 16khz, 22.05khz, 24khz, 32khz, 44.1khz, 48khz ? pll master mode: 8khz, 11.025khz, 12khz, 16khz, 22.05khz, 24khz, 32khz, 44.1khz, 48khz ? ext slave mode: 7.35khz 48khz (256fs), 7.35khz 26khz (512fs), 7.35khz 13khz (1024fs) 8. p i/f: 3-wire serial, i 2 c bus 9. master/slave mode 10. audio interface format: msb first, 2?s compliment ? adc : 16bit msb justified, i 2 s ? dac : 16bit msb justified, 16bit lsb justified, i 2 s 11. ta = ? 40 85 c (spk-amp=off) ? 40 70 c (spk-amp=on) 12. power supply: ? avdd, dvdd: 2.6 3.6v (typ. 3.3v) ? hvdd: 2.6 5.25v (typ. 3.3v/5.0v) 13. package: 32pin qfn (5.2mm x 5.2mm) 14. register upper-compatible with mono codec (ak4536/4630/4631) ? block diagram mic power supply mic-amp a/d wind-noise reduction stereo separation hpf pmadl pmadr pmmp pmadl or pmadr audio i/f d/a datt smute pmdac pmhpl pmhpr internal mic external mic line in line out headphone pmspk speaker alc bass boost pll pmbp pmpll control register mpwr lin1 rin1 lin2 rin2 hpl hpr mutet spp spn hvdd hvss beep avdd avss vcom dvdd csn pdn cclk cdti bick lrck sdto sdti mcko mcki vcoc pmlo lout rout alc dvss stereo separation hpf or i2c figure 1. block diagram asahi kasei [ak4642] ms0358-e-00 2004/11 - 3 - ? ordering guide AK4642VN ? 40 +85 c 32pin qfn (0.4mm pitch) akd4642 evaluation board for ak4642 ? pin layout mutet rout lout beep rin2 / in2 ? lin2 / in2+ lin1 / in1 ? rin1 / in1+ hpl hpr hvss hvdd spp spn mcko mcki mpwr vcom avss avdd vcoc i2c pdn csn / cad0 dvss dvdd bick lrck sdto sdti cdti / sda cclk / scl AK4642VN top view 25 26 27 28 29 30 31 32 24 23 22 1 16 15 14 13 12 11 10 9 21 20 19 18 17 2 3 4 5 6 7 8 asahi kasei [ak4642] ms0358-e-00 2004/11 - 4 - ? comparison with ak4537 function ak4537 ak4642 mic input single-ended single-ended / full-differential stereo mic input 1-input 2-input selectable mic-power 2-output, r l =2k ? (min) 1-output, r l =0.5k ? (min) mic-amp +20db or 0db +32db/+26db/+20db or 0db mic alc +27.5db to ?8db, 0.5db step +36db to ?54db, 0.375db step, mute wind-noise reduction filter n/a available stereo separation emphasis n/a available mono mic mode n/a available alc for playback sp only, +18db to ?8db line/hp/sp, +36db to ?54db datt 0 to ?127db, mute +12 to ?115db, mute bass boost +5.74db/+5.94db/+16.04db@ 20hz +5.76db/+10.80db/+16.06db@20hz dac digital filter stopband attenuation 43db 59db line output level 1.98vpp 1.98vpp/2.50vpp usage for piezo speaker n/a available pll input frequency 11.2896mhz, 12mhz, 12.288mhz 11.2896mhz, 12mhz, 12.288mhz, 13.5mhz, 24mhz, 27mhz p i/f 4-wire/i 2 c(100khz mode) 3-wire/i 2 c(400khz mode) x?tal available n/a mcki ac input available n/a mcki pull-down available n/a analog loopback available n/a mono line output available n/a stereo beep input available n/a power supply (hvdd) 2.4 3.6v 2.6 5.25v package 52pin qfn (7.2mm x 7.2mm) 32pin qfn (5.2mm x 5.2mm) register map no compatibility asahi kasei [ak4642] ms0358-e-00 2004/11 - 5 - ? comparison with ak4631 function ak4631 ak4642 mic input single-ended single-ended / full-differential stereo mic input n/a available adc mono stereo mic alc +27.5db to ?8db, 0.5db step +36db to ?54db, 0.375db step, mute wind-noise reduction filter n/a available stereo separation emphasis n/a available alc for playback sp only, +18db to ?8db line/hp/sp, +36db to ?54db soft mute n/a available bass boost n/a available de-emphasis n/a available dac mono stereo hp-amp n/a available line output mono stereo line output level 1.98vpp 1.98vpp/2.50vpp p i/f 3-wire 3-wire/i 2 c mcki pull-down available n/a analog loopback available n/a dsp mode available n/a package 28pin qfn (5.2mm x 5.2mm) 32pin qfn (5.2mm x 5.2mm) regester map upper-compatible (difference: alc parameter, analog loopback & dsp mode removed) asahi kasei [ak4642] ms0358-e-00 2004/11 - 6 - ? register compatibility with ak4631 ak4631 addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 0 pmvcm pmbp pmspk pmao pmdac pmmic pmadc 01h power management 2 0 0 0 0 m/s mckpd mcko pmpll 02h signal select 1 spps beeps alc2s daca dacm mpwr micad mgain0 03h signal select 2 0 aopsn mgai n1 spkg1 spkg0 beepa alc1m alc1a 04h mode control 1 pll3 pll2 pl l1 pll0 bcko1 bcko0 dif1 dif0 05h mode control 2 0 0 fs3 msbs bckp fs2 fs1 fs0 06h timer select dvtm rotm ztm1 ztm0 wtm1 wtm0 ltm1 ltm0 07h alc mode control 1 0 alc2 alc1 zelm lmat1 lmat0 ratt lmth 08h alc mode control 2 0 ref6 re f5 ref4 ref3 ref2 ref1 ref0 09h input pga control 0 ipga6 ipga 5 ipga4 ipga3 ip ga2 ipga1 ipga0 0ah digital volume control dvol7 dvol6 dvol5 dvol4 dvol3 dvol2 dvol1 dvol0 0bh alc2 mode control 0 0 rfs5 rfs4 rfs3 rfs2 rfs1 rfs0 ak4642 addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 0 pmvcm pmbp pmspk pmlo pmdac 0 pmadl 01h power management 2 0 hpmtn pmhpl pmhpr m/s 0 mcko pmpll 02h signal select 1 sppsn beeps dacs dacl 0 pmmp 0 mgain0 03h signal select 2 lovl lops mgain1 spkg1 spkg0 beepl 0 0 04h mode control 1 pll3 pll2 pll1 pll0 bcko 0 dif1 dif0 05h mode control 2 ps1 ps0 fs3 0 0 fs2 fs1 fs0 06h timer select dvtm 0 ztm1 ztm0 wtm1 wtm0 0 0 07h alc mode control 1 0 0 alc zelmn lmat1 lmat0 rgain0 lmth0 08h alc mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 09h lch input volume control ivl7 ivl6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 0ah lch digital volume control dvl7 dv l6 dvl5 dvl4 dvl3 dvl2 dvl1 dvl0 0bh alc mode control 3 rgain1 lmth1 0 0 0 0 0 0 0ch to 1fh additional function for ak4642 only bits which are not needed for ak4642 asahi kasei [ak4642] ms0358-e-00 2004/11 - 7 - pin/function no. pin name i/o function 1 mpwr o mic power supply pin 2 vcom o common voltage output pin, 0.45 x avdd bias voltage of adc inputs and dac outputs. 3 avss - analog ground pin 4 avdd - analog power supply pin 5 vcoc o output pin for loop filter of pll circuit this pin should be connected to avss with one resistor and capacitor in series. 6 i2c i control mode select pin ?h?: i 2 c bus, ?l?: 3-wire serial 7 pdn i power-down mode pin ?h?: power-up, ?l?: power-down, reset and initializes the control register. csn i chip select pin (i2c pin = ?l?) 8 cad0 i chip address 1 select pin (i2c pin = ?h?) cclk i control data clock pin (i2c pin = ?l?) 9 scl i control data clock pin (i2c pin = ?h?) cdti i control data input pin (i2c pin = ?l?) 10 sda i/o control data input pin (i2c pin = ?h?) 11 sdti i audio serial data input pin 12 sdto o audio serial data output pin 13 lrck i/o input / output channel clock pin 14 bick i/o audio serial data clock pin 15 dvdd - digital power supply pin 16 dvss - digital ground pin 17 mcki i external master clock input pin 18 mcko o master clock output pin 19 spn o speaker amp negative output pin 20 spp o speaker amp positive output pin 21 hvdd - headphone & speaker amp power supply pin 22 hvss - headphone & speaker amp ground pin 23 hpr o rch headphone-amp output pin 24 hpl o lch headphone-amp output pin 25 mutet o mute time constant control pin connected to hvss pin with a capacitor for mute time constant. 26 rout o rch stereo line output pin 27 lout o lch stereo line output pin 28 beep i mono beep signal input pin rin2 i rch analog input 2 pin (mdif2 bit = ?0?) 29 in2 ? i microphone negative input 2 pin (mdif2 bit = ?1?) lin2 i lch analog input 2 pin (mdif2 bit = ?0?) 30 in2+ i microphone positive input 2 pin (mdif2 bit = ?1?) lin1 i lch analog input 1 pin (mdif1 bit = ?0?) 31 in1 ? i microphone negative input 1 pin (mdif1 bit = ?1?) rin1 i rch analog input 1 pin (mdif1 bit = ?0?) 32 in1+ i microphone positive input 1 pin (mdif1 bit = ?1?) note 1. all input pins except analog input pins (beep, lin1, rin1, lin2, rin2) should not be left floating. note 2. avdd or avss voltage should be input to i2c pin. asahi kasei [ak4642] ms0358-e-00 2004/11 - 8 - ? handling of unused pin the unused i/o pins should be processed appropriately as below. classification pin name setting analog mpwr, vcoc, spn, spp, hpr, hpl, mutet, rout, lout, beep, rin2/in2 ? , lin2/in2+, lin1/in1 ? , rin1/in1+ these pins should be open. mcko this pin should be open. digital mcki this pin should be connected to dvss. asahi kasei [ak4642] ms0358-e-00 2004/11 - 9 - absolute maximum ratings (avss, dvss, hvss=0v; note 3) parameter symbol min max units power supplies: analog avdd ? 0.3 6.0 v digital dvdd ? 0.3 6.0 v headphone-amp / speaker-amp hvdd ? 0.3 6.0 v |avss ? dvss| (note 4) ? gnd1 - 0.3 v |avss ? hvss| (note 4) ? gnd2 - 0.3 v input current, any pin except supplies iin - 10 ma analog input voltage (note 5) vina ? 0.3 avdd+0.3 v digital input voltage (note 6) vind ? 0.3 dvdd+0.3 v ambient temperature (powered applied) ta ? 40 85 c storage temperature tstg ? 65 150 c maximum power dissipation ta=85 c (note 8) pd1 - 400 mw (note 7) ta=70 c (note 9) pd2 - 550 mw note 3. all voltages with respect to ground. note 4. avss, dvss and hvss must be connected to the same analog ground plane. note 5. i2c, beep, rin2/in2 ? , lin2/in2+, lin1/in1 ? , rin1/in1+ pins note 6. pdn, csn/cad0, cclk/scl, cdti/sda, sdti, lrck, bick, mcki pins note 7. in case that pcb wiring density is 100%. this power is the ak4642 internal dissipation that does not include power of externally connected speaker and headphone. note 8. speaker-amp is not available. note 9. speaker-amp is available. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, dvss, hvss=0v; note 3) parameter symbol min typ max units power supplies analog avdd 2.6 3.3 3.6 v (note 10) digital dvdd 2.6 3.3 3.6 v hp / spk-amp (note 11) hvdd 2.6 3.3 / 5.0 5.25 v difference avdd ? dvdd ? 0.3 0 +0.3 v note 3. all voltages with respect to ground. note 10. the power-up sequence between avdd, dvdd and hvdd is not critical. when the power supplies are partially powered off, the ak4642 must be reset by bringing pdn pin ?l? after these power supplies are powered on again. note 11. hvdd = 2.6 3.6v when 8 ? dynamic speaker is connected to the ak4642. * akm assumes no responsibility for the usag e beyond the conditions in this datasheet. asahi kasei [ak4642] ms0358-e-00 2004/11 - 10 - analog characteristics (ta=25 c; avdd, dvdd, hvdd=3.3v; avss=dvss=hvss=0v; fs=44.1khz, bick=64fs; signal frequency=1khz; 16bit data; measurement frequency=20hz 20khz; unless otherwise specified) parameter min typ max units mic amplifier: lin1, rin1, lin2, rin2 pins; mdif1 = mdif2 bits = ?0? (single-ended inputs) mgain1-0 bits = ?00? 40 60 80 k ? input resistance mgain1-0 bits = ?01?, ?10?or ?11? 20 30 40 k ? mgain1-0 bits = ?00? - 0 - db mgain1-0 bits = ?01? - +20 - db mgain1-0 bits = ?10? - +26 - db gain mgain1-0 bits = ?11? - +32 - db mic amplifier: in1+, in1 ? , in2+, in2 ? pins; mdif1 = mdif2 bits = ?1? (full-differential input) maximum input voltage (note 12) mgain1-0 bits = ?01? - - 0.228 vpp mgain1-0 bits = ?10? - - 0.114 vpp mgain1-0 bits = ?11? - - 0.057 vpp mic power supply: mpwr pin output voltage (note 13) 2.22 2.47 2.72 v load resistance 0.5 - - k ? load capacitance - - 30 pf adc analog input characteristics: lin1/rin1/lin2/rin2 pins adc ivol, ivol=0db, alc=off resolution - - 16 bits (note 15) 0.168 0.198 0.228 vpp input voltage (note 14) (note 16) 1.68 1.98 2.28 vpp (note 15) 71 83 - dbfs s/(n+d) ( ? 1dbfs) (note 16) - 88 - dbfs (note 15) 76 86 - db d-range ( ? 60dbfs, a-weighted) (note 16) - 95 - db (note 15) 76 86 - db s/n (a-weighted) (note 16) - 95 - db (note 15) 75 90 - db interchannel isolation (note 16) - 100 - db (note 15) - 0.1 0.8 db interchannel gain mismatch (note 16) - 0.1 0.8 db note 12. the voltage difference between in1/2+ and in1/2 ? pins. ac coupling capacitor should be inserted in series at each input pin. full-differential mic input is not available at mgain1-0 bits = ?00?. maximum input voltage of in1+, in1 ? , in2+ and in2 ? pins is proportional to avdd voltage, respectively. vin = 0.069 x avdd (max)@mgain1-0 bits = ?01?, 0.035 x avdd (max)@mgain1-0 bits = ?10?, 0.017 x avdd (max)@mgain1-0 bits = ?11?. when the signal larger than above value is input to in1+, in1 ? , in2+ or in2 ? pin, adc does not operate normally. note 13. output voltage is proportional to avdd voltage. vout = 0.75 x avdd (typ) note 14. input voltage is proportional to avdd voltage. vin = 0.06 x avdd (typ)@mgain1-0 bits = ?01? (+20db), vin = 0.6 x avdd(typ)@mgain1-0 bits = ?00? (0db) note 15. mgain1-0 bits = ?01? (+20db) note 16. mgain1-0 bits = ?00? (0db) asahi kasei [ak4642] ms0358-e-00 2004/11 - 11 - parameter min typ max units dac characteristics: resolution - - 16 bits stereo line output characteristics: dac lout, rout pins, alc=off, ivol=0db, dvol=0db, lovl bit = ?0?, r l =10k ? output voltage (note 17) lovl bit = ?0? 1.78 1.98 2.18 vpp lovl bit = ?1? 2.25 2.50 2.75 vpp s/(n+d) ( ? 3dbfs) 78 88 - dbfs s/n (a-weighted) 82 92 - db interchannel isolation 80 100 - db interchannel gain mismatch - 0.1 0.5 db load resistance 10 - - k ? load capacitance - - 30 pf headphone-amp characteristics: dac hpl/hpr pins, alc=off, ivol=0db, dvol=0db (note 19) 1.58 1.98 2.38 vpp output voltage (note 18) (note 20) 2.40 3.00 3.60 vpp (note 19) 60 70 - dbfs s/(n+d) ( ? 3dbfs) (note 20) - 80 - dbfs (note 19) 80 90 - db s/n (a-weighted) (note 20) - 90 - db (note 19) 65 75 - db interchannel isolation (note 20) - 80 - db (note 19) - 0.1 0.8 db interchannel gain mismatch (note 20) - 0.1 0.8 db (note 19) 20 - - ? load resistance (note 20) 100 - - ? c1 in figure 2 - - 30 pf load capacitance c2 in figure 2 - - 300 pf note 17. output voltage is proportional to avdd voltage. vout = 0.6 x avdd (typ)@lovl bit = ?0?. note 18. output voltage is proportional to avdd voltage. vout = 0.6 x avdd(typ)@hpg bit = ?0?, 0.91 x avdd(typ)@hpg bit = ?1?. note 19. hpg bit = ?0?, hvdd=3.3v, rl=22.8 ? . note 20. hpg bit = ?1?, hvdd=5v, rl=100 ? . hpl/hpr pin hp-amp 47 f c1 16 ? c2 6.8 ? figure 2. headphone-amp output circuit asahi kasei [ak4642] ms0358-e-00 2004/11 - 12 - parameter min typ max units speaker-amp characteristics: dac spp/spn pins, alc=off, ivol=0db, dvol=0db, r l =8 ? , btl, hvdd=3.3v output voltage spkg1-0 bits = ?00?, ? 0.5dbfs 2.49 3.11 3.73 vpp (note 21) spkg1-0 bits = ?01?, ? 0.5dbfs - 3.92 - vpp s/(n+d) spkg1-0 bits = ?00?, ? 0.5dbfs (po=150mw) - 60 - db spkg1-0 bits = ?01?, ? 0.5dbfs (po=240mw) 20 50 - db spkg1-0 bits = ?01?, 0dbfs (po=250mw) - 20 - db s/n (a-weighted) 80 90 - db load resistance 8 - - ? load capacitance - - 30 pf speaker-amp characteristics: dac spp/spn pins, alc=off, ivol=0db, dvol=0db, c l =3 f, r serial =10 ? x 2, r l =50 ? , btl, hvdd=5.0v output voltage spkg1-0 bits = ?10?, 0dbfs - 6.75 - vpp (note 21) spkg1-0 bits = ?11?, 0dbfs 6.80 8.50 10.20 vpp s/(n+d) spkg1-0 bits = ?10?, 0dbfs - 60 - db (note 22) spkg1-0 bits = ?11?, 0dbfs 40 50 - db s/n (a-weighted) 80 90 - db load resistance (note 23) 50 - - ? load capacitance (note 23) - - 3 f beep input: beep pin (external input resistance=20k ? ) maximum input voltage (note 24) - 1.98 - vpp gain (note 25) beep ? lout/rout lovl bit = ?0? ? 4.5 0 +4.5 db lovl bit = ?1? - +2 - db beep ? hpl/hpr hpg bit = ?0? ? 24.5 ? 20 ? 15.5 db hpg bit = ?1? - ? 16.4 - db beep ? spp/spn alc bit = ?0?, spkg1-0 bits = ?00? ? 0.57 +4.43 +8.93 db alc bit = ?0?, spkg1-0 bits = ?01? - +6.43 - db alc bit = ?0?, spkg1-0 bits = ?10? - +10.65 - db alc bit = ?0?, spkg1-0 bits = ?11? - +12.65 - db alc bit = ?1?, spkg1-0 bits = ?00? - +6.43 - db alc bit = ?1?, spkg1-0 bits = ?01? - +8.43 - db alc bit = ?1?, spkg1-0 bits = ?10? - +12.65 - db alc bit = ?1?, spkg1-0 bits = ?11? - +14.65 - db note 21. output voltage is proportional to avdd voltage. vout = 0.94 x avdd(typ)@spkg1-0 bits = ?00?, 1.19 x avdd(typ)@spkg1-0 bits = ?01?, 2.05 x avdd(typ)@spkg1-0 bits = ?10?, 2.58 x avdd(typ)@spkg1-0 bits = ?11? at full-differential output. note 22. in case of measuring at spp and spn pins. note 23. load impedance is total impedance of series resist ance and piezo speaker impedance at 1khz in figure 33. load capacitance is capacitance of piezo speaker. when piezo speaker is used, 10 ? or more series resistors should be connected at both spp and spn pins, respectively. note 24. maximum voltage is in proportion to both avdd and external input resistance (rin). vin = 0.6 x avdd x rin / 20k ? (typ). note 25. the gain is in inverse proportion to external input resistance. asahi kasei [ak4642] ms0358-e-00 2004/11 - 13 - parameter min typ max units power supplies: power-up (pdn pin = ?h?) all circuit power-up: avdd+dvdd (note 26) - 15 23 ma hvdd: hp-amp normal operation no output (note 27) - 5 8 ma hvdd: spk-amp normal operation no output (note 28) - 8 24 ma power-down (pdn pin = ?l?) (note 29) avdd+dvdd+hvdd - 10 100 a note 26. pll master mode (mcki=12.288mhz) and pmadl = pmadr = pmdac = pmlo = pmhpl = pmhpr = pmspk = pmvcm = pmpll = mcko = pmbp = pmmp = m/s bits = ?1?. mpwr pin outputs 0ma. avdd=11ma(typ), dvdd=4ma(typ). ext slave mode (pmpll = m/s = mcko bits = ?0?): avdd=10ma(typ), dvdd=3ma(typ). note 27. pmadl = pmadr = pmdac = pmlo = pmhpl = pmhpr = pmvcm = pmpll = pmbp bits = ?1? and pmspk bit = ?0?. note 28. pmadl = pmadr = pmdac = pmlo = pmspk = pmvcm = pmpll = pmbp bits = ?1? and pmhpl = pmhpr bits = ?0?. note 29. all digital input pins are fixed to dvdd or dvss. asahi kasei [ak4642] ms0358-e-00 2004/11 - 14 - filter characteristics (ta=25 c; avdd, dvdd=2.6 3.6v; hvdd=2.6 5.25v; fs=44.1khz; dem=off; fil1=fil3=eq=off) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 30) 0.16db pb 0 - 17.3 khz ? 0.66db - 19.4 - khz ? 1.1db - 19.9 - khz ? 6.9db - 22.1 - khz stopband sb 26.1 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 73 - - db group delay (note 31) gd - 19 - 1/fs group delay distortion ? gd - 0 - s adc digital filter (hpf): (note 32) frequency response (note 30) ? 3.0db fr - 0.9 - hz ? 0.5db - 2.7 - hz ? 0.1db - 6.0 - hz dac digital filter (lpf): passband (note 30) 0.1db pb 0 - 19.6 khz ? 0.7db - 20.0 - khz ? 6.0db - 22.05 - khz stopband sb 25.2 - - khz passband ripple pr - - 0.01 db stopband attenuation sa 59 - - db group delay (note 31) gd - 22 - 1/fs dac digital filter (lpf) + scf: frequency response: 0 20.0khz fr - 1.0 - db dac digital filter (hpf): (note 32) frequency response (note 30) ? 3.0db fr - 0.9 - hz ? 0.5db - 2.7 - hz ? 0.1db - 6.0 - hz boost filter: (note 33) min 20hz fr - 5.76 - db 100hz - 2.92 - db 1khz - 0.02 - db mid 20hz fr - 10.80 - db 100hz - 6.84 - db 1khz - 0.13 - db max 20hz fr - 16.06 - db 100hz - 10.54 - db frequency response 1khz - 0.37 - db note 30. the passband and stopband frequencies scale with fs (system sampling rate). for example, adc is pb=0.454*fs (@-1.0db). each response refers to that of 1khz. note 31. the calculated delay time caused by digital filtering. this time is from the input of analog signal to setting of the 16-bit data of both channels from the input register to the output register of the adc. this time includes the group delay of the hpf. for the dac, this time is from setting the 16-bit data of both channels from the input register to the output of analog signal. note 32. when pmadl bit = ?1? or pmadr bit = ?1?, the hpf of adc is enabled but the hpf of dac is disabled. when pmadl=pmadr bits = ?0?, pmdac bit = ?1?, the hpf of dac is enabled but the hpf of adc is disabled. note 33. these frequency responses scale with fs. if a high-level and low frequency signal is input, the analog output clips to the full-scale. asahi kasei [ak4642] ms0358-e-00 2004/11 - 15 - dc characteristics (ta=25 c; avdd, dvdd=2.6 3.6v; hvdd=2.6 5.25v) parameter symbol min typ max units high-level input voltage vih 70%dvdd - - v low-level input voltage vil - - 30%dvdd v high-level output voltage (iout= ? 200 a) voh dvdd ? 0.2 - - v low-level output voltage (except sda pin: iout=200 a) vol - - 0.2 v (sda pin: iout=3ma) vol - - 0.4 v input leakage current iin - - 10 a switching characteristics (ta=25 c; avdd, dvdd=2.6 3.6v; hvdd=2.6 5.25v; c l =20pf) parameter symbol min typ max units pll master mode (pll reference clock = mcki pin) mcki input timing frequency fclk 11.2896 - 27 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns mcko output timing frequency fmck 0.2352 - 12.288 mhz duty cycle except 256fs at fs=32khz, 29.4khz dmck 40 50 60 % 256fs at fs=32khz, 29.4khz dmck - 33 - % lrck output timing frequency fs 7.35 - 48 khz duty cycle duty - 50 - % bick output timing period bcko bit = ?0? tbck - 1/(32fs) - ns bcko bit = ?1? tbck - 1/(64fs) - ns duty cycle dbck - 50 - % pll slave mode (pll reference clock = mcki pin) mcki input timing frequency fclk 11.2896 - 27 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns mcko output timing frequency fmck 0.2352 - 12.288 mhz duty cycle except 256fs at fs=32khz, 29.4khz dmck 40 50 60 % 256fs at fs=32khz, 29.4khz dmck - 33 - % lrck input timing frequency fs 7.35 - 48 khz duty duty 45 - 55 % bick input timing period tbck 1/(64fs) - 1/(32fs) ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns asahi kasei [ak4642] ms0358-e-00 2004/11 - 16 - parameter symbol min typ max units pll slave mode (pll reference clock = lrck pin) lrck input timing frequency fs 7.35 - 48 khz duty duty 45 - 55 % bick input timing period tbck 1/(64fs) - 1/(32fs) ns pulse width low tbckl 240 - - ns pulse width high tbckh 240 - - ns pll slave mode (pll reference clock = bick pin) lrck input timing frequency fs 7.35 - 48 khz duty duty 45 - 55 % bick input timing period pll3-0 bits = ?0010? tbck - 1/(32fs) - ns pll3-0 bits = ?0011? tbck - 1/(64fs) - ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns external slave mode mcki input timing frequency 256fs fclk 1.8816 - 12.288 mhz 512fs fclk 3.7632 - 13.312 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck input timing frequency 256fs fs 7.35 - 48 khz 512fs fs 7.35 - 26 khz 1024fs fs 7.35 - 13 khz duty duty 45 - 55 % bick input timing period tbck 312.5 - - ns pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns audio interface timing master mode bick ? ? to lrck edge (note 34) tmblr ? 40 - 40 ns lrck edge to sdto (msb) (except i 2 s mode) tlrd ? 70 - 70 ns bick ? ? to sdto tbsd ? 70 - 70 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns slave mode lrck edge to bick ? ? (note 34) tlrb 50 - - ns bick ? ? to lrck edge (note 34) tblr 50 - - ns lrck edge to sdto (msb) (except i 2 s mode) tlrd - - 80 ns bick ? ? to sdto tbsd - - 80 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns note 34. bick rising edge must not occur at the same time as lrck edge. asahi kasei [ak4642] ms0358-e-00 2004/11 - 17 - parameter symbol min typ max units control interface timing (3-wire serial mode) cclk period tcck 200 - - ns cclk pulse width low tcckl 80 - - ns pulse width high tcckh 80 - - ns cdti setup time tcds 40 - - ns cdti hold time tcdh 40 - - ns csn ?h? time tcsw 150 - - ns csn ? ? to cclk ? ? tcss 50 - - ns cclk ? ? to csn ? ? tcsh 50 - - ns control interface timing (i 2 c bus mode): scl clock frequency fscl - - 400 khz bus free time between transmissions tbuf 1.3 - - s start condition hold time (prior to first clock pulse) thd:sta 0.6 - - s clock low time tlow 1.3 - - s clock high time thigh 0.6 - - s setup time for repeated start condition tsu:sta 0.6 - - s sda hold time from scl falling (note 35) thd:dat 0 - - s sda setup time from scl rising tsu:dat 0.1 - - s rise time of both sda and scl lines tr - - 0.3 s fall time of both sda and scl lines tf - - 0.3 s setup time for stop condition tsu:sto 0.6 - - s pulse width of spike noise suppressed by input filter tsp 0 - 50 ns power-down & reset timing pdn pulse width (note 36) tpd 150 - - ns pmadl or pmadr ? ? to sdto valid (note 37) tpdv - 1059 - 1/fs note 35. data must be held long enough to bridge the 300ns-transition time of scl. note 36. the ak4642 can be reset by the pdn pin = ?l?. note 37. this is the count of lrck ? ? from the pmadl or pmadr bit = ?1?. purchase of asahi kasei microsystems co., ltd i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system, provided the system conform to the i 2 c specifications defined by philips. asahi kasei [ak4642] ms0358-e-00 2004/11 - 18 - ? timing diagram lrck 1/fclk mcki tclkh tclkl vih vil 1/fmck mcko tmckl 50%dvdd 1/fs tlrckh tlrckl 50%dvdd duty = tlrckh x fs x 100 tlrckl x fs x 100 dmck = tmckl x fmck x 100 figure 3. clock timing (pll master mode) lrck 50%dvdd bick 50%dvdd sdto 50%dvdd tbsd tsds sdti vil tsdh vih tblr tbckl tdlr figure 4. audio interface timing (pll master mode) asahi kasei [ak4642] ms0358-e-00 2004/11 - 19 - 1/fclk mcki tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil tlrckh tlrckl fmck mcko tmckl 50%dvdd dmck = tmckl x fmck x 100 duty = tlrckh x fs x 100 = tlrckl x fs x 100 figure 5. clock timing (pll slave mode; pll reference clock = mcki pin) 1/fclk mcki tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil tlrckh tlrckl duty = tlrckh x fs x 100 tlrckl x fs x 100 figure 6. clock timing (ext slave mode) asahi kasei [ak4642] ms0358-e-00 2004/11 - 20 - lrck vih vil tblr bick vih vil tlrd sdto 50%dvdd tlrb tbsd tsds sdti vil tsdh vih msb figure 7. audio interface timing (pll/ext slave mode) asahi kasei [ak4642] ms0358-e-00 2004/11 - 21 - csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil c1 c0 r/w tcck figure 8. write command input timing csn vih vil tcsh cclk vih vil cdti vih tcsw vil d1 d0 d2 figure 9. write data input timing stop start start stop thigh thd:dat sda scl tbuf tlow tr tf tsu:dat vih vil thd:sta tsu:sta vih vil tsu:sto tsp figure 10. i 2 c bus mode timing asahi kasei [ak4642] ms0358-e-00 2004/11 - 22 - pmadl bit or pmadr bit tpdv sdto 50%dvdd figure 11. power down & reset timing 1 tpd pdn vil figure 12. power down & reset timing 2 asahi kasei [ak4642] ms0358-e-00 2004/11 - 23 - operation overview ? system clock there are the following four clock modes to interface with external devices (see table 1 and table 2). mode pmpll bit m/s bit pll3-0 bits figure pll master mode 1 1 see table 4 figure 13 pll slave mode 1 (pll reference clock: mcki pin) 1 0 see table 4 figure 14 pll slave mode 2 (pll reference clock: lrck or bick pin) 1 0 see table 4 figure 15 ext slave mode 0 0 x figure 16 don?t care (note 38) 0 1 x - note 38. if this mode is selected, the invalid clocks are output from mcko pin when mcko bit is ?1?. table 1. clock mode setting (x: don?t care) mode mcko bit mcko pin mcki pin bick pin lrck pin 0 ?l? pll master mode 1 selected by ps1-0 bits selected by pll3-0 bits output (selected by bcko bit) output (1fs) 0 ?l? pll slave mode (pll reference clock: mcki pin) 1 selected by ps1-0 bits selected by pll3-0 bits input (selectet by bcko bit) input (1fs) pll slave mode (pll reference clock: lrck or bick pin) 0 ?l? gnd input (selected by bcko bit) input (1fs) ext slave mode 0 ?l? selected by fs3-0 bits input ( 32fs) input (1fs) table 2. clock pins state in clock mode ? master mode/slave mode the m/s bit selects either master or slave mode. m/s bit = ?1? selects master mode and ?0? selects slave mode. when the ak4642 is power-down mode (pdn pin = ?l?) and exits reset state, the ak4642 is slave mode. after exiting reset state, the ak4642 goes to master mode by changing m/s bit = ?1?. when the ak4642 is used by master mode, lrck and bick pins are a floating state until m/s bit becomes ?1?. lrck and bick pins of the ak4642 should be pulled-down or pulled-up by the resistor (about 100k ? ) externally to avoid the floating state. m/s bit mode 0 slave mode default 1 master mode table 3. select master/salve mode asahi kasei [ak4642] ms0358-e-00 2004/11 - 24 - ? pll mode when pmpll bit is ?1?, a fully integrated analog phase locked loop (pll) generates a clock that is selected by the pll3-0 and fs3-0 bits. the pll lock time is shown in table 4, whenever the ak4642 is supplied to a stable clocks after pll is powered-up (pmpll bit = ?0? ?1?) or sampling frequency changes. 1) setting of pll mode r and c of vcoc pin mode pll3 bit pll2 bit pll1 bit pll0 bit pll reference clock input pin input frequency r[ ? ] c[f] pll lock time (max) 0 0 0 0 0 lrck pin 1fs 6.8k 220n 160ms default 1 0 0 0 1 n/a - - - - 2 0 0 1 0 bick pin 32fs 10k 4.7n 2ms 10k 10n 4ms 3 0 0 1 1 bick pin 64fs 10k 4.7n 2ms 10k 10n 4ms 4 0 1 0 0 mcki pin 11.2896mhz 10k 4.7n 40ms 5 0 1 0 1 mcki pin 12.288mhz 10k 4.7n 40ms 6 0 1 1 0 mcki pin 12mhz 10k 4.7n 40ms 7 0 1 1 1 mcki pin 24mhz 10k 4.7n 40ms 12 1 1 0 0 mcki pin 13.5mhz 10k 10n 40ms 13 1 1 0 1 mcki pin 27mhz 10k 10n 40ms others others n/a table 4. setting of pll mode (*fs: sampling frequency) 2) setting of sampling frequency in pll mode when pll2 bit is ?1? (pll reference clock input is mcki pin), the sampling frequency is selected by fs3-0 bits as defined in table 5. mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency 0 0 0 0 0 8khz default 1 0 0 0 1 12khz 2 0 0 1 0 16khz 3 0 0 1 1 24khz 4 0 1 0 0 7.35khz 5 0 1 0 1 11.025khz 6 0 1 1 0 14.7khz 7 0 1 1 1 22.05khz 10 1 0 1 0 32khz 11 1 0 1 1 48khz 14 1 1 1 0 29.4khz 15 1 1 1 1 44.1khz others others n/a table 5. setting of sampling frequency at pll2 bit = ?1? and pmpll bit = ?1? when pll2 bit is ?0? (pll reference clock input is lrck or bick pin), the sampling frequency is selected by fs3 and fs1-0 bits. (see table 6). fs2 bit is ?don?t care?. mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency range 0 0 don?t care 0 0 7.35khz fs 8khz default 1 0 don?t care 0 1 8khz < fs 12khz 2 0 don?t care 1 0 12khz < fs 16khz 3 0 don?t care 1 1 16khz < fs 24khz 6 1 don?t care 1 0 24khz < fs 32khz 7 1 don?t care 1 1 32khz < fs 48khz others others n/a table 6. setting of sampling frequency at pll2 bit = ?0? and pmpll bit = ?1? asahi kasei [ak4642] ms0358-e-00 2004/11 - 25 - ? pll unlock state 1) pll master mode (pmpll bit = ?1?, m/s bit = ?1?) in this mode, lrck and bick pins go to ?l? and irregular frequency clock is output from mcko pins at mcko bit is ?1? before the pll goes to lock state after pmpll bit = ?0? ? ?1?. if mcko bit is ?0?, mcko pin goes to ?l? (see table 7). after the pll is locked, a first period of lrck and bick may be invalid clock, but these clocks return to normal state after a period of 1/fs. when sampling frequency is changed, bick and lrck pins do not output irregular frequency clocks but go to ?l? by setting pmpll bit to ?0?. mcko pin pll state mcko bit = ?0? mcko bit = ?1? bick pin lrck pin after that pmpll bit ?0? ? ?1? ?l? output invalid ?l? output ?l? output pll unlock (except above case) ?l? output invalid invalid invalid pll lock ?l? output see table 9 see table 10 1fs output table 7. clock operation at pll master mode (pmpll bit = ?1?, m/s bit = ?1?) 2) pll slave mode (pmpll bit = ?1?, m/s bit = ?0?) in this mode, an invalid clock is output from mcko pin before the pll goes to lock state after pmpll bit = ?0? ? ?1?. after that, the clock selected by table 9 is output from mcko pin when pll is locked. adc and dac output invalid data when the pll is unlocked. for dac, the output signal should be muted by writing ?0? to dacl, dach and dacs bits. mcko pin pll state mcko bit = ?0? mcko bit = ?1? after that pmpll bit ?0? ? ?1? ?l? output invalid pll unlock ?l? output invalid pll lock ?l? output output table 8. clock operation at pll slave mode (pmpll bit = ?0?, m/s bit = ?0?) asahi kasei [ak4642] ms0358-e-00 2004/11 - 26 - ? pll master mode (pmpll bit = ?1?, m/s bit = ?1?) when an external clock (11.2896mhz, 12mhz, 12.288mhz, 13.5mhz, 24mhz or 27mhz) is input to mcki pin, the mcko, bick and lrck clocks are generated by an internal pll circuit. the mcko output frequency is selected by ps1-0 bits (see table 9) and the output is enabled by mcko bit. the bick output frequency is selected among 32fs or 64fs, by bcko bit (see table 10). a k4642 dsp or p mcko bick lrck sdto sdti bclk lrck sdti sdto mcki 1fs 32fs, 64fs 256fs/128fs/64fs/32fs 11.2896mhz, 12mhz, 12.288mhz 13.5mhz, 24mhz, 27mhz mclk figure 13. pll master mode mode ps1 bit ps0 bit mcko pin 0 0 0 256fs default 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs table 9. mcko output frequency (pll mode, mcko bit = ?1?) bcko bit bick output frequency 0 32fs default 1 64fs table 10. bick output frequency at master mode asahi kasei [ak4642] ms0358-e-00 2004/11 - 27 - ? pll slave mode (pmpll bit = ?1?, m/s bit = ?0?) a reference clock of pll is selected among the input clocks to mcki, bick or lrck pin. the required clock to the ak4642 is generated by an internal pll circuit. input frequency is selected by pll3-0 bits (see table 4). a) pll reference clock: bick or lrck pin sampling frequency corresponds to 7.35khz to 48khz by changing fs3-0 bits (see table 6). a k4642 dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto mcko 1fs 32fs, 64fs figure 14. pll slave mode 1 (pll reference clock: lrck or bick pin) b) pll reference clock: mcki pin bick and lrck inputs should be synchronized with mcko output. the phase between mcko and lrck dose not matter. mcko pin outputs the frequency selected by ps1-0 bits (see table 9) and the output is enabled by mcko bit. sampling frequency can be selected by fs3-0 bits (see table 5). a k4642 dsp or p mcko bick lrck sdto sdti bclk lrck sdti sdto mcki 1fs 32fs 11.2896mhz, 12mhz, 12.288mhz 13.5mhz, 24mhz, 27mhz mclk 256fs/128fs/64fs/32fs figure 15. pll slave mode 2 (pll reference clock: mcki pin) the external clocks (mcki, bick and lrck) should always be present whenever the adc or dac is in operation (pmadl bit = ?1?, pmadr bit = ?1? or pmdac bit = ?1?) . if these clocks are not provided, the ak4642 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. if the external clocks are not present, the adc and dac should be in the power-down mode (pmadl=pmadr=pmdac bits = ?0?). asahi kasei [ak4642] ms0358-e-00 2004/11 - 28 - ? ext slave mode (pmpll bit = ?0?, m/s bit = ?0?) when pmpll bit is ?0?, the ak4642 becomes ext mode. master clock is input from mcki pin, the internal pll circuit is not operated. this mode is compatible with i/f of the normal audio codec. the clocks required to operate are mcki (256fs, 512fs or 1024fs), lrck (fs) and bick ( 32fs). the master clock (mcki) should be synchronized with lrck. the phase between these clocks does not matter. the input fre quency of mcki is selected by fs1-0 bits (see table 11). mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 don?t care 0 0 256fs 7.35khz 48khz default 1 don?t care 0 1 1024fs 7.35khz 13khz 2 don?t care 1 0 256fs 7.35khz 48khz 3 don?t care 1 1 512fs 7.35khz 26khz others others n/a n/a table 11. mcki frequency at ext slave mode (pmpll bit = ?0?, m/s bit = ?0?) the s/n of the dac at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. the out-of-band noise can be improved by using higher frequency of the master clock. the s/n of the dac output through lout/rout pins at fs=8khz is shown in table 12. mcki s/n (fs=8khz, 20khzlpf + a-weighted) 256fs 83db 512fs 93db 1024fs 93db table 12. relationship between mcki and s/n of lout/rout pins the external clocks (mcki, bick and lrck) should always be present whenever the adc or dac is in operation (pmadl bit = ?1?, pmadr bit = ?1? or pmdac bit = ?1?) . if these clocks are not provided, the ak4642 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. if the external clocks are not present, the adc and dac should be in the power-down mode (pmadl=pmadr=pmdac bits = ?0?). a k4642 dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto mcko 1fs 32fs mclk 256fs, 512fs or 1024fs figure 16. ext slave mode asahi kasei [ak4642] ms0358-e-00 2004/11 - 29 - ? system reset upon power-up, the ak4642 should be reset by bringing the pdn pin = ?l?. this ensures that all internal registers reset to their initial values. the adc enters an initialization cycle that starts when the pmadl or pmadr bit is changed from ?0? to ?1? at pmdac bits is ?0?. the initialization cycle time is 1059/fs=24ms@ fs=44.1khz. during the initialization cycle, the adc digital data outputs of both channels are forced to a 2's compliment, ?0?. the adc output reflects the analog input signal after the initialization cycle is complete. when pmdac bit is ?1?, the adc does not require an initialization cycle. the dac enters an initialization cycle that starts when the pmdac bit is changed from ?0? to ?1? at pmadl and pmadr bits are ?0?. the initialization cycle time is 1059/ fs=24ms@fs=44.1khz. during the initialization cycle, the dac input digital data of both channels are internally forced to a 2's compliment, ?0?. the dac output reflects the digital input data after the in itialization cycle is comp lete. when pmadc or pmadr bit is ?1?, the dac does not require an initialization cycle. ? audio interface format three types of data formats are available and are selected by setting the dif1-0 bits (seetable 13). in all modes, the serial data is msb first, 2?s complement format. audio interface formats can be used in both master and slave modes. lrck and bick are output from the ak4642 in master mode, but must be input to the ak4642 in slave mode. the sdto is clocked out on the falling edge (? ?) of bick and the sdti is latched on the rising edge (? ?). mode dif1 bit dif0 bit sdto (adc) sdti (dac) bick figure 0 0 0 n/a n/a n/a - 1 0 1 msb justified msb justified 32fs figure 17 2 1 0 msb justified msb justified 32fs figure 18 default 3 1 1 i 2 s compatible i 2 s compatible 32fs figure 19 table 13. audio interface format if 16-bit data that adc outputs is converted to 8-bit data by removing lsb 8-bit, ? ? 1? at 16bit data is converted to ? ? 1? at 8-bit data. and when the dac playbacks this 8-bit data, ? ? 1? at 8-bit data will be converted to ? ? 256? at 16-bit data and this is a large offset. this offset can be removed by addi ng the offset of ?128? to 16-bit data before converting to 8-bit data. lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 110 13 13 23 7 76543 210 6543 10 2 9 1112131415 0 12 3 15 14 13 1 0 15 15 76543 210 10 9 1112131415 bick(64fs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 13 don't care 10 1 15 15 210 15 0 15 14 15 14 don't care 15:msb, 0:lsb lch data rch data 15 14 13 76543 10 2 15 14 13 10 figure 17. mode 1 timing asahi kasei [ak4642] ms0358-e-00 2004/11 - 30 - lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 110 13 13 23 7 76543 210 6543 10 2 9 1112131415 0 12 3 15 14 13 1 0 15 15 76543 210 10 9 1112131415 bick(64fs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 13 don't care 1 15 15 15 0 15 14 15 14 don't care 15:msb, 0:lsb lch data rch data 13 10 13 10 15 15 14 13 76543 10 2 15 14 13 10 figure 18. mode 2 timing lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 110 23 7 76543 210 6543 10 2 9 1112131415 0 12 3 15 14 1 0 76543 210 10 9 1112131415 bick(64fs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 don't care 2 15 1 15 15 15 don't care 15:msb, 0:lsb lch data rch data 14 21 14 21 8 8 8 0 0 0 0 0 15 14 76543 210 8 15 14 21 0 figure 19. mode 3 timing ? mono/stereo mode pmadl and pmadr bits set mono/stereo adc operation. pmadl bit pmadr bit adc lch data adc rch data 0 0 all ?0? all ?0? default 0 1 rch input signal rch input signal 1 0 lch input signal lch input signal 1 1 lch input signal rch input signal table 14. mono/stereo adc operation asahi kasei [ak4642] ms0358-e-00 2004/11 - 31 - ? digital high pass filter the adc has a digital high pass filter for dc offset can cellation. the cut-off freque ncy of the hpf is 0.9hz (@fs=44.1khz) and scales with sampling rate (fs). when pmadl bit = ?1? or pmadr bit = ?1?, the hpf of adc is enabled but the hpf of dac is disabled. when pmadl=pmadr bits = ?0?, pmdac bit = ?1?, the hpf of dac is enabled but the hpf of adc is disabled. ? mic/line input selector the ak4642 has input selector. when mdif1 and mdif2 bits are ?0?, inl and inr bits select lin1/lin2 and rin1/rin2, respectively. when mdif1 and mdif2 bits ar e ?1?, lin1, rin1, lin2 and rin2 pins become in1 ? , in1+, in2+ and in2 ? pins respectively. in this case, full-differential input is available (figure 21). mdif1 bit mdif2 bit inl bit inr bit lch rch 0 lin1 rin1 default 0 1 lin1 rin2 0 lin2 rin1 0 1 1 lin2 rin2 0 x lin1 in2+/ ? 0 1 1 x n/a n/a 0 n/a n/a 0 x 1 in1+/ ? rin2 1 1 x x in1+/ ? in2+/ ? table 15. mic/line in path select lin1/in1 ? pin a dc lch rin1/in1+ pin inl bit mdif1 bit rin2/in2 ? pin a dc rch lin2/in2+ pin inr bit mdif2 bit ak4642 figure 20. mic/line input selector asahi kasei [ak4642] ms0358-e-00 2004/11 - 32 - in1 ? pin in1+ pin mpwr pin ak4642 mic-amp 1k 1k figure 21. connection example for full-differential mic input (mdif1/2 bits = ?1?) ? mic gain amplifier the ak4642 has a gain amplifier for microphone input. the gain of mic-amp is selected by the mgain1-0 bits (see table 16). the typical input impedance is 60k ? (typ)@mgain1-0 bits = ?00? or 30k ? (typ)@mgain1-0 bits = ?01?, ?10? or ?11?. mgain1 bit mgain0 bit input gain 0 0 0db 0 1 +20db default 1 0 +26db 1 1 +32db table 16. mic input gain ? mic power when pmmp bit = ?1?, the mpwr pin supplies power for the microphone. this output voltage is typically 0.75 x avdd and the load resistance is minimum 0.5k ? . in case of using two sets of stereo mic, the load resistance is minimum 2k ? for each channel. no capacitor must not be connected directly to mpwr pin (see figure 22). pmmp bit mpwr pin 0 hi-z default 1 output table 17. mic power mpwr pin 2k ? mic power microphone lin1 pin microphone rin1 pin microphone lin2 pin microphone rin2 pin 2k ? 2k ? 2k ? figure 22. mic block circuit asahi kasei [ak4642] ms0358-e-00 2004/11 - 33 - ? digital eq/hpf/lpf the ak4642 performs wind-noise reduction filter, stereo separation emphasis, gain compensation and alc (automatic level control) by digital domain for a/d converted data (figure 23). fil1, fil3 and eq blocks are iir filters of 1 st order. the filter coefficient of fil3, eq and fil1 blocks can be set to any value. refer to the section of ?alc operation? about alc. when only dac is powered-up, digital eq/hpf/lpf circuit operates at playback path. when only adc is powered-up or both adc and dac are powered-up, digital eq/hpf/lpf circuit operates at recording path. even if the path is switched from recording to playback, the register setting of filter coefficient at recording remains. therefore, fil3, eq, fil1 and gn1-0 bits should be set to ?0? if digital eq/hpf/lpf is not used for playback path. pmadl bit, pmadr bit pmdac bit loop bit status digital eq/hpf/lpf 0 x power-down power-down default ?00? 1 x playback playback path 0 x recording recording path 0 recording & playback recording path ?01?, ?10? or ?11? 1 1 recording monitor playback recording path note 39. stereo separation emphasis circuit is effective only at stereo operation. table 18. digital eq/hpf/lpf cirtcuit setting (x: don?t care) fil3 coefficient also sets the attenuation of the stereo separation emphasis. the combination of gn1-0 bit (table 19) and eq coefficient set the compensation gain. fil1 and fil3 blocks become hpf when f1as and f3as bits are ?0? and become lpf when f1as and f3as bits are ?1?, respectively. when eq and fil1 bits are ?0?, eq and fil1 blocks become ?through? (0db). when fil3 bit is ?0?, fil3 block become ?mute?. when each filter coefficient is changed, each filter should be set to ?through? (?mute? in case of fil3). mix lch fil1 fil3 + att eq gain alc lch mix rch fil1 eq gain alc rch fil3 + att any coefficient f1a13-0 f1b13-0 f1as any coefficient f3a13-0 f3b13-0 f3as any coefficient eqa15-0 eqb13-0 eqc15-0 +12db 0db 0db -10db mute (set by fil3 coefficient) gn1-0 +24/+12/0db wind-noise reduction stereo separation emphasis gain compensation figure 23. digital eq/hpf/lpf gn1 gn0 gain 0 0 0db default 0 1 +12db 1 x +24db table 19. gain select of gain block (x: don?t care) asahi kasei [ak4642] ms0358-e-00 2004/11 - 34 - [filter coefficient setting] 1) when fil1 and fil2 are set to ?hpf? fs: sampling frequency fc: cut-off frequency f: input signal frequency k: filter gain [db] (filter gain of should be set to 0db.) register setting fil1: f1as bit = ?0?, f1a[13:0] bits =a, f1b[13:0] bits =b fil3: f3as bit = ?0?, f3a[13:0] bits =a, f3b[13:0] bits =b (msb=f1a13, f1b13, f3a13, f3b13; lsb=f1a0, f1b0, f3a0, f3b0) a = 10 k/20 x 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function amplitude phase h(z) = a 1 ? z ? 1 1 + bz ? 1 m(f) = a 2 ? 2cos (2 f/fs) 1 + b 2 + 2bcos (2 f/fs) (f) = tan ? f/fs) 1 - b + (b ? 1)cos (2 f/fs) 2) when fil1 and fil2 are set to ?lpf? fs: sampling frequency fc: cut-off frequency f: input signal frequency k: filter gain [db] (filter gain of fil1 should be set to 0db.) register setting fil1: f1as bit = ?1?, f1a[13:0] bits =a, f1b[13:0] bits =b fil3: f3as bit = ?1?, f3a[13:0] bits =a, f3b[13:0] bits =b (msb=f1a13, f1b13, f3a13, f3b13; lsb=f1a0, f1b0, f3a0, f3b0) a = 10 k/20 x 1 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function amplitude phase h(z) = a 1 + z ? 1 1 + bz ? 1 m(f) = a 2 + 2cos (2 f/fs) 1 + b 2 + 2bcos (2 f/fs) (f) = tan ? ? 1)sin (2 f/fs) 1 + b + (b+1)cos (2 f/fs) asahi kasei [ak4642] ms0358-e-00 2004/11 - 35 - 3) eq fs: sampling frequency fc 1 : pole frequency fc 2 : zero-point frequency f: input signal frequency k: filter gain [db] (maximum +12db) register setting eqa[15:0] bits =a, eqb[13:0] bits =b, eqc[15:0] bits =c (msb=eqa15, eqb13, eqc15; lsb=eqa0, eqb0, eqc0) a = 10 k/20 x 1 + 1 / tan ( fc 2 /fs) 1 + 1 / tan ( fc 1 /fs) b = 1 ? 1 / tan ( fc 1 /fs) 1 + 1 / tan ( fc 1 /fs) , c =10 k/20 x 1 ? 1 / tan ( fc 2 /fs) 1 + 1 / tan ( fc 1 /fs) , transfer function amplitude phase h(z) = a + cz ? 1 1 + bz ? 1 m(f) = a 2 + c 2 + 2accos (2 f/fs) 1 + b 2 + 2bcos (2 f/fs) (f) = tan ? ? c)sin (2 f/fs) a + bc + (ab+c)cos (2 f/fs) [translation the filter coefficient calculated by the equations above from real number to binary code (2?s complement)] x = (real number of filter coefficient calculated by the equations above) x 2 13 x should be rounded to integer, and then should be translated to binary code (2?s complement). msb of each filter coefficient setting register is sine bit. [filter coefficient setting example] 1) fil1 block example: hpf, fs=44.1khz, fc=100hz f1as bit = ?0? f1a[13:0] bits = 01 1111 1100 0110 f1b[13:0] bits = 10 0000 0111 0100 2) eq block example: fs=44.1khz, fc 1 =300hz, fc 2 =3000hz, gain=+8db gain[db] +8db fc 1 fc 2 frequency eqa[15:0] bits = 0000 1001 0110 1110 eqb[13:0] bits = 10 0001 0101 1001 eqc[15:0] bits = 1111 1001 1110 1111 asahi kasei [ak4642] ms0358-e-00 2004/11 - 36 - ? alc operation the alc (automatic level control) is done by alc block wh en alc bit is ?1?. when only dac is powered-up, alc circuit operates at playback path. when only adc is powered-up or both adc and dac are powered-up, alc circuit operates at recording path. pmadl bit, pmadr bit pmdac bit loop bit status alc 0 x power-down power-down default ?00? 1 x playback playback path 0 x recording recording path 0 recording & playback recording path ?01?, ?10? or ?11? 1 1 recording monitor playback recording path table 20. alc setting (x: don?t care) 1. alc limiter operation during the alc limiter operation, when either lch or rch exceeds the alc limiter detection level (table 21), the ivl and ivr values (same value) are attenuated automatically by the amount defined by the alc limiter att step (table 22). the ivl and ivr are then set to the same value for both channels. when zelmn bit = ?0? (zero cro ss detection is enabled), the ivl and ivr values are cha nged by alc li miter operation at the individual zero crossing points of lch and rch or at the zero crossing timeout. ztm1-0 bits set the zero crossing timeout period of both alc limiter and recovery operation (table 23). when zelmn bit = ?1? (zero cross detection is disabled), ivl and ivr values are immediatel y (period: 1/fs ) changed by alc limiter operation. attenuation step is fixed to 1 step regardless as the setting of lmat1-0 bits. the attenuation operation is done continuously until the input signal level becomes alc limiter detection level (table 21) or less. after completing the attenuation operation, unless alc bit is changed to ?0?, the operation repeats when the input signal level exceeds lmth1-0 bits. lmth1 lmth0 alc limier detection level alc recovery waiting counter reset level 0 0 alc output ? 2.5dbfs ? 2.5dbfs > alc output ? 4.1dbfs default 0 1 alc output ? 4.1dbfs ? 4.1dbfs > alc output ? 6.0dbfs 1 0 alc output ? 6.0dbfs ? 6.0dbfs > alc output ? 8.5dbfs 1 1 alc output ? 8.5dbfs ? 8.5dbfs > alc output ? 12dbfs table 21. alc limiter detection level / recovery counter reset level zelmn lmat1 lmat0 alc limiter att step 0 0 1 step default 0 1 2 step 1 0 4 step 0 1 1 8 step 1 x x 1step table 22. alc limiter att step zero crossing timeout period ztm1 ztm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms default 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 23. alc zero crossing timeout period asahi kasei [ak4642] ms0358-e-00 2004/11 - 37 - 2. alc recovery operation the alc recovery operation waits for the wtm1-0 bits (table 24) to be set after completing the alc limiter operation. if the input signal does not exceed ?alc recovery waiting counter reset level? (table 21) during the wait time, the alc recovery operation is done. the ivl and ivr values are automatically incremented by rgain1-0 bits (table 25) up to the set reference level (table 26) with zero crossing detection which timeout period is set by ztm1-0 bits (table 23). then the ivl and ivr are set to the same value for both channels. the alc recovery operation is done at a period set by wtm1-0 bits. when zero cross is detected at both channels during the wait period set by wtm1-0 bits, the alc recovery operation waits until wtm1-0 period and the next recovery operation is done. for example, when the current ivol value is 30h and rgain1-0 bits are set to ?01?, ivol is changed to 32h by the auto limiter operation and then the input signal level is gained by 0.75db (=0.375db x 2). when the ivol value exceeds the reference level (ref7-0), the ivol values are not increased. when ?alc recovery waiting counter reset level (lmth1-0) output signal < alc limiter detection level (lmth1-0)? during the alc recovery operation, the waiting timer of alc recovery operation is reset. when ?alc recovery waiting counter reset level (lmth1-0) > output signal?, the waiting timer of alc recovery operation starts. the alc operation corresponds to the impulse noise. when the impulse noise is input, the alc recovery operation becomes faster than a normal recovery operation. when large noise is input to microphone instantaneously, the quality of small level in the large noise can be improved by this fast recovery operation. alc recovery operation waiting period wtm1 wtm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms default 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 24. alc recovery operation waiting period rgain1 rgain0 gain step 0 0 1 default 0 1 2 1 0 3 1 1 4 table 25. alc recovery gain step ref7-0 gain(db) f1h +36.0 f0h +35.625 efh +35.25 : : e2h +30.375 e1h +30.0 default e0h +29.625 : : 03h -53.25 02h -53.625 01h -54.0 00h mute table 26. reference level at alc recovery operation asahi kasei [ak4642] ms0358-e-00 2004/11 - 38 - 3. example of alc operation table 27 shows the examples of the alc setting for mic recording. fs=8khz fs=44.1khz register name comment data operation data operation lmth limiter detection level 01 ? 4.1dbfs 01 ? 4.1dbfs zelmn limiter zero crossing de tection 0 enable 0 enable ztm1-0 zero crossing timeout period 00 16ms 10 11.6ms wtm1-0 recovery waiting period *wtm1-0 bits should be the same data as ztm1-0 bits 00 16ms 10 11.6ms ref7-0 maximum gain at recovery operation e1h +30db e1h +30db ivl7-0, ivr7-0 gain of ivol e1h +30db e1h +30db lmat1-0 limiter att step 00 1 step 00 1 step rgain1-0 recovery gain step 00 1 step 00 1 step alc alc enable 1 enable 1 enable table 27. example of the alc setting the following registers should not be changed during the alc operation. these bits should be changed after the alc operation is finished by alc bit = ?0? or pmadl=pmadr bits = ?0?. ? lmth, lmat1-0, wtm1-0, ztm1-0, rgain1-0, ref7-0, zelmn manual mode * the value of ivol should be the same or smaller than ref?s wr (ztm1-0, wtm1-0) wr (ref7-0) wr (ivl/r7-0) wr (lmat1-0, rgain0, zelmn, lmth0; alc= ?1?) example: limiter = zero crossing enable recovery cycle = 16ms@8khz limiter and recovery step = 1 maximum gain = +30.0db limiter detection level = ? 4.1dbfs alc bit = ?1? (1) addr=06h, data=00h (2) addr=08h, data=e1h (5) addr=07h, data=01h (3) addr=09h&0ch, data=e1h alc operation wr (rgain1, lmth1) (4) addr=0bh, data=00h note : wr : write figure 24. registers set-up sequence at alc operation asahi kasei [ak4642] ms0358-e-00 2004/11 - 39 - ? input digital volume (manual mode) the input digital volume becomes a manual mode when alc bit is ?0?. this mode is used in the case shown below. 1. after exiting reset state, set-up the registers for the alc operation (ztm1-0, lmth and etc) 2. when the registers for the alc operation (limiter period, recovery period and etc) are changed. for example; when the change of the sampling frequency. 3. when ivol is used as a manual volume. ivl7-0 and ivr7-0 bits set the gain of the volume control (table 28). the ivol value is changed at zero crossing or timeout. zero crossing timeout period is set by ztm1-0 bits. if ivl7-0 or ivr7-0 bits are written during pmadl=pmadr bits = ?0?, ivol operation starts with the written values at the end of the adc initialization cycle after pmadl or pmadr bit is changed to ?1?. even if the path is switched from recording to playback, th e register setting of ivol remains. therefore, ivl7-0 and ivr7-0 bits should be set to ?91h? (0db). ivl7-0 ivr7-0 gain (db) f1h +36.0 f0h +35.625 efh +35.25 : : e2h +30.375 e1h +30.0 default e0h +29.625 : : 03h ? 53.25 02h ? 53.625 01h ? 54 00h mute table 28. input digital volume setting asahi kasei [ak4642] ms0358-e-00 2004/11 - 40 - when writing to the ivl7-0 and ivr7-0 bits continuouslly, the control register should be written by an interval more than zero crossing timeout. if not, ivl and ivr are not changed since zero crossing counter is reset at every write operation. if the same register value as the previous write operation is written to ivl and ivr, this write operation is ignored and zero crossing counter is not reset. therefore, ivl and ivr can be written by an interval less than zero crossing timeout. a lc bit a lc status disable enable disable ivl7-0 bits e1h(+30db) ivr7-0 bits c6h(+20db) internal ivl e1h(+30db) e1(+30db) --> f1(+36db) e1(+30db) internal ivr c6h(+20db) e1(+30db) --> f1(+36db) c6h(+20db) (1) (2) figure 25. ivol value during alc operation (1) the ivl value becomes the start value if the ivl and ivr are different when the alc starts. (2) writing to iv l and ivr registers (09h and 0ch) is ignored during alc operation. after alc is disabled, the ivol changes to the last written data by zero crossing or timeout. asahi kasei [ak4642] ms0358-e-00 2004/11 - 41 - ? de-emphasis filter the ak4642 includes the digital de-emphasis filter (tc = 50/15 s) by iir filter. setting the dem1-0 bits enables the de-emphasis filter (table 29). dem1 dem0 mode 0 0 44.1khz 0 1 off default 1 0 48khz 1 1 32khz table 29. de-emphasis control ? bass boost function the bst1-0 bits control the amount of low frequency boost applied to the dac output signal (table 30). if the bst1-0 bits are set to ?01? (min level), use a 47 f capacitor for ac-coupling. if the boosted signal exceeds full scale, the analog output clips to the full scale. figure 26 shows th e boost frequency response at ?20db signal input. boost filter (fs=44.1khz) -5 0 5 10 15 20 10 100 1000 10000 frequency [hz] level [db] max mid min figure 26. bass boost frequency response (fs=44.1khz) bst1 bst0 mode 0 0 off default 0 1 min 1 0 mid 1 1 max table 30. bass boost control asahi kasei [ak4642] ms0358-e-00 2004/11 - 42 - ? digital output volume the ak4642 has a digital output volume (256 levels, 0.5db step, mute). the volume can be set by the dvl7-0 and dvr7-0 bits. the volume is included in front of a dac block. the input data of dac is changed from +12 to ?115db or mute. when the dvolc bit = ?1?, the dvl7-0 bits control both lch and rch attenuation levels. when the dvolc bit = ?0?, the dvl7-0 bits control lch level and dvr7-0 bits control rch level. this volume has a soft transition function. the dvtm bit sets the transition time between set values of dvl/r7-0 bits as either 1061/fs or 256/fs (table 32). when dvtm bit = ?0?, a soft transition between the set values occurs (1062 levels). it takes 1061/fs (=24ms@fs=44.1khz) from 00h (+12db) to ffh (mute). dvl/r7-0 gain 00h +12.0db 01h +11.5db 02h +11.0db : : 18h 0db default : : fdh ? 114.5db feh ? 115.0db ffh mute ( ? ) table 31. digital volume code table transition time between dvl/r7-0 bits = 00h and ffh dvtm bit setting fs=8khz fs=44.1khz 0 1061/fs 133ms 24ms default 1 256/fs 32ms 6ms table 32. transition time setting of digital output volume asahi kasei [ak4642] ms0358-e-00 2004/11 - 43 - ? soft mute soft mute operation is performed in the digital domain. when the smute bit goes to ?1?, the output signal is attenuated by ? (?0?) during the cycle set by the dvtm bit. when the smute bit is returned to ?0?, the mute is cancelled and the output attenuation gradually changes to the value set by the dvl/r7-0 bits during the cycle set of the dvtm bit. if the soft mute is cancelled within the cycle set by the dvtm bit after starting the operation, the attenuation is discontinued and returned to the value set by the dvl/r7-0 bits. the soft mute is effective for changing the signal source without stopping the signal transmission (figure 27). smute bit a ttenuation dvtm bit dvl/r7-0 bits - dvtm bit gd gd (1) (2) (3) a nalog output figure 27. soft mute function (1) the output signal is attenuated until ? (?0?) by the cycle set by the dvtm bit. (2) analog output corresponding to digital input has the group delay (gd). (3) if the soft mute is cancelled within the cycle set by the dvtm bit, the attenuation is discounted and returned to the value set by the dvl/r7-0 bits. asahi kasei [ak4642] ms0358-e-00 2004/11 - 44 - ? beep input when the pmbp bit is set to ?1?, the beep input is powered-up. when the beeps bit is set to ?1?, the input signal from the beep pin is output to speaker-amp. when the beeph bit is set to ?1?, the input signal from the beep pin is output to headphone-amp. when the beepl bit is set to ?1?, the input signal from the beep pin is output to the stereo line output amplifier. the external resister ri adjusts the signal level of beep input. table 33, table 34 and table 35 show the typical gain example at r i = 20k ?. this gain is in inverse proportion to r i . beep ri lout/rout pin beepl hpl/hpr pin beeph spp/spn pin beeps figure 7. block diagram of beep pin lovl bit beep ? lout/rout 0 0db default 1 +2db table 33. beep input ? lout/rout output gain (typ) at r i = 20k ? hpg bit beep ? hpl/hpr 0 ? 20db default 1 ? 16.4db table 34. beep input ? headphone-amp output gain (typ) at r i = 20k ? beep ? spp/spn spkg1-0 bits alc bit = ?0? alc bit = ?1? 00 +4.43db +6.43db default 01 +6.43db +8.43db 10 +10.65db +12.65db 11 +12.65db +14.65db table 35. beep input ? speaker-amp output gain (typ) at r i = 20k ? asahi kasei [ak4642] ms0358-e-00 2004/11 - 45 - ? stereo line output (lout/rout pins) when dacl bit is ?1?, lch/rch signal of dac is output from the lout/rout pins which is single-ended. when dacl bit is ?0?, output signal is muted and lout/rout pins output vcom voltage. the load impedance is 10k ? (min.). when the pmlo bit = lops bit = ?0?, the stereo line output enters power-down mode and the output is pulled-down to avss by 100k ? (typ). when the lops bit is ?1?, stereo line output enters power-save mode. pop noise at power-up/down can be reduced by changing pmlo bit at lops bit = ?1?. in this case, output signal line should be pulled-down to avss by 20k ? after ac coupled as figure 29. rise/fall time is 300ms(max) at c=1 f. when pmlo bit = lops bit = ?1?, stereo line output is in normal operation. lovl bit set the gain of stereo line output. dac ?dacl? lout pin rout pin ?lovl? figure 28. stereo line output lops pmlo mode lout/rout pin 0 power-down pull-down to avss default 0 1 normal operation normal operation 0 power-save fall down to avss 1 1 power-save rise up to vcom table 36. stereo line output mode select (x: don?t care) lovl gain output voltage (typ) 0 0db 0.6 x avdd default 1 +2db 0.757 x avdd table 37. stereo line output volume setting lout rout 1 ? ? figure 29. external circuit for stereo line output (in case of using pop reduction circuit) asahi kasei [ak4642] ms0358-e-00 2004/11 - 46 - [stereo line output control sequence (in case of using pop reduction circuit)] pmlo bit lo p s bit lout, rout pins (1) (2) norm al output (3) (4) (5) (6) 300 m s 300 m s figure 30. stereo line output control sequence (in case of using pop reduction circuit) (1) set lops bit = ?1?. stereo line output enters the power-save mode. (2) set pmlo bit = ?1?. stereo line output exits the power-down mode. lout and rout pins rise up to vcom voltage. rise time is 200ms (max 300ms) at c=1 f. (3) set lops bit = ?0? after lout and rout pins rise up. stereo line output exits the power-save mode. stereo line output is enabled. (4) set lops bit = ?1?. stereo line output enters power-save mode. (5) set pmlo bit = ?1?. stereo line output enters power-down mode. lout and rout pins fall down to avss. fall time is 200ms (max 300ms) at c=1 f. (6) set lops bit = ?0? after lout and rout pins fall down. stereo line output exits the power-save mode. asahi kasei [ak4642] ms0358-e-00 2004/11 - 47 - ? headphone output power supply voltage for the headphone-amp is supplied from the hvdd pin and centered on the hvdd/2 voltage. the load resistance and output voltage are specified by hvdd voltage. hpg bit selects the output voltage (see table 38). hvdd 2.6 5.25v 4.0 5.25v hpg bit 0 1 output voltage [vpp] 0.6 x avdd 0.91 x avdd load resistance (min) 22 ? 100 ? table 38. headphone-amp output voltage and load resistance when the hpmtn bit is ?0?, the common voltage of headphone-amp falls and the outputs (hpl and hpr pins) go to ?l? (hvss). when the hpmtn bit is ?1 ?, the common voltage rises to hvdd/ 2. a capacitor between the mutet pin and ground reduces pop noise at power-up. rise/fall time constant is in proportional to hvdd voltage and the capacitor at mutet pin. [example]: a capacitor between the mutet pin and ground = 1.0 f, hvdd=3.3v: rise/fall time constant: = 100ms(typ), 250ms(max) time until the common goes to hvss when hpmtn bit = ?1? ? ?0?: 500ms(max) when pmhpl and pmhpr bits are ?0?, the headphone-amp is powered-down, and the outputs (hpl and hpr pins) go to ?l? (hvss). pmhpl bit, pmhpr bit (1) (2) (4) (3) hpmtn bit hpl pin, hpr pin figure 31. power-up/power-down timing for headphone-amp (1) headphone-amp power-up (p mhpl, pmhpr bit = ?1?). th e outputs are still hvss. (2) headphone-amp common voltage rises up (hpmtn bit = ?1?). common voltage of headphone-amp is rising. (3) headphone-amp common voltage falls down (hpmtn bit = ?0?). common voltage of headphone-amp is falling. (4) headphone-amp power-down (pmhpl, pmhpr bit = ?0?). th e outputs are hvss. if the power supply is switched off or headphone-amp is powered-down before the co mmon voltage goes to hvss, some pop noise occurs. asahi kasei [ak4642] ms0358-e-00 2004/11 - 48 - when boost=off, the cut-off frequency (fc) of headphone-amp depends on the external resistor and capacitor. this fc can be shifted to lower frequency by using bass boost function. table 39 shows the cut off frequency and the output power for various resistor/capacitor combinations. the headphone impedance r l is 16 ? . output powers are shown at hvdd = 2.7, 3.0 and 3.3v. the output voltage of headphone is 0.6 x avdd (vpp). when an external resist or r is smaller than 12 ? , put an oscillation prevention circuit (0.22 f 20% capacitor and 10 ? 20% resistor) because it has the possibility that headphone-amp oscillates. ak4642 hp-amp 16 ? headphone 10 ? 0.22 r c figure 32. external circuit example of headphone output power [mw]@0dbfs hpg bit r [ ? ] c [ f] fc [hz] boost=off fc [hz] boost=min @fs=44.1khz 2.7v 3.0v 3.3v 100 70 28 6.8 47 149 78 10.1 12.5 15.1 100 50 19 0 16 47 106 47 5.1 6.3 7.7 22 62 25 1 100 10 137 69 0.9 1.1 1.3 table 39. external circuit example asahi kasei [ak4642] ms0358-e-00 2004/11 - 49 - ? speaker output power supply for speaker-amp (hvdd) is 2.6v to 5.25v. in case of dynamic (electromagnetic) speaker (load resistance < 50 ? ), hvdd is 2.6v to 3.6v. speaker type dynamic speaker piezo (ceramic) speaker hvdd 2.6 3.6v 2.6 5.25v load resistance (min) 8 ? 50 ? load capacitance (max) 30pf 3 f note 22. in case of measuring at spp and spn pins. note 23. load impedance is total impedance of series resist ance and piezo speaker impedance at 1khz in figure 33. load capacitance is capacitance of piezo speaker. when piezo speaker is used, 10 ? or more series resistors should be connected at both spp and spn pins, respectively. table 40. speaker type and power supply range the dac output signal is input to the speaker-amp as [(l+r)/2]. the speaker-amp is mono and btl output. the gain is set by spkg1-0 bits. output level depends on avdd voltage and spkg1-0 bits. gain spkg1-0 bits alc bit = ?0? alc bit = ?1? 00 +4.43db +6.43db default 01 +6.43db +8.43db 10 +10.65db +12.65db 11 +12.65db +14.65db table 41. spk-amp gain spk-amp output (dac input = 0dbfs) avdd hvdd spkg1-0 bits alc bit = ?0? alc bit = ?1? (lmth1-0 bits = ?00?) 00 3.30vpp 3.11vpp 01 4.15vpp (note 40) 3.92vpp 10 6.75vpp (note 40) 6.37vpp (note 40) 3.3v 11 8.50vpp (note 40) 8.02vpp (note 40) 00 3.30vpp 3.11vpp 01 4.15vpp 3.92vpp 10 6.75vpp 6.37vpp 3.3v 5.0v 11 8.50vpp 8.02vpp note 40. the output level is calculated by assuming that output signal is not clipped. in actual case, output signal may be clipped when dac outputs 0dbfs signal. dac output level should be set to lower level by setting digital volume so that speaker-amp output level is 4.0vpp or less and output signal is not clipped. table 42. spk-amp output level asahi kasei [ak4642] ms0358-e-00 2004/11 - 50 - asahi kasei [ak4642] ms0358-e-00 2004/11 - 51 - asahi kasei [ak4642] ms0358-e-00 2004/11 - 52 - ? serial control interface (1) 3-wire serial control mode (i2c pin = ?l?) internal registers may be written by using the 3-wire p interface pins (csn, cclk and cdti). the data on this interface consists of a 2-bit chip address (fixed to ?10?), read/write (fixed to ?1?), register address (msb first, 5bits) and control data (msb first, 8bits). each bit is clocked in on the rising edge (? ?) of cclk. address and data are latched on the 16th cclk rising edge (? ?) after csn falling edge(? ?). clock speed of cclk is 5mhz (max). the value of internal registers are initialized by pdn pin = ?l?. csn cclk 0 1 2 345 67891011 12 13 14 15 cdti c1 c0 a 2 a 3 a 2 a 0 a 4 d7d6d5d4d3d2d1d0 r/w c1-c0: chip address (c1 = ?1?, c0 = ?0?); fixed to ?10? r/w: read/write (?1?: write, ?0?: read); fixed to ?1? a 4-a0: register address d7-d0: control data ?1? ?0? ?1? figure 35. serial control i/f timing asahi kasei [ak4642] ms0358-e-00 2004/11 - 53 - (2) i 2 c-bus control mode (i2c pin = ?h?) the ak4642 supports the fast-mode i 2 c-bus (max: 400khz). (2)-1. write operations figure 36 shows the data transfer sequence for the i 2 c-bus mode. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition (figure 42). after the start condition, a slave address is sent. this address is 7 bits long followed by an eighth bit that is a data direction bit (r/w). the most significant five bits of the slave address are fixed as ?00100?. the next two bits are cad1 and cad0 (device address bits). these two bits identify the specific device on the bus. the hard-wired input pins (cad1 and cad0 pins) set these device address bits (figure 37). if the slav e address matches that of the ak4642, the ak4642 generates an acknowledge and the operation is executed. the master must generate the acknowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse (figure 43). a r/w bit value of ?1? indicates that the read operation is to be executed. a ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the ak4642. the format is msb first, and those most significant 3-bits are fixed to zeros (figure 38). the data after the second byte contains control data. the format is msb first, 8bits (figure 39). the ak4642 generates an acknowledge after each byte has been received. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition (figure 42). the ak4642 can perform more than one byte write operation per sequence. after receipt of the third byte the ak4642 generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. the data on the sda line must remain stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low (figure 44) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 36. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 1 cad0 r/w (those cad1/0 should match with cad1/0 pins) figure 37. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 38. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 39. byte structure after the second byte asahi kasei [ak4642] ms0358-e-00 2004/11 - 54 - (2)-2. read operations set the r/w bit = ?1? for the read operation of the ak4642. after transmission of data, the master can read the next address?s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. after receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 1fh prior to generating a stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the ak4642 supports two basic read operations: current address read and random address read. (2)-2-1. current address read the ak4642 contains an internal address counter that maintain s the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) were to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit set to ?1?, the ak4642 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but instead generates a stop condition, the ak4642 ceases transmission. sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) a c k p s t o p data(n) figure 40. current address read (2)-2-2. random address read the random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues a start request, a slave address (r/w bit = ?0?) and then the register address to read. after the register address is acknowledged, the master immediately reissues the start request and the slave address with the r/w bit set to ?1?. the ak4642 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but instead generates a stop condition, the ak4642 ceases transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k a c k figure 41. random address read asahi kasei [ak4642] ms0358-e-00 2004/11 - 55 - scl sda stop condition start condition s p figure 42. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 43. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 44. bit transfer on the i 2 c-bus asahi kasei [ak4642] ms0358-e-00 2004/11 - 56 - ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 0 pmvcm pmbp pmspk pmlo pmdac 0 pmadl 01h power management 2 0 hpmtn pmhpl pmhpr m/s 0 mcko pmpll 02h signal select 1 sppsn beeps dacs dacl 0 pmmp 0 mgain0 03h signal select 2 lovl lops mgain1 spkg1 spkg0 beepl 0 0 04h mode control 1 pll3 pll2 pll1 pll0 bcko 0 dif1 dif0 05h mode control 2 ps1 ps0 fs3 0 0 fs2 fs1 fs0 06h timer select dvtm 0 ztm1 ztm0 wtm1 wtm0 0 0 07h alc mode control 1 0 0 alc zelmn lmat1 lmat0 rgain0 lmth0 08h alc mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 09h lch input volume control ivl7 ivl6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 0ah lch digital volume control dvl7 dv l6 dvl5 dvl4 dvl3 dvl2 dvl1 dvl0 0bh alc mode control 3 rgain1 lmth1 0 0 0 0 0 0 0ch rch input volume control ivr7 ivr6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 0dh rch digital volume control dvr7 dvr6 dvr5 dvr4 dvr3 dvr2 dvr1 dvr0 0eh mode control 3 0 loop smut e dvolc bst1 bst0 dem1 dem0 0fh mode control 4 0 0 0 0 ivolc hpm beeph dach 10h power management 3 0 0 hpg mdif2 mdif1 inr inl pmadr 11h digital filter select gn1 gn0 0 fil1 eq fil3 0 0 12h fil3 co-efficient 0 f3a7 f3a6 f3a5 f3a4 f3a3 f3a2 f3a1 f3a0 13h fil3 co-efficient 1 f3as 0 f3a13 f3a12 f3a11 f3a10 f3a9 f3a8 14h fil3 co-efficient 2 f3b7 f3b6 f3b5 f3b4 f3b3 f3b2 f3b1 f3b0 15h fil3 co-efficient 3 0 0 f3b1 3 f3b12 f3b11 f3 b10 f3b9 f3b8 16h eq co-efficient 0 eqa7 eqa6 eqa5 eqa4 eqa3 eqa2 eqa1 eqa0 17h eq co-efficient 1 eqa15 eqa14 eqa13 eqa12 eqa11 eqa10 eqa9 eqa8 18h eq co-efficient 2 eqb7 eqb6 eqb5 eqb4 eqb3 eqb2 eqb1 eqb0 19h eq co-efficient 3 0 0 eqb13 eqb12 eqb11 eqb10 eqb9 eqb8 1ah eq co-efficient 4 eqc7 eqc6 eqc5 eqc4 eqc3 eqc2 eqc1 eqc0 1bh eq co-efficient 5 eqc15 eqc14 e qc13 eqc12 eqc11 eqc10 eqc9 eqc8 1ch fil1 co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 1dh fil1 co-efficient 1 f1as 0 f1 a13 f1a12 f1a11 f1a10 f1a9 f1a8 1eh fil1 co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 1fh fil1 co-efficient 3 0 0 f1b1 3 f1b12 f1b11 f1 b10 f1b9 f1b8 note 41. pdn pin = ?l? resets the registers to their default values. note 42. unused bits must contain a ?0? value. asahi kasei [ak4642] ms0358-e-00 2004/11 - 57 - ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 0 pmvcm pmbp pmspk pmlo pmdac 0 pmadl default 0 0 0 0 0 0 0 0 pmadl: mic-amp lch and adc lch power management 0: power-down (default) 1: power-up when the pmadl or pmadr bit is changed from ?0? to ?1?, the initialization cycle (1059/fs=24ms @44.1khz) starts. after initializing, digital data of the adc is output. pmdac: dac power management 0: power-down (default) 1: power-up pmlo: stereo line out power management 0: power-down (default) 1: power-up pmspk: speaker-amp power management 0: power-down (default) 1: power-up pmbp: beep input power management 0: power-down (default) 1: power-up both pmdac and pmbp bits should be set to ?1? when dac is powered-up for playback. after that, beepl, beeph or beeps bit is used to control each path when beep input is used. pmvcm: vcom power management 0: power-down (default) 1: power-up when any blocks are powered-up, the pmvcm bit must be set to ?1?. pmvcm bit can be set to ?0? only when all power management bits of 00h, pmpll and mcko bits are ?0?. each block can be powered-down respectively by writing ?0? in each bit of this address. when the pdn pin is ?l?, all blocks are powered-down regardless as setting of this address. in this case, register is initialized to the default value. when all power management bits are ?0? in the 00h, 01h, 02h and 10h addresses and mcko bit is ?0?, all blocks are powered-down. the register values remain unchanged. when neither adc nor dac are used, external clocks may not be present. when adc or dac is used, external clocks must always be present. asahi kasei [ak4642] ms0358-e-00 2004/11 - 58 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h power management 2 0 hpmtn pmhpl pmhpr m/s 0 mcko pmpll default 0 0 0 0 0 0 0 0 pmpll: pll power management 0: ext mode and power-down (default) 1: pll mode and power-up mcko: master clock output enable 0: disable: mcko pin = ?l? (default) 1: enable: output frequency is selected by ps1-0 bits. m/s: master / slave mode select 0: slave mode (default) 1: master mode pmhpr: headphone-amp rch power management 0: power-down (default) 1: power-up pmhpl: headphone-amp lch power management 0: power-down (default) 1: power-up hpmtn: headphone-amp mute control 0: mute (default) 1: normal operation asahi kasei [ak4642] ms0358-e-00 2004/11 - 59 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h signal select 1 sppsn beeps dacs dacl 0 pmmp 0 mgain0 default 0 0 0 0 0 0 0 1 mgain1-0: mic-amp gain control (see table 16) mgain1 bit is d5 bit of 03h. pmmp: mpwr pin power management 0: power-down: hi-z (default) 1: power-up dacl: switch control from dac to stereo line output 0: off (default) 1: on when pmlo bit is ?1?, dacl bit is enabled. when pmlo bit is ?0?, the lout/rout pins go to avss. dacs: switch control from dac to speaker-amp 0: off (default) 1: on when dacs bit is ?1?, dac output signal is input to speaker-amp. beeps: switch control from beep pin to speaker-amp 0: off (default) 1: on when beeps bit is ?1?, beep signal is input to speaker-amp. sppsn: speaker-amp power-save mode 0: power-save mode (default) 1: normal operation when sppsn bit is ?0?, speaker-amp is in power-save mode. in this mode, spp pin goes to hi-z and spn pin is outputs hvdd/2 voltage. when pmspk bit = ?1?, sppsn bit is enabled. after the pdn pin is set to ?h?, speaker-amp is in power-down mode since pmspk bit is ?0?. asahi kasei [ak4642] ms0358-e-00 2004/11 - 60 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h signal select 2 lovl lops mgain1 spkg1 spkg0 beepl 0 0 default 0 0 0 0 0 0 0 0 beepl: switch control from beep pin to stereo line output 0: off (default) 1: on when pmlo bit is ?1?, beepl bit is enabled. when pmlo bit is ?0?, the lout/rout pins go to avss. spkg1-0: speaker-amp output gain select (see table 41) mgain1: mic-amp gain control (see table 16) lops: stereo line output power-save mode 0: normal operation (default) 1: power-save mode lovl: stereo line output gain select (table 37) 0: 0db (default) 1: +2db addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h mode control 1 pll3 pll2 pll1 pll0 bcko 0 dif1 dif0 default 0 0 0 0 0 0 1 0 dif1-0: audio interface format (see table 13) default: ?10? (left jutified) bcko: bick output frequency select at master mode (see table 10) pll3-0: pll reference clock select (see table 4) default: ?0000?(lrck pin) addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h mode control 2 ps1 ps0 fs3 0 0 fs2 fs1 fs0 default 0 0 0 0 0 0 0 0 fs3-0: sampling frequency select (see table 5 and table 6.) and mcki frequency select (see table 11.) fs3-0 bits select sampling frequency at pll mode and mcki frequency at ext mode. ps1-0: mcko output frequency select (table 9) default: ?00?(256fs) asahi kasei [ak4642] ms0358-e-00 2004/11 - 61 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h timer select dvtm 0 ztm1 ztm0 wtm1 wtm0 0 0 default 0 0 0 0 0 0 0 0 wtm1-0: alc recovery waiting period (see table 24.) default: ?00? (128/fs) ztm1-0: alc limiter/recovery operation zero crossing timeout period (see table 23.) default: ?00? (128/fs) dvtm: digital volume transition time setting (see table 32.) 0: 1061/fs (default) 1: 256/fs this is the transition time between dvl/r7-0 bits = 00h and ffh. addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h alc mode control 1 0 0 alc zelmn lmat1 lmat0 rgain0 lmth0 default 0 0 0 0 0 0 0 0 lmth1-0: alc limiter detection level / recovery counter reset level (see table 21.) default: ?00? lmth1 bit is d6 bit of 0bh. rgain1-0: alc recovery gain step (see table 25.) default: ?00? rgain1 bit is d7 bit of 03h. lmat1-0: alc limiter a tt step (see table 22.) default: ?00? zelmn: zero cro ssing detection enable at alc limiter operation 0: enable (default) 1: disable alc: alc enable 0: alc disable (default) 1: alc enable addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h alc mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 default 1 1 1 0 0 0 0 1 ref7-0: reference value at alc recovery operation. 0.375db step, 242 level (table 26.) default: ?e1h? (+30.0db) asahi kasei [ak4642] ms0358-e-00 2004/11 - 62 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h lch input volume control ivl7 iv l6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 0ch rch input volume control ivr7 iv r6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 default 1 1 1 0 0 0 0 1 ivl7-0, ivr7-0: input digital volume; 0.375db step, 242 level (table 28.) default: ?e1h? (+30.0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah lch digital volume control dvl7 dvl6 dvl5 dvl4 dvl3 dvl2 dvl1 dvl0 0dh rch digital volume control dvr7 dvr6 dvr5 dvr4 dvr3 dvr2 dvr1 dvr0 default 0 0 0 1 1 0 0 0 dvl7-0, dvr7-0: output digital volume (see table 31.) default: ?18h? (0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh alc mode control 3 rgain1 lmth1 0 0 0 0 0 0 default 0 0 0 0 0 0 0 0 lmth1: alc limiter detection level / recovery counter reset level (see table 21.) rgain1: alc recovery gain step (see table 25.) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh mode control 3 0 loop smute dvolc bst1 bst0 dem1 dem0 default 0 0 0 1 0 0 0 1 dem1-0: de-emphasis frequency select (table 29) default: ?01? (off) bst1-0: bass boost function select (table 30) default: ?00? (off) dvolc: output digital volume control mode select 0: independent 1: dependent (default) when dvolc bit = ?1?, dvl7-0 bits control both lch and rch volume level, while register values of dvl7-0 bits are not written to dvr7-0 bits. when dvolc bit = ?0?, dvl7-0 bits control lch level and dvr7-0 bits control rch level, respectively. smute: soft mute control 0: normal operation (default) 1: dac outputs soft-muted loop: digital loopback mode 0: sdti dac (default) 1: sdto dac asahi kasei [ak4642] ms0358-e-00 2004/11 - 63 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0fh mode control 4 0 0 0 0 ivolc hpm beeph dach default 0 0 0 0 1 0 0 0 dach: switch control from dac to headphone-amp 0: off (default) 1: on beeph: switch control from beep pin to headphone-amp 0: off (default) 1: on hpm: headphone-amp mono output select 0: stereo (default) 1: mono when the hpm bit = ?1?, (l+r)/2 signals are output to lch and rch of the headphone-amp. both pmhpl and pmhpr bits should be ?1? when hpm bit is ?1?. ivolc: input digital volume control mode select 0: independent 1: dependent (default) when ivolc bit = ?1?, ivl7-0 bits control both lch and rch volume level, while register values of ivl7-0 bits are not written to ivr7-0 bits. when ivolc bit = ?0?, ivl7-0 bits control lch level and ivr7-0 bits control rch level, respectively. asahi kasei [ak4642] ms0358-e-00 2004/11 - 64 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h power management 3 0 0 hpg mdif2 mdif1 inr inl pmadr default 0 0 0 0 0 0 0 0 pmadr: mic-amp lch and adc rch power management 0: power-down (default) 1: power-up inl: adc lch input source select 0: lin1 pin (default) 1: lin2 pin inr: adc rch input source select 0: rin1 pin (default) 1: rin2 pin mdif1: adc lch input type select 0: single-ended input (lin1/lin2 pin: default) 1: full-differential input (in1+/in1 ? pin) mdif2: adc rch input type select 0: single-ended input (rin1/rin2 pin: default) 1: full-differential input (in2+/in2 ? pin) hpg: headphone-amp gain select (see table 38.) 0: 0db (default) 1: +3.6db asahi kasei [ak4642] ms0358-e-00 2004/11 - 65 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 11h digital filter select gn1 gn0 0 fil1 eq fil3 0 0 default 0 0 0 0 0 0 0 0 gn1-0: gain select at gain block (see table 19.) default: ?00? fil3: fil3 (stereo separation emphasis filter) coefficient setting enable 0: disable (default) 1: enable when fil3 bit is ?1?, the settings of f3a13-0 and f3b13-0 bits are enabled. when fil3 bit is ?0?, fil3 block is off (mute). eq: eq (gain compensation filter) coefficient setting enable 0: disable (default) 1: enable when eq bit is ?1?, the settings of eqa15-0, eqb13-0 and eqc15-0 bits are enabled. when eq bit is ?0?, eq block is through (0db). fil1: fil1 (wind-noise reduction filter) coefficient setting enable 0: disable (default) 1: enable when fil1 bit is ?1?, the settings of f1a13-0 and f1b13-0 bits are enabled. when fil1 bit is ?0?, fil1 block is through (0db). asahi kasei [ak4642] ms0358-e-00 2004/11 - 66 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 12h fil3 co-efficient 0 f3a7 f3a6 f3a5 f3a4 f3a3 f3a2 f3a1 f3a0 13h fil3 co-efficient 1 f3as 0 f3a13 f3a12 f3a11 f3a10 f3a9 f3a8 14h fil3 co-efficient 2 f3b7 f3b6 f3b5 f3b4 f3b3 f3b2 f3b1 f3b0 15h fil3 co-efficient 3 0 0 f3b13 f3b12 f3b11 f3b10 f3b9 f3b8 16h eq co-efficient 0 eqa7 eqa6 eqa5 eqa4 eqa3 eqa2 eqa1 eqa0 17h eq co-efficient 1 eqa15 eqa14 eqa13 eqa12 eqa11 eqa10 eqa9 eqa8 18h eq co-efficient 2 eqb7 eqb6 eq b5 eqb4 eqb3 eqb2 eqb1 eqb0 19h eq co-efficient 3 0 0 eqb1 3 eqb12 eqb11 eqb10 eqb9 eqb8 1ah eq co-efficient 4 eqc7 eqc6 eq c5 eqc4 eqc3 eqc2 eqc1 eqc0 1bh eq co-efficient 5 eqc15 eqc14 eq c13 eqc12 eqc11 eqc10 eqc9 eqc8 1ch fil1 co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 1dh fil1 co-efficient 1 f1as 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 1eh fil1 co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 1fh fil1 co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 default 0 0 0 0 0 0 0 0 f3a13-0, f3b13-0: fil3 (stereo separation emphasis filter) coefficient (14bit x 2) default: ?0000h? f3as: fil3 (stereo separation emphasis filter) select 0: hpf (default) 1: lpf eqa15-0, eqb13-0, eqc15-c0: eq (gain compensation filter) coefficient (14bit x 2 + 16bit x 1) default: ?0000h? f1a13-0, f1b13-b0: fil1 (wind-noise reduction filter) coefficient (14bit x 2) default: ?0000h? f1as: fil1 (wind-noise reduction filter) select 0: hpf (default) 1: lpf asahi kasei [ak4642] ms0358-e-00 2004/11 - 67 - system design figure 45 shows the system connection diagram for the ak4642. an evaluation board [akd4642] is available which demonstrates the optimum layout, power supply arrangements and measurement results. mutet rout lout beep rin2 lin2 lin1 rin1 hpl hpr hvss hvdd spp spn mcko mcki mpi vcom a vss a vdd vcoc i2c pdn csn dvss dvdd bick lrck sdto sdti cdti cclk a k4642vn top view 25 26 27 28 29 30 31 32 24 23 22 1 16 15 14 13 12 11 10 9 21 20 19 18 17 2 3 4 5 6 7 8 2.2 k 2.2 k 2.2 k 2.2 k external mic or line in internal mic 1u 0.1u 2.2u 0.1u rp 6.8 47u 6.8 47u 10 0.22u 10 0.22u power supply 2.6 3.6v 0.1u 0.1u 10 dsp 10 ? zd1, zd2: required r1 r2 notes: - avss, dvss and hvss of the ak4642 should be distributed separately from the ground of external controllers. - values of r and c in figure 45 should depend on system. - all digital input pins should not be left floating. - when the ak4642 is ext mode (pmpll bit = ?0?), a resistor and capacitor of vcoc pin is not needed. - when the ak4642 is pll mode (pmpll bit = ?1?), a resistor and capacitor of vcoc pin is shown in table 4. - when piezo speaker is used, 2.6 5.25v power should be supplied to hvdd and 10 ? or more series resistors should be connected to both spp and spn pins, respectively. - when the ak4642 is used at master mode, lrck and bick pins are floating before m/s bit is changed to ?1?. therefore, 100k ? around pull-up resistor should be connected to lrck and bick pins of the ak4642. figure 45. typical connection diagram asahi kasei [ak4642] ms0358-e-00 2004/11 - 68 - 1. grounding and power supply decoupling the ak4642 requires careful attention to power supply and grounding arrangements. avdd, dvdd and hvdd are usually supplied from the system?s analog supply. if avdd, dvdd and hvdd are supplied separately, the power-up sequence is not critical. avss, dvss and hvss of the ak4642 should be connected to the analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to th e ak4642 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference vcom is a signal ground of this chip. a 2.2 f electrolytic capacitor in parallel with a 0.1 f ceramic capacitor attached to the vcom pin eliminates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the vcom pin in order to avoid unwanted coupling into the ak4642. 3. analog inputs the mic, line and beep inputs are single-ended. the input signal range scales with nominally at 0.06 x avdd vpp (typ) for the mic input and 0.6 x avdd vpp (typ) for the beep input, centered around the internal common voltage (0.45 x avdd). usually the input signal is ac coupled using a capacitor. the cut-off frequency is fc = (1/2 rc). the ak4642 can accept input voltages from avss to avdd. 4. analog outputs the input data format for the dac is 2?s complement. the output voltage is a positive full scale for 7fffh(@16bit) and a negative full scale for 8000h(@16bit). stereo line output is centered at 0.45 x avdd. the headphone-amp and speaker-amp outputs are centered at hvdd/2. asahi kasei [ak4642] ms0358-e-00 2004/11 - 69 - control sequence ? clock set up when adc or dac is powered-up, the clocks must be supplied. 1. pll master mode. bick pin lrck pin mcko bit (addr:01h, d1) pmpll bit (addr:01h, d0) 40msec(max) output (1) (6) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) mcki pin (5) (4) input m/s bit (addr:01h, d3) mcko pin output (8) (7) 40msec(max) example: audio i/f format: msb justified (adc & dac) bick frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz mcko: enable sampling frequency: 8khz (1) power supply & pdn pin = ?l? ? ?h? ( 3 ) addr:00h, data:40h (2)addr:01h, data:08h addr:04h, data:4ah addr:05h, data:00h ( 4 ) addr:01h, data:0bh mcko, bick and lrck output figure 46. clock set up sequence (1) asahi kasei [ak4642] ms0358-e-00 2004/11 - 70 - 2. pll slave mode (lrck or bick pin) pmpll bit (addr:01h, d0) internal clock (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) lrck pin bick pin (4) (5) input 4fs of example: audio i/f format : msb justified (adc & dac) pll reference clock: bick bick frequency: 64fs sampling frequency: 8khz (1) power supply & pdn pin = ?l? ? ?h? (3) addr:00h, data:40h (2) addr:04h, data:32h addr:05h, data:00h (4) addr:01h, data:01h figure 47. clock set up sequence (2) asahi kasei [ak4642] ms0358-e-00 2004/11 - 71 - 3. pll slave mode (mcki pin) bick pin lrck pin mcko bit (addr:01h, d1) pmpll bit (addr:01h, d0) (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) mcki pin (5) (4) input mcko pin output (6) (7) 40msec(max) (8) input example: audio i/f format: msb justified (adc & dac) bick frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz mcko: enable sampling frequency: 8khz (1) power supply & pdn pin = ?l? ? ?h? ( 3 ) addr:00h, data:40h (2)addr:04h, data:4ah addr:05h, data:00h ( 4 ) addr:01h, data:03h mcko output start bick and lrck input start figure 48. clock set up sequence (3) asahi kasei [ak4642] ms0358-e-00 2004/11 - 72 - 4. ext slave mode (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) lrck pin bick pin (4) input (4) mcki pin input example: audio i/f format: msb justified (adc and dac) input mcki frequency: 1024fs sampling frequency: 8khz mcko: disable (1) power supply & pdn pin = ?l? ? ?h? (3) addr:00h, data:40h (2) addr:04h, data:02h addr:05h, data:01h mcki, bick and lrck input figure 49. clock set up sequence (4) asahi kasei [ak4642] ms0358-e-00 2004/11 - 73 - ? mic input recording (stereo) fs3-0 bits (addr:05h, d5&d2-0) mic control (addr:02h, d2-0) pmadl/r bit (addr:00h&10h, d0) adc internal state 1,111 x,xxx 001 101 power down initialize normal state power down 1059 / fs (1) (2) (7) alc state alc enable alc disable alc disable (5) alc control 1 (addr:06h) xxh 28h (3) alc control 2 (addr:08h) xxh e1h (4) alc control 3 (addr:0bh) xxh 00h (8) (6) alc control 4 (addr:07h) xxh 21h 01h (9) example: pll master mode audio i/f format:msb justified (adc & dac) sampling frequency:44.1khz pre mic amp:+20db mic power on alc setting:refer to figrure 23 alc bit=?1? (2) addr:02h, data:05h (3) addr:06h, data:28h (1) addr:05h, data:27h (4) addr:08h, data:e1h (5) addr:0bh, data:00h (7) addr:00h, data:41h addr:10h, data:01h recording (8) addr:00h, data:40h addr:10h, data:00h (6) addr:07h, data:21h (9) addr:07h, data:01h figure 50. mic input recording sequence asahi kasei [ak4642] ms0358-e-00 2004/11 - 74 - ? speaker-amp output fs3-0 bits (addr:05h, d5&d2-0) dvl/r7-0 bits (addr:0ah&0dh, d7-0) pmdac bit (addr:00h, d2) pmspk bit (addr:00h, d4) 1,111 x,xxx 18h xxh spp pin normal output sppsn bit (addr:02h, d7) hi-z hi-z spn pin normal output hi-z hi-z hvdd/2 hvdd/2 (1) (9) x 0 (7) alc bit (addr:07h, d5) (10) (11) (14) (12) dacs bit (addr:02h, d3) (13) 01 00 (3) spkg1-0 bits (addr:03h, d4-3) ivl/r7-0 bits (addr:09h&0ch, d7-0) e1h 91h (8) (2) (6) alc control 1 (addr:06h) xxh 28h (4) alc control 2 (addr:08h) xxh c1h (5) alc control 3 (addr:0bh) xxh 00h pmbp bit (addr:00h, d5) example: pll master mode audio i/f format: msb justified (adc & dac) sampling frequency: 44.1khz digital volume: 0db alc: enable (2) addr:02h, data:20h (7) addr:07h, data:20h (1) addr:05h, data:27h (9) addr:0ah & 0dh, data:28h (10) addr:00h, data:74h (11) addr:02h, data:a0h (12) addr:02h, data:20h playback (13) addr:02h, data:00h (14) addr:00h, data:40h (3) addr:03h, data:08h (8) addr:09h & 0ch, data:91h (4) addr:06h, data:28h (5) addr:08h, data:e1h (6) addr:0bh, data:00h figure 51. speaker-amp output sequence asahi kasei [ak4642] ms0358-e-00 2004/11 - 75 - ? beep signal output from speaker-amp dacs bit (addr:02h, d5) pmspk bit (addr:00h, d4) beeps bit (addr:02h, d6) spp pin normal output sppsn bit (addr:02h, d7) hi-z hi-z spn pin normal output hi-z hi-z hvdd/2 hvdd/2 (2) (1) (5) (4) pmbp bit (addr:00h, d5) x 0 clocks can be stopped. clock (3) (6) example: ( 2 ) addr:02h, data:60h ( 1 ) addr:00h, data:70h ( 3 ) addr:02h, data:e0h beep signal output (4) addr:02h, data:60h (5) addr:00h, data:40h (6) addr:02h, data:00h figure 52. ?bepp-amp ? speaker-amp? output sequence asahi kasei [ak4642] ms0358-e-00 2004/11 - 76 - ? headphone-amp output fs3-0 bits (addr:05h, d5&d2-0) dvl/r7-0 bits (addr:0ah&0dh, d7-0) pmhpl/r bits (addr:01h, d5-4) hpmtn bit (addr:01h, d6) hpl/r pins 1,111 x,xxx 18h xxh normal output (1) bst1-0 bits (addr:0eh, d3-2) 00 xx 00 (2) (4) (11) pmdac bit (addr:00h, d2) (5) (10) (6) (8) (7) (9) ivl/r7-0 bits (addr:09h&0ch, d7-0) e1h 91h (3) pmbp bit (addr:00h, d5) exam ple : pll master m ode sam pling frequency: 44.1khz d v o lc bit = ?1?(default) d ig ita l v o lu m e l e ve l: 0 db bass boost level: middle de-em phases response: off soft mute tim e: 256/fs (1) addr:05h, data:27h (4) a ddr:0a h &0d h , d ata 28h (5) addr:00h, data 64h playback (2) a ddr:0e h , d ata 14 h (8) addr:01h, data 39h (9) addr:01h, data 09h (6) addr:01h, data 39h (7) addr:01h, data 79h (10) addr:00h, data 40h (1 1 ) a d d r:0 e h , d a ta 0 0 h (3) addr:09h&0ch, data 91h figure 53. headphone-amp output sequence asahi kasei [ak4642] ms0358-e-00 2004/11 - 77 - ? stereo line output fs3-0 bits (addr:05h, d5&d2-0) dvl/r7-0 bits (addr:0ah&0dh, d7-0) pmdac bit (addr:00h, d2) pmlo bit (addr:00h, d3) 1,111 x,xxx 18h xxh lout pin rout pin (1) (4) (5) (2) dacl bit (addr:02h, d4) (10) normal output (7) lops bit (addr:03h, d6) (6) >300 ms (8) (9) >300 ms (11) ivl/r7-0 bits (addr:09h&0ch, d7-0) e1h 91h (3) pmbp bit (addr:00h, d5) example: pll, master mode audio i/f format :msb justified (adc & dac) sampling frequency: 44.1khz digital volume: 0db mgain1=spkg1=spkg0=beepl bits = ?0? (1) addr:05h, data:27h (2) addr:02h, data:10h (4) addr:0ah&0dh, data:28h (5) addr:03h, data:40h (6) addr:00h, data:6ch (7) addr:03h, data:00h playback (8) addr:03h, data:40h (9) addr:00h, data:40h (10) addr:02h, data:00h (11) addr:03h, data:00h (3) addr:09h&0ch, data:91h figure 54. stereo lineout sequence asahi kasei [ak4642] ms0358-e-00 2004/11 - 78 - ? stop of clock master clock can be stopped when adc and dac are not used. 1. pll master mode external mcki pmpll bit (addr:01h, d0) mcko bit (addr:01h, d1) input (3) (1) (2) "h" or "l" example: audio i/f format: msb justified (adc & dac) bick frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz sampling frequency: 8khz (3) stop an external mcki (1) (2) addr:01h, data:08h figure 55. clock stopping sequence (1) asahi kasei [ak4642] ms0358-e-00 2004/11 - 79 - 3. pll slave (mcki pin) external mcki pmpll bit (addr:01h, d0) input (1) (2) mcko bit (addr:01h, d1) (1) example audio i/f format: msb justified (adc & dac) pll reference clock: mcki bick frequency: 64fs sampling frequency: 8khz ( 1 ) addr:01h, data:00h ( 2 ) stop the external clocks figure 57. clock stopping sequence (3) asahi kasei [ak4642] ms0358-e-00 2004/11 - 80 - package 32pin qfn (unit: mm) 0 . 3 0 5.0 0.10 5.2 0.20 5.0 0.10 0 . 5 5 + 0 . 1 0 - 0 . 2 0 5.2 0.20 0.40 0.18 0.05 32 25 1 9 24 0.05 m 24 17 16 9 8 1 25 45 45 0.21 0.05 0.01 + 0.04 - 0.01 0.78 + 0.07 - 0.28 0.05 8 16 17 4 - c 0 . 6 0.60 0.10 32 0.80 0.10 note) the part of black at four corners on reverse side must not be soldered and must be open. ? material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatm ent: solder plate (pb free) asahi kasei [ak4642] ms0358-e-00 2004/11 - 81 - marking 4642 x xxxx 1 xxxxx : date code identifier (5 digits) revision history date (yy/mm/dd) revision reason page contents 04/11/16 00 first edition important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. |
Price & Availability of AK4642VN
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |