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tundra semiconductor corporation tsi106 ? powerpc host bridge hardware specifications manual document number: 80c1000_ma002_02 document status: formal release date: october 2006 titlepage - 80c1000_ma002_02
trademarks tundra is a registered trademark of tundra semiconduc tor corporation (canada, u.s., and u.k.). tundra, the tundra logo, tsi106, and silicon behind the network, are trademarks of tundra semiconductor corporation. all other registered and unregistered marks (including trademarks, service marks and logos) are the property of their respective owners. the absence of a mark identifier is not a representation that a particular product name is not a mark. copyright copyright ? october 2006 tundra semiconductor corporation. all rights reserved. published in canada this document contains information which is proprieta ry to tundra and may be used for non-commercial purposes within your organization in support of tundra prod ucts. no other use or transmission of all or any part of this document is permitted without written permission from tundra, and must include all copyright and other proprietary notices. use or transmission of all or any pa rt of this document in violation of any applicable canadian or other legislation is hereby expressly prohibited. user obtains no rights in the information or in any produc t, process, technology or tr ademark which it includes or describes, and is expressly prohibited from modifying the information or creating derivative works without the express written consent of tundra. disclaimer tundra assumes no responsibility for th e accuracy or completeness of the in formation presented which is subject to change without notice. in no event will tundra be liable for any direct, indirect, speci al, incidental or consequential damages, including lost profits, lost business or lost data, resulting from the use of or reliance upon the information, whether or not tundra has been advised of the possibility of such damages. mention of non-tundra products or services is for information purposes only and constitutes neither an endorsement nor a recommendation.
tsi106 hardware specifications manual 80c1000_ma002_02 tundra semiconductor corporation www.tundra.com 3 about this document this section discusses general do cument information about the tsi106 hardware specifications manual . the following topics are described: ? ?scope? on page 3 ? ?revision history? on page 3 scope the tsi106 hardware specifications manual provides electrical and physical information about the tsi106. it is intended for hardware engineers who are d esigning system interconnect applications with the device. revision history 80c2000_ma002_02, formal, october 2006 ? added operating conditio n information (see ?ordering information? on page 31 ). ? fixed several minor typographical errors. 80c2000_ma002_01, formal, october 2003 this is the first tundra version of the tsi106 hardware specifications manual.
mpc106ec/d 4 tsi106 hardware specifications manual 80c1000_ma002_02 tundra semiconductor corporation www.tundra.com
tsi106 powerpc host bridge hard- ware specifica tions manual tsi106 powerpc host bridge hardware specifications manual the tundra tsi106 powerpc host bridge prov ides a powerpc? micropro cessor common hardware reference platform (chrp?) comp liant bridge between the powerp c microprocessor family and the peripheral component intercon nect (pci) bus. in this do cument, the term tsi106 is used as an abbreviation for the phrase tsi106 powerpc host bridge. this document contains pe rtinent physical characteristics of the tsi106. for functional char acteristics, refer to the tsi106 powerpc host bridge user manual . this document contains the following topics: topic page section 1.1, ?overview? 6 section 1.2, ?features? 7 section 1.3, ?general parameters? 9 section 1.4, ?electrical and thermal characteristics? 9 section 1.5, ?pin assignments? 19 section 1.6, ?pinout listings 20 section 1.7, ?package description? 24 section 1.8, ?system design information? 26 section 1.9, ?ordering information? 31
6 tsi106 powerpc host bridge hardware specifications manual 80c1000_ma002_02 overview in this document, the term ?60x? is used to denote a 32-bit microprocessor from the powerpc architecture family that conforms to the bus interface of the powerpc 601?, powerpc 603?, or powerpc 604? microprocessors. note that this does not includ e the powerpc 602? microprocessor which has a multiplexed address/data bus. 60x pr ocessors implement the powerpc arch itecture as it is specified for 32-bit addressing, which provides 32 -bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits (single-precision and double-precision). 1.1 overview the tsi106 provides an integrated high-bandwidth, high-performance, ttl-compatible interface between a 60x processor, a secondary (l2) ca che or additional (up to four total) 60x processors, the pci bus, and main memory. this section provides a block diagram sh owing the major functional units of the tsi106 and describes briefly how those units interact. figure 1 shows the major functional units within the tsi106. note that th is is a conceptual block diagram intended to show the basic features rather than ho w these features are physic ally implemented on the device. figure 1. block diagram 32-bit address and data 25-33 mhz pci bus (rev. 2.1) 64-bit data/32-bit address 66-83 mhz bus 66 mhz, 64-bit bu s dram, sdram , rom, flash up to 1-mbyte of sram 80c1000_bk001_01 i eee1149.1 b oundary s can processor interface pci interface jtag memory interface l2 cache interface power management error/interrupt control configuration registers
tsi106 powerpc host bridge hardware specifications manual 7 80c1000_ma002_02 features the tsi106 provides a powerpc microprocessor ch rp-compliant bridge between the powerpc microprocessor family and the pci bus. chrp documenta tion provides a set of specifications that define a unified personal computer architecture. pci support a llows the rapid design of systems using peripherals already designed for pci and the other standard inte rfaces available in the personal computer hardware environment. the tsi106 integrat es secondary cache control and a high -performance memory controller, uses an advanced, 3.3-v cmos process technolo gy, and is fully compa tible with ttl devices. the tsi106 supports a programmable interface to a variety of powerpc microprocessors operating at select bus speeds. the 60x address bus is 32 bits wide and the data bus is 64 bits wide. the 60x processor interface of the tsi106 uses a subset of the 60x bus protocol, supporting single-beat and burst data transfers. the address and data buses are d ecoupled to support pipelined transactions. the tsi106 provides support for the following configurations of 60x processors and l2 cache: ? up to four 60x processors with no l2 cache ? a single 60x processor plus a direct-mapped, lookaside l2 cache using the internal l2 cache controller of the tsi106 ? up to four 60x processors plus an externally controlled l2 cache (such as the motorola mpc2605 integrated secondary cache) the memory interface controls processor and pci interactions to main memory and is capable of supporting a variety of configurations using dram, edo, sdram, rom, or flash rom. the pci interface of the tsi106 complies with the pci local bus specification, revision 2.1, and follows the guidelines in the pci system design guide, revision 1.0, for host bridge architecture. the pci interface connects the processor an d memory buses to the pci bus, to which i/o components are connected. the pci bus uses a 32-bit multiplexed address/da ta bus, plus various co ntrol and error signals. the pci interface of the tsi106 functions as both a master and target device. as a master, the tsi106 supports read and write operations to the pci memory space, the pci i/o space, and the pci configuration space. the tsi106 also supports pci special-cycle an d interrupt-acknowledge commands. as a target, the tsi106 supports read and write operations to system memory. the tsi106 provides hardware support for four levels of power reduction: doze, nap, sleep, and suspend. the design of the tsi106 is fully static, allowing internal logic states to be preserved during all power-saving modes. 1.2 features this section summarizes the major features of the tsi106, as follows: ? 60x processor interface ? supports up to four 60x processors ? supports various operating frequencies and bus divider ratios ? 32-bit address bus, 64-bit data bus ? supports full memory coherency ? supports optional 60x local bus slave ? decoupled address and data bu ses for pipelining of 60x accesses ? store gathering on 60x-to-pci writes
8 tsi106 powerpc host bridge hardware specifications manual 80c1000_ma002_02 features ? secondary (l2) cache control ? configurable for write-through or write-back operation ? supports cache sizes of 256 kbytes, 512 kbytes, and 1 mbyte ? up to 4 gbytes of cacheable space ?direct-mapped ? supports byte parity ? supports partial update with extern al byte decode for write enables ? programmable interface timing ? supports pipelined burst, synchronous burst, or asynchronous srams ? alternately supports an external l2 cache controller or integrated l2 cache module ? memory interface ? 1 gbyte of ram space, 16 mbytes of rom space ? supports parity or error checking and correction (ecc) ? high-bandwidth, 64-bit data bus (72 bits including parity or ecc) ? supports fast page mode drams, extended data out (edo) drams, and synchronous drams (sdrams) ? supports 1 to 8 banks of dram/edo/sdram with sizes ranging from 2 mbyte to 128 mbytes per bank ? rom space may be split between the pci bus and the 60x/memory bus (8 mbytes each) ? supports 8-bit asynchronous rom or 64-bit burst-mode rom ? supports writing to flash rom ? configurable external buffer control logic ? programmable interface timing ? pci interface ? compliant with pci local bus specification, revision 2.1 ? supports pci interlocked ac cesses to memory using lock signal and protocol ? supports accesses to all pci address spaces ? selectable big- or little-endian operation ? store gathering on pci writes to memory ? selectable memory prefetching of pci read accesses ? only one external load presente d by the tsi106 to the pci bus ? interface operates at 20?33 mhz ? word parity supported ? 3.3 v/5.0 v-compatible ? support for concurrent transactions on 60x and pci buses ? power management ? fully-static 3.3-v cmos design ? supports 60x nap, doze, and sleep power management modes and suspend mode ? ieee 1149.1-compliant, jt ag boundary-scan interface ? 304-pin ceramic ball grid array (cbga) package
tsi106 powerpc host bridge hardware specifications manual 9 80c1000_ma002_02 general parameters 1.3 general parameters the following list provides a summary of the general parameters of the tsi106: technology 0.5 m cmos, four-layer metal die size 5.8 mm x 7.2 mm (41.8 mm 2 ) transistor count 250,000 logic design fully-static packages surface mount 304-lead c4 ceramic ball grid array (cbga) power supply 3.3 v 5% v dc maximum input rating 5.0 v 10% v dc 1.4 electrical and thermal characteristics this section provides both the ac and dc electrical specifications and therma l characteristics for the tsi106. 1.4.1 dc electrica l characteristics the tables in this section describe th e tsi106 dc electrical characteristics. table 1 provides the absolute maximum ratings. functional and tested operating conditions are given in table 2. absolute maximum ratings are stress ratings only, and functional opera tion at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause it permanent damage. table 2 provides the recomm ended operating conditions for the tsi106. proper device operation outside of these recommended an d tested conditions is not guaranteed. table 1. absolute maximum ratings characteristic symbol value unit notes supply voltage vdd ?0.3 to 3.6 v ? pll supply voltage avdd ?0.3 to 3.6 v ? input voltage v in ?0.3 to 5.5 v 1 junction temperature t j 0 to 105 o c2 storage temperature range t stg ?55 to 150 o c? notes : 1 caution : v in must not exceed vdd by more than 2.5 v at all times including during power-on reset. 2 the extended temperature parts have di e junction temperature of -40 to 105 o c.
10 tsi106 powerpc host bridge hardware specifications manual 80c1000_ma002_02 electrical and thermal characteristics table 3 provides the package therma l characteristics for the tsi106. table 4 provides the dc electrical characteristics fo r the tsi106, assuming vdd = avdd = 3.3 5% v dc, gnd = 0 v dc, and 0 t j 105 o c. table 5 lists the power consumption of the tsi106. table 2. recommended operating conditions characteristic symbol value unit notes supply voltage vdd 3.3 165 mv v ? pll supply voltage avdd 3.3 165 mv v ? input voltage v in 0 to 5.5 v ? die junction temperature t j 0 to 105 o c the extended temperature parts have die junction temperature of -40 to 105 o c table 3. package thermal characteristics characteristic symbol value rating cbga package thermal resistance, junction-to-top of die jc 0.133 o c/w note : refer to section 1.8, ?system design information,? for more details about thermal management. table 4. dc electrical specifications characteristic sy mbol min max unit input high voltage (all inputs except sysclk) v ih 25.5v input low voltage (all inputs except sysclk) v il gnd 0.8 v sysclk input high voltage cv ih 2.4 5.5 v sysclk input low voltage cv il gnd 0.4 v input leakage current, v in =3.3 v 1 i in ? 15.0 a hi-z (off-state) leakage current, v in = 3.3 v 1 i tsi ? 15.0 a output high voltage, i oh = -7 ma 2 v oh 2.4 ? v output low voltage, i ol = 7 ma 2 v ol ?0.5v pci 3.3 v signaling output high voltage, i oh = -0.5 ma 2 v oh 2.7 ? v pci 3.3 v signaling output low voltage, i ol = 1.5 ma 2 v ol ?0.3v capacitance, v in = 0 v, f = 1 mhz 3 c in ?7.0pf notes: 1 excludes test signals (lssd _mode and jtag signals). 2 this value represents worst case 40-ohm drivers (default value fo r processor/l2 control signals ci , wt , gbl , tbst , tsiz[0?2], tt[0?4], twe , and tv ) only. other signals have lo wer default driver impedance and will support larger i oh and i ol . all drivers may optionally be program med to different driver strengths. 3 capacitance is periodi cally sampled rather than 100% tested.
tsi106 powerpc host bridge hardware specifications manual 11 80c1000_ma002_02 electrical and thermal characteristics 1.4.2 ac electrica l characteristics this section provides ac electrical characteristics for the tsi106. afte r fabrication, parts are sorted by maximum 60x processor bus frequency, as shown in section 1.4.2.1, ?clock ac specifications,? and tested for conformance to the ac specifications fo r that frequency. these specifications are for operation between 16.67 and 33.33 mhz pci bus (sysclk) frequencies. the 60x processor bus frequency is determined by the pci bus (sysclk) frequency and the settings of the pll[0?3] signals. all timings are specified relative to the rising edge of sysclk. 1.4.2.1 clock ac specifications table 6 provides the clock ac timing specifications as shown in figure 2, and assumes vdd = avdd = 3.3 5% v dc, gnd = 0 v dc, and 0 t j 105 o c. table 5. power consumption mode sysclk/core 33/66 mhz sysclk/core 33/83.3 mhz unit full-on typical maximum 1.2 2.2 w 1.4 2.4 w doze typical maximum 1.0 1.1 w 1.2 1.4 w nap typical maximum 1.0 1.1 w 1.2 1.4 w sleep typical maximum 260 330 mw 360 450 mw suspend typical maximum 140 220 mw 190 270 mw notes: ? power consumption for common system configurations assuming 50 pf loads ? suspend power-saving mode assumes sysclk off and pll in bypass mode. ? typical power is an average value measured at vdd = avdd = 3.30 v and t a = 25 o c. ? maximum power is measured at vdd = avdd = 3.45 v and t a = 25 o c.
12 tsi106 powerpc host bridge hardware specifications manual 80c1000_ma002_02 electrical and thermal characteristics figure 2 provides the sysc lk input timing diagram. figure 2. sysclk input timing diagram 1.4.2.2 input ac specifications table 7 provides the input ac timing specifications for the tsi106 as defined in figure 3 and figure 4. these specifications are for operation betwee n 16.67 and 33.33 mhz pci bus clock (sysclk) frequencies. assume vdd = avdd = 3.3 5% v dc, gnd = 0 v dc, and 0 t j 105 o c. table 6. clock ac ti ming specifications num characteristic sysclk/core 33/66 mhz sysclk/core 33/83.3 mhz unit notes min max min max ? 60x processor bus (core) frequency 16.67 66 16.67 83.3 mhz 1 ? vco frequency 120 200 120 200 mhz 1, 2 ? sysclk frequency 16. 67 33.33 16.67 33.33 mhz 1 1 sysclk cycle time 30.0 60.0 30.0 60.0 ns ? 2, 3 sysclk rise and fall time ? 2.0 ? 2.0 ns 3 4 sysclk duty cycle measured at 1.4 v 40 60 40 60 % 4 ? sysclk jitter ? 200 ? 200 ps 5 ? tsi106 internal pll relock time ? 100 ? 100 s4, 6 notes : 1 caution : the sysclk frequency and pll[0?3] sett ings must be chosen such that th e resulting sysclk (bus) frequency, cpu (core) frequency, and pll (vco) frequency do not exceed their respec tive maximum or minimum operating frequencies. refer to the pll[0?3] signa l description in section 1 .8, ?system design informat ion,? for valid pll[0?3] settings for available freque ncies and part numbers. 2 vco operating range for extended temp erature devices is different. 3 rise and fall times for the sysclk i nput are measured from 0.4 v to 2.4 v. 4 timing is guaranteed by design and ch aracterization and is not tested. 5 the total input jitter (short- term and long-term combined ) must be under 200 ps. 6 pll-relock time is the maximum time required for pll lock af ter a stable vdd, avdd, and sysclk are reached during the power-on reset sequence. this sp ecification also applies when the pll has been disabled and subseque ntly re-enabled during the sleep and suspend power-savin g modes. also note that hrst must be held asserted for a minimum of 255 bus clocks after the pll-relock time (100 s) during the power-on reset sequence. vm vm = midpoint voltage (1.4 v) 2 3 cv il cv ih 1 sysclk vm vm 4 4
tsi106 powerpc host bridge hardware specifications manual 13 80c1000_ma002_02 electrical and thermal characteristics figure 3 provides the input tim ing diagram for the tsi106. table 7. input ac timing specifications num characteristic 66 mhz 83.3 mhz unit notes min max min max 10a group i input signals valid to 60x bu s clock (input setup) 4.0 3.5 ns 1,2,3 10a group ii input signals valid to 60x bus clock (input setup) 3.5 3.5 ns 1,2,4 10a group iii input signals valid to 60x bus clock (input setup) 3.0 2.5 ns 1,2,5 10a group iv input signals valid to 60x bus clock (input setup) 5.0 4.0 ns 1,2,6 10b group v input signals valid to sysclk (input setup) 7.0 7.0 ns 7,8 10b group vi input signals valid to sysclk (input setup) 7.0 7.0 ns 7,9 11a 60x bus clock to group i?iv inputs invalid (input hold) 0 ? 0 ? ns 3,4,5,6 11b sysclk to group v?vi inputs invalid (input hold) ?0.5 ? ?0.5 ? ns 8,9 hrst pulse width 255 x t sysclk + 100 s ? 255 x t sysclk + 100 s ?? 10c mode select inpu ts valid to hrst (input setup) 3 x t sysclk ? 3 x t sysclk ? ns 10, 11,12 11c hrst to mode select input inva lid (input hold) 1.0 ? 1.0 ? ns 10, 12 notes: 1 input specifications are measured from the tt l level (0.8 or 2.0 v) of the signal in question to the 1.4 v of the rising edge of sysclk. both input and out put timings are me asured at the pin (see figure 3). 2 processor and memory interface signals are specified from the rising edge of the 60x bus clock (which is internally synchronized to sysclk). 3 group i input signals include the following processor, l2 , and memory interface signals: a[0?31], par[0?7]/ar[1?8], br [0?4], brl2 , xats , lbclaim , ads , ba0, tv and hit (when configured for external l2) 4 group ii input signals include the following pr ocessor and memory interface signals: tbst , tt[0?4], tsiz[0?2], wt , ci , gbl , aack , and ta . 5 group iii input signals include the fo llowing processor and memory interfa ce signals: dl[0?31] and dh[0?31]. 6 group iv input signals include the followin g processor and l2 interface signals: ts , artry , dirty_in , and hit (when configured for internal l2 controller). 7 pci 3.3 v signaling environmen t signals are measured from 1.65 v (vdd 2) on the rising edge of sysclk to v oh =3.0v or v ol = 0.3 v. pci 5 v signaling environment si gnals are measured from 1.65 v (vdd 2) on the rising edge of sysclk to v oh = 2.4 v or v ol =0.55v. 8 group v input signals include the follow ing bussed pci interface signals: frame , c/be [0?3], ad[0?31], devsel , irdy , trdy , stop , par , perr , serr , lock , flshreq , and isa_master . 9 group vi input signal is the point-to-point pci gnt input signal. 10 the setup and hold time is with re spect to the rising edge of hrst (see figure 4). mode sele ct inputs include the rcs0 , foe , and dbg0 configuration inputs. 11 t sysclk is the period of the external clock (sysclk) in nanoseconds (ns) . when the unit is given as t sysclk , the numbers given in the table must be multiplied by the pe riod of sysclk to compute the actual ti me duration (in nanoseconds) of the parameter in question. 12 these values are guaranteed by design and are not tested.
14 tsi106 powerpc host bridge hardware specifications manual 80c1000_ma002_02 electrical and thermal characteristics figure 3. input timing diagram figure 4 provides the mode select in put timing diagram for the tsi106. figure 4. mode select input timing diagram 1.4.2.3 output ac specifications table 8 provides the output ac timing specifications for tsi106 (shown in table 5). assume vdd = avdd = 3.3 5% v dc, gnd = 0 v dc, cl = 50 pf, and 0 t j 105 o c. processor and memory interface signals are specified from the rising edge of the 60x bus clock (which is internally synchronized to sysclk). all units are nanoseconds. 11a vm 60x bus clock 10a 11b vm vm = midpoint voltage (1.4 v) sysclk 10b group i, ii, iii, group v and and iv inputs vi inputs vm vm = midpoint voltage (1.4 v) hrst 11c mode pins 10c
tsi106 powerpc host bridge hardware specifications manual 15 80c1000_ma002_02 electrical and thermal characteristics table 8. output ac ti ming specifications num characteristic 66 mhz 83.3 mhz notes min max min max 12 sysclk to output driven (output enable time) 2.0 ? 2.0 ? 1 13a sysclk to output valid for ts and artry ? 7.0 ? 6.0 2, 3, 4 13b sysclk to output valid for all non-pci signals except ts , artry , ras [0?7], cas [0?7], and dwe[0-2] ? 7.0 ? 6.0 2, 3, 5 14a sysclk to output valid (for ras[0?7] and cas[0?7]) ? 7.0 ? 6.0 2, 3 14b sysclk to output valid fo r pci signals ? 11.0 ? 11.0 3, 6 15a sysclk to output invalid for all non-pci signals (output hold) 1.0 ? 1.0 ? 7, 10 15b sysclk to output i nvalid for pci signals (output hold) 1.0 ? 1.0 ? 7 18 sysclk to artry high impedance before precharge (output hold) ? 8.0 ? 8.0 1 19 sysclk to artry precharge enable (0.4 * t sysclk ) + 2.0 ? (0.4 x t sysclk ) + 2.0 ?8, 1 21 sysclk to artry high impedance after precharge ? (1.5 * t sysclk ) + 8.0 ? (1.5 x t sysclk ) + 8.0 8, 1 notes: 1 these values are guaranteed by design and are not tested. 2 output specifications are measured from 1. 4 v on the rising edge of the appropriate cl ock to the ttl level (0.8 v or 2.0 v) of the signal in question. both input and output timings are measured at the pin (see figure 5). 3 the maximum timing specification assumes c l = 50 pf. 4 the shared outputs ts and artry require pull-up resistors to hold them negated when there is no bus master driving them. 5 when the tsi106 is configured for as ynchronous l2 cache srams, the dwe[0?2] signals have a maximum sysclk to output valid time of (0.5 x t proc ) + 8.0 ns (where t proc is the 60x bus cl ock cycle time). 6 pci 3.3 v signaling environmen t signals are measured from 1.65 v (vdd 2) on the rising edge of sysclk to v oh =3.0v or v ol =0.3v. 7 the minimum timing specification assumes c l = 0 pf. 8 t sysclk is the period of the external bus clock (sysclk) in nanoseconds (n s). when the unit is given as t sysclk the numbers given in the table must be mu ltiplied by the period of sysclk to compute the actual time duration (in nanoseconds) of the parameter in question. 9 pci devices which require more than the pci-specifie d hold time of t h = 0ns or systems where clock skew approaches the pci-specified allowance of 2ns may not work with the tsi106.
16 tsi106 powerpc host bridge hardware specifications manual 80c1000_ma002_02 electrical and thermal characteristics figure 5 provides the output timing diagram for the tsi106. figure 5. output timing diagram 1.4.3 jtag ac timing specifications table 9 provides the jtag ac timing specifications . assume vdd = avdd = 3.3 5% v dc, gnd = 0 v dc, cl = 50 pf, and 0 t j 105 o c. table 9. jtag ac timing specifica tions (independent of sysclk) num characteristic min max unit notes ? tck frequency of operation 0 25 mhz ? 1 tck cycle time 40 ? ns ? 2 tck clock pulse width measured at 1.4 v 20 ? ns ? 3 tck rise and fall times 0 3 ns 1 4trst setup time to tck rising edge 10 ? ns 2 5trst assert time 10 ? ns 1 60x bus clock 12 15a 16 16 all non-pci ts artry vm vm vm = midpoint voltage (1.4v) 15a vm 18 14 13a 13 21 19 (except ts and artry ) sysclk 12 15b all vm vm 14 outputs 13b pci outputs
tsi106 powerpc host bridge hardware specifications manual 17 80c1000_ma002_02 electrical and thermal characteristics figure 6 provides the jtag clock input timing diagram. figure 6. jtag clock input timing diagram figure 7 provides the trst timing diagram. figure 7. trst timing diagram 6 boundary-scan input da ta setup time 5 ? ns 3 7 boundary-scan input da ta hold time 15 ? ns 3 8 tck to output data valid 0 30 ns 4 9 tck to output high impedance 0 30 ns 4 10 tms, tdi data setup time 5 ? ns ? 11 tms, tdi data hold time 15 ? ns 1 12 tck to tdo data valid 0 15 ns ? 13 tck to tdo high impedance 0 15 ns ? notes : 1 these values are guaranteed by design, and are not tested. 2 trst is an asynchronous signal. the set up time is for te st purposes only. 3 non-test signal input timi ng with respect to tck. 4 non-test signal output timin g with respect to tck. table 9. jtag ac timing specifications (independent of sysclk) (continued) num characteristic min max unit notes tck 2 2 1 3 3 vm = midpoint voltage (1.4 v) vm vm vm 4 5 trst tck
18 tsi106 powerpc host bridge hardware specifications manual 80c1000_ma002_02 electrical and thermal characteristics figure 8 provides the boundary-scan timing diagram. figure 8. boundary-scan timing diagram figure 9 provides the test access port timing diagram. figure 9. test access port timing diagram 6 7 input data valid 8 9 8 output data valid output data valid tck data inputs data outputs data outputs data outputs 10 11 input data valid 12 13 12 output data valid output data valid tck tdi, tms tdo tdo tdo
tsi106 powerpc host bridge hardware specifications manual 19 80c1000_ma002_02 pin assignments 1.5 pin assignments figure 10 contains the pin assign ments for the tsi106, and figure 11 provides a key to the shading. figure 11. pin assignments shading key 16151413121110987654321 w dl26 dl28 dl30 dh31 dh29 dh27 dh25 dh23 dh21 dh19 dh17 dh15 dh13 dh11 dh9 dh7 w v dl24 dl27 dl29 dl31 dh30 dh28 dh26 dh24 dh20 dh18 dh16 dh14 dh12 dh10 dh8 dl22 v u ma1/ sdba0/ ar9 dl23 dl25 dl14 pll2 pll0 dl12 dl10 dl4 dl2 dl0 doe / dbgl2 toe dbg1 dh6 dl21 dl20 u t ma2/ sdma2/ ar10 we dh0 dl15 pll3 pll1 dl13 dl11 dl3 dl1 tv/ br2 ba0/ br3 hit dirty_in / br1 dl19 dcs / bg3 t r ma3/ sdma3/ ar11 rcs0 dh2 dh1 dl16 vss vdd dl9 dl5 vss vdd twe / bg2 dirty_out / bg1 ads / dale/ brl2 a0 ts r p ma5/ sdma5/ ar13 ma4/ sdma4/ ar12 dh4 dh3 vss vdd vss dl8 dl6 vdd vss vdd ba1/ baa / bgl2 dwe0 / dbg2 a1 xats /sdma 1 p n ma6/ sdma6/ ar14 ma0/ sdba1/ sdma0/ ar0 dl17 dh5 vdd vss vdd dl7 dh22 vss vdd vss lbclaim ci a2 ta n m ma8/ sdma8/ ar16 ma7/ sdma7/ ar15 ras0 / cs0 dl18 vss vdd vss nc nc vdd vss vdd wt gbl a3 tt4 m l hrst ma9/ sdma9/ ar17 qack ras1 / cs1 vdd cko/ dwe2 ras5 / cs5 vss vdd vss sysclk dbg0 tbst br0 a4 tt3 l k ma11/ sdma11/ ar19 ma10/ sdma10/ ar18 ras3 / cs3 ras2 / cs2 ras4 / cs4 ras7 / cs7 vdd avdd vss vdda9a8a7bg0 a5 tt2 k j ma12/ sdma12/ ar20 cas0 / dqm0 ppen rcs1 ras6 / cs6 mcp dbglb / cke vss vdd vss a11 a6 a13 a12 a10 tea j h qreq cas1 / dqm1 suspend trst vss dwe1 / dbg3 pirq / sdras nc nc vdd vss vdda15a14a16tt1 h g cas2 / dqm2 rtc cas4 / dqm4 cas5 / dqm5 vdd lssd_mode vdd par lock vss vdd vss tsiz1 tsiz0 a17 tt0 g f bctl0 bctl1 cas6 / dqm6 tck vss vdd vss perr devsel vdd vss vdd a21 tsiz2 artry a18 f e cas3 / dqm3 nmi cas7 / dqm7 mdle / sdcas tdo vss vdd serr irdy vss vdd a31 a29 a22 a20 a19 e d par0/ ar1 par1/ ar2 tms foe ad28 ad24 ad21 ad17 ad14 ad10 c/be0 ad4 ad0 a30 aack a23 d c par2/ ar3 par3/ ar4 par5/ ar6 ad30 ad26 ad23 ad19 c/be2 c/be1 ad12 ad8 ad6 ad2 a27 a25 a24 c b par4/ ar5 par7/ ar8 ad1 tdi ad7 ad11 ad15 trdy ad18 ad22 ad25 ad29 req isa_master / berr a28 a26 b a par6/ ar7 gnt ad3 ad5 ad9 ad13 frame stop ad16 ad20 c/be3 ad27 ad31 flshreq memack a 16151413121110987654321 figure 10. pin assignments nc vss vdd no connect power supply ground power supply positive av d d clock power supply positive (k9) view signals
20 tsi106 powerpc host bridge hardware specifications manual 80c1000_ma002_02 pinout listings 1.6 pinout listings table 10 provides the pinout listing for the tsi106. some signals have dual functions and are shown more than once. table 10. pinout listing signal name pin number active i/o 60x processor interface signals a[0?31] r2, p2, n2, m2, l2, k2, j5, k4, k5, k6, j2, j6, j3, j4, h3, h4, h2, g2, f1, e1, e2, f4, e3, d1, c1, c2, b1, c3, b2, e4, d3, e5 high i/o aack d2 low i/o artry f2 low i/o bg0 k3 low output bg1 (dirty_out ) r4 low output bg2 (twe) r5 low output bg3 (dcs ) t1 low output br0 l3 low input br1 (dirty_in ) t3 low input br2 (tv) t6 low input br3 (ba0) t5 low input ci n3 low i/o dbg0 l5 low output dbg1 (toe ) u4 low output dbg2 (dwe0 ) p3 low output dbg3 (dwe1 ) h11 low output dbglb (cke) j10 low output dh[0?31] t14, r13, r14, p13, p14, n 13, u3, w1, v2, w2, v3, w3, v4, w4, v5, w5, v6, w6, v7, w7, v8, w8, n8, w9, v9, w10, v10, w11, v11, w12, v12, w13 high i/o dl[0?31] u6, t7, u7, t8, u8, r8, p8, n9 , p9, r9, u9, t9, u10, t10, u13, t13, r12, n14, m13, t2, u1, u2, v1, u15, v16, u14, w16, v15, w15, v14, w14, v13 high i/o gbl m3 low i/o lbclaim n4 low input
tsi106 powerpc host bridge hardware specifications manual 21 80c1000_ma002_02 pinout listings mcp j11 low output ta n1 low i/o tbst l4 low i/o tea j1 low output ts r1 low i/o tsiz[0?2] g3, g4, f3 high i/o tt[0?4] g1, h1, k1, l1, m1 high i/o wt m4 low i/o xats (sdma1) p1 low input l2 cache interface signals ads /dale /brl2 r3 low i/o ba0 (br3 ) t5 low output ba1/baa /bgl2 p4 low output dbgl2 /doe u5 low output dcs (bg3 ) t1 low output dirty_in (br1 ) t3 low input dirty_out (bg1 ) r4 low output dwe0 (dbg2 ) p3 low output dwe1 (dbg3) h11 low output dwe2 (cko) l11 low output hit t4 low input toe (dbg1 ) u4 low output tv (br2 ) t6 high i/o twe (bg2 ) r5 low output memory interface signals bctl [0?1] f16, f15 low output berr (isa_master ) b3 low input cas /dqm[0?7] j15, h15, g16, e16, g14, g13, f14, e14 low output table 10. pinout listing (continued) signal name pin number active i/o
22 tsi106 powerpc host bridge hardware specifications manual 80c1000_ma002_02 pinout listings cke/dbglb j10 high output foe d13 low output ma0/sdba1/sdma0/ar0 n15 high output sdma1 (xats ) p1 high output ma1/sdba0/ar9 u16 high output ma[2?12]/sdma[2?12]/ar [10?20] t16, r16, p15, p16, n16, m15, m16, l15, k15, k16, j16 high output mdle /sdcas e13 low output par[0?7]/ar[1?8] d16, d15, c16, c 15, b16, c14, a16, b15 high i/o ppen j14 low output ras /cs [0?7] m14, l13, k13, k14, k12, l10, j12, k11 low output rcs0 r15 low i/o rcs1 j13 low output rtc g15 high input sdras (pirq ) h10 low output we t15 low output pci interface signals1 ad[31?0] a4, c13, b5, d12, a5, c12, b6, d11, c11, b7, d10, a7, c10, b8, d9, a8, b10, d8, a11, c7, b11, d7, a12, c6, b12, c5, a13, d5, a14, c4, b14, d4 high i/o c/be [3?0] a6, c9, c8, d6 low i/o devsel f8 low i/o flshreq a3 low input frame a10 low i/o gnt a15 low input irdy e8 low i/o isa_master (berr) b3 low input lock g8 low input memack a2 low output par g9 high i/o perr f9 low i/o pirq (sdras ) h10 low output req b4 low output serr e9 low i/o table 10. pinout listing (continued) signal name pin number active i/o
tsi106 powerpc host bridge hardware specifications manual 23 80c1000_ma002_02 pinout listings stop a9 low i/o trdy b9 low i/o interrupt, clock, and power management signals cko (dwe2 ) l11 high output hrst l16 low input nmi e15 high input qack l14 low output qreq h16 low input sysclk l6 clock input suspend h14 low input test/configuration signals pll[0?3] u11, t11, u12, t12 high input tck f13 clock input tdi b13 high input tdo e12 high output tms d14 high input trst h13 low input power and ground signals avdd k9 high clock power lssd_mode 2 g11 low input vdd e10, e6, f11, f5, f7, g10, g12, g6, h5, h7, k10, k7, l12, m11, m5, m7, n10, n12, n6, p11, p5, p7, r10, r6, j8, l8 high power vss e11, e7, f10, f12, f6, g5, g7, h12, h6, j7, l7, m10, m12, m6, n11, n5, n7, p10, p12, p6, r11, r7, k8, j9, l9 low ground nc h8, h9, m8, m9 ? ? note: 1 all pci signals are in little-endian bit order. 2 this test signal is for factory use only. it must be pulled up to vdd for normal device operation. table 10. pinout listing (continued) signal name pin number active i/o
24 tsi106 powerpc host bridge hardware specifications manual 80c1000_ma002_02 package description 1.7 package description the following sections provide the package parameters and the mechanical dimensions for the tsi106. 1.7.1 package parameters the package parameters are as provided in the followi ng list. the package type is a 21 mm x 25 mm, 304-lead c4 ceramic ba ll grid array (cbga). package outline 21 mm x 25 mm interconnects 303 (16 x 19 ball array minus one) pitch 1.27 mm solder balls 10/90 sn/pb, 0.89 mm diameter maximum module height 3.16 mm co-planarity specification 0.15 mm
tsi106 powerpc host bridge hardware specifications manual 25 80c1000_ma002_02 package description 1.7.2 mechanical dimensions figure 12 shows the mechanical dimensions for the tsi106. figure 12. mechanical dimensions c a1 0.200 2x 0.200 2x ? e ? ? f ? 0.150 ? t ? t h g k ? 0.300 12 345678910111213141516 w v u t r p n m l k j h g f e d c b a 303x ? d s t s e s f ? 0.150 s t *not to scale note: all measurements are in mm. min max a 25.0 basic b 21.0 basic c2.3 3.16 d0.82 0.93 g1.27 basic h0.79 0.99 k 0.635 basic n 5.8 6.0 p 7.2 7.4 top view bottom view p b a n
26 tsi106 powerpc host bridge hardware specifications manual 80c1000_ma002_02 system design information 1.8 system design information this section provides electrical and thermal design recommendations for successful application of the tsi106. 1.8.1 pll configuration the tsi106 requires a single syst em clock input, sysclk. the sysc lk frequency dictates the frequency of operation for the pc i bus. an internal pll on the tsi106 generate s a master clock that is used for all of the internal (core) logic. the master clock provides th e core frequency reference and is phase-locked to the sysclk input. the 60x processor, l2 cache, and memory interfaces opera te at the core frequency. in the 5:2 clock mode (rev. 4.0 only), the tsi106 n eeds to sample the 60x bu s clock (on the lbclaim configuration input) to resolve clock ph asing with the pci bus clock (sysclk). the pll is configured by the pll[0?3] signals. for a given sy sclk (pci bus) frequency, the clock mode configuration signals (pll[0?3]) set the core frequency (and the frequen cy of the vco controlling the pll lock). the supported core and vco frequencies and the corresponding pll[0?3] settings are provided in table 11. table 11. pll configuration pll[0?3] 1 core/sysclk ratio vco multiplier core frequency (vco frequency) in mhz pci bus 16.6 mhz pci bus 20 mhz pci bus 25 mhz pci bus 33.3 mhz 0001 1:1 x4 ? ? ? 33.3 (133) 0100 2:1 x2 ? ? ? 66.6 (133) 0101 2:1 x4 33.3 (133) 40 (160) 50 (200) ? 0110 5:2 2 x2 ? ? ? 83.3 (166) 0111 5:2 2 x4 41.6 (166) ? ? ? 1000 3:1 x2 ? 60(120) 75 (150) ? 0011 pll-bypass 3 pll off sysclk clocks core circuitry directly 1x core/sysclk ratio implied 1111 clock off 4 pll off no core clocking occurs notes : 1 pll[0?3] settings not listed are reserved . some pll configurations may select bu s, cpu, or vco frequencies which are not useful, not supported, or not tested . see section 1.4.2.1, ?clock ac specifications,? for valid sysclk and vco frequencies. 2 5:2 clock modes are only supported by tsi 106 rev 4.0; earlier revisions do not su pport 5:2 clock modes. the 5:2 modes require a 60x bus clock applied to the 60x clock phase (lbclaim ) configuration input signal during power-on reset, hard reset, and coming out of sl eep and suspend power-saving modes. 3 in pll-bypass mode, the sysclk input si gnal clocks the internal circuitry di rectly, the pll is disabled, and the core/sysclk ratio is set for 1:1 mode ope ration. this mode is intended for fact ory use and third-party tool vendors only. note also : the ac timing specifications given in this document do not apply in pll-bypass mode. 4 in clock-off mode, no clocking occurs inside the tsi106 regardless of the sysclk input.
tsi106 powerpc host bridge hardware specifications manual 27 80c1000_ma002_02 system design information 1.8.2 pll power supply filtering the avdd power signal is provided on the tsi106 to provide power to the clock generation phase-locked loop. to ensure stability of the internal clock, th e power supplied to the av dd input signal should be filtered using a circuit similar to the one shown in figure 13. the circuit should be placed as close as possible to the avdd pin to ensure it fi lters out as much noise as possible. figure 13. pll power supply filter circuit 1.8.3 decoupling recommendations due to the tsi106?s large address and data buses and high operating frequencies, it can generate transient power surges and high frequency noise in its power su pply, especially while driving large capacitive loads. this noise must be prevented from reaching other comp onents in the syst em, and the tsi106 itself requires a clean, tightly regulated source of power. it is strongly reco mmended that the system design include six to eight 0.1 f (ceramic) and 10 f (tantalum) decoupling capacitors to provide both high- and low-frequ ency filtering. these capacitors should be placed closely around the perimeter of the tsi106 package (or on the underside of the pcb). it is also recommended that these decoupling capacitors receive their power from separate vdd and gnd power planes in the pcb, utilizing short traces to minimize inductance. only surface mount technology (smt) capacitors should be us ed to minimize lead inductance. in addition, it is recommended that there be several bulk storage capa citors distributed around the pcb, feeding the vdd plane, to enable qu ick recharging of the smaller chip capacitors. these bulk capacitors should have a low equivalent series resistance (esr ) rating to ensure the quick response time necessary. they should also be connected to the power and gr ound planes through two vias to minimize inductance. suggested bulk capacitors?100 f (avx tps tantalum) or 330 f (avx tps tantalum). 1.8.4 connection recommendations to ensure reliable operation, it is recommended to connect unused inputs to an appropriate signal level. unused active low inputs shou ld be tied (using pull-up resistors) to vdd. unused active high inputs should be tied (using pull-down resistors) to gnd. all no-connect (nc) signals must remain unconnected. power and ground connections must be made to all external vdd, avdd, and gnd pins of the tsi106. 1.8.4.1 pull-up resistor recommendations the tsi106 requires pull-up (or pull-down) resistors on several control signals of the 60x and pci buses to maintain the control signals in the negated state after they have been actively negated and released by the tsi106 or other bus masters. the jtag test reset signal, trst , should be pulled down during normal system operation. also, as indicated in table 10, the factory test signal, lssd_mode , must be pulled up for normal device operation during inactive periods on the bus, the address and transfer attributes on the bus (a[0?31], tt[0?4], tbst , wt , ci , and gbl ) are not driven by any master and ma y float in the high-impedance state for relatively long periods of time. si nce the tsi106 must co ntinually monitor the se signals, this float vdd avdd 10 10 f 0 . 1 f gnd (3.3 v)
28 tsi106 powerpc host bridge hardware specifications manual 80c1000_ma002_02 system design information condition may cause excessive power draw by the input receivers on the tsi1 06 or by other receivers in the system. it is recommended that these signals be pulle d up or restored in some manner by the system. the 60x data bus input receivers on the tsi106 do no t require pull-up resistors on the data bus signals (dh[0?31], dl[0?31], and par[0?7]). however, other data bus receivers in the system may require pull-up resistors on these signals. in general, the 60x address and control signals are pu lled up to 3.3 vdc and the pci control signals are pulled up to 5 vdc through weak (2?10 k ) resistors. resistor values may need to be adjusted stronger to reduce induced noise on specific board designs. table 12 summarizes the pull-up/pull-down recommendations for the tsi106. 1.8.5 thermal mana gement information this section provides thermal manage ment information for the c4/cbga package. proper thermal control design is primarily dependent on the system-level design. the use of c4 die on a cbga interconnect technology of fers significant reduction in both the signal delay and the microelectronic packagin g volume. figure 14 shows the salient features of the c4/cbga interconnect technology. the c4 interconnection provides both th e electrical and the mechanical connections for the die to the ceramic substrate. after the c4 solder bump is re flowed, epoxy (encapsulant) is under-filled between the die and the substrate. under-fill material is co mmonly used on large high-power die; however, this is not a requiremen t of the c4 technology. the package substrate is a multilayer-cofired ceramic. the package-to-board inte rconnection is by an a rray of orthogonal 90/10 (lead/tin) solder balls on 1.27 mm pitch. during assembly of the c4 /cbga package to the board, the high-melt balls do not collapse. table 12. pull-up/pull-down recommendations signal type signals pull-up/pull-down 60x bus control br n ts , xats , aack artry ta pull up to 3.3 vdc 60x bus address/transfer attributes a[0?31], tt[0?4], tbst wt , ci , gbl pull up to 3.3 vdc cache control ads pull up to 3.3 vdc hit, tv pull up to 3.3 vdc or pull-down to gnd depending on programmed polarity pci bus control req frame , irdy devsel , trdy , stop serr , perr lock flshreq , isa_master . typically pull up to 5 vdc note: for closed systems not requiring 5v power, these may be pulled up to 3.3 vdc. jtag trst pull down to gnd (dur ing normal system operation) factory test lssd_mode pull up to 3.3 vdc
tsi106 powerpc host bridge hardware specifications manual 29 80c1000_ma002_02 system design information figure 14. exploded cross-sectional view 1.8.5.1 internal package conduction resistance for this c4/cbga packaging technolo gy, the intrinsic conduction ther mal resistance paths are as follows: ? the die junction-to-case thermal resistance ? the die junction-to-lead thermal resistance these parameters are shown in table 1 3. in this c4/cbga package, the s ilicon chip is exposed; therefore, the package ?case? is th e top of the silicon. figure 15 provides a simplified thermal network in which a c4/cbga package is mounted to a printed-circuit board. figure 15. c4/cbga package mounte d to a printed-circuit board table 13. thermal resistance thermal metric effective thermal resistance junction-to-case ther mal resistance 0.133 o c/w junction-to-lead (ball) thermal resistance 3.8 o c/w chip with c4 encapsulant ceramic substrate cbga joint printed-circuit board external resistance external resistance internal resistance (note the internal versus external package resistance) radiation convection radiation convection heat sink printed-circuit board thermal interface material package/leads die junction die/package
30 tsi106 powerpc host bridge hardware specifications manual 80c1000_ma002_02 system design information 1.8.5.2 board and system-level modeling a common figure-of-merit used fo r comparing the thermal performan ce of various microelectronic packaging technologies is the junc tion-to-ambient thermal resistance. the final chip-junction operating temperature is not only a function of the component-level thermal resi stance, but the system-level design and its operating conditions. in add ition to the component?s power consum ption, a number of factors affect the final operating die-junction te mperature. for example, these factors might include airflow, board population, heat sink efficiency, h eat sink attach, next-level interc onnect technology, and system air temperature rise. due to the complexity and the ma ny variations of system-level boundary conditio ns for today?s microelectronic equipment, the combined effects of the heat transfer mechanis ms (radiation, convection, and conduction) may vary widely. for this reason, we recommend using conjugate heat transfer models for the board as well as system-level designs. to expedi te system-level thermal an alysis, several ?compact? cbga thermal models are available on request within flotherm ? . the die junction-to-ambient thermal resistance is shown in table 14. the model results are in accordance with semi specification g38. this standard specifies a single component be placed on a 7.5 cm x 10 cm single-layer printed-circuit card. note that th is single metric may not adequately describe three-dimensional heat flow. table 14. die junction-to- ambient thermal resistance airflow velocity (meter/second) airflow velocity (feet/minute) die junction-to-ambient thermal resistance (semi g38) ( o c/w) 1 196.8 22.0 2 393.7 18.5 3 590.0 17.0
tsi106 powerpc host bridge hardware specifications manual 31 80c1000_ma002_02 ordering information 1.9 ordering information table 15 provides the tundra part-numbering nome nclature for the tsi106. in addition to the core frequency, the part numbering scheme also consists of a part modifier and app lication modifier. the part modifier indicates any enhancements in the part from the original productio n design. the application modifier may specify special bus frequencies or appli cation conditions. each part number also contains a revision code. this refers to the die mask revision number and is specified in the part-numbering scheme for identification purposes only. 1.9.1 extended temperature device this device differs slightly from the other tsi106 offerings. the ex tended temperature has different operating condition temperatur e requirements and vcd opera ting ranges (see table 16). 1.9.1.1 electrical and thermal characteristics this section provides any changes to the ac and dc electrical specifications and thermal characteristics for the tsi106 parts described herein. 1.9.1.1.1 dc electr ical characteristics the following table describes the changed thermal operating conditio ns for the tsi106 part numbers described herein. 1.9.1.1.2 clock ac specifications the following tables provides the revised vco ac tim ing specifications for the parts described herein. assume vdd = avdd = 3.3 5% v dc, ovdd = 3.3 5% v dc, gnd = 0 v dc, and -40 t j 105 o c. current tundra part number obsolete motorola part number operating condition tsi106g-66jb mpc106arx66cg 0 to 70oc tsi106g-66jbtr m pc106arx66cgr2 0 to 70oc tsi106g-66kb mpc106arx66tg -40 to 105oc tsi106g-83jb mpc106arx83dg 0 to 70oc TSI106G-83KB mpc106arx83tg -40 to 105oc table 15. part number key table 16. part numbers addressed by this part number specification tundra part number motorola part number operating condition significant differences t j ( o c) TSI106G-83KB mpc106arxtg -40 to 105 extended temperature; vcd operating range table 17. recommended operating conditions characteristic symbol value unit junction temperature t j -40 to 105 oc
32 tsi106 powerpc host bridge hardware specifications manual 80c1000_ma002_02 ordering information 1.9.1.1.3 pll configuration table 18. clock ac timing specifications num characteristic sysclk/core 33/66 mhz sysclk/core 33/83.3 mhz unit min max min max ? 60x processor bus (core) frequency 16.67 66 16.67 83.3 mhz ? vco frequency 150 400 150 400 mhz ? sysclk frequency 16. 67 33.33 16.67 33.33 mhz 1 sysclk cycle time 30.0 60.0 30.0 60.0 ns 2, 3 sysclk rise and fall time ? 2.0 ? 2.0 ns 4 sysclk duty cycle measured at 1.4 v 40 60 40 60 % ? sysclk jitter ? 200 ? 200 ps ? 106 internal pll relock time ? 100 ? 100 s table 19. pll configuration pll[0?3] 1 core/sysclk ratio vco multiplier core frequency (vco frequency) in mhz pci bus 16.6 mhz pci bus 20 mhz pci bus 25 mhz pci bus 33.3 mhz 0010 1:1 x8 ? ? ? 33.3 (266) 0101 2:1 x4 ? 40 (160) 50 (200) 66.6 (266) 0110 5:2 2 x2 ? ? ? 83.3 (166) 0111 5:2 2 x4 41.6 (166) 50 (200) 62.5 (250) 83.3 (333) 1000 3:1 x2 ? ? 75 (150) ? 1001 3:1 x4 ? 60 (240) 75 (300) ? 0011 pll-bypass 3 pll off sysclk clocks core circuitry directly 1x core/sysclk ratio implied 1111 clock off 4 pll off no core clocking occurs notes : 1 pll[0?3] settings not listed are reserved . some pll configurations may select bu s, cpu, or vco frequencies which are not useful, not supported, or not tested . see section 1.4.2.1, ?clock ac specifications,? for valid sysclk and vco frequencies. 2 5:2 clock modes are only supported by tsi106; earlier revisi ons do not support 5:2 clock mo des. the 5:2 modes require a 60x bus clock applied to the 60x clock phase (lbclaim ) configuration input signal duri ng power-on reset, hard reset, and coming out of sleep and suspend power-saving modes. 3 in pll-bypass mode, the sysclk input si gnal clocks the internal circuitry di rectly, the pll is disabled, and the core/sysclk ratio is set for 1:1 mode ope ration. this mode is intended for fact ory use and third-party tool vendors only. note also : the ac timing specifications given in this document do not apply in pll-bypass mode. 4 in clock-off mode, no clocking occurs inside the tsi106 regardless of the sysclk input.

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