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technical note large current external fet contro ller type switching regulator dual-output, high voltage, high-efficiency step-down switching controller BD9012KV overview the BD9012KV is a 2-ch synchronous controller with rectific ation switching for enhanced power management efficiency. it supports a wide input range, enabling low power co nsumption ecodesign for an array of electronics. features 1) wide input voltage range: 4.5v to 30v 2) precision voltage references: 0.8v 1% 3) fet direct drive 4) rectification switching for increased efficiency 5) variable frequency: 250k to 1200k hz (external synchronization to 1200khz) 6) built-in selected auto remo ve over current protection 7) built-in independent power up/power down sequencing control 8) make various application , step-down , step-up and step-up-down 9) small footprint packages: vqfp48c applications car audio and navigation systems, crttv lcdtv pdptv stb dvd and pc systems portable cd and dvd players, etc. absolute maximum ratings (ta=25 ) parameter symbol limits unit parameter symbol limits unit vcc voltage vcc 34 *1 v vreg33 voltage vreg33 vreg5 v extvcc voltage extvcc 34 *1 v ss1,2 ? fb1,2 voltage ss1,2 ? fb1,2 vcccl1,2 voltage vcccl1,2 34 v comp1,2 voltage comp1,2 cl1,2 voltage cl1,2 34 v det1,2 voltage det1,2 sw1,2 voltage sw1,2 34 *1 v rt ? sync voltage rt ? sync boot1,2 voltage boot1,2 40 *1 v power dissipation pd 1.1 *2 w boot1,2-sw1,2 voltage boot1,2 -sw1,2 7 *1 v operating temperature range topr -40 to +105 stb, en1,2 voltage stb, en1,2 vcc v storage temperature range ts t g -55 to +150 vreg5,5a voltage vreg5,5a 7 *1 v maximum junction temperature tj +150 *1 regardless of the listed rating, do not exceed pd in any circumstances. *2 pd de-rated at 7mw/ for temperature above ta=25 , mounted on pcb 70mm70mm1.6mm. apr.2008
2/16 operating conditions (ta=25 ) parameter symbol min. typ. max. unit input voltage 1 extvcc 4.5 *1 *2 12 30 v input voltage 2 vcc 4.5 *1 *2 12 30 v boot sw voltage boot sw 4.5 5 vreg5 v carrier frequency osc 250 300 1200 khz synchronous frequency sync osc - 1200 *3*4 khz synchronous pulse duty duty 40 50 60 min off pulse tmin - 150 - nsec this product is not designed to prov ide resistance against radiation. *1 after more than 4.5v, voltage range. *2 in case of using less than 6v, short to vcc, extvcc and vreg5. *3 please do not exceed osc1.5. *4 do not do such things as switching over to internal o scillating frequency while external synchronization frequency is used. electrical characteristics (unless otherwise specified, ta=25 vcc=12v stb=5v en1,2=5v ) parameter symbol limit unit conditions min. typ. max. vin bias current iin - 6 10 ma shutdown mode current ist - 0 10 a vstb=0v error amp block feedback reference voltage vob 0.792 0.800 0.808 v feedback reference voltage (ta=-40 to 105 ) vob+ 0.784 0.800 0.816 v ta=-40 to 105 open circuit voltage gain averr - 46 - db vo input bias current ivo+ - - 1 a oscillator carrier frequency fosc 900 1000 1100 khz rt=27 k synchronous frequency fsync - 1200 - khz rt=27 k ,sync=1200khz over current protection block cl threshold voltage vswth 70 90 110 v cl threshold voltage ta=-40 to 105 vswth+ 67 90 113 v ta=-40 to 105 vreg block vreg5 output voltage vreg5 4.8 5 5.2 v iref=6ma vreg33 reference voltage vreg 33 3.0 3.3 3.6 v ireg=6ma vreg5 threshold voltage vreg_uvlo 2.6 2.8 3.0 v vreg:sweep down vreg5 hysteresis voltage dvreg_uvlo 50 100 200 mv vreg:sweep up soft start block charge current iss 6.5 10 13.5 a vss=1v charge current (ta=-40 to 105 ) iss+ 6 10 14 a vss=1v,ta=-40 to 105 note: not all shipped products are subject to outgoing inspection.
3/16 reference data (unless otherwise specified, ta=25 ) fig.1 efficiency 1 fig.4 reference voltage vs. temperature characteristics fig.5 over current detection vs. temperature characteristics fig.6 frequency vs. tem p erature characteristics 0.784 0.788 0.792 0.796 0.800 0.804 0.808 0.812 0.816 -40 -15 10 35 60 85 110 ambient temperature ta[] reference voltage vob[v] 60 70 80 90 100 110 -40 -15 10 35 60 85 110 ambient temperature ta[] ^??R vswth[mv] 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 -40 -15 10 35 60 85 110 ambient temperature ta[] output voltage vo[v] vreg5 vreg33 fig.7 internal reg vs. tem p erature characteristics fig.2 efficiency 2 0 1 2 3 4 5 6 0 5 10 15 20 25 input voltage v in [v] output voltage vo[v] 3.3v 5.0v fig.8 line regulation fig.9 load regulation 0 1 2 3 4 5 6 0246 input voltagev en [v] outputvoltage vo[v] 105 25 -40 fig.10 en threshold voltage fig.11 load transient response 1 fig.12 load transient response 2 0 1 2 3 4 5 6 0 102030 input voltagev in [v] circuitcurrent[ma] 105 25 -40 fig.3 circuit current v out v out i out i out 1a/div 50mv/div 1a/div 50mv/div 0 10 20 30 40 50 60 70 80 90 100 01 23 output currentio[a] efficiency[%] 3.3v 5.0v vin=12v 0 10 20 30 40 50 60 70 80 90 100 6 9 1215182124 input voltage v in [v] efficiency[%] 3.3v 5.0v io=2a rt=27k 90 0 92 0 94 0 96 0 98 0 100 0 102 0 104 0 106 0 108 0 110 0 -40 -1 5 10 35 6 0 8 5 11 0 ambient temperature ta[] osi l at in g f re qu e ncy f osc [khz] rt=27k 0.0 0.5 1.0 1.5 2.0 2.5 3.0 01 23 45 6 outpu t curr ent io [a] output voltage vo[v] r cl =15m
4/16 block diagram fig-13 tsd 5v reg 2.7v 3.3v reg tsd uvlo pw m comp err amp 0.8v sequence det uvlo fb2 ss2 comp2 det2 loff en2 en1 vreg5a extvcc stb vcc rt sync set q reset q reset set drv set reset vreg5 ocp uvlo tsd b.g sync osc slope pw m comp tsd uvlo q set reset drv set reset sw logic set q reset sequence det err amp 0.8v ocp slope gnd det1 sw logic outh1 sw1 outl1 dgnd1 ss1 comp1 boot1 cl1 vcccl1 vreg33 fb1 19 35 34 7 24 39 44 37 47 8 13 10 12 4(17) 3(15) 2(14) 23 21 22 11 3 5 2 1 48 38 46 41 25 33 29 26 27 31 36 30 (gnds) llm
5/16 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 outh2 boot2 cl2 n.c vcccl2 n.c vcc vcccl1 n.c cl1 boot1 outh1 21 20 19 18 17 16 15 14 13 24 23 22 fb1 n.c vreg33 n.c vreg5a n.c outl1 dgnd1 sw1 det1 ss1 comp1 27 26 25 37 38 39 n.c extvcc n.c n.c vreg5 n.c outl2 dgnd2 sw2 ss2 comp2 fb2 det2 llm sync rt loff gnds gnd n.c en2 en1 stb n.c pin configuration pin function table fig-15 block functional descriptions ? error amp the error amp compares output feedback voltage to the 0.8v refer ence voltage and provides the comparison result as comp voltage , which is used to determine the switching duty. comp voltage is limited to the ss voltage, since soft start at power up is based on ss pi n voltage. ? oscillator (osc) oscillation frequency is determined by the switching frequency pin (rt) in this block. the frequency can be set between 250khz and 550khz. ? slope the slope block uses the clock produced by the oscillator to genera te a triangular wave, and sends the wave to the pwm comparat or. ? pwm comp the pwm comparator determines switching duty by comparing the comp voltage, output from the error amp, with the triangular wave from the slope block. switching duty is limited to a percentage of the in ternal maximum duty, and thus cannot be 100% of the maximum. ? reference voltage (5vreg 33vreg) this block generates the internal reference voltages: 5v and 3.3v. ? external synchronization (sync) determines the switching frequency, based on the external pulse applied. ? over current protection (ocp) over current protection is activated when the vcccl-cl voltage re aches or exceeds 90mv. when over current protection is active, duty is low, and output voltage also decreases. when loff=l, the output voltage has fallen to 70% or below and output is latched off. the of f latch mode ends when the latch is set to stb, en. ? sequence control (sequence det) compares fb voltage with reference voltage (0.56v) and outputs the result as det. ? protection circuits (uvlo/tsd) the uvlo lock out function is activated when vreg falls to about 2.8v, while tsd turns outputs off when the chip temperature re aches or exceeds 150 . output is restored when temperature falls back below the threshold value. pin no. pin name function 1 outh2 high side fet gate drive pin 2 2 boot2 outh2 driver power pin 3 cl2 over current detection pin 2 4 n.c non-connect (unused) pin 5 vcccl2 over current detection vcc2 6 n.c non-connect (unused) pin 7 vcc input power pin 8 vcccl1 over current detection cc1 9 n.c non-connect (unused) pin 10 cl1 over current detection setting pin 1 11 boot1 outh1 driver power pin 12 outh1 high side fet gate drive pin 1 13 sw1 high side fet source pin 1 14 dgnd1 low side fet source pin 1 15 outl1 low side fet gate drive pin 1 16 n.c non-connect (unused) pin 17 vreg5a fet drive reg input 18 n.c non-connect (unused) pin 19 vreg33 reference input reg output 20 n.c non-connect (unused) pin 21 fb1 error amp input 1 22 comp1 error amp output 1 23 ss1 soft start setting pin 1 24 det1 fb detector output 1 25 stb standby on/off pin 26 en1 output 1 on/off pin 27 en2 output 2 on/off pin 28 n.c non-connect (unused) pin 29 gnd ground 30 gnds sense ground 31 loff test mode terminal 32 n.c non-connect (unused) pin 33 rt switching frequency setting pin 34 sync external synchronous pulse input pin 35 llm built-in pull-down resistor pin 36 det2 fb detector output 2 37 ss2 soft start setting pin 2 38 comp2 error amp output 2 39 fb2 error amp input 2 40 n.c non-connect (unused) pin 41 extvcc external power input pin 42 n.c non-connect (unused) pin 43 n.c non-connect (unused) pin 44 vreg5 fet drive reg output 45 n.c non-connect (unused) pin 46 outl2 low side fet gate drive pin 2 47 dgnd2 low side fet source pin 2 48 sw2 high side fet source pin 2
6/16 application circuit example (parentheses indicate vqfp48c pin numbers) fig-16b step-down cout=ceramic capacitor there are many factors(the pcb board layout, output curr ent, etc.)that can affect t he dcdc characteristics. please verify and confirm using practical applications. sw1 dgnd1 outl1 vreg5a vreg33 fb1 comp1 ss1 det1 stb en1 en2 gnd loff rt sync llm sw2 det2 dgnd2 outl2 vreg5 extvcc fb2 comp2 ss2 outh1 boot1 cl1 vcccl1 vcc vcccl2 cl2 boot2 outh2 0.1uf 1uf 1uf 1k 10000pf 0.1uf 0.33 uf 10 23m 23m 0.33uf 1uf 3.3k 3300pf 20k 43 k 12k vo(1.8v/2a) rb051 l-40 rb051 l-40 10uh vo(2.5v/2a) sp8k2 sp8k2 vin(12v) 31 (5) 27 (48) 0.1 uf 0.1 uf 36 (12) 35 (11 ) 33 (8) 32 (7) 30 (3) 29 (2) 28 (1) 26 (47) 24 (44) 22 (41) 21 (39) 20 (38) 19 (37) 18 (36) 17 (35) 15 (33) 14 (31) 13 (29) 1 (13) 3 (15) 4 (17) 5 (19) 6 (21) 7 (22) 9 (24) 2 (14) 25 (46) 8 (23) 23 100 1nf 1nf 100 330pf 15k 150 3300pf 330pf 1000pf 510 10uh rb160 va-40 rb160 va-40 34 (10) 100uf 100k 16 (34) 12 (27) 11 (26) 10 (25) 30uf (c2012jb 0j106k tdk) 30uf (c2012jb 0j106k tdk) (slf10145 tdk) (slf10145 tdk)
7/16 vcc-vout vout l vcc f il = [a] ??? 5 vcc-vout vout il vcc f l = [h] ??? 7 fig-17 vout vcc - vout vcc irms = iout [a] ?? ? 10 application component selection (1) setting the output l value the coil value significantly influences the output ripple current. thus, as seen in equation (5), the larger the coil, and the higher the switching frequency, the lowe r the drop in ripple current. the optimal output ripple current setting is 30% of maximum current. il = 0.3 ioutmax.[a] ??? 6 il output ripple current f switching frequency outputting a current in excess of the coil current rating will cause magnetic saturation of the coil and decrease efficiency. please establish sufficient margin to ensure that peak current does not exceed the coil current rating. use low resistance (dcr, acr) coils to minimize coil loss and increase efficiency. (2) setting the output capacitor co value select the output capacitor with the highest value for ripple voltage (v pp ) tolerance and maximum drop voltage (at rapid load change). the following equation is used to determine the output ripple voltage. i l vo 1 step down v pp = i l r esr + [v] note: f switching frequency co vcc f be sure to keep the output co setting within the allowable ripple voltage range. please allow sufficient output voltage margin in establishing the capacitor rating. note that low-esr capacitors enable lower output ripple voltage. also, to meet the requirement for setting t he output startup time parameter within th e soft start time range, please factor in the conditions described in the capacitance equation (9) for output capacitors, below. tss (limit ? iout) tss soft start time co Q ??? 9 vout ilimit over current detection value 2/16 reference note: less than optimal capacitance values may cause problems at startup. (3) input capacitor selection the input capacitor serves to lower the output impedance of the power source connected to the input pin (vcc). increased power supply output impedance can cause input voltage (v cc) instability, and may negatively impact oscillation and ripple rejecti on characteristics. therefore, be certain to establish an input capacitor in close proximity to the vcc and gnd pins. select a low-esr capacitor with the required ripple current capacity and the capability to withstand temperature changes without wide tolerance fluctuations. the ripple current irmss is determined using equation (10). also, be certain to ascertain the op erating temperature, load range and mosfet conditions for the application in which the capacitor will be used, since capacitor performance is heav ily dependent on the application?s input power characteristics, subs trate wiring and mosfet gate drain capacity. l vin vout co cin i l output ripple current i l vcc co l vout fig-18 input capacitor fig-19
8/16 vo r8 r9 internal ref. 0.8v fb (4) feedback resistor design please refer to the following equation in determining the pro per feedback resistance. the recommended setting is in a range between 10k and 330k . resistance less than 10k risks decreased power efficiency, while setting the resistance value higher than 330k will result in an internal error amp input bias current of 0.2ua increasing the offset vo ltage. please use it with 150nsec or more so that there is a possibility that the output becomes unstable when the output pulse width is small. 12 r8 +r9 vo = 0.8 [v] ??? 11 r9 vo 1 R 150ns ??? 12 fig-20 vin f (5) setting switching frequency the triangular wave switching frequency can be set by connecting a resistor to the rt 15(33) pin. the rt sets the frequency by adjusting the charge/discharge current in relation to the inte rnal capacitor. refer to the figure below in determining prope r rt resistance, noting that the recommended resistance setting is between 50k and 130k . settings outside this range may render the switching function inoperable, and proper oper ation of the controller overa ll cannot be guaranteed when unsupported resistance values are used. fig-21 rt vs. switching frequency (6) setting the soft start delay the soft start function is necessary to prevent an inrush of coil current and output voltage over shoot at startup. the figure below shows the relation between soft start delay time and capacitance, which can be calculated using equation (12) at right. 0.8v(typ.) css tss = [sec] ??? (12) iss(10 a typ.) fig-22 ss capacitance vs. delay time recommended capacitance values are between 0.01uf and 0. 1uf. capacitance lower than 0.01uf may generate output overshoots. please use high accuracy components (such as x5r) when implementing sequential startups involving other power sources. be sure to test the actual devices and applicat ions to be used, since the soft start time varies, depending on input voltage, output voltage and capaci tance, coils and other characteristics. 0.01 0.1 1 10 0.001 0.01 0.1 ss capacitance[uf] delay time[ms]
9/16 over current detection point i l a comp fb c r feedback l vin i l vo vcccl cl rcl -18 0 -9 0 0 90 18 0 a 0 0 -90 -180 (a) gbw(b) -180 phase margin -90 -20db/decade gain [db] phase [deg] 1 2 rca point (a) fa = 1.25[hz] 1 2 rc point (b) fa = gbw [hz] (7) setting over current detection values the current limit value ilimit is determined by the resistance of the rcl established between cl and vcccl. 90m ilimit = [a] ??? (13) rcl fig-23 fig-24 when the current goes beyond the threshold va lue, the current can be limited by reduci ng the on duty cycle. when the load goes back to the normal operation, the output voltage also becomes back on to the specific level. (8) method for determining phase compensation conditions for application stability feedback stability conditions are as follows: ? when gain is 1 (0db) and phase shift is 150 or less (i.e., phase margin is at least 30): a dual-output high-frequency step-down switching regulator is required additionally, in dc/dc applications, sampling is based on the switching frequency; therefore, overall gbw may be set at no more than 1/10 the switching frequency. in summary, target characteristics fo r application stability are: ? phase shift of 150 or less (i.e., phase margin of 30 or more) with gain of 1 (0db) ? gbw (i.e., gain 0db frequency) no more than 1/10 the switching frequency. stability conditions mandate a relatively higher switching fre quency, in order to limit gbw enough to increase response. the key to achieving successful stabilization using phase co mpensation is to cancel the secondary phase margin/delay (-180) generated by lc resonance, by employing a dual phase lead. in short, adding two phase leads stabilizes the application. gbw (the frequency at gain 1) is determined by the phase compensati on capacitor connected to the error amp. thus, a larger capacitor will serve to lower gbw if desired. general use integrator (low-pass filter) integrator open loop characteristics fig-26 fig-27 the error amp is provided with phase compensation similar to that depicted in figures and above and thus serves as the system?s low-pass filter. in dc/dc converter applications, r is establ ished parallel to the feedback resistance. the current limit value io v o fig-25
10/16 fb r2 a comp vo c2 c1 r1 fb r2 a comp vo c2 r1 r3 1 2 lc fr = [hz] resonance point phase margin -180 resonance point1 2 lc fr = [hz] resonance point f esr = [hz] :zero 1 2 r esr c -90 :pole fig-28 fig-29 fig-32 1 2 lc when electrolytic or other high-esr output capacitors are used: phase compensation is relatively simple for applications empl oying high-esr output capacitors (on the order of several ). in dc/dc converter applications, where lc resonance circ uits are always incorporated, the phase margin at these locations is -180. however, wherever esr is present, a 90 phase lead is generated, limiting t he net phase margin to -90 in the presence of esr. since the desired phase margin is in a range less than 150, this is a highly advantageous approach in terms of the phase margin. however, it also has t he drawback of increasing output voltage ripple components. lc resonance circuit esr connected since esr changes the phase characteristics, only one phase le ad need be provided for high-esr applications. please choose one of the following methods to add the phase lead. add c to feedback resistor add r3 to aggregator fig-30 fig-31 phase lead fz = [hz] phase lead fz = [hz] set the phase lead frequency close to the lc resonanc e frequency in order to cancel the lc resonance. when using ceramic, os-con, or other low- esr capacitors for the output capacitor: where low-esr (on the order of tens of m ) output capacitors are employed, a two phase-lead insertion scheme is required, but this is different fr om the approach described in figure ~ , since in this case the lc resonance gives rise to a 180 phase margin/delay. here, a phase compensation method such as that shown in figure below can be implemented. phase compensation provided by secondary (dual) phase lead phase lead fz1 = [hz] phase lead fz2 = [hz] lc resonance frequency fr = [hz] once the phase-lead frequency is determined, it should be set close to the lc resonance frequency. this technique simplifies the phase topology of the dcdc converter. therefore, it might need a certain amount of trial-and-error process. there ar e many factors(the pcb board layout, ou tput current, etc.)that can affect the dcdc characteristics. please verify an d confirm using practical applications. 1 2 c1r1 1 2 c2r3 vcc vo l c vcc vo l c r esr 1 2 r1c1 1 2 r3c2 fb r2 a comp vo c2 r1 r3 c1
11/16 vo1 vcc vreg5 vreg5 outh1 boot1 vcc boot2 sw1 outl1 dgnd1 fb1 vo2 comp1 ss1 det2 outh2 outl2 sw2 dgnd2 fb2 comp2 ss2 det1 stb en1 en2 gnd 9 mosfet selection fet uses nch mos ? v ds vcc ? v gsm1 boot-sw interval voltage ? v gsm2 vreg5 ? allowable current voltage current + ripple current should be at least the over current protection value select a low on-resistance mosfet for highest efficiency fig-33 ? the shoot-through may happen when the input parasitic capacitance of fet is extremely big or the duty ratio is less than or equal to 10%. less than or equal to 1000pf input parasitic capacitance is recommended. please confirm operation on the actual application since this character is affected by pcb layout and components. 10 schottky barrier diode selection ? reverse voltage v r vcc ? allowable current voltage current + ripple current should be at least the over current protection value select a low forward voltage, fast recovery diode for highest efficiency 11 sequence function circuit diagram timing chart fig-35 fig-36 v cc i l vo v ds v gsm1 v gsm2 v ds v cc vo v r with en1, 2 at ?h? level, when en1 goes ?l?, vo1 turns off, but vo2 output continues. when en1 stays ?h? and en2 returns to ?h?, det1 is in open state; thus ss2 is asserted, and vo2 output starts. if vo2 is 76% of the voltage setting or higher, det2 goes open and ss1 is asserted, starting vo1 output. en1 en2 det2 ss1 fb1 vo1 det1 ss2 fb2 vo2 0.61v over 76% under 70% 0.56v 0.61v 0.56v over 76% over 70% with en1,2 at ?h? level, i f vo1 starts at 76% or more o f voltage setting, det goes open and ss1 is asserted, starting vo2 output. same as ?a? at left a with en2 set ?l?, if vo2 goes below 70% the voltage setting, det2 shorts and ss1 is asserted, turning vo1 off a fig-34
12/16 input/output equiv alent circuits 13 48pin sw1 sw2 2 11pin boot2 boot1 1 15pin outh1 outh2 14 47pin dgnd1 dgnd2 15 46pin outl1 outl2 44 17pin vreg5 vreg5a 31pin loff 34pin sync 21 39pin fb1 fb2 23 37pin ss1 ss2 25 26 27pin stb en1 en2 24 36pin det1 det2 33pin rt 35pin llm 3 10pin cl2 cl1 5 8pin vcccl2 vcccl1 22 38pin comp1 comp2 41pin extvcc 44pin vreg5 19pin vreg33 17pin vreg5a boot outh sw 300k outl dgnd loff 100k 135.8k 172.2k v reg5 fb vreg5 / vreg5a 1k 2.5 ss vreg5 / vreg5a 100k 50k 2k vcc stb en 172.2k 135.8k 100k det vreg5 / vreg5a 10k vreg5 rt sync 5k 250k v reg5 1p vreg5a llm 308k comp vreg5 / vreg5a 20 5k 5k vcc vreg5a extvcc vreg5 vcc vcc 150k 746.32k 255k vreg33 vreg5a vcc 150k 746.32k 469.06k vcccl vcc cl 5k 5p vcc 1k
13/16 n p + (pina) resistor parasitic element p p + gnd p n operation notes 1 absolute maximum ratings exceeding the absolute maximum ratings for supply voltage, operating temperature or other parameters can damage or destroy the ic. when this occurs, it is impossible to identify the source of the damage as a short circuit, open circuit, etc. therefore, if any special mode is bei ng considered with values expected to exceed absolute maximum ratings, consider taking physical safety measures to protect the circuits, such as adding fuses. 2 gnd electric potential keep the gnd terminal potential at the lowest (mi nimum) potential under any operating condition. 3 thermal design be sure that the thermal design allows sufficient margin for power dissipation (pd) under actual operating conditions. 4 inter-pin shorts and mounting errors use caution when positioning the ic for mounting on printed surf ace boards. connection errors may result in damage or destruction of the ic. the ic can also be damaged when fore ign substances short output pi ns together, or cause shorts between the power supply and gnd. 5 operation in strong el ectromagnetic fields use caution when operating in the presence of strong electromagnetic fields, as this may cause the ic to malfunction. 6 testing on application boards connecting a capacitor to a low impedance pin for testing on an application board may subject the ic to stress. be sure to discharge the capacitors after every test process or step. alwa ys turn the ic power supply off before connecting it to or removing it from any of the apparatus us ed during the testing process. in addition, ground the ic during all steps in the assembly process, and take similar antistatic pr ecautions when transporting or storing the ic. 7) the output fet the shoot-through may happen when the input parasitic capacitance of fet is extremely big or the duty ratio is less than or equal to 10%. less than or equal to 1000pf input parasi tic capacitance is recommended. please confirm operation on the actual application since this character is affected by pcb layout and components. 8 this monolithic ic contains p+ isolation and p substrate layers between adjacent elements in order to keep them isolated. p-n junctions are formed at the intersection of these p layers wi th the n layers of other elements, creating a parasitic diode or transistor. relations between each potential may form as sh own in the example below, where a resistor and transistor are connected to a pin: with the resistor, when gnd pin a, and with the transistor (npn), when gnd pin b: the p-n junction operates as a parasitic diode with the transistor (npn), when gnd pin b: the p-n junction operates as a parasitic transistor by intera cting with the n layers of elements in proximity to the parasitic diode described above. parasitic diodes inevitably occur in the structure of the ic. t heir operation can result in mut ual interference between circuit s, and can cause malfunctions, and, in turn, physical damage or dest ruction. therefore, do not employ any of the methods under which parasitic diodes can operate, such as applying a voltage to an input pin lower than the (p substrate) gnd. fig-37 fig-38 fig-39 fig-40 9 gnd wiring pattern when both a small-signal gnd and high curr ent gnd are present, single-point gr ounding (at the set standard point) is recommended, in order to separate the small-signal and high current patterns, and to be sure voltage changes stemming from the wiring resistance and high current do not cause any voltage change in the sma ll-signal gnd. in the same way, care must be taken to avoid wiring pattern fluctuati ons in any connected external component gnd. 10 in some application and process testing, vcc and pin potential may be reversed, possi bly causing internal circuit or element damage. for example, when the external capacitor is charged, t he electric charge can cause a vcc short circuit to the gnd. (pinb) transistor npn p + p + n n p substrate gnd n p c e b parasitic element or transistor gnd c b parasitic element or transisto r (pinb) e (pina) parasitic element
14/16 in order to avoid these problems, lim iting output pin capacitance to 100 f or less and inserting a vcc series countercurrent prevention diode or bypass diode between the various pins and the vcc is recommended. fig-41 11 thermal shutdown (tsd) this ic is provided with a built-in thermal shutdown (t sd) circuit, which is designed to prevent thermal damage to or destruction of the ic. normal operation should be within the power dissipation parameter, but if the ic should run beyond allowable pd for a continued period, junction temperature (tj) will rise, thus activating the tsd circuit, and turning all outp ut pins off. when tj again falls below the tsd threshold, circui ts are automatically restored to normal operation. note that the tsd circuit is only asserted beyond the absolute maximu m rating. therefore, under no circumstances should the tsd be used in set design or for any purpose ot her than protecting the ic against overheating 12 the sw pin when the sw pin is connected in an application, its coil count er-electromotive force may give rise to a single electric potential. when setting up the applicatio n, make sure that the sw pin never exceeds the absolute maximum value. connecting a resistor of several will reduce the electric potential. (see fig. 43) fig-42 13 dropout operation when input voltage falls below approximately output voltage / 0.9 (varying depending on operating frequency) the on interval on the outl side mos is lost, making boost applicat ions and wrap operation impossible. if a small differential between input and output voltage is envision ed for a prospective application, connec t the load such that the sw voltage drops to the gnd level. managing this load requires discharg ing the sw line capacitance (sw pin capacitance: approx. 500pf; outl side mos d-s capacitance; schottky capacitanc e). supported loads can be ca lculated using the equation below. output voltage sw line capacitance iload = 25n note that sw line capacitance is lower with smaller loads, and more stable operation is attained when low voltage bias circuits are configured as in the example below (fig. 44). however, the degree to which line capacitance is reduced or operational stability is attained will vary depending on the board layout and components. theref ore, be certain to confirm the effectiveness of these desi gn factors in actual operation before entering mass production. fig-43 vcc pin bypass diode countercurrent prevention diode out sw vcc vcc vreg vo out boot dgnd outl outh sw r vcc vo
15/16 14 logic of output when each function operates, each output is as follows. function upper side fet outh lower side fet outl en= l off l off l ocp off l on h uvlo off l off l tsd off l off l
16/16 vqfp48c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 25 50 75 100 125 150 ambient temperatoreta [] power dissipation pd [w] pd(w) 1.1w 0.75w power dissipation vs. temperature characteristics ? stand-alone ic ? mounted on rohm standard board 70mm x 70mm x 1.6mm glass-epoxy board part order number b d 9 0 1 2 k v e 2 rohm part code type/no. package type kv vqfp48c unit:mm) vqfp48c < packing information > when you order , please order in times the amount of package quantity. ta p e quantit y direction of feed embossed carrier tape 1500pcs (the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand) e2 reel 1pin direction of feed
notes no technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of rohm co.,ltd. the contents described herein are subject to change without notice. the specifications for the product described in this document are for reference only. upon actual use, therefore, please request that specifications to be separately delivered. application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. rohm co.,ltd. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by rohm co., ltd. is granted to any such buyer. products listed in this document are no antiradiation design. appendix1-rev2.0 thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact your nearest sales office. rohm customer support system the americas / europe / asia / japan contact us : webmaster@ rohm.co. jp www.rohm.com copyright ? 2008 rohm co.,ltd. the products listed in this document are designed to be used with ordinary electronic equipment or de vices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of which would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. it is our top priority to supply products with the utmost quality and reliability. however, there is always a chance of failure due to unexpected factors. therefore, please take into account the derating characteristics and allow for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in order to prevent possible accidents that may result in bodily harm or fire caused by component failure. rohm cannot be held responsible for any damages arising from the use of the products under conditions out of the range of the specifications or due to non-compliance with the notes specified in this catalog. 21 saiin mizosaki- cho, ukyo-ku, kyoto 615-8585, japan tel : +81-75-311-2121 fax : +81-75-315-0172 appendix

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