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freescale semiconductor advance information document number: mm912_637d1 rev. 3.0, 1/2012 ? freescale semiconductor, inc., 2010-2012. all rights reserved. this document contains information on a product under development. freescale reserves the right to change or discontinue this product without notice. xtrinsic battery sensor with lin for 12 v lead-acid batteries freescale's xtrinsic mm912_637 battery sensors are fully integrated battery monitoring devices. the devices allow simultaneous measurement of battery current and voltage for precise determination of soc (state of charge), soh (state of health), and ot her parameters. the integrated temperature sensor combin ed with the close proximity to the battery allows batt ery temperature measurement. multiple application-specific hardware blocks reduce mcu overhead and related powe r consumption. configurable low-power modes with automated battery state observation and sophisticat ed wake-up capability further redu ce current consumption. the integrated lin 2.1 interface allows communicati on and control of batter y monitoring functions. features ? battery voltage measurement ? battery current measurement in up to eight ranges ? on chip temperature measurement ? normal and two low-power modes ? current threshold detection and current averaging in standby => wake-up from low-power mode ? triggered wake-up from lin and periodic wake-up ? signal low pass filtering (current, voltage) ? pga (programmable low-noise gain amplifier) with automatic gain co ntrol feature ? accurate internal oscillator (an external quartz oscillator may be used for extended accuracy) ? communication via a lin 2.1, lin2.0 bus interface ? s12 microcontroller with 128 kbyte flash, 6.0 kbyte ram, 4.0 kbyte data flash ? background debug module ? external temperature sens or option (tsup, vtemp) ? optional 2nd external voltage sense input (vopt) ? four x 5.0 v gpio including one wake-up capable high voltage input (ptb3/l0) ? eight x mcu general purpose i/o including spi functionality ? industry standard emc compliance figure 1. simplified application diagram mm912_637 ep suffix (pb-free) 98asa00343d 48-pin qfn mm912_637 vddl vdda agnd reset reset_a pa0/miso lin vsup isensel test_a vddh ptb0 tclk ptb1 ptb2 ptb3/l0 lgnd isenseh gndsub tsup vtemp vopt vsense pa1/mosi pa2/sck pa3/ss pa4 pa5 pa6 pa7 bkgd/modc pe0/extal pe1/xtal test adcgnd vddd2d vddx vddrx dgnd vssrx vssd2d adc supply 2.5 v supply 5.0 v supply digital ground reset 5.0 v digital i/o debug and external oscillator mcu test lin interface optional temp sense voltage sense module power supply current sense module -5.0 v gpi/o shared analog test internal temp sense module + _ input and supply with timer, sci and lin -ptb3 high voltage wake capable 4 chassis ground (optional) battery positive pole battery negative pole shunt
ordering information mm912_637, rev. 3.0 freescale semiconductor 2 1 ordering information 2 part identification this section provides an explanation of the part numbers and their alpha numeric breakdown. 2.1 description part numbers for the chips have fields that identify the specific part configuration. you can use the values of these fields to determine the specific part you have received. 2.2 format and examples part numbers for a given device have the following format, followed by a device example: table 3 - part numbering - analog embedded mcu + power : mm 9 cc f xxx r v ppp rr - MM912I637AM2EP 2.3 fields these tables list the possible values for each field in the part number (not all combinations are valid). table 1. ordering information device (add an r2 suffix for tape and reel orders) temperature range (t a ) package maximum input voltage analog option flash (kb) MM912I637AM2EP -40 c to 125 c 48 qfn-ep 42 v 2 96 mm912j637am2ep 128 mm912i637av1ep -40 c to 105 c 1 96 mm912j637av1ep 128 table 2. analog options feature analog option 1 analog option 2 cranking mode not characterized or tested fully characterized and tested external wake-up (ptb3/l0) no ye s external temperature sensor option (vtemp) no ye s optional 2nd external voltage sense input (vopt) no ye s
part identification mm912_637, rev. 3.0 freescale semiconductor 3 table 3. part numbering - analog embedded mcu + power field description values mm product category ? mm- qualified standard ? sm- custom device ? pm- prototype device 9 memory type ? 9 = flash, otp ? blank = rom cc micro core ?08 = hc08 ?12 = hc12 f memory size ?a 1 k ?b 2 k ?c 4 k ?d 8 k ? e 16 k ? f 32 k ? g 48 k ? h 64 k ? i 96 k ? j 128 k xxx analog core/target ? assigned by marketing r revision ? (default a) t temperature range ? i = 0 c to 85 c ? c = -40 c to 85 c ? v = -40 c to 105 c ? m = -40 c to 125 c v variation ? (default blank) ppp package designator ? assigned by packaging rr tape and reel indicator
mm912_637, rev. 3.0 freescale semiconductor 4 table of contents 1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 part identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 format and examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 mm912_637 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 recommended external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 pin structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 static electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.7 thermal protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.8 electromagnetic compatibility (emc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5 functional description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1 mm912_637 - analog die overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.2 analog die - power, clock and resets - pcr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3 interrupt module - irq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.4 current measurement - isense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.5 voltage measurement - vsense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.6 temperature measurement - tsense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.7 channel acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.8 window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 5.9 basic timer module - tim (tim16b4c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 5.10 general purpose i/o - gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.11 lin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 5.12 serial communication interface (s08sciv4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 5.13 life time counter (ltc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 5.14 die to die interface - target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 5.15 embedded microcontroller - overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 5.16 mcu - port integration module (9s12i128pimv1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 5.17 mcu - interrupt module (s12sintv1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 5.18 memory map control (s12pmmcv1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 5.19 mcu - debug module (s12sdbg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 5.20 mcu - security (s12xs9secv2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 5.21 background debug module (s12sbdmv1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 5.22 s12 clock, reset, and power management unit (s12cpmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 5.23 mcu - serial peripheral interface (s12spiv5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 5.24 128 kbyte flash module (s12ftmrc128k1v1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 5.25 mcu - die-to-die initiator (d2div1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 6 mm912_637 - trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 6.2 ifr trimming content and location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 6.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 7 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 7.1 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
mm912_637, rev. 3.0 freescale semiconductor 5 figure 2. sample block diagram cascaded voltage regulators vddh = 2.5v (d2d buffer) vddl = 2.5v (internal digital) vddx = 5v (mcu core) die to die interface reset control module reset_a vdda isensel lin vsup d2ddat6 d2ddat7 d2dclk d2dint wake up control module (with current threshold and current averaging) current sense module (pga with auto gain control) interrupt control module vbat / vopt sense module low pass filter and control isenseh internal chip temp sense with optional external input vddl vddx sci d2ddat2 d2ddat3 adc regulator ptb1 gpio ptb0 ptb2 lin physical layer analog die m68hcs12 cpu cpu register alu d2di flash 128k bytes with ecc dataflash 4k bytes with ecc ram 6k byte debug module include 64 byte trace buffer ram reset generation and test entry amplitude controlled low power pierce osc. pll with freq. modulation option osc clock monitor single-wire background debug module cop watchdog periodic interrupt interrupt module spi ddra mosi miso sck pta mcu die ss pa2 pa3 pa4 pa5 pa7 test pte1 / xtal bkgd/modc reset vssd2d vddd2d dgnd agnd test interface tclk test_a vddh bias 4 channel timer trimming / calibration lgnd internal bus vsense vtemp vopt internal bus vreg 1.8v core 2.7v flash vddrx vssrx d2ddat4 d2ddat5 d2ddat0 d2ddat1 pc0 pd7 pd3 pd6 pd2 pd5 pd1 pd4 pd0 pc1 temp sense supply tsup 16 bit adc adcgnd pa0 pa1 gndsub gndsub gndsub gndsub pte0 / extal pa6 ptb3 (l0) 16 bit -adc 16 bit -adc pte [1:0]
pin assignment mm912_637, rev. 3.0 freescale semiconductor 6 3 pin assignment figure 3. mm912_637 pin connections 3.1 mm912_637 pin description the following table gives a brief description of all available pins on the mm912_637 device. refer to the highlighted chapter f or detailed information table 4. mm912_637 pin description pin # pin name formal name description 1 pa6 mcu pa6 general purpose port a input or output pin 6. see section 5.16, ?mcu - port integration module (9s12i128pimv1)" . 2 pe0/extal mcu oscillator extal in one of the optional crystal/res onator drivers and exte rnal clock pins, and the pe0 port may be used as a general purpose i/o. on reset, all the device clocks are derived from the in ternal reference clock. see section 5.22, ?s12 clock, reset, and power management unit (s12cpmu)" . reset_a 1 2 3 4 5 6 7 8 9 10 11 12 pa6 vssrx vddrx pte0/extal pte1/xtal test pa5 pa4 pa3/ss pa2/sck pa1/mosi pa0/miso 36 35 34 33 32 31 30 29 28 27 26 25 ptb3 / l0 vdda vopt vsense adcgnd isenseh isensel gndsub tsup vtemp 37 38 39 40 41 42 43 44 45 46 47 48 dgnd bkgd/modc pa7 vddl ptb0 ptb2 ptb1 gndsub test_a tclk reset 24 23 22 21 20 19 18 17 16 15 14 13 lin vddd2d vssd2d vsup lgnd nc (vfuse) gndsub dgnd vddh gndsub vddx nc ep agnd nc
pin assignment mm912_637, rev. 3.0 freescale semiconductor 7 3 pe1/xtal mcu oscillator xtal is one of the optional crystal/res onator drivers and external clock pins, and the pe1 port may be used as a general purpos e i/o. on reset all the device clocks are derived from the internal reference clock. see section 5.22, ?s12 clock, reset, and power management unit (s12cpmu)" . 4 test mcu test this input only pin is reserv ed for test. this pin has a pull-down device. the test pin must be tied to vssrx in user mode. 5 pa5 mcu pa5 general purpose port a input or output pin 5. see section 5.16, ?mcu - port integration module (9s12i128pimv1)" . 6 pa4 mcu pa4 general purpose port a input or output pin 4. see section 5.16, ?mcu - port integration module (9s12i128pimv1)" . 7 pa3 mcu pa3 / ss general purpose port a input or output pin 3, shared with the ss signal of the integrated spi interface. see section 5.16, ?mcu - port integration module (9s12i128pimv1)" . 8 pa2 mcu pa2 / sck general purpose port a input or output pin 2, shared with the sclk signal of the integrated spi interface. see section 5.16, ?mcu - port integration module (9s12i128pimv1)" . 9 pa1 mcu pa1 / mosi general purpose port a input or output pin 1, shared with the mosi signal of the integrated spi interface. see section 5.16, ?mcu - port integration module (9s12i128pimv1)" . 10 pa0 mcu pa0 / miso general purpose port a input or output pin 0, shared with the miso signal of the integrated spi interface. see section 5.16, ?mcu - port integration module (9s12i128pimv1)" . 11 vssrx mcu 5.0 v ground external ground for the mcu - vddrx return path. 12 vddrx mcu 5.0 v supply 5.0 v mcu power supply. mcu core- (internal 1.8 v regulator) and flash (internal 2.7 v regulator) supply. 13 vssd2d mcu 2.5 v ground external ground for the mcu - vddd2d return path. 14 vddd2d mcu 2.5 v supply 2.5 v mcu power supply. die to die buffer supply. 15 nc not connected this pin must be grounded in the application. 16 gndsub substrate ground substrate ground connection to improve emc behavior. 17 vddx voltage regulator output 5.0 v 5.0 v main voltage regulator output pin. an external capacitor (c vddx ) is needed. see section 5.2, ?analog die - power, clock and resets - pcr" . 18 dgnd digital ground this pin is the device di gital ground connection. see section 5.2, ?analog die - power, clock and resets - pcr" . 19 vddh voltage regulator output 2.5 v 2.5 v high power main voltage regulator output pin to be connected with the vddd2d mcu pin. an external capacitor (c vddh ) is needed. see section 5.2, ?analog die - power, clock and resets - pcr" . 20 gndsub substrate ground substrate ground connection to improve emc behavior. 21 vsup power supply this pin is the device pow er supply pin. a reverse battery protection diode is required. see section 5.2, ?analog die - power, clock and resets - pcr" . 22 lin lin bus i/o this pin represents the single-wire bus transmitter and receiver. see section 5.11, ?lin" . 23 lgnd lin ground pin this pin is the device lin ground connection. see section 5.2, ?analog die - power, clock and resets - pcr" . 24 nc not connected (reserved) this pin must be grounded in the application. 25 nc not connected this pin must be grounded in the application. 26 vdda analog voltage regulator output low power analog voltage regulator output pin, permanently supplies the analog front end. an external capacitor (c vdda ) is needed. see section 5.2, ?analog die - power, clock and resets - pcr" . 27 agnd analog ground this pin is the device analog voltage regulator and lp oscillator ground connection. see section 5.2, ?analog die - power, clock and resets - pcr" . table 4. mm912_637 pin description pin # pin name formal name description
pin assignment mm912_637, rev. 3.0 freescale semiconductor 8 28 vtemp temperature sensor input external temperature sensor input. see section 5.6, ?temperature measurement - tsense" . 29 tsup temperature sensor supply output supply for the external temperature sensor. tsup frequency compensation option to allow capacitor ctsup . see section 5.6, ?temperature measurement - tsense" . 30 gndsub substrate ground substrate ground connection to improve emc behavior. 31 isensel current sense l current sense input ?low?. this pin is used in combination with isenseh to measure the voltage drop across a shunt resistor. see section 5.4, ?current measurement - isense" . 32 isenseh current sense h current sense input ?high?. this pin is used in combination with isensel to measure the voltage drop across a shunt resistor. see section 5.4, ?current measurement - isense" . 33 adcgnd analog digital converter ground analog digital converter ground connection. see section 5.2, ?analog die - power, clock and resets - pcr" . 34 vsense voltage sense precision battery voltage measurement inpu t. this pin can be connected directly to the battery line for voltage measurements. the voltage preset at this input is scaled down by an internal voltage divide r. the pin is self protected against reverse battery connections. an external resistor (r vsense ) is needed for protection. see section 5.5, ?voltage measurement - vsense" . 35 vopt optional voltage sense optional voltage measurement input. see section 5.5, ?voltage measurement - vsense" . 36 ptb3 / l0 general purpose input 3 - high voltage input 0 this is the high voltage general purpose input pin 3, based on vddx with the following shared functions: ? internal clamping structure to operate as a high voltage input (l0). when used as high voltage input, a series resistor ( rl0 ) and capacitor to gnd (c l0 ) must be used to protect against automotive transients, when used to connect outside the pcb. ? 5.0 v (vddx) digital port input ? selectable internal pull-down resistor ? selectable wake-up input during low power mode. ? selectable timer channel input ? selectable connection to the lin / sci (input only) see section 5.10, ?general purpose i/o - gpio" . 37 ptb2 general purpose i/o 2 this is the general purpose i/o pin 2 based on vddx with the following shared functions: ? bidirectional 5.0 v (vddx) digital port i/o ? selectable internal pull-up resistor ? selectable timer channel input/output ? selectable connection to the lin / sci see section 5.10, ?general purpose i/o - gpio" . 38 ptb1 general purpose i/o 1 this is the general purpose i/o pin 1, based on vddx with the following shared functions: ? bidirectional 5.0 v (vddx) digital port i/o ? selectable internal pull-up resistor ? selectable timer channel input/output ? selectable connection to the lin / sci see section 5.10, ?general purpose i/o - gpio" . 39 ptb0 general purpose i/o 0 this is the general purpose i/o pin 0 based on vddx with the following shared functions: ? bidirectional 5.0 v (vddx) digital port i/o ? selectable internal pull-up resistor ? selectable timer channel input/output ? selectable connection to the lin / sci see section 5.10, ?general purpose i/o - gpio" . table 4. mm912_637 pin description pin # pin name formal name description
pin assignment mm912_637, rev. 3.0 freescale semiconductor 9 40 tclk test clock input test mode clock input pin for test mode only. this pin must be grounded in user mode. 41 gndsub substrate ground substrate ground connection to improve emc behavior. 42 vddl low power voltage regulator output 2.5 v low power voltage regulator output pin. see section 5.2, ?analog die - power, clock and resets - pcr" . 43 test_a test mode analog die test mode pin for test mode only. this pin must be grounded in user mode. 44 dgnd digital ground this pin is the device di gital ground connection. see section 5.2, ?analog die - power, clock and resets - pcr" . 45 reset_a reset i/o reset output pin of the analog die. active low signal with internal pull-up. v ddx based. see section 5.2, ?analog die - power, clock and resets - pcr" . 46 reset mcu reset bidirectional reset i/o pin of the mcu die. active low signal with internal pull-up. v ddrx based. see section 5.2, ?analog die - power, clock and resets - pcr" . 47 bkgd mcu background debug and mode the bkgd/modc pin is used as a pseud o-open-drain pin for the background debug communication. it is used as an m cu operating mode select pin during reset. the state of this pin is latched to the modc bit at the rising edge of reset . the bkgd pin has a pull-up device. see section 5.19, ?mcu - debug module (s12sdbg)" . 48 pa7 mcu pa7 general purpose port a input or output pin 7. see section 5.16, ?mcu - port integration module (9s12i128pimv1)" . table 4. mm912_637 pin description pin # pin name formal name description
pin assignment mm912_637, rev. 3.0 freescale semiconductor 10 3.2 recommended external components figure 4 and ta b l e 5 list the required / recommended / optional external components for the application. figure 4. required / recommended external components table 5. required / recommended external components name description value connection comment d 1 reverse battery diode n.a. vsup-vbat c vbat battery blocking capacitor 4.7 f/100 nf vsup-gnd ceramic r vsense vsense current limitation 2.2 k ? vsense-vbat r vopt vopt current limitation 2.2 k ? vopt-signal optional (1) r shunt current shunt resistor 100 ? isenseh-isensel r isensel emc resistor 500 ? max select for best emc performance r isenseh emc resistor 500 ? max select for best emc performance c isensel emc capacitor tbd select for best emc performance c isensehl emc capacitor tbd select for best emc performance c isenseh emc capacitor tbd select for best emc performance battery minus pole chassis ground isensel isenseh gndsub vsense vsup battery plus pole lin lin r vsense c lin c vbat r shunt note: module gnd connected to battery minus or chassis ground ? based on configuration. d 1 vddh vddx vdda agnd dgnd c vddh c vddx c vdda vddl vddd2d vssd2d vddrx vssrx gndsub gndsub gndsub exposed pad (ep) adcgnd ptb3 / l0 r l0 c l0 tsup c tsup vtemp r vtemp vopt r vopt lgnd r isensel r isenseh c isensel c isensehl c isenseh
pin assignment mm912_637, rev. 3.0 freescale semiconductor 11 3.3 pin structure table 6 documents the individual pin characteristic. c vddh blocking capacitor 1.0 f vddh-gnd c vddx blocking capacitor 220 nf vddx-gnd c vdda blocking capacitor 47 nf vdda-gnd c vddl blocking capacitor n.a. vddl-gnd not required c lin lin bus filter n.a. lin-lgnd not required r l0 ptb3 / l0 current limitation 47 k ? l0 c l0 ptb3 / l0 esd protection 47 nf l0-gnd c tsup blocking capacitor 220 pf tsup-gnd not required (2) r vtemp vtemp current limitation 20 k ? vtemp-signal optional (1) notes 1.required if extended emc protection is needed 2.if an external temperature sensor is used, emc compliance may require the addition of ctsup. in this case the ecap bit must b e set to ensure the stability of the tsup power supply circuit. see section 5.6.1.2, ?block diagram" . table 6. pin type / structure pin # pin name alternative pin function power supply structure 1 pa6 n.a. vddrx n.a. 2 pe0 extal vddrx pupee / oscpins_en 3 pe1 xtal vddrx pupee / oscpins_en 4 test n.a. n.a. n.a. 5 pa5 n.a. vddrx n.a. 6 pa4 n.a. vddrx n.a. 7 pa3 ss vddrx n.a. 8 pa2 sck vddrx n.a. 9 pa1 mosi vddrx n.a. 10 pa0 miso vddrx n.a. 11 vssrx n.a. gnd 12 vddrx n.a. 13 vssd2d n.a. gnd 14 vddd2d n.a. 15 nc n.a. 16 gndsub n.a. gnd 17 vddx n.a. vddx 18 dgnd n.a. gnd b2b-diode to gndsub 19 vddh n.a. vddh negative clamp diode, dy namic esd (transient protection) 20 gndsub n.a. gnd gndsub 21 vsup n.a. vsup negative clamp diode, >42 v esd 22 lin n.a. vsup no negative clamping diode (-40 v), >42 v esd 23 lgnd n.a. gnd b2b-diode to gndsub table 5. required / recommended external components name description value connection comment
pin assignment mm912_637, rev. 3.0 freescale semiconductor 12 24 nc n.a. n.a. negative clamp diode, >15 v esd 25 nc n.a. n.a. n.a. 26 vdda n.a. vdda negative clamp diode, dy namic esd (transient protection) 27 agnd n.a. gnd b2b-diode to gndsub 28 vtemp vdda negative clamp diode, >6.0 v esd 29 tsup tsup negative clamp diode, dyna mic esd (transient protection) 30 gndsub gnd gnd 31 isensel n.a. negative clamp diode, 2nd clamp diode to vdda 32 isenseh n.a. negative clamp diode, 2nd clamp diode to vdda 33 adcgnd gnd b2b-diode to gndsub 34 vsense n.a. no negative clamping diode (-40 v), >42 v esd 35 vopt n.a. no negative clamping diode (-40 v), >42 v esd 36 ptb3 / l0 vddrx negative clamp diode, >6.0 v esd 37 ptb2 vddrx negative clamp, dynamic 5.5 v esd 38 ptb1 vddrx negative clamp, dynamic 5.5 v esd 39 ptb0 vddrx negative clamp, dynamic 5.5 v esd 40 tclk vddrx negative clamp, dynamic 5.5 v esd 41 gndsub gnd gnd 42 vddl vddl negative clamp diode, dyna mic esd (transient protection) 43 test_a vddrx negative clamp, positive 10 v clamp 44 dgnd gnd b2b-diode to gndsub 45 reset_a vddrx negative clamp, positive 10 v clamp 46 reset vddrx pull-up 47 bkgd modc vddrx bkpue 48 pa7 vddrx n.a. table 6. pin type / structure pin # pin name alternative pin function power supply structure
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 13 4 electrical characteristics 4.1 general this section contains electrical information for the microcontroller, as well as the mm912_637 analog die. 4.2 absolute maximum ratings absolute maximum ratings are stress ratings only. a functional operation under or outside these maximums is not guaranteed. stress beyond these limits may affect the reliabilit y, or cause permanent damage of the device. this device contains circuitry protecting against damage due to hi gh static voltage or electrical fields. however, it is advise d that normal precautions be taken to avoid application of any voltage s higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. all voltages are with respect to ground, unless otherwise noted. table 7. absolute maximum electri cal ratings - analog die ratings symbol value unit vsup pin voltage v vsup -0.3 to 42 v vsense pin voltage (3) v vsense -16 to 42 v vopt pin voltage v vopt -16 to 42 v vtemp pin voltage v vtemp -0.3 to v dda +0.25 v isenseh and isensel pin voltage v isense -0.5 to v dda +0.25 v isenseh and isensel pin current i isense -1 to 1 ma lin pin voltage v bus -33 to 42 v lin pin current (internally limited) i buslim on page 18 ma l0 pin voltage with r ptb3 v ptb3 -0.3 to 42 max. v input / output pins ptb[0:2] voltage v ptb0-2 -0.3 to v ddx +0.5 v pin voltage at vddx v ddx -0.3 to 5.75 v pin voltage at vddh v ddh -0.3 to 2.75 v vddh output current i vddh internally limited a vddx output current i vddx internally limited a tclk pin voltage v tclk -0.3 to v ddx +0.5 v reset_a pin voltage v in -0.3 to v ddx +0.5 v notes 3.it has to be assured by the application circuit that t hese limits will not be exceeded, e.g. by iso pulse 1. table 8. maximum electrical ratings - mcu die ratings symbol value unit 5.0 v supply voltage v ddrx -0.3 to 6.0 v 2.5 v supply voltage v ddd2d -0.3 to 3.6 v digital i/o input voltage (pta0...7) v in -0.3 to 6.0 v extal, xtal v in -0.3 to 2.16 v instantaneous maximum current single pi n limit for all digital i/o pins (4) i d -25 to 25 ma instantaneous maximum current single pin limit for extal, xtal i dl -25 to 25 ma notes 4.all digital i/o pins ar e internally clamped to v ssrx and v ddrx .
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 14 4.3 operating conditions this section describes the operating condit ions of the device. conditions apply to all the following data, unless otherwise not ed. 4.4 supply currents this section describes the current consumpt ion characteristics of the device, as well as the conditions for the measurements. 4.4.1 measurement conditions all measurements are without out put loads. the currents are measured in mcu special single chip mode, and the cpu code is executed from ram, unless otherwise noted. for run and wait current measurements, pll is on and the reference clock is the irc1m, trimmed to 1.024 mhz. the bus frequency is 32.768 mhz and the cpu frequency is 65.536 mhz. ta b l e 11 and table 12 show the configuration of the cpmu module for run, wait, and stop current measurements. ta b l e 13 shows the configuration of the peripherals for run current measurements table 9. maximum th ermal ratings ratings symbol value unit storage temperature t stg -55 to 150 ? c package thermal resistance (5) r ? ja 25 typ. ? c/w notes 5.r ? ja value is derived using a jedec 2s2p test board table 10. operating conditions ratings symbol value unit functional operating supply voltage - device is fully functional. all features are operating. v sup 3.5 to 28 v extended range for ram content is guaranteed. other device functionary is limited. with cranking mode enabled (see section 5.2.3.4, ?low voltage operation - cranking mode device option" ). v supl 2.5 to 3.5 v functional operating vsense voltage (6) v sense 0 to 28 v functional operating vopt voltage v opt 0 to 28 v external temperature sense input - vtemp v temp 0 to 1.25 v lin output voltage range v vsup_lin 7 to 18 v isenseh / isensel terminal voltage v isense -0.5 to 0.5 v mcu 5.0 v supply voltage v ddrx 3.13 to 5.5 v mcu 2.5 v supply voltage v ddd2d 2.25 to 3.6 v mcu oscillator f osc 4 to 16 mhz mcu bus frequency f bus max. 32.768 mhz operating ambient temperature t a -40 to 125 ? c operating junction temperature - analog die t j_a -40 to 150 ? c operating junction temperature - mcu die t j_m -40 to 150 ? c notes 6.values v sense > 28 v are flagged in the vsense
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 15 table 11. cpum configuration for run/wait and full stop current measurement cpmu register bit settings/conditions cpmusynr vcofrq[1:0]=01,syndiv[5:0] = 32.768 mhz cpmupostdiv postdiv[4:0]=0, cpmuclks pllsel=1 cpmuosc osce=0, reference clock for pll is f ref =f irc1m trimmed to 1.024 mhz table 12. cpmu configuration for pseudo stop current measurements cpmu register bit settings/conditions cpmuclks pllsel=0, pstp=1, pre=pce=rtioscsel=coposcsel=1 cpmuosc osce=1, external square wave on extal f extal =16 mhz, v ih = 1.8 v, v il =0 v cpmurti rtdec=0, rtr[6:4]=111, rtr[3:0]=1111; cpmucop wcop=1, cr[2:0]=111 table 13. mcu peripheral configurations for run supply current measurements peripheral configuration spi configured to master mode, continuously transmit data (0x55 or 0xaa) at 1.0 mbit/s d2di continuously transmit data (0x55 or 0xaa) cop cop watchdog rate 2 24 rti enabled, rti control register (rtictl) set to $ff dbg the module is enabled and the comparators are configured to trigger in outside range. the range covers all the code executed by the core. table 14. analog die configurations for normal mode supply current measurements peripheral configuration d2d maximum frequency lin enabled, recessive state timer enabled ltc enabled channels current, voltage, and temperature measurement enabled, lpf and auto gain enabled
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 16 4.5 static electrical characteristics all characteristics noted under conditions 3.5 v ?? v sup ??? 28 v, -40 ? c ?? t a ??? 125 ? c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. 4.5.1 static electrical ch aracteristics analog die table 15. supply currents (7) ratings symbol min typ. (8) max unit mm912_637 combined consumption normal mode current both dice. i run 25 35 ma analog die contribution - excluding mcu and external load current, (3.5 v ? v sup ? 28 v; -40 c ? t a ? 125 c) normal mode current measured at v sup i normal 1.5 4.0 ma stop mode current measured at v sup continuous base current (9) stop current during cranking mode current adder during current trigger event - (typ. 10 ms duration (10) , temperature measurement = off) i stop 75 107 1500 100 130 1750 a sleep mode measured at v sup continuous base current (9) current adder during current trigger event - (typ. 10 ms duration (10) , temperature measurement = off) i sleep 52 1500 85 1750 a mcu die contribution, v ddrx = 5.5 v run current, t a ? 125 c i run 13.5 18.8 ma wait current, t a ? 125 c i wait 7.0 8.8 ma stop current t a = 125 c t a = 25 c t a = -40 c i stp 90 25 15 200 40 25 a pseudo stop current, rti and cop enabled t a = 150 c t a = 25 c t a = -40 c i stp 450 350 330 520 500 410 a notes 7.see table 11 , table 12 , table 13 , and table 14 for conditions. currents measured in test mode with external loads (100 pf) and the external clock at 64 mhz. 8.typical values noted reflect the approximate parameter mean at t a = 25 c. 9.from v sup 6.0 to 28 v 10.duration based on channel configuration. 10ms ty pical for decimation factor = 512, chopper = on. table 16. static electrical char acteristics - power supply ratings symbol min typ max unit low voltage reset l (por) assert (measured on vddl) cranking mode disabled v porl 1.75 1.9 2.1 v low voltage reset l (por) deassert (measured on vddl) cranking mode disabled v porh 1.85 2.1 2.35 v
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 17 low voltage reset l (por) assert (measured on vddl) cranking mode enabled (11) v porcl 1.0 1.3 1.7 v low voltage reset a (lvra) assert (measured on vdda) v lvral 1.9 2.05 2.2 v low voltage reset a (lvra) deassert (measured on vdda) v lvrah 2.0 2.15 2.3 v low voltage reset x (lvrx) assert (measured on vddx) v lvrxl 2.5 2.75 3.0 v low voltage reset x (lvrx) deassert (measured on vddx) v lvrxh 2.7 2.95 3.25 v low voltage reset h (lvrh) assert (measured on vddh) v lvrhl 1.95 2.075 2.2 v low voltage reset h (lvrh) deassert (measured on vddh) v lvrhh 2.05 2.175 2.3 v under-voltage interrupt (uvi) assert (measured on vsup), cranking mode disabled v uvil 4.65 5.2 6.1 v under-voltage interrupt (uvi) deassert (measured on vsup), cranking mode disabled v uvih 4.9 5.4 6.2 v under-voltage cranking interrupt (uvi) assert (measured on vsup) cranking mode enabled v uvcil 3.4 3.6 4.0 v under-voltage cranking interrupt (uvi) deassert (measured on vsup) cranking mode enabled v uvcih 3.5 3.8 4.1 v vsense/vopt high voltage warning threshold assert (12) v th 28 v notes 11.deassert with cranking off = v porh 12.5.0 v < v sup < 28 v, digital threshold at the end of channel chain (incl. compensation) table 17. static electrical characteristics - resets ratings symbol min typ max unit low-state output voltage i out = 2.0 ma v ol 0.8 v pull-up resistor r rpu 25 50 kohm low-state input voltage v il 0.3v ddx v high-state input voltage v ih 0.7v ddx v reset release voltage (vddx) v rstrv 0 0.02 1.0 v reset_a pin current limitation i limrst 10 ma table 16. static electrical ch aracteristics - power supply ratings symbol min typ max unit
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 18 table 18. static electrical characteris tics - voltage regulator outputs ratings symbol min typ max unit analog voltage regulator - vdda (13) output voltage 1.0 ma ? i vdda ? 1.5 ma v dda 2.25 2.5 2.75 v output current limitation i vdda 10 ma low power digital voltage regulator - vddl (13) output voltage v ddl 2.25 2.5 2.75 v high power digital voltage regulator - vddh (14) output voltage 1.0 ma ? i vddh ? 30 ma v ddh 2.4 2.5 2.75 v output current limitation i vddh 65 ma 5.0 v voltage regulator - vddx (14) output voltage 1.0 ma ? i vddx ? 30 ma v ddx 3.15 5.0 5.9 v output current limitation i vddx 45 60 80 ma notes 13.no additional current must be taken from those outputs. 14.the specified current ranges does include the current for the mcu die. no external loads recommended. table 19. static electrical char acteristics - lin physica l layer interface - lin ratings symbol min typ max unit current limitation for driver dominant state. v bus = 18 v i buslim 40 120 200 ma input leakage current at the receiver incl. pull-up resistor r slave ; driver off; v bus = 0 v; v bat = 12 v i bus_pas_dom -1.0 ma input leakage current at the receiver incl. pull-up resistor r slave ; driver off; 8.0 v ?? v bat ? 18 v; 8.0 v ?? v bus ? 18 v; v bus ? v bat i bus_pas_rec 20 a input leakage current; gnd disconnected; gnd device = v sup ; 0 < v bus < 18 v; v bat = 12 v i bus_no_gnd -1.0 1.0 ma input leakage current; v bat disconnected; v sup_device = gnd; 0 < v bus < 18 v i bus_no_bat 100 a receiver input voltage; receiver dominant state v busdom 0.4 v sup receiver input voltage; receiver recessive state v busrec 0.6 v sup receiver threshold center (v th_dom + v th_rec )/2 v bus_cnt 0.475 0.5 0.525 v sup receiver threshold hysteresis (v th_rec - v th_dom ) v bus_hys 0.175 v sup voltage drop at the serial diode d ser_int 0.3 0.7 1.0 v lin pull-up resistor r slave 20 30 60 kohm low level output voltage, i bus =40 ma v dom 0.3 v sup high level output voltage, i bus =-10 a, r l =33 kohm v rec vsup-1 v j2602 detection deassert threshold for vsup level v j2602h 5.9 6.3 6.7 v j2602 detection assert threshold for vsup level v j2602l 5.8 6.2 6.6 v j2602 detection hysteresis v j2602hys 70 190 250 mv bus wake-up threshold v linwup 4.0 5.25 6.0 v
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 19 table 20. static electrical characteristics - high voltage input - ptb3 / l0 ratings symbol min typ max unit wake-up threshold - rising edge v wthr 1.3 2.6 3.4 v input high voltage (digital input) v ih 0.7v ddx v ddx +0.3 v input low voltage (digital input) v il v ss -0.3 0.35v ddx v input hysteresis v hys 50 140 200 mv internal clamp voltage v l0clmp 4.9 6.0 7.0 v input current ptb3 / l0 (v in = 42 v; r l0 =47 kohm) i in 1.1 ma internal pull-down resistance (15) r pd 50 100 200 kohm ptb3 / l0 series resistor r ptb3 42.3 47 51.7 kohm ptb3 / l0 capacitor c l0 42.3 47 51.7 nf notes 15.disabled by default. table 21. static electrical ch aracteristics - general purpose i/o - ptb[0...2] ratings symbol min typ max unit input high voltage v ih 0.7v ddx v ddx +0.3 v input low voltage v il v ss -0.3 0.35v ddx v input hysteresis v hys 50 140 200 mv input leakage current (pins in high-impedance input mode) (v in = v ddx or v ssx ) i in -1.0 1.0 a output high voltage (pins in output mode) full drive i oh = ?5.0 ma v oh v ddx -0.8 v output low voltage (pins in output mode) full drive i ol = 5.0 ma v ol 0.8 v internal pull-up resistance (v ih min. > input voltage > v il max) (16) r pul 25 37.5 50 kohm input capacitance c in 6.0 pf maximum current all ptb combined (17) i bmax -17 17 ma output drive strength at 10 mhz c out 100 pf notes 16.disabled by default. 17.overall vddr regulator capability to be considered.
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 20 table 22. static electrical characte ristics - current sense module (18) ratings symbol min typ max unit gain error with temperature based gain compensation adjustment (19) , (20) with default gain compensation i gainerr -0.5 -1.0 +/-0.1 0.5 1.0 % offset error (21) , (22) i offseterr 0.5 v resolution i res 0.1 v isenseh, isensel terminal voltage differential signal voltage range v inc v ind -300 -200 300 200 mv differential leakage current: differential voltage between isenseh/ isensel, ? 200 mv i sense_dlc -2.0 2.0 na wake-up current threshold resolution i reswake 0.2 v resistor threshold for open detection r open 0.8 1.25 1.8 mohm notes 18.3.5 v ? v sup ? 28 v, after applying defaul t trimming values - see section 6, ?mm912_637 - trimming" . 19.gain compensation adjustment on calibration request interrupt with tcalstep 20. ? 0.65%, including lifetime drift for gain 256 and 512 21.chopper mode = on, gain with automatic gain control enabled 22.parameter not tested. guarant eed by design and characterization table 23. static electrical characteristics - voltage sense module (23) ratings symbol min typ max unit gain error (24) 18 v ? v in ? 28 v 3.5 v ? v in ? 18 v 3.5 v ? v in ? 5.0 v (25) 5.0 v ? v in ? 18 v (25) , (27) v gainerr -0.5 -0.4 -0.25 -0.15 0.1 0.1 0.1 0.1 0.5 0.4 0.25 0.15 % offset error (26) , (28) v offseterr -1.5 1.5 mv resolution with r vsense = 2.2 kohm v res 0.5 mv notes 23.3.5 v ? v sup ? 28 v, after applying default trimming values - see section 6, ?mm912_637 - trimming" . 24.including resistor mismatch drift 25.gain compensation adjustment on calibr ation request interrupt with tcalstep 26.chopper mode = on. 27. ? 0.2%, including lifetime drift 28.parameter not tested. guaranteed by design and characterization. table 24. static electrical characteri stics - temperature sense module (29) ratings symbol min typ max unit measurement range t range -40 150 c accuracy -40 c ? t a ?? 60 c (30) -40 c ? t a ??? 50 c t acc -2.0 -3.0 2.0 3.0 k resolution t res 8.0 mk tsup voltage output, 10 a ? i tsup ? 100 a v tsup 1.1875 1.25 1.3125 v tsup capacitor with ecap = 1 c tsup 209 220 231 pf
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 21 4.5.2 static electrical characteristics mcu die max calibration request interrupt temperature step t calstep -25 25 k notes 29.3.5 v ? v sup ? 28 v, after applying default trimming values - see section 6, ?mm912_637 - trimming" . 30.temperature not tested in production. guaranteed by design and characterization. table 25. static electrical characteristics - mcu ratings symbol min typ max unit power on reset assert (measured on vddrx) v pora 0.6 0.9 - v power on reset deassert (measured on vddrx) v pord - 0.95 1.6 v low voltage reset assert (measured on vddd2d) v lvra 2.97 3.06 - v low voltage reset deassert (measured on vddd2d) v lvrd - 3.09 3.3 v low voltage interrupt assert (measured on vddd2d) v lvia 4.06 4.21 4.36 v low voltage interrupt deassert (measured on vddd2d) v lvid 4.19 4.34 4.49 v table 26. static electrical characte ristics - oscillator (osclcp) ratings symbol min typ max unit startup current i osc 100 ? a input capacitance (extal, xtal pins) c in 7.0 pf extal pin input hysteresis v hys,extal ? 180 ? mv extal pin oscillation amplit ude (loop controlled pierce) v pp,extal ? 0.9 ? v table 27. 5.0 v i/o characteristics for all i/o pins except extal, xtal, test, d2di, and supply pins (4.5 v < v ddrx < 5.5 v; t j : ?40 c to +150 c, unless otherwise noted) ratings symbol min typ max unit input high voltage v ih 0.65*v ddrx ? ? v input high voltage v ih ? ? v ddrx +0.3 v input low voltage v il ? ? 0.35*v ddrx v input low voltage v il v ssrx ?0.3 ? ? v input hysteresis v hys 250 ? mv input leakage current (pins in high-impedance input mode) (31) ? v in = v ddrx or v ssrx i in ?1.00 ? 1.00 ? a table 24. static electrical characte ristics - temperature sense module (29) ratings symbol min typ max unit
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 22 4.5.2.1 current injection the power supply must maintain regulation within the v ddx operating range during instantaneous and operating maximum current conditions. if pos itive injection current (v in > v ddx ) is greater than i ddx , the injection current may flow out of vddx and could result in the external power supply going out of regulation. ensure that the external v ddx load will shunt current greater than the maximum injection current. this will be the greatest risk when the mcu is not consuming power; e.g. , if no system cloc k is present, or if the clock rate is very lo w, which would reduce overall power consumption. input leakage current (pins in high-impedance input mode) (32) ? v in = v ddx or v ssx t a = ?40 ? c t a = 25 ? c t a = 70 ? c t a = 85 ? c t a = 105 ? c t a = 110 ? c t a = 120 ? c t a = 125 ? c t a = 130 ? c t a = 150 ? c i in ? 1.0 ? 1.0 ? 8.0 ? 14 ? 26 ? 32 ? 40 ? 60 ? 74 ? 92 ? 240 na output high voltage (pins in output mode), i oh = ?4.0 ma v oh v ddrx ? 0.8 ? ? v output low voltage (pins in output mode), i ol = 4.0 ma v ol ? ? 0.8 v internal pull-up current, v ih min > input voltage > v il max i pul -10 ? -130 ? a internal pull-down current, v ih min > input voltage > v il max i pdh 10 ? 130 ? a input capacitance c in ? 7 ? pf injection current (33) single pin limit total device limit, sum of all injected currents i ics i icp ?2.5 ?25 ? 2.5 25 ma notes 31.maximum leakage current occurs at maximum operating temperatur e. current decreases by approx imately one-half for each 8.0 ? c to 12 ? c in the temperature range from 50 ? c to 125 ? c. 32.maximum leakage current occurs at maximum operating temperatur e. current decreases by approx imately one-half for each 8.0 ? c to 12 ? c in the temperature range from 50 ? c to 125 ? c. 33.refer to section 4.5.2.1, ?current injection" for more details table 27. 5.0 v i/o characteristics for all i/o pins except extal, xtal, test, d2di, and supply pins (4.5 v < v ddrx < 5.5 v; t j : ?40 c to +150 c, unless otherwise noted) ratings symbol min typ max unit
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 23 4.6 dynamic electrical characteristics dynamic characteristics note d under conditions 3.5 v ?? v sup ??? 28 v, -40 ? c ?? t a ??? 125 ? c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. 4.6.1 dynamic electrical characteristics analog die table 28. dynamic electrical characteristics - modes of operation ratings symbol min typ max unit low power oscillator frequency f oscl ? 512 ? khz low power oscillator tolerance over full temperature range analog option 2 analog option 1 f tol_a -4.0 -5.0 ? ? 4.0 5.0 % low power oscillator tole rance - synchronized alfclk (34) alf clock cycle = 1.0 ms alf clock cycle = 2.0 ms alf clock cycle = 4.0 ms alf clock cycle = 8.0 ms f tolc_a f tol -0.2 f tol -0.1 f tol -0.05 f tol -0.025 f tol f tol +0.2 f tol +0.1 f tol +0.05 f tol +0.025 % notes 34.parameter not tested. guaranteed by design and characterization. table 29. dynamic electrical characteri stics - die to die interface - d2d ratings symbol min typ max unit operating frequency (d2dclk, d2d[0:3]) f d2d ? ? 32.768 mhz table 30. dynamic electrical characteristics - resets ratings symbol min typ max unit reset deglitch filter time t rstdf 1.0 2.0 3.2 s reset release time for wdr and hwr t rstrt ? 32 ? s table 31. dynamic electrical characteristics - wake-up / cyclic sense ratings symbol min typ max unit cyclic wake-up time (35) t wakeup alfclk ? tim4ch ms cyclic current measurement step width (36) t step alfclk ? 16bit ms notes 35.cyclic wake-up on alfclk cl ock based 16 bit timer with ma ximum 128x prescaler (min 1x) 36.cyclic wake-up on alfclk cloc k with 16 bit programmable counter table 32. dynamic electrical charact eristics - window watchdog ratings symbol min typ max unit initial non-window watchdog timeout t iwdto see figure 2 ms
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 24 figure 5. lin transmitter timing table 33. dynamic electrical characteristics - lin physical layer interface - lin ratings symbol min typ max unit bus wake-up deglitcher (sleep and stop mode) t propwl 60 80 100 s fast bit rate (programming mode) br fast ? ? 100 kbit/s propagation delay of receiver t rx_pd ? ? 6.0 s symmetry of receiver propagation delay rising edge w.r.t. falling edge t rx_sym -2.0 ? 2.0 s lin driver - 20.0 kbit/s; bus load conditions (c bus ; r bus ): 1.0 nf; 1.0 k ? / 6,8 nf;660 ? / 10 nf;500 ? duty cycle 1: th rec(max) = 0.744 x v sup th dom(max) = 0.581 x v sup 7.0 v ?? v sup ??? 18 v; t bit = 50 s; d1 = t bus_rec(min) /(2 x t bit ) d1 0.396 ? ? duty cycle 2: th rec(min) = 0.422 x v sup th dom(min) = 0.284 x v sup 7.6 v ?? v sup ??? 18 v; t bit = 50 s d2 = t bus_rec(max) /(2 x t bit ) d2 ? ? 0.581 lin driver - 10.0 kbit/s; bus load conditions (c bus ; r bus ): 1.0 nf; 1.0 k ? / 6,8 nf;660 ? / 10 nf;500 ? duty cycle 3: th rec(max) = 0.778 x v sup th dom(max) = 0.616 x v sup 7.0 v ?? v sup ??? 18 v; t bit = 96 s d3 = t bus_rec(min) /(2 x t bit ) d3 0.417 ? ? duty cycle 4: th rec(min) = 0.389 x v sup th dom(min) = 0.251 x v sup 7.6 v ?? v sup ??? 18 v; t bit = 96 s d4 = t bus_rec(max) /(2 x t bit ) d4 ? ? 0.590 lin transmitter timing, (v sup from 7.0 to 18 v) - see figure 5 transmitter symmetry t tran_sym < max(ttran_sym60%, t tran_sym 40%) t tran_sym 60% = t tran_pdf 60% - t tran_pdr 60% t tran_sym 40% = t tran_pdf 40% - t tran_pdr 40% t tran_sym -7.25 0 7.25 s bus tx 60% 40% ttran_pdr60% ttran_pdr40% ttran_pdf60% ttran_pdf40%
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 25 table 34. dynamic electrical characteristics - general purpose i/o - ptb3 / l0] ratings symbol min typ max unit wake-up glitch filter time t wupf 20 s table 35. dynamic electrical ch aracteristics - general purpose i/o - ptb[0...2] ratings symbol min typ max unit gpio digital frequency f ptb 10 mhz propagation delay - rising edge (37) t pdr 20 ns rise time - rising edge (37) t rise 17.5 ns propagation delay - falling edge (37) t pdf 20 ns rise time - falling edge (37) t fall 17.5 ns notes 37.load ptbx = 100 pf table 36. dynamic electrical characteristics - current sense module ratings symbol min typ max unit frequency attenuation (38) , (39) <100 hz (f pass ) >500 hz (f stop ) 40 3.0 db signal update rate (40) f iupdate 0.5 8.0 khz signal path match with voltage channel f ivmatch 2.0 s gain change duration (automatic gcb active) (41) t gc 14 s notes 38.characteristics identical to voltage sense module 39.with default lpf coefficients 40.after passing decimation filter 41.parameter not tested. guaranteed by design and characterization. table 37. dynamic electrical characteristics - voltage sense module ratings symbol min typ max unit frequency attenuation (42) , (43) 95...105 hz (f pass ) >500 hz (f stop ) 40 3.0 db signal update rate (44) f vupdate 0.5 8.0 khz signal path match with current channel (45) f ivmatch 2.0 s notes 42.characteristics identical to voltage sense module 43.with default lpf coefficients 44.after passing decimation filter 45.parameter not tested. guaranteed by design and characterization.
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 26 4.6.2 dynamic electrical characteristics mcu die 4.6.2.1 nvm 4.6.2.1.1 timing parameters the time base for all nvm program or erase operations is deriv ed from the bus clock using the fclkdiv register. the frequency of this derived clock must be se t within the limits specified as f nvmop . the nvm module does not have any means to monitor the frequency, and will not prevent program or erase operations at frequencies above or below the specified minimum. when attempting to program or erase the nvm module at a lower frequency, a full prog ram or erase transition is not assured. the following sections provide equations which can be used to det ermine the time required to ex ecute specific flash commands. all timing parameters are a function of the bus clock frequency, f nvmbus . all program and erase times are also a function of the nvm operating frequency, f nvmop . a summary of key timing parameters can be found in table 39 . 4.6.2.1.1.1 erase verify all bl ocks (blank check) (fcmd=0x01) the time required to perform a blank check on all blocks is dependen t on the location of the first non-blank word starting at r elative address zero. it takes one bus cycl e per phrase to verify, plus a setup of the command . assuming that no non -blank location is found, then the time to erase verify all blocks is given by: 4.6.2.1.1.2 erase verify blo ck (blank check) (fcmd=0x02) the time required to perform a blank check is dependent on the lo cation of the first non-blank word starting at relative addres s zero. it takes one bus cycle per phrase to verify, plus a setup of the command. assuming that no non-blank location is found, then the time to erase verify a p-flash block is given by: assuming that no non-blank location is found, then the time to erase verify a d-flash block is given by: 4.6.2.1.1.3 erase verify p-flash section (fcmd=0x03) the maximum time to erase verify a section of p-flas h depends on the number of phrases being verified (n vp ) and is given by: 4.6.2.1.1.4 read once (fcmd=0x04) the maximum read once time is given by: table 38. dynamic electrical characteris tics - temperature sense module ratings symbol min typ max unit signal update rate (46) f tupdate 1.0 4.0 khz notes 46.1.0 khz with chopper enabled, 4.0 khz with chopper disabled (fixed decimeter = 128) t check 35500 1 f nvmbus -------------------- - ? = t pcheck 33500 1 f nvmbus --------------------- ? = t dcheck 2800 1 f nvmbus -------------------- - ? = t 450 n vp + ?? 1 f nvmbus -------------------- - ? ?
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 27 4.6.2.1.1.5 program p-flash (fcmd=0x06) the programming time for a single phrase of four p-flash words and the two seven-bit ecc fields is dependent on the bus frequency, f nvmbus , as well as on the nvm operating frequency, f nvmop . the typical phrase programming time is given by: the maximum phrase programming time is given by: 4.6.2.1.1.6 program once (fcmd=0x07) the maximum time required to program a p-flash program once field is given by: 4.6.2.1.1.7 erase al l blocks (fcmd=0x08) the time required to erase all blocks is given by: 4.6.2.1.1.8 erase p-fl ash block (fcmd=0x09) the time required to erase the p-flash block is given by: 4.6.2.1.1.9 erase p-flash sector (fcmd=0x0a) the typical time to erase a 512-byte p-flash sector is given by: the maximum time to erase a 512-by te p-flash sector is given by: 4.6.2.1.1.10 unsecure flash (fcmd=0x0b) the maximum time required to erase and unsecure the flash is given by: (for 128 kbyte p-flash and 4.0 kbyte d-flash) t 400 1 f nvmbus -------------------- - ? = t ppgm 164 1 f nvmop ------------------ 2000 1 f nvmbus -------------------- - ? + ? ? t ppgm 164 1 f nvmop ------------------ 2500 1 f nvmbus -------------------- - ? + ? ? t 164 1 f nvmop ------------------ 2150 1 f nvmbus -------------------- - ? + ? ? t mass 100100 1 f nvmop ------------------ 70000 1 f nvmbus -------------------- - ? + ? ? t pmass 100100 1 f nvmop ------------------ 67000 1 f nvmbus -------------------- - ? + ? ? t pera 20020 1 f nvmop ------------------ ? 700 1 f nvmbus -------------------- - ? + ? t pera 20020 1 f nvmop ------------------ ? 1400 1 f nvmbus -------------------- - ? + ? t uns 100100 1 f nvmop ------------------ 70000 1 f nvmbus --------------------- ? + ? ?
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 28 4.6.2.1.1.11 verify back door access key (fcmd=0x0c) the maximum verify back door access key time is given by: 4.6.2.1.1.12 set user ma rgin level (fcmd=0x0d) the maximum set user margin level time is given by: 4.6.2.1.1.13 set field ma rgin level (fcmd=0x0e) the maximum set field margin level time is given by: 4.6.2.1.1.14 erase verify d-flash section (fcmd=0x10) the time required to erase verify d-flash for a given number of words n w is given by: 4.6.2.1.1.15 program d-flash (fcmd=0x11) d-flash programming time is dependent on the number of words being programmed and their location with respect to a row boundary, since programming across a row boundary requires extr a steps. the d-flash programming time is specified for different cases: 1,2,3,4 words and 4 words across a row boundary. the typical d-flash programming time is given by the following equation, where n w denotes the number of words; bc=0 if no row boundary is crossed and bc=1, if a row boundary is crossed: the maximum d-flash programming time is given by: 4.6.2.1.1.16 erase d-fl ash sector (fcmd=0x12) typical d-flash sector erase times, expected on a new dev ice where no margin verify fails occur, is given by: maximum d-flash sector er ase times is given by: the d-flash sector erase time is ~5.0 ms on a new device and can extend to ~20 ms as the flash is cycled. t 400 1 f nvmbus -------------------- - ? = t 350 1 f nvmbus -------------------- - ? = t 350 1 f nvmbus -------------------- - ? = t dcheck 450 n w + ?? 1 f nvmbus --------------------- ? ? t dpgm 14 54 n w ? ?? + ? 14 bc ? ??? + 1 f nvmop ------------------ ? ? ? ? ? 500 525 n w ? ?? 100 bc ? ?? ++ ?? 1 f nvmbus -------------------- - ? ? ? ? ? + ? t dpgm 14 54 n w ? ?? + ? 14 bc ? ??? + 1 f nvmop ------------------ ? ? ? ? ? 500 750 ? n w ? ? 100 bc ? ?? ++ ?? 1 f nvmbus -------------------- - ? ? ? ? ? + ? t dera 5025 1 f nvmop ------------------ 700 1 f nvmbus --------------------- ? + ? ? t dera 20100 1 f nvmop ------------------ 3400 1 f nvmbus -------------------- - ? + ? ?
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 29 4.6.2.1.2 nvm reliability parameters the reliability of the nvm blocks is guaranteed by stress test du ring qualification, constant process monitors, and burn-in to screen early life failures. the data retention and program/erase cycling failure rates are spec ified at the operating conditio ns noted. the program/erase cycle count on the sector is in cremented every time a sector or mass erase event is executed. table 39. nvm timing characteristics (ftmrc) rating symbol min typ (47) max (48) unit (49) bus frequency f nvmbus 1.0 ? 32.768 mhz operating frequency f nvmop 0.8 1.0 1.05 mhz erase all blocks (mass erase) time t mass ? 100 130 ms erase verify all blocks (blank check) time t check ? ? 35500 t cyc unsecure flash time t uns ? 100 130 ms p-flash block erase time t pmass ? 100 130 ms p-flash erase verify (blank check) time t pcheck ? ? 33500 t cyc p-flash sector erase time t pera ? 20 26 ms p-flash phrase programming time t ppgm ? 226 285 ? s d-flash sector erase time t dera ? 5 (50) 26 ms d-flash erase verify (blank check) time t dcheck ? ? 2800 t cyc d-flash one word programming time t dpgm1 ? 100 107 ? s d-flash two word programming time t dpgm2 ? 170 185 ? s d-flash three word programming time t dpgm3 ? 241 262 ? s d-flash four word programming time t dpgm4 ? 311 339 ? s d-flash four word programming time crossing row boundary t dpgm4c ? 328 357 ? s notes 47.typical program and erase times are based on typical f nvmop and maximum f nvmbus 48.maximum program and erase times are based on minimum f nvmop and maximum f nvmbus 49.t cyc = 1 / f nvmbus 50.typical value for a new device table 40. nvm reliability characteristics (51) rating symbol min typ max unit data retention at an average junction temperature of t javg = 85 ? c (51) after up to 10,000 program/erase cycles t nvmret 20 100 (53) ? years program flash number of program/erase cycles (-40 ? c ? t j ? 150 ? c ? n flpe 10 k 100 k (54) ? cycles data retention at an average junction temperature of t javg = 85 ? c (51) after up to 50,000 program/erase cycles t nvmret 5.0 100 (53) ? years data retention at an average junction temperature of t javg = 85 ? c (51) after up to 10,000 program/erase cycles t nvmret 10 100 (53) ? years data retention at an average junction temperature of t javg = 85 ? c (51) after less than 100 program/erase cycles t nvmret 20 100 (53) ? years
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 30 4.6.2.2 phase locked loop 4.6.2.2.1 jitter definitions with each transition of the feedback clock, the deviation from the reference clock is measured and input voltage to the vco is adjusted accordingly.the adjustment is done continuously wit h no abrupt changes in the vcoclk frequency. noise, voltage, temperature, and other factors, c ause slight variations in the control loop resulting in a clock jitter. this jitter affects th e real minimum and maximum clock periods as illustrated in figure 6 . figure 6. jitter definitions the relative deviation of t nom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (n). defining the jitter as: for n < 100, the following equation is a good fit for the maximum jitter: data flash number of program/erase cycles (-40 ? c ? t j ? 150 ? c ? n flpe 50 k 500 k (54) ? cycles notes 51.conditions are shown in table 10 , unless otherwise noted 52.t javg does not exceed 85 ? c in a typical temperature profile over the lifetime of a consumer, industrial, or automotive application. 53.typical data retention values are based on intrinsic capabili ty of the technology measured at high temperature and de-rated to 25 ? c using the arrhenius equation. for additional information on how freescale defines typical data retention, refer to engineering bullet in eb618 54.spec table quotes typical endurance evaluated at 25 ? c for this product family. for additional in formation on how freescale defines typical endurance, refer to engineering bulletin eb619. table 40. nvm reliability characteristics (51) 23 n-1n 1 0 t nom t max1 t min1 t maxn t minn jn ?? max 1 t max n ?? nt nom ? ----------------------- ?1 t min n ?? nt nom ? ---------------------- - ? , ?? ?? ?? = jn ?? j 1 n -------- =
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 31 figure 7. maximum bus clock jitter approximation note on timers and serial modules a prescaler will elim inate the effect of the jitter to a large extent. 4.6.2.2.2 electrical char acteristics for the pll 4.6.2.3 reset, oscillator and internal clock generation table 41. pll characteristics rating symbol min typ max unit vco frequency during system reset f vcorst 8 32 mhz vco locking range f vco 32.768 65.536 mhz lock detection ?? lock | 0 1.5 % (55) un-lock detection ?? unl | 0.5 2.5 % (55) time to lock t lock 150 + 256/f ref ? s jitter fit parameter 1 (56) j 1 1.2 % notes 55.% deviation from target frequency 56.f ref = 1.024 mhz, f bus = 32.768 mhz equivalent f pll = 65.536 mhz, refrq=00, syndiv=$1f, vcofrq=01, postdiv=$00 table 42. dynamic electrical characte ristics - mcu clock generator ratings symbol min typ max unit bus frequency f bus ? ? 32.768 mhz internal reference frequency f irc1m_trim ? 1.024 ? mhz internal clock frequency tolerance (57) , (58) analog option 2 analog option 1 f tol -1.0 -1.2 ? ? 1.0 1.2 % clock frequency tolerance wi th external oscillator (59) t tolext -0.5 0.5 % crystal oscillator range f osc 4.0 16 mhz oscillator start-up time (lcp, 4.0 mhz) (60) t uposc ? 2.0 10 ms oscillator start-up time (lcp, 8.0 mhz) (60) t uposc ? 1.6 8.0 ms oscillator start-up time (lcp, 16 mhz) (60) t uposc ? 1.0 5.0 ms 1 5 10 20 n j(n)
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 32 4.6.2.4 reset characteristics 4.6.2.5 spi timing this section provides electrical parameters and ratings for the spi. the measurement conditions are listed in ta b l e 44 . clock monitor failure assert frequency f cmfa 200 400 1000 khz notes 57.-40 ? c ?? t a ??? 125 ? c 58. ? 1.3%, including lifetime drift 59.dependent on the external osc 60.these values apply for carefully designed pcb layouts with capacitors that match the crystal/resonator requirements table 43. reset and stop characteristics (61) rating symbol min typ max unit reset input pulse width, minimum input time pw rstl 2.0 t vcorst startup from reset n rst 768 t vcorst stop recovery time t stp_rec 50 ? s notes 61.conditions are shown in table 10 unless otherwise noted table 44. measurement conditions description value unit drive mode full drive mode ? load capacitance c load (62) , on all outputs 50 pf notes 62.conditions are shown in table 10 unless otherwise noted table 42. dynamic electrical charac teristics - mcu clock generator ratings symbol min typ max unit
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 33 4.6.2.5.1 master mode the timing diagram for master mode with tr ansmission format cpha = 0 is depicted in figure 8 . figure 8. spi master timing (cpha = 0) the timing diagram for master mode with transmission format cpha=1 is depicted in figure 9 . figure 9. spi master timing (cpha = 1) the timing characteristics for master mode are listed in ta b l e 45 . sck (output) sck (output) miso (input) mosi (output) ss (output) 1 9 5 6 msb in2 bit msb-1... 1 lsb in msb out2 lsb out bit msb-1... 1 11 4 4 2 10 (cpol = 0) (cpol = 1) 3 13 13 1. if configured as an output. 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, bit 2... msb. 12 12 sck (output) sck (output) miso (input) mosi (output) 1 5 6 msb in2 bit msb-1... 1 lsb in master msb out2 master lsb out bit msb-1... 1 4 4 9 12 13 11 port data (cpol = 0) (cpol = 1) port data ss (output) 2 12 13 3 1.if configured as output 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1,bit 2... msb.
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 34 4.6.2.5.2 slave mode the timing diagram for slave mode with transmission format cpha = 0 is depicted in figure 10 . figure 10. spi slave timing (cpha = 0) the timing diagram for slave mode with transmission format cpha = 1 is depicted in figure 11 . table 45. spi master mode timing characteristics num c characteristic symbol min typ max unit 1 d sck frequency f sck 1/2048 ? 1 ? 2 f bus 1 d sck period t sck 2.0 ? 2048 t bus 2 d enable lead time t lead ? 1/2 ? t sck 3 d enable lag time t lag ? 1/2 ? t sck 4 d clock (sck) high or low time t wsck ? 1/2 ? t sck 5 d data setup time (inputs) t su 8.0 ? ? ns 6 d data hold time (inputs) t hi 8.0 ? ? ns 9 d data valid after sck edge t vsck ? ? 29 ns 10 d data valid after ss fall (cpha = 0) t vss ? ? 15 ns 11 d data hold time (outputs) t ho 20 ? ? ns 12 d rise and fall time inputs t rfi ? ? 8.0 ns 13 d rise and fall time outputs t rfo ? ? 8.0 ns sck (input) sck (input) mosi (input) miso (output) ss (input) 1 9 5 6 msb in bit msb-1... 1 lsb in slave msb slave lsb out bit msb-1... 1 11 4 4 2 7 (cpol = 0) (cpol = 1) 3 13 note: not defined 12 12 11 see 13 note 8 10 see note
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 35 figure 11. spi slave timing (cpha = 1) the timing characteristics for slave mode are listed in ta b l e 46 . table 46. spi slave mode timing characteristics num c characteristic symbol min typ max unit 1 d sck frequency f sck dc ? 1 ? 4 f bus 1 d sck period t sck 4.0 ? ? f bus 2 d enable lead time t lead 4.0 ? ? f bus 3 d enable lag time t lag 4.0 ? ? f bus 4 d clock (sck) high or low time t wsck 4.0 ? ? f bus 5 d data setup time (inputs) t su 8.0 ? ? ns 6 d data hold time (inputs) t hi 8.0 ? ? ns 7 d slave access time (time to data active) t a ? ? 20 ns 8 d slave miso disable time t dis ? ? 22 ns 9 d data valid after sck edge t vsck ? ? 29 + 0.5 ? t bus (63) ns 10 d data valid after ss fall t vss ? ? 29 + 0.5 ? t bus (63) ns 11 d data hold time (outputs) t ho 20 ? ? ns 12 d rise and fall time inputs t rfi ? ? 8.0 ns 13 d rise and fall time outputs t rfo ? ? 8.0 ns notes 63.0.5 t bus added due to internal synchronization delay sck (input) sck (input) mosi (input) miso (output) 1 5 6 msb in bit msb-1... 1 lsb in msb out slave lsb out bit msb-1... 1 4 4 9 12 13 11 (cpol = 0) (cpol = 1) ss (input) 2 12 13 3 note: not defined slave 7 8 see note
electrical characteristics mm912_637, rev. 3.0 freescale semiconductor 36 4.7 thermal protection characteristics characteristics noted under conditions 3.5 v ?? v sup ??? 28 v, -40 ? c ?? t a ??? 125 ? c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. table 47. thermal characteristics ratings symbol min typ max unit vddh/vdda/vddx high temperature warning (hti) threshold hysteresis t hti t hti_h 110 125 10 140 c vddh/vdda/vddx over-temperature shutdown threshold hysteresis t sd t sd_h 155 165 10 180 c lin over-temperature shutdown t linsd 150 165 180 c lin over-temperature shutdown hysteresis t linsd_hys 20 c
mm912_637, rev. 3.0 freescale semiconductor 37 4.8 electromagnetic compatibility (emc) all esd testing is in conformity with the cdf-aec-q100 stress test qualification for automotive grade integrated circuits. duri ng the device qualification, esd stresses ar e performed for the human bo dy model (hbm), machine model (mm), charge device model (cdm), as well as lin tran sceiver specific specifications. a device will be defined as a failure, if after exposure to esd pulses, the device no longer meets the device specification. complete dc parametric and functional te sting is performed per the applicable device specificati on at room temperature, followed by hot temperature, unless specified otherwise in the device specification. the immunity against transients for the lin, ptb3/l0, vsense, isenseh , isensel, and vsup, is specified according to the lin conformance test specification - sect ion lin emc test specificat ion (iso7637-2), refer to the lin conformance test certification report - available as separate document. table 48. electromagnetic compatibility ratings symbol value / limit unit esd - human body model (hbm) following aec-q100 / jesd22-a114 ? (c zap = 100 pf, r zap = 1500 ? ) - lin (all gnds shorted) - all other pins v hbm 8.0 2.0 kv esd - charged device model (cdm) following aec-q100 corner pins all other pins v cdm 750 500 v esd - machine model (mm) following aec-q100 (c zap = 200 pf, r zap = 0 ? ), all pins v mm 200 v latch-up current at t a = 125 ? c (64) i lat 100 ma esd gun - lin conformance test specification (65) , unpowered, contact discharge. (c zap = 150 pf, r zap = 330 ? ); lin (no bus filter c bus ); vsense with serial r vsense ; vsup with c vsup ; ptb3 with serial r ptb3 6000 v esd gun - iec 61000-4-2 test specification (66) , unpowered, contact discharge. (c zap = 150 pf, r zap = 330 ? ); lin (no bus filter c bus ); vsense with serial r vsense ; vsup with c vsup ; ptb3 with serial r ptb3 6000 v esd gun - iso10605 (66) , unpowered, contact discharge, c zap = 150 pf, ? r zap = 2.0 k ??? lin (no bus filter c bus ); vsense with serial r vsense ; vsup with c vsup ; ptb3 with serial r ptb3 8000 v esd gun - iso10605 (66) , powered, contact discharge, c zap = 330 pf, r zap = 2.0 k ??? lin (no bus filter c bus ); vsense with serial r vsense ; vsup with c vsup ; ptb3 with serial r ptb3 8000 v notes 64.input voltage limit = -2.5 to 7.5 v 65.certification available on request 66.tested internally only, following the reference document test procedure.
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 38 5 functional description and application information this chapter describes the mm912_637 dual die device functions on a block by block base. the following symbols are shown on all module cover pages to distinguish between the module location being the mcu die or the analog die: the documented module is physically located on the analog die. this applies to section 5.1, ?mm912_637 - analog die overview" through section 5.14, ?die to die interface - target" . the documented module is physically located on the microcontroller die. this applies to section 5.1, ?mm912_637 - analog die overview" through section 5.25, ?mcu - die-to-die initiator (d2div1)" . sections concerning both die or the complete de vice will not have a specific indication (e.g. section 6, ?mm912_637 - trimming" ). 5.0.1 introduction many types of electronic control units (e cus) are connected to and supplied from the main car battery in modern cars. depending on the cars mode of operation (drive, start, stop, standby), the battery must deliver different currents to the different ecus. the vehicle power management has several sub-f unctions, like control of the set-point valu e of the power generator, dynamic load management during drive, star t, stop, and standby mode. the application specific integrated circuit (asic) allows for two application circuits , depending on whether the bias current o f the mm912_637 itself shall be incl uded into the current measurement. figure 12. typical ibs application (device gnd = chassis gnd) analog mcu battery minus pole chassis ground isensel isenseh gnd vsense vsup battery plus pole lin lin r sense c lin c bat r shunt
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 39 figure 13. typical ibs application (device gnd = battery minus) the vehicle power system needs actual measurement data from th e battery, mainly voltage, current, and temperature. out of these measurement data, it needs calculat ed characteristics, such as dynamic inte rnal battery resistance. therefore, an intelligent battery sensor (ibs) module is required. to efficiently measure the batt ery voltage, current, and temperat ure, the ibs module is directly connected to and supplied from the battery. it is located directly on the n egative pole of the battery; the supply of the ibs module comes from 'kl30'. the ba ttery current is measured via a low-ohmic shunt resistor, connected between the negative pole of the battery and the chassis ground of the car. the battery vo ltage is measured at 'kl30'. the data communication between the ibs module and the higher level ecu is done via a lin interface. the mm912_637 is able to measure its junction temperature. that temperature is the basis for a mo del in software that calculate s the battery temperature out of the junction temperature. an optional external temperature se nse input is provided as well. 5.0.2 device register map table 49 shows the device register memory map overview. table 49. device register memory map overview address module size (bytes) 0x0000?0x0003 pim (port integration module ) 4 0x0004?0x0009 reserved 6 0x000a?0x000b mmc (memory map control) 2 0x000c?0x000d pim (port integration module ) 2 0x000e?0x000f reserved 2 0x0010?0x0015 mmc (memory map control) 8 0x0016?0x0019 reserved 2 0x001a?0x001b device id register 2 0x001c?0x001e reserved 4 0x001f int (interrupt module) 1 0x0020?0x002f dbg (debug module) 16 0x0030?0x0033 reserved 4 0x0034?0x003f cpmu (clock and power management) 12 0x0040?0x00d7 reserved 152 0x00d8?0x00df d2di (die 2 die initiator) 8 battery minus pole chassis ground isensel isenseh gnd vsense vsup battery plus pole lin lin r sense c lin c bat r shunt
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 40 note the reserved register space shown in table 49 is not allocated to any module. this register space is reserved for future use. writing to these locations has no effect. read access to these locations returns a zero. 5.0.3 detailed module register map table 50 to ta b l e 63 show the detailed module maps of the mm912_637. 0x00e0?0x00e7 reserved 32 0x00e8?0x00ef spi (serial peripheral interface) 8 0x00f0?0x00ff reserved 32 0x0100?0x0113 ftmrc control registers 20 0x0114?0x011f reserved 12 0x0120?0x017f pim (port integration module ) 96 0x0180?0x01ef reserved 112 0x01f0?0x01fc cpmu (clock and power management) 13 0x01fd?0x01ff reserved 3 0x0200-0x02ff d2di (die 2 die initiator, blocking access window) 256 0x0300?0x03ff d2di (die 2 die initiator, non-blocking write window) 256 table 50. 0x0000?0x0009 port integration module (pim) 1 of 3 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0000 pta r pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 w 0x0001 pte r 0 0 0 0 0 0 pe1 pe0 w 0x0002 ddra r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 w 0x0003 ddre r 0 0 0 0 0 0 ddre1 ddre0 w 0x0004-0 x0009 reserved r 0 0 0 0 0 0 0 0 w table 51. 0x000a?0x000b memory map control (mmc) 1 of 2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x000a reserved r 0 0 0 0 0 0 0 0 w 0x000b mode r modc 0 0 0 0 0 0 0 w table 49. device register memo ry map overview (continued) address module size (bytes)
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 41 table 52. 0x000c?0x000f port integration module (pim) map 2 of 3 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x000c pucr r 0 bkpue 0 0 0 0 pdpee 0 w 0x000d rdriv r 0 0 0 0 rdrd rdrc 0 0 w 0x000e-0 x000f reserved r 0 0 0 0 0 0 0 0 w table 53. 0x0010?0x0019 memory map control (mmc) 2 of 2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0010 reserved r 0 0 0 0 0 0 0 0 w 0x0011 direct r dp15 dp14 dp13 dp12 dp11 dp10 dp9 dp8 w 0x0012-0x 0014 reserved r 0 0 0 0 0 0 0 0 w 0x0015 ppage r 0 0 0 0 pix3 pix2 pix1 pix0 w 0x0016-0x 0019 reserved r 0 0 0 0 0 0 0 0 w table 54. 0x001a?0x001e miscellaneous peripheral address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x001a partidh r partidh w 0x001b partidl r partidl w 0x001c-0 x001e reserved r 0 0 0 0 0 0 0 0 w table 55. 0x001f interrupt module (s12sint) 0x001f ivbr r ivb_addr[7:0] w table 56. 0x0020?0x002f debug module (s12xdbg) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0020 dbgc1 r arm 0 0 bdm dbgbrk 0 comrv w trig 0x0021 dbgsr r tbf (67) 0 0 0 0 ssf2 ssf1 ssf0 w 0x0022 dbgtcr r 0 tsource 0 0 trcmod 0 talign w
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 42 0x0023 dbgc2 r 0 0 0 0 0 0 abcm w 0x0024 dbgtbh r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0025 dbgtbl r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0026 dbgcnt r tbf (67) 0 cnt w 0x0027 dbgscrx r 0 0 0 0 sc3 sc2 sc1 sc0 w 0x0027 dbgmfr r 0 0 0 0 0 mc2 mc1 mc0 w 0x0028 (68) dbgactl r sze sz tag brk rw rwe ndb compe w 0x0028 (69) dbgbctl r sze sz tag brk rw rwe 0 compe w 0x0028 (70) dbgcctl r 0 0 tag brk rw rwe 0 compe w 0x0029 dbgxah r 0 0 0 0 0 0 bit 17 bit 16 w 0x002a dbgxam r bit 15 14 13 12 11 10 9 bit 8 w 0x002b dbgxal r bit 7 6 5 4 3 2 1 bit 0 w 0x002c dbgadh r bit 15 14 13 12 11 10 9 bit 8 w 0x002d dbgadl r bit 7 6 5 4 3 2 1 bit 0 w 0x002e dbgadhm r bit 15 14 13 12 11 10 9 bit 8 w 0x002f dbgadlm r bit 7 6 5 4 3 2 1 bit 0 w notes 67.this bit is visible at dbgcnt[7] and dbgsr[7] 68.this represents the contents if the comparator a control register is blended into this address. 69.this represents the contents if the comparator b control register is blended into this address. 70.this represents the contents if the comparator c control register is blended into this address. table 56. 0x0020?0x002f debug module (s12xdbg) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 43 table 57. 0x0034?0x003f clock and power management (cpmu) 1 of 2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0034 cpmu synr r vcofrq[1:0] syndiv[5:0] w 0x0035 cpmu refdiv r reffrq[1:0] 0 0 refdiv[3:0] w 0x0036 cpmu postdiv r 0 0 0 postdiv[4:0] w 0x0037 cpmuflg r rtif porf lvrf lockif lock ilaf oscif uposc w 0x0038 cpmuint r rtie 0 0 lockie 0 0 oscie 0 w 0x0039 cpmuclks r pllsel pstp 0 0 pre pce rti oscsel cop oscsel w 0x003a cpmupll r 0 0 fm1 fm0 0 0 0 0 w 0x003b cpmurti r rtdec rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 w 0x003c cpmucop r wcop rsbck 0 0 0 cr2 cr1 cr0 w wrtmask 0x003d reserved r 0 0 0 0 0 0 0 0 w 0x003e reserved r 0 0 0 0 0 0 0 0 w 0x003f cpmu armcop r 0 0 0 0 0 0 0 0 w bit 7 6 5 4 3 2 1 bit 0 table 58. 0x00d8?0x00df die 2 die initiator (d2di) 1 of 3 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00d8 d2dctl0 r d2den d2dcw d2dswai 0 0 0 d2dclkdiv[1:0] w 0x00d9 d2dctl1 r d2die 0 0 0 timout[3:0] w 0x00da d2dstat0 r errif ackerf cnclf timef terrf parf par1 par0 w 0x00db d2dstat1 r d2dif d2dbsy 0 0 0 0 0 0 w 0x00dc d2dadrhi r rwb sz8 0 nblk 0 0 0 0 w 0x000d d2dadrlo r adr[7:0] w 0x00de d2ddatahi r data[15:8] w 0x00df d2ddatalo r data[7:0] w
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 44 table 59. 0x00e8?0x00ef serial peripheral interface (spi) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00e8 spicr1 r spie spe sptie mstr cpol cpha ssoe lsbfe w 0x00e9 spicr2 r 0 xfrw 0 modfen bidiroe 0 spiswai spc0 w 0x00ea spibr r 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w 0x00eb spisr r spif 0 sptef modf 0 0 0 0 w 0x00ec spidrh r r15 r14 r13 r12 r11 r10 r9 r8 w t15 t14 t13 t12 t11 t10 t9 t8 0x00ed spidrl r r7 r6 r5 r4 r3 r2 r1 r0 w t7 t6 t5 t4 t3 t2 t1 t0 0x00ee reserved r 0 0 0 0 0 0 0 0 w 0x00ef reserved r 0 0 0 0 0 0 0 0 w table 60. 0x0100?0x0113 flash control & status register ftmrc address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0100 fclkdiv r fdivld fdivlck fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 w 0x0101 fsec r keyen1 keyen0 rnv5 rnv4 rnv3 rnv2 sec1 sec0 w 0x0102 fccobix r 0 0 0 0 0 ccobix2 ccobix1 ccobix0 w 0x0103 reserved r 0 0 0 0 0 0 0 0 w 0x0104 fcnfg r ccie 0 0 ignsf 0 0 fdfd fsfd w 0x0105 fercnfg r 0 0 0 0 0 0 dfdie sfdie w 0x0106 fstat r ccif 0 accerr fpviol mgbusy rsvd mgstat1 mgstat0 w 0x0107 ferstat r 0 0 0 0 0 0 dfdif sfdif w 0x0108 fprot r fpopen rnv6 fphdis fphs1 fphs0 fpldis fpls1 fpls0 w 0x0109 dfprot r dpopen 0 0 0 dps3 dps2 dps1 dps0 w 0x010a fccobhi r ccob15 ccob14 ccob13 ccob12 ccob11 ccob10 ccob9 ccob8 w
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 45 0x010b fccoblo r ccob7 ccob6 ccob5 ccob4 ccob3 ccob2 ccob1 ccob0 w 0x010c-0 x010f reserved r 0 0 0 0 0 0 0 0 w 0x0110 fopt r nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 w 0x0111- 0x0113 reserved r 0 0 0 0 0 0 0 0 w table 61. 0x0120 port integration module (pim) 2 of 2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0120 ptia r ptia7 ptia6 ptia5 ptia4 ptia3 ptia2 ptia1 ptia0 w 0x0121 ptie r 0 0 0 0 0 0 ptie1 ptie0 w 0x0122- 0x017f reserved r 0 0 0 0 0 0 0 0 w table 62. 0x01f0?0x01ff clock and power management (cpmu) 2of 2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x01f0 reserved r 0 0 0 0 0 0 0 0 w 0x01f1 cpmu lvctl r 0 0 0 0 0 lvds lvie lvif w 0x01f2- 0x01f7 reserved r 0 0 0 0 0 0 0 0 w 0x01f8 cpmu irctrimh r tctrim[3:0] 0 0 irctrim[9:8] w 0x01f9 cpmu irctriml r irctrim[7:0] w 0x01fa cpmuosc r osce oscbw oscpins_ en oscfilt[4:0] w 0x01fb cpmuprot r 0 0 0 0 0 0 0 prot w 0x01fc reserved r 0 0 0 0 0 0 0 0 w table 60. 0x0100?0x0113 flash control & status register ftmrc
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 46 table 63. analog die registers - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset (71) name 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0 0x00 pcr_ctl pcr control register r 0 0 0 0 0 0 0 0 w htiem uviem hwrm 0 pfm[1:0] opmm[1:0] r htie uvie 0 0 pf[1:0] opm[1:0] w hwr 0 0x02 pcr_sr (hi) r htf uvf hwrf wdrf hvrf lvrf wultcf wlpmf pcr status register w write 1 will clear the flags 0x03 pcr_sr (lo) r wuahth f wucthf wucalf wulinf wuptb3 f wuptb2 f wuptb1 f wuptb0 f pcr status register w write 1 will clear the flags 0x04 pcr_presc pcr 1.0 ms prescaler r presc[15:0] w r w 0x06 pcr_wue (hi) r wuahth wucth wucal wulin wuptb3 wuptb2 wuptb1 wuptb0 wake-up enable register w 0x07 pcr_wue (lo) r wultc 0 0 0 0 0 0 0 wake-up enable register w 0x08 int_src (hi) r tov ch3 ch2 ch1 ch0 lti hti uvi interrupt source register w 0x09 int_src (lo) r 0 0 cal ltc cvmi rx tx err interrupt source register w 0x0a int_vect r 0 0 0 0 irq[3:0] interrupt vector register w 0x0b reserved r 0 0 0 0 0 0 0 0 w 0x0c int_msk (hi) r tovm ch3m ch2m ch1m ch0m ltim htim uvim interrupt mask register w 0x0d int_msk (lo) r 0 0 calm ltcm cvmm rxm txm errm interrupt mask register w 0x0e trim_alf (hi) r prdf 0 0 apresc[12:8] trim for accurate 1.0 ms low freq clock w 0x0f trim_alf (lo) r apresc[7:0] trim for accurate 1.0 ms low freq clock w 0x10 wd_ctl watchdog control register r 0 0 0 0 0 0 0 0 w wdtstm wdtom[2:0] r wdtst 0 0 0 0 wdto[2:0] w 0x12 wd_sr r 0 0 0 0 0 0 wdoff wdwo watchdog status register w
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 47 0x13 reserved r 0 0 0 0 0 0 0 0 w 0x14 wd_rr r wdr[7:0] watchdog rearm register w 0x15 reserved r 0 0 0 0 0 0 0 0 w 0x16 reserved r 0 0 0 0 0 0 0 0 w 0x17 reserved r 0 0 0 0 0 0 0 0 w 0x18 scibd (hi) r lbkdie rxedgi e 0 sbr12 sbr11 sbr10 sbr9 sbr8 sci baud rate register w 0x19 scibd (lo) r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 sci baud rate register w 0x1a scic1 r loops 0 rsrc m 0 ilt pe pt sci control register 1 w 0x1b scic2 r tie tcie rie ilie te re rwu sbk sci control register 2 w 0x1c scis1 r tdre tc rdrf idle or nf fe pf sci status register 1 w 0x1d scis2 r lbkdif rxedgif 0 rxinv rwuid brk13 lbkde raf sci status register 2 w 0x1e scic3 r r8 t8 txdir txinv orie neie feie peie sci control register 3 w 0x1f scid r r7 r6 r5 r4 r3 r2 r1 r0 sci data register w t7 t6 t5 t4 t3 t2 t1 t0 0x20 tios r 0 0 0 0 ios3 ios2 ios1 ios0 timer input capture/output compare select w 0x21 cforc r 0 0 0 0 0 0 0 0 timer compare force register w foc3 foc2 foc1 foc0 0x22 oc3m r 0 0 0 0 oc3m3 oc3m2 oc3m1 oc3m0 output compare 3 mask register w 0x23 oc3d r 0 0 0 0 oc3d3 oc3d2 oc3d1 oc3d0 output compare 3 data register w 0x24 tcnt (hi) r tcnt[15:0] timer count register w 0x25 tcnt (lo) r timer count register w table 63. analog die registers - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset (71) name 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 48 0x26 tscr1 r ten 0 0 tffca 0 0 0 0 timer system control register 1 w 0x27 ttov r 0 0 0 0 tov3 tov2 tov1 tov0 timer toggle overflow register w 0x28 tctl1 r om3 ol3 om2 ol2 om1 ol1 om0 ol0 timer control register 1 w 0x29 tctl2 r edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a timer control register 2 w 0x2a tie r 0 0 0 0 c3i c2i c1i c0i timer interrupt enable register w 0x2b tscr2 r toi 0 0 0 tcre pr2 pr1 pr0 timer system control register 2 w 0x2c tflg1 r 0 0 0 0 c3f c2f c1f c0f main timer interrupt flag 1 w 0x2d tflg2 r tof 0 0 0 0 0 0 0 main timer interrupt flag 2 w 0x2e tc0 (hi) r tc0[15:0] timer input capture/output compare register 0 w 0x2f tc0 (lo) r timer input capture/output compare register 0 w 0x30 tc1 (hi) r tc1[15:0] timer input capture/output compare register 1 w 0x31 tc1 (lo) r timer input capture/output compare register 1 w 0x32 tc2 (hi) r tc2[15:0] timer input capture/output compare register 2 w 0x33 tc2 (lo) r timer input capture/output compare register 2 w 0x34 tc3 (hi) r tc3[15:0] timer input capture/output compare register 3 w 0x35 tc3 (lo) r timer input capture/output compare register 3 w 0x36 timtst r 0 0 0 0 0 0 tcbyp 0 timer test register w table 63. analog die registers - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset (71) name 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 49 0x37 reserved r 0 0 0 0 0 0 0 0 w 0x38 ltc_ctl (hi) r 0 0 0 0 0 0 0 0 life time counter control register w ltciem ltcem 0x39 ltc_ctl (lo) r ltcie 0 0 0 0 0 0 ltce life time counter control register w 0x3a ltc_sr r ltcof 0 0 0 0 0 0 0 life time counter status register w 1 will clr 0x3b reserved r 0 0 0 0 0 0 0 0 w 0x3c ltc_cnt1 life time counter register r ltc[31:16] w r w 0x3e ltc_cnt0 life time counter register r ltc[15:0] w r w 0x40 gpio_ctl gpio control register r 0 0 0 0 0 0 0 0 w dir2m dir1m dir0m pe3m pe2m pe1m pe0m r 0 dir2 dir1 dir0 pe3 pe2 pe1 pe0 w 0x42 gpio_puc r 0 0 0 0 pde3 pue2 pue1 pue0 gpio pull up/down configuration w 0x43 gpio_data r 0 0 0 0 pd3 pd2 pd1 pd0 gpio port data register w 0x44 gpio_in0 r 0 tcap3 tcap2 tcap1 tcap0 scirx lintx 0 port 0 input configuration w 0x45 gpio_out0 r wkup tcomp3 tcomp2 tcomp1 tcomp0 scitx linrx 0 port 0 output configuration w ptbx0 0x46 gpio_in1 r 0 tcap3 tcap2 tcap1 tcap0 scirx lintx 0 port 1 input configuration w 0x47 gpio_out1 r wkup tcomp3 tcomp2 tcomp1 tcomp0 scitx linrx 0 port 1 output configuration w ptbx1 0x48 gpio_in2 r 0 tcap3 tcap2 tcap1 tcap0 scirx lintx 0 port 2 input configuration w 0x49 gpio_out2 r wkup tcomp3 tcomp2 tcomp1 tcomp0 scitx linrx 0 port 2 output configuration w ptbx2 table 63. analog die registers - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset (71) name 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 50 0x4a gpio_in3 r ptwu ptwu tcap3 tcap2 tcap1 tcap0 0 0 port 3 input configuration w 0x4b reserved r 0 0 0 0 0 0 0 0 w 0x4c reserved r 0 0 0 0 0 0 0 0 w 0x4d reserved r 0 0 0 0 0 0 0 0 w 0x4e reserved r 0 0 0 0 0 0 0 0 w 0x4f reserved r 0 0 0 0 0 0 0 0 w 0x50 lin_ctl lin control register r 0 0 0 0 0 0 0 0 w otiem txdm lvsdm enm srsm[1:0] r otie 0 0 txd lvsd en srs[1:0] w 0x52 lin_sr (hi) r ot 0 hf 0 uv 0 0 0 lin status register w write 1 will clear the flags 0x53 lin_sr (lo) r rdy 0 0 0 0 0 rx tx lin status register w 0x54 lin_tx r 0 0 0 0 0 0 frompt b fromsc i lin transmit line definition w 0x55 lin_rx r 0 0 0 0 0 0 toptb tosci lin receive line definition w 0x56 reserved r 0 0 0 0 0 0 0 0 w 0x57 reserved r 0 0 0 0 0 0 0 0 w 0x58 acq_ctl acquisition control register r 0 0 0 0 0 0 0 0 w ahcrm optem openem cvmiem etmenm itmenm vmenm cmenm r 0 opte opene cvmie etmen itmen vmen cmen w ahcr 0x5a acq_sr (hi) r avrf pgag vmow cmow etm itm vm cm acquisition status register w write 1 will clear the flags 0x5b acq_sr (lo) r open 0 0 vth etchop itchop vchop cchop acquisition status register w 0x5c acq_acc1 acquisition chain control 1 r 0 0 0 0 0 0 0 0 w tcompm vcomp m ccomp m lpfenm etchop m itchop m cvchop m agenm r tcomp vcomp ccomp lpfen etchop itchop cvchop agen w table 63. analog die registers - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset (71) name 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 51 0x5e acq_acc0 acquisition chain control 0 r 0 0 0 0 0 0 0 0 w zerom ecapm tadcgm vadcgm cadcgm tdenm vdenm cdenm r zero ecap tadcg vadcg cadcg tden vden cden w 0x60 acq_dec r 0 0 0 0 0 dec[2:0] decimation rate w 0x61 acq_bgc r 0 0 bgadc[1:0] bgldo bg3en bg2en bg1en bandgap control w 0x62 acq_gain r 0 0 0 0 0 igain[2:0] pga gain w 0x63 acq_gcb r d[7:0] gcb threshold w 0x64 acq_itemp (hi) r itemp[15:8] internal temperature measurement w 0x65 acq_itemp (lo) r itemp[7:0] internal temperature measurement w 0x66 acq_etemp (hi) r eemp[15:8] external temperature measurement w 0x67 acq_etemp (lo) r eemp[7:0] external temperature measurement w 0x68 reserved r 0 0 0 0 0 0 0 0 w 0x69 acq_curr1 r curr[23:16] current measurement w 0x6a acq_curr0 current measurement r curr[15:8] w r curr[7:0] w 0x6c acq_volt voltage measurement r volt[15:8] w r volt[7:0] w 0x6e acq_lpfc r 0 0 0 0 lpfc[3:0] low pass filter coefficient number w 0x6f reserved r 0 0 0 0 0 0 0 0 w table 63. analog die registers - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset (71) name 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 52 0x70 acq_tcmp low power trigger current measurement period r tcmp[15:0] w r w 0x72 acq_thf r thf[7:0] low power current threshold filtering period w 0x73 reserved r 0 0 0 0 0 0 0 0 w 0x74 acq_cvcr (hi) r 0 0 0 0 0 0 0 0 i and v chopper control register w dbtm[1:0] iircm[2:0] pgafm 0x75 acq_cvcr (lo) r 0 0 dbt[1:0] iirc[2:0] pgaf i and v chopper control register w 0x76 acq_cth r cth[7:0] low power current threshold w 0x77 reserved r 0 0 0 0 0 0 0 0 w 0x78 acq_ahth1 (hi) r 0 low power ah counter threshold w ahth[30:16] 0x79 acq_ahth1 (lo) r low power ah counter threshold w 0x7a acq_ahth0 (hi) r ahth[15:0] low power ah counter threshold w 0x7b acq_ahth0 (lo) r low power ah counter threshold w 0x7c acq_ahc1 (hi) r ahc[31:24] low power ah counter w 0x7d acq_ahc1 (lo) r ahc[23:16] low power ah counter w 0x7e acq_ahc0 (hi) r ahc[15:8] low power ah counter w 0x7f acq_ahc0 (lo) r ahc[7:0] low power ah counter w 0x80 lpf_a0 (hi) r a0[15:0] a0 filter coefficient w 0x81 lpf_a0 (lo) r a0 filter coefficient w table 63. analog die registers - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset (71) name 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 53 0x82 lpf_a1 (hi) r a1[15:0] a1 filter coefficient w 0x83 lpf_a1 (lo) r a1 filter coefficient w 0x84 lpf_a2 (hi) r a2[15:0] a2 filter coefficient w 0x85 lpf_a2 (lo) r a2 filter coefficient w 0x86 lpf_a3 (hi) r a3[15:0] a3 filter coefficient w 0x87 lpf_a3 (lo) r a3 filter coefficient w 0x88 lpf_a4 (hi) r a4[15:0] a4 filter coefficient w 0x89 lpf_a4 (lo) r a4 filter coefficient w 0x8a lpf_a5 (hi) r a5[15:0] a5 filter coefficient w 0x8b lpf_a5 (lo) r a5 filter coefficient w 0x8c lpf_a6 (hi) r a6[15:0] a6 filter coefficient w 0x8d lpf_a6 (lo) r a6 filter coefficient w 0x8e lpf_a7 (hi) r a7[15:0] a7 filter coefficient w 0x8f lpf_a7 (lo) r a7 filter coefficient w 0x90 lpf_a8 (hi) r a8[15:0] a8 filter coefficient w 0x91 lpf_a8 (lo) r a8 filter coefficient w 0x92 lpf_a9 (hi) r a9[15:0] a9 filter coefficient w 0x93 lpf_a9 (lo) r a9 filter coefficient w 0x94 lpf_a10 (hi) r a10[15:0] a10 filter coefficient w 0x95 lpf_a10 (lo) r a10 filter coefficient w table 63. analog die registers - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset (71) name 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 54 0x96 lpf_a11 (hi) r a11[15:0] a11 filter coefficient w 0x97 lpf_a11 (lo) r a11 filter coefficient w 0x98 lpf_a12 (hi) r a12[15:0] a12 filter coefficient w 0x99 lpf_a12 (lo) r a12 filter coefficient w 0x9a lpf_a13 (hi) r a13[15:0] a13 filter coefficient w 0x9b lpf_a13 (lo) r a13 filter coefficient w 0x9c lpf_a14 (hi) r a14[15:0] a14 filter coefficient w 0x9d lpf_a14 (lo) r a14 filter coefficient w 0x9e lpf_a15 (hi) r a15[15:0] a15 filter coefficient w 0x9f lpf_a15 (lo) r a15 filter coefficient w 0xa0 comp_ctl compensation control register r 0 0 0 0 0 0 0 w bgcalm[1:0] pgazm pgaom diagvm diagim caliem r bgcal[1:0] pgaz pgao diagv diagi calie w 0xa2 comp_sr r 0 bgrf 0 pgaof 0 0 0 calf compensation status register w write 1 will clear the flags 0xa3 comp_tf r 0 0 0 0 0 tmf[2:0] temperature filtering period w 0xa4 comp_tmax max temp before recalibration r tcmax[15:0] w r w 0xa6 comp_tmin min temp before recalibration r tcmin[15:0] w r w 0xa8 reserved r 0 0 0 0 0 0 0 0 w 0xa9 reserved r 0 0 0 0 0 0 0 0 w 0xaa comp_vo r voc[7:0] offset voltage compensation w table 63. analog die registers - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset (71) name 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 55 0xab comp_io r coc[7:0] offset current compensation w 0xac comp_vsg gain voltage compensation vsense channel r 0 0 0 0 0 0 vsgc[9:8] w r vsgc[7:0] w 0xae reserved r 0 0 0 0 0 0 0 0 w 0xaf reserved r 0 0 0 0 0 0 0 0 w 0xb0 comp_ig4 gain current compensation 4 r 0 0 0 0 0 0 igc4[9:8] w r igc4[7:0] w 0xb2 comp_ig8 gain current compensation 8 r 0 0 0 0 0 0 igc8[9:8] w r igc8[7:0] w 0xb4 comp_ig16 gain current compensation 16 r 0 0 0 0 0 0 igc16[9:8] w r igc16[7:0] w 0xb6 comp_ig32 gain current compensation 32 r 0 0 0 0 0 0 igc32[9:8] w r igc32[7:0] w 0xb8 comp_ig64 gain current compensation 64 r 0 0 0 0 0 0 igc64[9:8] w r igc64[7:0] w 0xba comp_ig128 gain current compensation 128 r 0 0 0 0 0 0 igc128[9:8] w r igc128[7:0] w 0xbc comp_ig256 gain current compensation 256 r 0 0 0 0 0 0 igc256[9:8] w r igc256[7:0] w 0xbe comp_ig512 gain current compensation 512 r 0 0 0 0 0 0 igc512[9:8] w r igc512[7:0] w table 63. analog die registers - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset (71) name 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 56 0xc0 comp_pgao4 offset pga compensation 4 r 0 0 0 0 0 pgaoc4[10:8] w r pgaoc4[7:0] w 0xc2 comp_pgao8 offset pga compensation 8 r 0 0 0 0 0 pgaoc8[10:8] w r pgaoc8[7:0] w 0xc4 comp_pgao16 offset pga compensation 16 r 0 0 0 0 0 pgaoc16[10:8] w r pgaoc16[7:0] w 0xc6 comp_pgao32 offset pga compensation 32 r 0 0 0 0 0 pgaoc32[10:8] w r pgaoc32[7:0] w 0xc8 comp_pgao64 offset pga compensation 64 r 0 0 0 0 0 pgaoc64[10:8] w r pgaoc64[7:0] w 0xca comp_pgao128 offset pga compensation 128 r 0 0 0 0 0 pgaoc128[10:8] w r pgaoc128[7:0] w 0xcc comp_pgao256 offset pga compensation 256 r 0 0 0 0 0 pgaoc256[10:8] w r pgaoc256[7:0] w 0xce comp_pgao512 offset pga compensation 512 r 0 0 0 0 0 pgaoc512[10:8] w r pgaoc512[7:0] w 0xd0 comp_ito r itoc[7:0] internal temp. offset compensation w 0xd1 comp_itg r itgc[7:0] internal temp. gain compensation w 0xd2 comp_eto r etoc[7:0] external temp. offset compensation w table 63. analog die registers - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset (71) name 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 57 0xd3 comp_etg r etgc[7:0] external temp. gain compensation w 0xd4 reserved r 0 0 0 0 0 0 0 0 w 0xd5 reserved r 0 0 0 0 0 0 0 0 w 0xd6 reserved r 0 0 0 0 0 0 0 0 w 0xd7 reserved r 0 0 0 0 0 0 0 0 w 0xd8 reserved r 0 0 0 0 0 0 0 0 w 0xd9 reserved r 0 0 0 0 0 0 0 0 w 0xda reserved r 0 0 0 0 0 0 0 0 w 0xdb reserved r 0 0 0 0 0 0 0 0 w 0xdc reserved r 0 0 0 0 0 0 0 0 w 0xdd reserved r 0 0 0 0 0 0 0 0 w 0xde reserved r 0 0 0 0 0 0 0 0 w 0xdf reserved r 0 0 0 0 0 0 0 0 w 0xe0 trim_bg0 (hi) r 0 0 tcibg2[2:0] tcibg1[2:0] trim bandgap 0 w 0xe1 trim_bg0 (lo) r 0 0 ibg2[2:0] ibg1[2:0] trim bandgap 0 w 0xe2 trim_bg1 (hi) r ubg3 dbg3 tcbg2[2:0] tcbg1[2:0] trim bandgap 1 w 0xe3 trim_bg1 (lo) r 0 0 0 0 0 slpbg[2:0] trim bandgap 1 w 0xe4 trim_bg2 (hi) r v1p2bg2[3:0] v1p2bg1[3:0] trim bandgap 2 w 0xe5 trim_bg2 (lo) r v2p5bg2[3:0] v2p5bg1[3:0] trim bandgap 2 w 0xe6 trim_lin r 0 0 0 0 0 0 0 lin trim lin w table 63. analog die registers - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset (71) name 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 58 0xe7 trim_lvt r 0 0 0 0 0 0 0 lvt trim low voltage threshold w 0xe8 trim_osc (hi) r trim lp oscillator w lposc[12:0] 0xe9 trim_osc (lo) r trim lp oscillator w 0xea reserved r 0 0 0 0 0 0 0 0 w 0xeb reserved r 0 0 0 0 0 0 0 0 w 0xec reserved r 0 0 0 0 0 0 0 0 w 0xed reserved r 0 0 0 0 0 0 0 0 w 0xee reserved r 0 0 0 0 0 0 0 0 w 0xef reserved r 0 0 0 0 0 0 0 0 w 0xf0 reserved r 0 0 0 0 0 0 0 0 w 0xf1 reserved r 0 0 0 0 0 0 0 0 w 0xf2 reserved r 0 0 0 0 0 0 0 0 w 0xf3 reserved r 0 0 0 0 0 0 0 0 w 0xf4 reserved r 0 0 0 0 0 0 0 0 w 0xf5 reserved r 0 0 0 0 0 0 0 0 w 0xf6 reserved r 0 0 0 0 0 0 0 0 w 0xf7 reserved r 0 0 0 0 0 0 0 0 w 0xf8 reserved r 0 0 0 0 0 0 0 0 w 0xf9 reserved r 0 0 0 0 0 0 0 0 w 0xfa reserved r 0 0 0 0 0 0 0 0 w 0xfb reserved r 0 0 0 0 0 0 0 0 w table 63. analog die registers - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset (71) name 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0
functional description and application information mm912_637, rev. 3.0 freescale semiconductor 59 0xfc reserved r 0 0 0 0 0 0 0 0 w 0xfd reserved r 0 0 0 0 0 0 0 0 w 0xfe reserved r 0 0 0 0 0 0 0 0 w 0xff reserved r 0 0 0 0 0 0 0 0 w notes 71.register offset with the ?lo? address value not shown have to be accessed in 16- bit mode. 8-bit access will not function. table 63. analog die registers - 0x0200?0x02ff d2d blocking access (d2di) 2 of 3/ 0x0300?0x03ff d2d non blocking access (d2di) 3 of 3 offset (71) name 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0
mm912_637 - analog die overview mm912_637, rev. 3.0 freescale semiconductor 60 5.1 mm912_637 - analog die overview 5.1.1 introduction the mm912_637 anal og die implements all system base functionality to operate the integr ated microcontrolle r, and delivers application specific input capturing. figure 14. analog die block overview the following chapters describe the analog die functionality on a module by module basis. 5.1.2 analog die options note this document describes the features and functions of analog option 2 (all modules available and tested). beyond this chapter, there wi ll be no additional note or differentiation between the different implementations. the following section describes the differ ences between analog die options 1 and 2. watchdog mmc d2d interface interrupt control test interface internal bus gpio bias regulator(s) lin sci oscillator timer wake up / power down fuse box gain and offset compensation prog. low pass filter decv decc gain and offset compensation battery voltage measurement battery current measurement temperature measurement analog digital mcu die ptb0 ptb1 ptb2 ptb3 vddx vddh dgnd vddl vsup gnda lin lgnd vdda vfuse gndsub adcgnd tsup vtemp isenseh isensel vopt vsense test_a tclk reset_a d2ddat0..7 d2dclk d2dint analog mcu
mm912_637, rev. 3.0 freescale semiconductor 61 5.1.2.1 cranking mode for devices with analog option 1 (cranking mode not char acterized), the following considerations are to be made: 5.1.2.1.1 data sheet considerations in analog option 1 devices, operation in cranking mode is ne ither characterized not tested. all data sheet parameters and descriptions relating to cranking mode operation apply to analog option 2 devices only. 5.1.2.2 external wake-up (ptb3/l0) for devices with analog option 1 (ext ernal wake-up not available), the follo wing considerations are to be made: 5.1.2.2.1 register considerations for analog option 1 devices, wuptb3 must be se t to 0 (wake-up on a gpio 3 event disabled). 5.1.2.3 external temperature sensor option (vtemp) for devices with analog option 1 (external temperature sensor option not available) , the following considerations are to be made: 5.1.2.3.1 pinout considerations table 64. analog opti ons (continued) feature analog option 1 analog option 2 cranking mode not characterized or tested fully characterized and tested external wake-up (ptb3/l0) no ye s external temperature sensor option (vtemp) no ye s optional 2nd external voltage sense input (vopt) no ye s table 65. wake-up enable register (pcr_wue (hi)) offset (72) 0x06 access: user read/write 7 6 5 4 3 2 1 0 r wuahth wucth wucal wulin wuptb3 wuptb2 wuptb1 wuptb0 w reset 0 0 0 0 0 0 0 0 notes 72.offset related to 0x0200 for bloc king access and 0x300 for non-blocking acce ss within the global address space. pin pin name for option 2 pin name for option 1 comment 28 vtemp nc nc pin should be connected to gnd 29 tsup nc pin should be left unconnected
mm912_637, rev. 3.0 freescale semiconductor 62 5.1.2.3.2 register considerations for analog option 1 devices, etmen must be set to 0 (external temperature measurement disabled). 5.1.2.4 optional 2nd external voltage sense input (vopt) for devices with analog option 1 (optional 2nd external voltage sense input not available), the following considerations are to be made: 5.1.2.4.1 pinout considerations 5.1.2.4.2 register considerations for analog option 1 devices, opte must be set to 0 (vsense routed to adc). table 66. acquisition control register (acq_ctl) offset (73) , (74) 0x58 access: user read/write 15 14 13 12 11 10 9 8 r 0 0 0 0 0 0 0 0 w ahcrm optem openem cvmiem etmenm itmenm vmenm cmenm reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r 0 opte opene cvmie etmen itmen vmen cmen w ahcr reset 0 0 0 0 0 0 0 0 notes 73.offset related to 0x0200 for bloc king access and 0x300 for non-blocking acce ss within the global address space. 74.this register is 16-bit access only. pin pin name for option 2 pin name for option 1 comment 28 vopt nc nc pin should be connected to gnd table 67. acquisition control register (acq_ctl) offset (75) , (76) 0x58 access: user read/write 15 14 13 12 11 10 9 8 r 0 0 0 0 0 0 0 0 w ahcrm optem openem cvmiem etmenm itmenm vmenm cmenm reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r 0 opte opene cvmie etmen itmen vmen cmen w ahcr reset 0 0 0 0 0 0 0 0 notes 75.offset related to 0x0200 for bloc king access and 0x300 for non-blocking acce ss within the global address space. 76.this register is 16-bit access only.
analog die - power, clock and resets - pcr mm912_637, rev. 3.0 freescale semiconductor 63 5.2 analog die - power, clock and resets - pcr 5.2.1 introduction the following chapter describes the mm912_637?s system base functi onality primary location on the analog die. the chapter is divided in the following sections: 1. 5.2.2, ?device operating modes" 2. 5.2.3, ?power management" 3. 5.2.4, ?wake-up sources" 4. 5.2.5, ?device clock tree" 5. 5.2.6, ?system resets" 6. 5.2.7, ?pcr - memory map and registers" 5.2.2 device operating modes the mm912_637 features three main operation modes: normal operation, stop mode, and sleep mode. the full signal conditioning and measurements are permanently running in normal operat ion mode. the total current consumption of the mm912_637 is reduced in the two low power modes. the analog die of the mm912_637 is still partially active and able to monitor the battery current, temperature, activities on t he lin interface and l0 terminal, during both low power modes. 5.2.2.1 operating mode overview ? normal mode ? all device modules active ? microcontroller fully supplied ? d2dclk active analog die clock source ? window watchdog clocked by the low power osci llator (lpclk) to operate on independent clock ? stop mode ? mcu in low power mode, mcu regulator supply (vddx) with reduced current capability ? d2d interface supply disabled (vddh=off) ? unused analog blocks disabled ? watchdogs = off ? lin wake-up, calibration request wa ke-up, cyclic wake-up, external wake -up, current threshold wake-up, and lifetime counter wake-up optional ? current measurement / current averaging and temperature measurement optional ?sleep mode ? mcu powered down (vddh and vddx = off) ? unused analog blocks disabled ? watchdogs = off ? lin wake-up, calibration request wa ke-up, cyclic wake-up, external wake -up, current threshold wake-up, and lifetime counter wake-up optional ? current measurement / current averaging and temperature measurement optional ? intermediate mode ? every transition from stop or sleep into normal mode will go through an intermediate mode where the analog die clock is not yet switched to the d2d clock. if required , the mm912_637 analog die can be put back to low power mode without changing the frequency domain. ? reset mode ? every reset source within the analog die will bring the system into a reset state analog mcu
analog die - power, clock and resets - pcr mm912_637, rev. 3.0 freescale semiconductor 64 ? power on reset mode ? for both low voltage thresholds are defined to indicate a loss of internal state. ? cranking mode (77) ? special mode implemented to guarantee the ram cont ent being valid though very low power conditions. notes 77.not available on all device derivatives 5.2.2.2 operating mode transitions the device operating modes are controlled by the microcontroller, as well as external and internal wake-up sources. figure 15 shows the basic principal. figure 15. modes of operation - transitions 5.2.2.3 power on reset - por during system startup, or in any other case when mcu_vdd drops bel ow vpora (mcu), or vddl drops below vporl (analog die), a power on reset (por) condition is reached. the mcu (por f) / analog die (lvrf) will indicate this state, setting the corresponding power on reset flag. the primary consequence of en tering por is that the ram or a nalog register content can no longer be guaranteed. normal mode sleep mode stop mode wake-up event mcu irq mcu wake-up event (mcu power on) mcu reset reset event reset event por analog: vddl < v porl mcu: vddrx v porh mcu: vddrx>v pord intermediate mode mcu intermediate mode mcu cranking mode 1 1 ) cranking mode not available on all device derivatives cranking event cranking event gone analog: vddl < v porl mcu: vddrx analog die - power, clock and resets - pcr mm912_637, rev. 3.0 freescale semiconductor 65 5.2.2.4 reset - mode if any of the analog die reset conditions are present, the mm912_637 analog die will enter reset mode. during that mode, the analog die will issue the reset_a pin to be pulled down to reset the microcontro ller die. entering reset mode will reset the analog die registers to their default values. the cause of the last reset is flagged in the pcr status register (pcr_sr (hi)) . 5.2.2.5 normal mode during normal mode operation, all modules are op erating and the microcontroller is fully supplied. 5.2.2.6 cranking mode (78) a specific power down behavior has been implemented to allow the mcu memory (ram ) content to be guaranteed during very low supply voltage conditions. the difference between the devi ce behavior, with or without t he cranking mode feature enabled, is described in section 5.2.3.3, ?power up / power down behavior" . notes 78.not available on all device derivatives 5.2.2.7 intermediate mode as the channel acquisition and the timer modules are switched to the lpckl, while the mm912_637 is operating in one of the two low power modes, the intermediate mode has been implemente d, to be able to go back to low power mode without the transition into the d2d clock domain. note the flag indicating the last wake-up source must be cleared before re-entering low power mode! once awakened, the mcu instructs the analog die to transit to no rmal mode by writing ?00? to the opm bits in the pcr control register. see figure 16 for details.
analog die - power, clock and resets - pcr mm912_637, rev. 3.0 freescale semiconductor 66 figure 16. low power mode to normal mode tran sition through the intermediate mode 5.2.2.8 low power modes in low power mode, the mm912_637 is still active to monitor th e battery current (triggered current measurement for current threshold detection and current accumulator function), and activities on the lin interface and wake-up inputs. a cyclic wake-up using timer module is implemented for ti med wake-up. temperature m easurements are optional to detect an out of calibration condition. the life time counter is also incremented during low power mode, to issue a wake-up on overflow. see section 5.13, ?life time counter (ltc)" for additional details. the average current consumption is reduce d, and based on the actual low power m ode, the active modules, and the wake-up timing. note to avoid any lock condition, no analog die interrupt should be enabled or pending when entering lpm. to accomplish that condition, the analog die interrupts should be masked and served before writing the pcr_ctl register. the mcu interrupts should be enabled right before the stop command, to avoid any interrupt to be handled in between. a wake-up from any of the low power modes will reset the window watchdog equal to a standard reset. 5.2.2.8.1 sleep mode writing the pcr control register (pcr_ctl) with opm=10, the mm912_637 will enter sleep mode with the configured wake-up sources (see section 5.2.4, ?wake-up sources" ). note the power supply to the mcu will be turned off during sleep mode. to safely approach this condition, the mcu should be put into a safe state (e.g stop). stop mode vddh = off vddx = limited tim / aq = lpclk mcu = stop sleep mode vddh & vddx = off tim / aq = lpclk mcu = off wake-up event wake-up event intermediate mode 1. vddh = on 2. vddx = full 3. mcu => irq intermediate mode 1. vddh & vddx = on 2. mcu => power on mcu can access d2d tim / aq are still on lpclk domain (e.g. check wake-up source) normal mode tim / aq = based on d2d clock write opm[1:0] bits in the pcr control register ?01? ?10? ?00?
analog die - power, clock and resets - pcr mm912_637, rev. 3.0 freescale semiconductor 67 during sleep mode, the only active voltage regulator is vddl, supplying the low power oscillator (lposc), and the permanently supplied digital blocks. when an enabled wake-up condition occurs, the shutdown voltag e regulators are re-enabled, and once their outputs are above reset threshold, the reset_a signal is released, and the microcontroller will start its normal operation. the wake-up source is flagged in the pcr status register (pcr_sr (hi)). the microcontroller has to acknowledge th e normal mode, by writing t he opm=00, to allow a contro lled transition into the d2d clock domain. if the clock domain transition is not required, the microcontroller may issue a sleep / stop mode entry instead ( see section 5.2.5, ?device clock tree" for details on the limitations during the intermediate state). 5.2.2.8.2 stop mode writing the pcr control register (pcr_ctl) with opm=01, t he mm912_637 analog die will enter stop mode with the configured wake-up sources (see section 5.2.4, ?wake-up sources" ), after the d2dclk signal has b een stopped by the mcu die entering stop. note after writing the pcr control register (pcr_ctl ) with opm=01, the regi ster content of the sci (s08sciv4) and timer (tim16b4c) module registers are only read until normal mode is entered again. this is important in case the mcu does not effectively enter stop, due to an irq pending from one of the two blocks. (having any analog die irq allowed when entering low power mode is not recommended). during stop mode, the mm912_637 has the same behavior as during sleep mode, except vddx is still powered by the internal clamp_5v, to supply the mcu stop mode current. as this current is limited, the mcu die must be switched into stop mode after sending the stop command for the analog die. if any enabled wake up condition occurs, the shutdown voltage re gulators are re-enabled, and once their outputs are above the reset threshold, vddx is switched to the main regulator, an d2 d interrupt (d2dint) is issued to wake-up the mcu, and the microcontroller will continue its normal operation. the wake-up s ource is flagged in the pcr status register (pcr_sr (hi)). the microcontroller has to acknowledge the normal mode by writing the opm=00. this allows a controlled transition into the d2d clock domain. if the clock domain transition is not required, the microcontroller may issue a sleep / stop mode entry instead ( see section 5.2.5, ?device clock tree" for details on the limitations during the intermediate state). note after writing the pcr control register (pcr_ ctl) with opm=01, writ ing opm=00 (normal mode) is allowed to wake-up the analog die. the reduced current capability of the mcu regulator supply (vddx) has to be considered.
analog die - power, clock and resets - pcr mm912_637, rev. 3.0 freescale semiconductor 68 5.2.3 power management to support the various operating modes and modules in the mm 912_637, the following power management architecture has been implemented. figure 17. system voltage monitoring 5.2.3.1 detailed power block description see recommended external components under section 3.2, ?recommended external components" ?. 5.2.3.1.1 vsup vsup is the system power supply input, and mu st be reverse battery prot ected by an external diode. vsup is monitored for under-voltage conditions (uvi). once vsup drops below v uvil an under-voltage interrupt (lvi) is issued. note if the device has the cranking mode feature enabl ed, the under-voltage threshold would be v uvcil instead of v uvil . 5.2.3.1.2 vddl vddl is the low power 2.5 v digital supply voltage, supplying the permanently active blocks. it is based on the internal clamp5v voltage and always on. it is available exter nally, but must not be connected to any load. 5.2.3.1.3 vddx vddx is the normal mode 5.0 v regulator output, suppling the lin block and the microcontroller via the vddx pin. during stop and sleep mode operation, t he vddx regulator is shut down (clamp5v does supply the m cu during stop mode). 5.2.3.1.4 vddh vddh is the normal mode 2.5 v regulator output, suppling only active blocks during normal mode and the mcu die to die interface, via the vddh terminal. the vddh regulat or is shut down during both low power modes. 5.2.3.1.5 vdda vdda is the 2.5 v analog supply voltage, active during normal mode and i/t acquisitions. no external load must be connected to the vdda terminal. analog die vddx mcu vddrx vddd2d vddh vddl vdda clamp5v vddl vddx vddh vdda vsup lvi v lvia / v lvid lvr v lvra / v lvrd por v pora / v pord lvrx v lvrxh / v lvrxl por v porh / v porl lvrh v lvrhh / v lvrhl lvra v lvrah / v lvral flash core vddf vdd d2d uvi v uvih / v uvil
analog die - power, clock and resets - pcr mm912_637, rev. 3.0 freescale semiconductor 69 5.2.3.2 power supply by module the following table summarized the active regulators vs. module for the different operating modes. 5.2.3.3 power up / power down behavior several system voltage monitors have been implemented in bot h die, to guarantee a defined power up and power down system behavior. see figure 17 for the various sensing points. the individual threshold levels are specified in ta b l e 16 for the analog die, and ta b l e 25 for the microcontroller. note to differentiate between the mcu and analog di e thresholds, the following symbol scheme is defined: v xxxxa - mcu assert level (lower threshold for low voltage events) ? v xxxxd - mcu deassert level (higher threshold for low voltage events) ? v xxxxh - analog die high threshold level (deassert threshold for low voltage events) ? v xxxxl - analog die low threshold level (assert threshold for low voltage events) 5.2.3.4 low voltage operation - cranking mode device option based on the device option (?cranking? or ?non-cranking ?), the mm912_637 will behave different during ?loss of power? conditions. the ?cranking? option is an op tion, allowing lower voltage operations to guarantee the mcu memory content during a standard cranking situation. as illustrated in figure 18 , the cranking mode is introduced to maintain both die in a stop mode alike state. the mcu die will remain in stop with the ram content bei ng guaranteed until the pora level is reached for the vddrx supply. the analog die will enter ?cranking mode? upon the mcu command out of normal mode, or when it reaches v uvcil during stop mode, with the lvt bit set in the trim_lvt register. note executing stop with vsup < v uvcil and lvt = 1, the mm912_637 will immediately enter cranking mode. during cranking mode, the analog die will gate its internal osci llator to stop all ongoing acqu isitions during the low power condition. returning from cranking mode will appear as a wake-up from under-voltage interrupt (uvi=1). the analog die will be in intermediate mode after wake-up, and could be sent into normal mode (stop, sleep), by writing the opm bits. table 68. power supply by module module / block vddh vdda vddl vddx gain control block (gcb) (79) x x programmable gain amplifier (pga) (80) x i/t - adc converters (80) x v - adc converters (79) x temperature sensor (80) x lin (79) x x d2d (79) x lposc (81) x permanent digital (81) x normal mode digital (79) x notes 79.enabled in normal mode only 80.enabled when a measuring in low power mode and always in normal mode 81.permanently enabled
analog die - power, clock and resets - pcr mm912_637, rev. 3.0 freescale semiconductor 70 figure 18. power down sequence cranking mode (mcu = stop or off, analog = cranking mode lposc gated => operation stopped) vsup decrease normal / intermediate mode stop / sleep mode device with cranking mode enabled device with cranking mode disabled normal / intermediate mode stop / sleep mode v uvil high precision comparator => on high precision comparator always on in normal / intermediate mode v uvcil cranking mode entry without mcu interaction. mcu will stay in stop mode or turned off. under voltage irq (uvi) issued. mcu initiates rapid shutdown to cranking mode (opm=11) and enters stop. v lvra v porl v pora v lvia v porcl v lvrhl v lvral v lvrxl inactive during stop / sleep handle irq, prepare for cranking mode inactive during cranking mode inactive during cranking mode inactive during cranking mode inactive for cranking mode device option mcu por , ram invalid, analog die remains in cranking mode analog die power on reset under voltage irq (uvi) issued. inactive during stop / sleep handle irq, prepare for cranking mode inactive during stop / sleep inactive for non cranking mode device option inactive for non cranking mode device option low voltage reset at vddx => analog die + mcu in reset mode mcu in lvr, analog die remains in low power mode inactive during stop / sleep system remains in reset mode mcu por , ram invalid, both dice remain in reset mode analog die power on reset inactive for non - cranking mode device option
analog die - power, clock and resets - pcr mm912_637, rev. 3.0 freescale semiconductor 71 5.2.4 wake-up sources several wake-up sources have been implemented in the mm912_637, to exit from sleep or stop mode. figure 19 shows the wake-up sources and the corresponding configuration and status bits. to indicate the internal wake-up signal, a routing of the internal wake-up signal to the ptbx output (wkip) is implemented. see section 5.10, ?general purpose i/o - gpio" , for additional details on the required configuration. figure 19. wake-up sources 5.2.4.1 wake-up source details 5.2.4.1.1 cyclic current acquisition / calibration temperature check a configurable (acq_tcmp) independent low power mode counte r/trigger, based on the alfclk, has been implemented to trigger a cyclic current measurement during the low power modes. to validate that the temperature is still within the calibrati on range, the temperature meas urement can be enabled during this event as well. as a result of the cyclic conversions, three wake-up conditions are implemented. ? current threshold wake-up ? current averaging wake-up ? calibration request wake-up the configuration of the counter and the cyclic measur ements is part of the acquisition paragraph (see section 5.7, ?channel acquisition" ). the actual cyclic measurement does not wake-up the microcontroller unless one of the three wake-up conditions become valid. tim4ch output compare ch0 output compare ch1 output compare ch2 output compare ch3 gpio tcomp3..0 ptb0 i/o ptb1 i/o ptb2 i/o ptb3 i/o wuptb0 wuptb1 wuptb2 wuptb3 wuptb3f wuptb2f wuptb1f wuptb0f lin wulin current trigger current accumulator threshold reached current threshold reached lin wake up detected calibration request wuahth wucth wucal life time counter life time counter overflow wultc ptwu =1 l0 wulinf wuahthf wucthf wucalf wultcf tcomp3..0 tcomp3..0 sytem wake up wkup wlpmf
analog die - power, clock and resets - pcr mm912_637, rev. 3.0 freescale semiconductor 72 5.2.4.1.1.1 current threshold wake-up every cyclic current measurement re sult (absolute content of the adc result i_curr register) is compared with a programmable unsigned current threshold (cth in the acq_cth register). the comparison is done with the cth conten t left - shifted by 1, as shown in figure 69 . if the absolute result is greater or equal to the programmed and shifted threshold, a filter counter is in cremented (decremente d if below). if the filter counter (8-bit) reaches the programm able low power current threshold filtering period (acq_thf), a wake-up initiated if the current threshold wake-up is enabled (w ucth). the filter counter is reset every time a low power mode is entered. the implementation is shown in figure 20 . the wake-up source is flagged with the wucthf bit. figure 20. current threshold - wake-up counter 5.2.4.1.1.2 current ampere hour threshold wake-up as shown in figure 21 , every cyclic current measurement (signed content of the adc resu lt acq_curr register) is added to the 32-bit (signed) current accumulator (acq_ahc) (both in two? s complement format). if the absolute accumulator value reaches (|acq_ahc| ? acq_ahth), the absolute programmable 31-bit curr ent threshold (acq_ahth), a wake-up is initiated if the current ah threshold wake-up is enabled (wuahth). the accumulator is reset on every low power mode entry. the wake-up source is flagged with the wuahthf bit. table 69. current threshold comparison 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 cth[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cth[7:0] 0 abs(curr[23:0]) x abs(curr[23:0])
analog die - power, clock and resets - pcr mm912_637, rev. 3.0 freescale semiconductor 73 figure 21. ah counter function 5.2.4.1.1.3 calibration request wake-up once the temperature measured during the cyclic sense is indicating a po tential ?out of calibration? situation, a wake-up is is sued if the calibration request wake-up is enabled (wucal). for additional details, refer to section 5.7.5, ?calibration" . the wake-up source is flagged with the wucalf bit. 5.2.4.1.2 timed wake-up to generate a programmable wake-up timer, the integrated 4 channel timer module is supplied, during both low power modes and running on the alfclk clock. to wake-up from one of the lo w power modes, the output compar e signal (oc) of any of the 4 channels can be routed to the ptb[2:0] logic (standard feature also in normal mode). enabling the corresponding wake-up enable bit (wuptbx) will generate the wake up , once the timer output compare becomes active. note only the internal gpio logic is active during the low power modes. the port i/o structures will not be active. to allow an accurate wake-up configuration during the clock trans ition, the timer should be configured before entering one of t he low power modes, without the timer enable bit (ten) being set. setting the timer wake-up enable bit (wuptb) will enable the timer interrupts as wake-up sources, and cause the timer enable bit (ten) to be set, once the timer clock domain was changed to the lposc clock. during low-power mode, only current and temperature measurements are performed, so only the current measurement channel is active with the temperature channel being optional - the volt age measurement channel is inactive. to reduce further the powe r consumption, only triggered current measurements are done. for this purpose, an independent timer module is used to periodically start a current measurement after a programmable time (acq_tcmp). 5.2.4.1.3 wake-up from lin during low power mode, operation of the transmitter of the physi cal layer is disabled. the receiver remain, active and able to detect wake-up events on the lin bus line. for further details, refer to section 5.11, ?lin" . a dominant level longer than t wupf followed by a rising edge, will generate a wake-up event if the wulin is enabled. the wake-up source is flagged with the wulinf bit. t ah counter accu threshold (progr.) uc wake-up start low-power mode = reset of ah counter measurement interval actual measured current
analog die - power, clock and resets - pcr mm912_637, rev. 3.0 freescale semiconductor 74 note if the lin module is disabled (lin_ctl:en=0), no wake-up will be issued after the dominant to recessive transition, when the device goes to low power mode, while the lin bus is in the dominant state. if the lin module is enabled (lin_ctl:en=1), the device will wake-up after the dominant to recessive transition, when the device goes to low power mode, while the lin bus is in the dominant state. a full dominant -> recessive -> dominant sequence, during low power mode, will wake-up the device in both cases. 5.2.4.1.4 wake-up on w ake-up pin high level once a wake-up signal (high level) is detected on the ptb3/l0 inpu t, with the wake-up enable bit (wuptb3) and the port configuration bit (ptwu) set, a wake-up is issued. t he wake-up source is flagged with the wuptb3f bit. 5.2.4.1.5 wake-up on life time counter overflow the life time counter continues to run during low power mode, if configured. once the counter ov erflows with the life time coun ter wake-up enabled (wultc=1), a wake-up is issued. the wake-up source is flagged with the wultc bit. 5.2.4.1.6 general wake-up indicator to indicate the system has been awakened after power up, the wlpmf flag will be set. 5.2.5 device clock tree 5.2.5.1 clock scheme overview there are two system oscillators implemented . the low power oscillator is located on t he analog die, and is supplied permanentl y and has a nominal frequency of f oscl , providing a lpclk clock signal. it is primarily used in low power mode, and as an independent clock source for the watchdog during normal mode. the high power oscillator is basically the internal or external microcontroller oscillator (act ive only during normal mode). th e high power oscillator is distributed to the analog die via the d2dclk (via configurable mcu prescale rs), and there it?s divided into two clocks (d2dsclk and d2dfclk), based on t he presc[15:0] prescaler. for the d2dscl k, an additi onal 2 bit divider pf[1:0] is implemented (82) . during normal mode, d2dsclk is continuously synchronizing the lpclk, to create the accurate alfclk (see section 5.2.5.2, ?alfclk calibration" ), it?s clock source of the tim16b4c (tim er), and s08sciv4 (sci) module with a fixed by 4 divider. notes 82.pf[1:0] is not implemented as a simple divider. to accomplish a d2dsclk period ranging from 1.0 ms to 8.0 ms, the following scheme is used: 00 - 1; 01 - 2; 10 - 4; 11 - 8. d2dsclk - d2d slow clock (1... 0.125 khz) eqn. 1 d2dfclk - d2d fast clock (512 khz) eqn. 2 during low power mode, d2dclk is not available. the low power oscillator is the only system clock. d 2 dsclk d 2 dclk 2 pf 10 ? ?? ?? presc 15 0 ? ?? ?? ? ----------------------------------------------------------------------------- = ?? ?? d 2 dfclk d 2 dclk 2 presc 15 10 ? ?? presc 9 ?? + ?? ? ---------------------------------------------------------------------------------------------- - = ?? ??
analog die - power, clock and resets - pcr mm912_637, rev. 3.0 freescale semiconductor 75 figure 22 and figure 23 show the different clock sources for normal and low power mode. note d2dfclk has to be set to match 512 khz, resulting in d2dsclk being 1.0, 2.0, 4.0, or 8.0 khz, based on pf[1:0] the minimum value for presc[15:0] has to be 0x0400. any value lower than 0x0400 will result in faulty behavior and is not recommend ed. values of 0x0003 or less are not stored by the internal logic. figure 22. clock tree overview - normal mode figure 23. clock tree overview - low power modes 5.2.5.2 alfclk calibration to increase the accuracy of the 1.0 khz (or 2.0, 4.0, 8.0 7khz based on pf[1:0]) system clock (alfclk), the low power oscillator (lpclk) is synchronized to the more precise d2dclk, via the d2dsclk signal. the ?calibrated low power clock? (alfclk) could be trimmed to the d2dclk accuracy plus a maximum error add er of 1 lpclk period, by inte rnally counting the number of periods of the lpclk (512 khz) during a d2dsclk period. the apresc[12:0] re gister will represent the calculated internal prescaler. the prdf bit (prescaler ready flag) will indicate the synchronization complete after a power up or prescaler (presc/pf) change. the adjustment is cont inuously performed during normal mo de. during low power mode (stop or sleep), the last adjustment factor would be used. d2d interface presc[15:0] [9:0] [15:10] pf[1:0] d2dfclk lposc (foscl) lpclk trim_lposc lp clk synch d2dsclk window watchdog wdto[2:0] wdto[2:0]=100 t wdto t iwdto tim16b4c (timer) s08sciv4 (sci) channel acquisition life time counter alfclk d2dclk div4 lposc lpclk trim_lposc lp clk synch channel acquisition life time counter alfclk tim16b4c (timer) current trigger
analog die - power, clock and resets - pcr mm912_637, rev. 3.0 freescale semiconductor 76 figure 24. alf clock calibration procedure during normal mode figure 25. alfclk after calibration 5.2.5.3 recommended clock settings considering the system is runnin g on the internal oscillator, ta b l e 70 shows the recommended clock settings to achieve the optimal 512 khz d2dfclk. for details on the mcu divider settings, including postdiv and syndiv, see section 5.22, ?s12 clock, reset, and power management unit (s12cpmu)" . the d2d initiator module includes d2dclkdiv see section 5.25, ?mcu - die-to-die in itiator (d2div1)" . table 70. recommended clock settings f d2d / mhz postdiv for (syndiv=fvco in mhz) divider for (83) d2dfclk=512khz presc[15:9] (dec) (83) d2dclkdiv=1 (f bus) d2dclkdiv=2 d2dclkdiv=3 d2dclkdiv=4 31=65.536 30=63.488 29=61.440 28=59.392 27=57.344 26=55.296 25=53.248 24=51.200 23=49.152 22=47.104 21=45.056 20=43.008 19=40.960 18=38.912 17=36.864 16=34.816 15=32.768 32.768 16.384 8.192 0 64 63;64 31.744 0 62 61;62 30.720 15.360 10.240 0 60 59;60 29.696 0 58 57;58 28.672 14.336 7.168 0 56 55;56 d2dclk presc[15:0]+pf[1:0] counter based ms clock (d2dsclk) period lpclk 12345 6789 apresc[12:0] prdf 0x0200 (512d) default 0x0009 (9d) 01 synch start synch finished lpclk 1 prdf 0x0009 (9d) 01 ? apresc[12:0] alfclk 234567891 234567891 2345
analog die - power, clock and resets - pcr mm912_637, rev. 3.0 freescale semiconductor 77 5.2.6 system resets to guarantee safe operation, several reset sources have been implemented in the mm912_637 device. both the mcu and the analog die are designed to initiate reset events on internal sour ces and the mcu is capable of being reset by external events including the analog die reset output. the analog die is capabl e of being reset by the mcu in stop and cranking mode only. 5.2.6.1 device reset overview the mm912_637 reset concept includes two external reset signals, r eset (mcu) and reset_a (analog die). figure 26 illustrates the general configuration. 27.648 9.216 0 54 53;54 26.624 13.312 0 52 51;52 25.600 0 50 49;50 24.576 12.288 8.192 6.144 0 48 47;48 23.552 0 46 45;46 22.528 11.264 0 44 43;44 21.504 7.168 0 42 41;42 20.480 10.240 5.120 0 40 39;40 19.456 0 48 47;48 18.432 9.216 6.144 0 36 35;36 17.408 0 34 33;34 16.384 8.192 4.096 1 0 32 31;32 15.360 5.120 1 30 29;30 14.336 7.168 1 28 27;28 13.312 1 26 25;26 12.288 6.144 4.096 3.072 1 24 23;24 11.264 1 22 21;22 10.240 5.120 2 1 20 19;20 9.216 3.072 2 1 18 17;18 8.192 4.096 2.048 3 2 1 16 15;16 7.168 3 2 14 13;14 6.144 3.072 2.048 4 3 2 12 11;12 5.120 5 4 3 10 9;10 4.096 2.048 7 6 5 4 3 8 7;8 3.072 9 8 7 6 5 6 5;6 2.048 15 14 13 12 11 10 9 8 7 4 4 notes 83.for d2dclkdiv=1 table 70. recommended clock settings f d2d / mhz postdiv for (syndiv=fvco in mhz) divider for (83) d2dfclk=512khz presc[15:9] (dec) (83) d2dclkdiv=1 (f bus) d2dclkdiv=2 d2dclkdiv=3 d2dclkdiv=4 31=65.536 30=63.488 29=61.440 28=59.392 27=57.344 26=55.296 25=53.248 24=51.200 23=49.152 22=47.104 21=45.056 20=43.008 19=40.960 18=38.912 17=36.864 16=34.816 15=32.768
analog die - power, clock and resets - pcr mm912_637, rev. 3.0 freescale semiconductor 78 figure 26. device reset overview both r eset and reset_a signals are low active i/os, based on the 5.0 v supply (vddrx for reset and vddx for reset_a ). 5.2.6.2 analog die reset implementation there are 7 internal reset sources implemented in the analog die of the mm912_637 that causin g the internal analog die status to be reset to default (internal analog rst), and to trigger an external reset, activating the reset_a pin. in addition, during stop and cranking mode, an external reset at the reset_a pin will also reset the analog die. figure 27. analog die reset implementation mcu analog die power-on reset (por) low voltage reset (lvr) external pin reset illegal address reset clock monitor reset cop watchdog reset reset module hardware reset watchdog reset low voltage reset reset module reset reset_a thermal shutdown reset wdr reset_a tsdr vddlr vddhr vddar hwr vddxr 16 lp 0 1 0 1 1 0 measure during lpm lpm cranking mode lpm = low power mode
mm912_637, rev. 3.0 freescale semiconductor 79 with the exception of the wdr, hwr, and tsdr, the reset_a pin is driven active as long t he condition is pending. the wdr, hwr, and tsdr will issue a 2 x lpclk cycle active at the pin. during cranking mode (84) , only the vddlr is active. during low power modes, only vddxr and vddar are active reset sources. vddar is only active during active measurement in lpm. vddxr and vddar are not active in normal mode. notes 84.not available on all device derivatives 5.2.6.3 reset source summary ? hwr - hardware reset ? forced internal reset caused by writing the hwr bin in th e pcr_ctl register. the source will be indicated by the hwrf bit. ? wdr - watchdog reset ? window watchdog failure. the source will be indicated by the wdrf bit. ? lvr - low voltage reset ? the voltage at the vddl, vddh, vddx, or vdda has dropped below its reset threshold level. the source will be indicated for the vddl by the lvrf + hvrf, for the vdda by the avrf, and for the vddh by the hvrf bit. vddx resets are not indicated via individual reset flags. see figure 27 for dependencies. ? tsdr - temperature shutdown reset ? the critical shutdown temperature threshold has been r eached. vdda, vddx, and vddh will be disabled as long as the over-temperature condition is pending (85) and the reset source is indicated by the htf bit. ? external reset ? during stop and cranking (85) mode, a low signal at the reset_a pin will reset the analog die. since this condition can only be initiated by the microcontroller, no specific indicator flag is implemented. notes 85.resulting in a vddh low voltage reset taking over the reset after the 2 lpclk reset pulse figure 28. reset status information 5.2.7 pcr - memory map and registers 5.2.7.1 overview this section provides a detailed descripti on of the memory map and registers. 5.2.7.2 module memory map the memory map for the analog die - power, clock and resets - pcr module is given in table 71 wdr tsdr vddlr vddhr vddar hwr vddxr htf hvrf wdrf hwrf lvrf no flag indicator avrf
mm912_637, rev. 3.0 freescale semiconductor 80 5.2.7.3 register descriptions this section consists of regist er descriptions in address order. each description includes a standard register diagram with an associated figure number. details of register bit and fi eld function follow the register diagrams, in bit order. table 71. module memory map offset (86) , (87) name 7 6 5 4 3 2 1 0 0x00 pcr_ctl pcr control register r 0 0 0 0 0 0 0 0 w htiem uviem hwrm 0 pfm[1:0] opmm[1:0] r htie uvie 0 0 pf[1:0] opm[1:0] w hwr 0 0x02 pcr_sr (hi) r htf uvf hwrf wdrf hvrf lvrf wultcf wlpmf pcr status register w write 1 will clear the flags 0x03 pcr_sr (lo) r wuahth f wucthf wucalf wulinf wuptb3f wuptb2f wuptb1f wuptb0f pcr status register w write 1 will clear the flags 0x04 pcr_presc pcr 1.0 ms prescaler r presc[15:0] w r w 0x06 pcr_wue (hi) r wuahth wucth wucal wulin wuptb3 wuptb2 wuptb1 wuptb0 wake-up enable register w 0x07 pcr_wue (lo) r wultc 0 0 0 0 0 0 0 wake-up enable register w 0x0e trim_alf (hi) r prdf 0 0 apresc[12:8] trim for accurate 1.0 ms low freq clock w 0x0f trim_alf (lo) r apresc[7:0] trim for accurate 1.0 ms low freq clock w notes 86.offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space. 87.register offset with the ?lo? address value not shown have to be accessed in 16-bit mode. 8-bit access will not function.
mm912_637, rev. 3.0 freescale semiconductor 81 5.2.7.3.1 pcr contro l register (pcr_ctl) table 72. pcr control register (pcr_ctl) offset (88) , (89) 0x00 access: user read/write 15 14 13 12 11 10 9 8 r 0 0 0 0 0 0 0 0 w htiem uviem hwrm 0 pfm[1:0] opmm[1:0] reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r htie uvie 0 0 pf[1:0] opm[1:0] w hwr 0 reset 0 0 0 0 0 0 0 0 notes 88.offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space. 89.register offset with the ?lo? addres s value not shown have to be accessed in 16- bit mode. 8-bit access will not function. table 73. pcr control register (pcr_ctl) - register field descriptions field description 15 htiem high temperature interrupt enable mask 0 - writing the htie bit will have no effect 1 - writing the htie bit will be effective 14 uviem supply under-voltage interrupt enable mask 0 - writing the uvie bit will have no effect 1 - writing the uvie bit will be effective 13 hwrm hardware reset mask 0 - writing the hwr bit will have no effect 1 - writing the hwr bit will be effective 12 reserved reserved. must remain ?0? 11-10 pfm[1:0] prescaler factor mask 00,01,10 - writing the pf bits will have no effect 1 - writing the pf bits will be effective 9-8 opmm[1:0] operation mode mask 00,01,10 - writing the opm bits will have no effect 11 - writing the opm bits will be effective 7 htie high temperature interrupt enable. writing only ef fective with corresponding mask bit htiem set. 0 - high temperature interrupt (hti) enabled 1 - high temperature interrupt (hti) disabled 6 uvie low supply voltage interrupt enable. writing only ef fective with corresponding mask bit uviem set. 0 - low supply voltage interrupt (uvi) enabled 1 - low supply voltage interrupt (uvi) disabled 5 hwr hardware reset. writing only effective with corresponding mask bit hwrm set. write only. 0 - no effect 1 - all analog die digital logic is reset and external reset ( reset_a ) is set to reset the mcu. 4 reserved reserved. must remain ?0?
mm912_637, rev. 3.0 freescale semiconductor 82 5.2.7.3.2 pcr status re gister (pcr_sr (hi)) 3-2 pf[1:0] 1.0 ms prescaler. writing only effective with corresponding mask bits pfm set to 11. 00 - 1 01 - 2 10 - 4 11 - 8 1-0 opm[1:0] operation mode select. writing only effectiv e with ?11? mask bits opmm set to 11. 00 - normal mode 01 - stop mode 10 - sleep mode 11 with cranking feature disabled - same effect as 01 (stop mode) 11 with cranking feature enabled - cranking mode table 74. pcr status register (pcr_sr (hi)) offset (90) 0x02 access: user read/write 7 6 5 4 3 2 1 0 r htf uvf hwrf wdrf hvrf lvrf wultcf wlpmf w write 1 will clear the flags (91) reset 00000000 notes 90.offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. 91.htf and uvf represent the current status and cannot be cleared. writing 1 to htf / uvf will clear the interrupt flag in the interrupt source register and interrupt vector register instead. table 75. pcr status register (pcr_sr (h i)) - register field descriptions field description 7 htf high temperature condition flag. this bit is set once a temper ature warning is detected, or the last reset being caused by a temperature shutdown event (tsdr). writing htf=1 will clear the flag and the interrupt flag in the interrupt source register and interrupt vector register, if the condition is gone. 0 - no high temperature condition detected. 1 - high temperature condition detected or last reset = tsdr. 6 uvf supply under-voltage condition flag. this bit is set once a under-voltage warning is detected. writing uvf=1 will clear the flag and the interrupt flag in the interrupt source register and interrupt vector register, if the condition is gone (uvf=0). 0 - no under-voltage condition detected. 1 - under-voltage condition detected. 5 hwrf hardware reset flag. writing this bit to logic 1 will clear the flag. 0 - n.a. 1 - last reset was caused by a hwr command. 4 wdrf watchdog reset flag. writing this bi t to logic 1 will clear the flag. 0 - n.a. 1 - last reset was caused by the analog die window watchdog. 3 hvrf vddh low voltage reset flag. writing this bit to logic 1 will clear the flag. 0 - n.a. 1 - last reset was caused by a low voltage co ndition at the vddh regulator. (lvrf = 0) 1 - last reset was caused by a low voltage co ndition at the vddl regulator. (lvrf = 1) 2 lvrf vddl low voltage (por) reset flag. writing this bit to logic 1 will clear the flag. 0 - n.a. 1 - last reset was caused by a low voltage conditi on at the vddl regulator. (power on reset - por) table 73. pcr control register (pcr _ctl) - register field descriptions field description
mm912_637, rev. 3.0 freescale semiconductor 83 5.2.7.3.3 pcr status re gister (pcr_sr (lo)) 1 wultcf life time counter wake-up flag. writing this bit to logic 1 will clear the flag. 0 - n.a. 1 - last wake-up was caused by a life time counter overflow 0 wlpmf wake-up after low power mode flag. writing this bit to logic 1 will clear the flag. 0 - n.a. 1 - indicates wake-up after low power mode. table 76. pcr status register (pcr_sr (lo)) offset (92) 0x03 access: user read/write 7 6 5 4 3 2 1 0 r wuahthf wucthf wucalf wulinf wuptb3f wuptb2f wuptb1f wuptb0f w write 1 will clear the flags reset 00000000 notes 92.offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space. table 77. pcr status register (pcr_sr (l o)) - register field descriptions field description 7 wuahthf wake-up on ah counter threshold flag. writi ng this bit to logic 1 will clear the flag. 0 - n.a. 1 - indicates wake-up after ah counter threshold reached. 6 wucthf wake-up on current threshold flag. writing this bit to logic 1 will clear the flag. 0 - n.a. 1 - indicates wake-up after current threshold reached. 5 wucalf wake-up on calibration request flag. writing this bit to logic 1 will clear the flag. 0 - n.a. 1 - indicates wake-up after calibration request. 4 wulinf wake-up on lin flag. writing this bit to logic 1 will clear the flag. 0 - n.a. 1 - indicates wake-up after lin wake-up detected 3 wuptb3f wake-up on gpio 3 event (l0 external wake-up) flag . writing this bit to logic 1 will clear the flag. 0 - n.a. 1 - indicates wake-up after gpio 3 event 2 wuptb2f wake-up on gpio 2 event (timer output compare) flag. writing this bit to logic 1 will clear the flag. 0 - n.a. 1 - indicates wake-up after gpio 2 event 1 wuptb1f wake-up on gpio 1 event (timer output compare) flag. writing this bit to logic 1 will clear the flag. 0 - n.a. 1 - indicates wake-up after gpio 1 event 0 wuptb0f wake-up on gpio 0 event (timer output compare) flag. writing this bit to logic 1 will clear the flag. 0 - n.a. 1 - indicates wake-up after gpio 0 event table 75. pcr status register (pcr_sr (hi)) - register field descriptions field description
mm912_637, rev. 3.0 freescale semiconductor 84 5.2.7.3.4 pcr 1.0 ms prescaler (pcr_presc) 5.2.7.3.5 wake-up enable re gister (pcr_wue (hi)) table 78. pcr 1.0 ms prescaler (pcr_presc) offset (93) , (94) 0x04 access: user read/write 15 14 13 12 11 10 9 8 r presc[15:8] w reset 0 1 1 1 1 1 0 1 7 6 5 4 3 2 1 0 r presc[7:0] w reset 0 0 0 0 0 0 0 0 notes 93.offset related to 0x0200 for blocking access and 0x300 fo r non blocking access with in the global address space. 94.this register is 16 bit access only. table 79. pcr 1.0 ms prescaler (pcr_presc) - register field descriptions field description 15-0 presc[15:0] 1.0 ms prescaler, used to derive d2dsclk and d2dfclk from the d2dclk signal. see 5.2.5, ?device clock tree" for details. table 80. wake-up enable register (pcr_wue (hi)) offset (95) 0x06 access: user read/write 7 6 5 4 3 2 1 0 r wuahth wucth wucal wulin wuptb3 wuptb2 wuptb1 wuptb0 w reset 0 0 0 0 0 0 0 0 notes 95.offset related to 0x0200 for blocking access and 0x3 00 for non blocking access wi thin the global address space. table 81. wake-up enable register (pcr_wue (hi)) - register field descriptions field description 7 wuahth 0 - wake-up on ah counter disabled 1 - wake-up on ah counter enabled 6 wucth 0 - wake-up on current threshold disabled 1 - wake-up on current threshold enabled 5 wucal 0 - wake-up on calibration request disabled 1 - wake-up on calibration request enabled 4 wulin 0 - wake-up on lin disabled 1 - wake-up on lin enabled 3 wuptb3 0 - wake-up on gpio 3 event disabled 1 - wake-up on gpio 3 event enabled
mm912_637, rev. 3.0 freescale semiconductor 85 5.2.7.3.6 wake-up enable re gister (pcr_wue (lo)) 5.2.7.3.7 trim for accurate 1ms lo w freq clock (trim_alf (hi)) 5.2.7.3.8 trim for accurate 1.0 ms low freq clock (trim_alf (lo)) 2 wuptb2 0 - wake-up on gpio 2 event disabled 1 - wake-up on gpio 2 event enabled 1 wuptb1 0 - wake-up on gpio 1 event disabled 1 - wake-up on gpio 1 event enabled 0 wuptb0 0 - wake-up on gpio 0 event disabled 1 - wake-up on gpio 0 event enabled table 82. wake-up enable register (pcr_wue (lo)) offset (96) 0x07 access: user read/write 7 6 5 4 3 2 1 0 r wultc 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 notes 96.offset related to 0x0200 for blocking access and 0x3 00 for non blocking access wi thin the global address space. table 83. wake-up enable register (pcr_wue (lo)) - register field descriptions field description 7 wultc 0 - wake-up on life timer counter overflow disabled 1 - wake-up on life timer counter overflow enabled table 84. trim for accurate 1ms low freq clock (trim_alf (hi)) offset (97) 0x0e access: user read 15 14 13 12 11 10 9 8 r prdf 0 0 apresc[12:8] w notes 97.offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. table 85. trim for accurate 1.0 ms low freq clo ck (trim_alf (lo)) offset (98) 0x0f access: user read 7 6 5 4 3 2 1 0 r apresc[7:0] w notes 98.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. table 81. wake-up enable register (pcr_wue (hi)) - register field descriptions field description
mm912_637, rev. 3.0 freescale semiconductor 86 table 86. trim for accurate 1.0 ms low freq clock (trim_alf (lo) ) - register field descriptions field description 15 prdf alfclk prescaler ready flag 0 - the alfclk synchronization after power up or presc[15:0] / pf[1:0] change is not completed. 1 - the alfclk synchronization is complete. t he alfclk signal is synchronized to the d2dclk. 12-0 apresc[12:0] alfclk prescaler this read only value represents the current alfclk prescale r value. with the synchronization complete (prdf=1), the prescaler is used to create the calibrated clock for the life time counter (normal mode and low power mode), and timer and current trigger (low power mode only), based on the low power oscillator. after power up, the apresc register is reset to 0x0200 (512 dec) until the first synchronization is complete. this will initialize the alfclk to 1.0 khz.
interrupt mo dule - irq mm912_637, rev. 3.0 freescale semiconductor 87 5.3 interrupt module - irq 5.3.1 introduction several interrupt sources are implemented on the analog die to i ndicate important system conditions. those interrupt events are signalized via the d2dint signal to the microcontroller. see section 5.17, ?mcu - interrupt module (s12sintv1)" . 5.3.2 interrupt source identification once an interrupt is signalized, there are tw o options to identify the corresponding source(s). note the following interrupt source registers (int errupt source mirror and interrupt vector emulation by priority) are indicators only. after identifying the interrupt source, the acknowledgement of the interrupt has to be performed in the corresponding block. 5.3.2.1 interrupt source mirror all interrupt sources in the mm912_637 analog die are mirrored to a special interrupt source regi ster (int_src). this register is read only and will indicate all currently pending interrupts. reading this register will not acknowledge any interrupt. an additional d2d access is necessary to serve the specific module. 5.3.2.2 interrupt vector emulation by priority to allow a vector based interrupt handling by the mcu, the number of the highest prioritized interrupt pending is returned in t he interrupt vector register (int_vect). re ading this register will not acknowledge an interrupt. an additional d2d access is necessary to serve the specific module. 5.3.3 interrupt global mask the global interrupt mask registers int_m sk (hi) and int_msk (lo) are implemented to allow a global enable / disable of all analog die interrupt sources. the individual blocks mask registers should be used to control the individual sources. 5.3.4 interrupt sources the following interrupt sources are implemented on the analog die. table 87. interrupt sources irq description uvi under-voltage interrupt (or wake-up from cranking mode) hti high temperature interrupt lti lin driver over-temperature interrupt ch0 tim channel 0 interrupt ch1 tim channel 1 interrupt ch2 tim channel 2 interrupt ch3 tim channel 3 interrupt tov tim timer overflow interrupt err sci error interrupt tx sci transmit interrupt rx sci receive interrupt analog mcu
interrupt mo dule - irq mm912_637, rev. 3.0 freescale semiconductor 88 5.3.4.1 under-voltage interrupt (uvi) this maskable interrupt signalizes a under-voltage condition on the vsup supply input. acknowledge the interrupt by writing a 1 into the uvf bit in th e pcr status register (pcr_sr (hi)). the flag cannot be cleared as long as the condition is present. to issue a new interrupt, the condition has to vanish and occur again. the uvf bit represe nts the current condition, and might not be set after an inte rrupt was signalized by the interrupt source registers. see section 5.2, ?analog die - power, clock and resets - pcr" for details on the pcr status register (pcr_sr (hi)), including masking information. note the under-voltage interrupt is not active in dev ices with the cranking mode enabled. for those devices, the under-voltage threshold is used to enable the high precision low voltage threshold during stop/sleep mode. once the device wakes up from cranking mo de, the uvi flag is i ndicating the wake-up source. 5.3.4.2 high temperature interrupt (hti) this maskable interrupt signalizes a high temperature condition on the analog die. the sensing element is located close to the major thermal contributors, th e system voltage regulators. acknowledge the interrupt by writing a 1 into the htf bit in the pcr status register (pcr_sr (hi)). the flag cannot be cleared as long as the condition is present. to issue a new interrupt, the condition has to vanish and occur again. the htf bit represe nts the current condition and might not be set after an interr upt was signalized by the interrupt source registers. see section 5.2, ?analog die - power, clock and resets - pcr" for details on the pcr status register (pcr_sr (hi)), including masking information. 5.3.4.3 lin driver over-te mperature interrupt (lti) acknowledge the interrupt by reading the lin re gister - linr. the flag cannot be cleared as long as the cond ition is present. t o issue a new interrupt, the condition has to vanish and occur again. see section 5.11, ?lin" for details on the lin register, including masking information. 5.3.4.4 tim channel 0 interrupt (ch0) see section 5.9, ?basic timer module - tim (tim16b4c)" . 5.3.4.5 tim channel 1 interrupt (ch1) see section 5.9, ?basic timer module - tim (tim16b4c)" . 5.3.4.6 tim channel 2 interrupt (ch2) see section 5.9, ?basic timer module - tim (tim16b4c)" . cvmi current / voltage measurement interrupt ltc lifetime counter interrupt cal calibration request interrupt table 87. interrupt sources irq description
interrupt mo dule - irq mm912_637, rev. 3.0 freescale semiconductor 89 5.3.4.7 tim channel 3 interrupt (ch3) see section 5.9, ?basic timer module - tim (tim16b4c)" . 5.3.4.8 tim timer overflow interrupt (tov) see section 5.9, ?basic timer module - tim (tim16b4c)" . 5.3.4.9 sci error interrupt (err) see section 5.12, ?serial communicat ion interface (s08sciv4)" . 5.3.4.10 sci transmit interrupt (tx) see section 5.12, ?serial communicat ion interface (s08sciv4)" . 5.3.4.11 sci receive interrupt (rx) see section 5.12, ?serial communicat ion interface (s08sciv4)" . 5.3.4.12 current / voltage me asurement interrupt (cvmi) indicates the current or voltage measur ement finished (vm or cm bit set). see section 5.7, ?channel acquisition" . 5.3.4.13 life time counter interrupt (ltc) in case a life time counter overflow occurs with the corresponding interrupt ena bled, the ltc interrupt is issued. see section 5.13, ?life time counter (ltc)" . 5.3.4.14 calibration request interrupt (cal) once a request for re-calibration is present (temperature out of pre-set range), the calibration interrupt is issued. see full documentation on the interrupt source in section 5.7, ?channel acquisition" . 5.3.5 irq - memory map and registers 5.3.5.1 overview this section provides a detailed descripti on of the memory map and registers. 5.3.5.2 module memory map the memory map for the irq module is given in table 88 table 88. module memory map offset (99) name 7 6 5 4 3 2 1 0 0x08 int_src (hi) r tov ch3 ch2 ch1 ch0 lti hti uvi interrupt source register w 0x09 int_src (lo) r 0 0 cal ltc cvmi rx tx err interrupt source register w 0x0a int_vect r 0 0 0 0 irq[3:0] interrupt vector register w
interrupt mo dule - irq mm912_637, rev. 3.0 freescale semiconductor 90 5.3.5.3 register descriptions this section consists of regist er descriptions in address order. each description includes a standard register diagram with an associated figure number. details of register bit and fi eld function follow the register diagrams, in bit order. 5.3.5.3.1 interrupt source register (int_src (hi)) 0x0b reserved r 0 0 0 0 0 0 0 0 w 0x0c int_msk (hi) r tovm ch3m ch2m ch1m ch0m ltim htim uvim interrupt mask register w 0x0d int_msk (lo) r 0 0 calm ltcm cvmm rxm txm errm interrupt mask register w notes 99.offset related to 0x0200 for blocking access and 0x300 for non blocking access with in the global address space. table 89. interrupt source register (int_src (hi)) offset (100 ) 0x08 access: user read 7 6 5 4 3 2 1 0 r tov ch3 ch2 ch1 ch0 lti hti uvi w notes 100.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. table 90. interrupt source register (int_src (hi)) - register field descriptions field description 7 tov tim16b4c - timer overflow interrupt status 0 - no timer overflow interrupt pending 1 - timer overflow interrupt pending 6 ch3 tim16b4c - tim channel 3 interrupt status 0 - no channel 3 interrupt pending 1 - channel 3 interrupt pending 5 ch2 tim16b4c - tim channel 2 interrupt status 0 - no channel 2 interrupt pending 1 - channel 2 interrupt pending 4 ch1 tim16b4c - tim channel 1 interrupt status 0 - no channel 1 interrupt pending 1 - channel 1 interrupt pending 3 ch0 tim16b4c - tim channel 0 interrupt status 0 - no channel 0 interrupt pending 1 - channel 0 interrupt pending 2 lti lin driver over-temperature interrupt status 0 - no lin driver over-temperature interrupt 1 - lin driver over-temperature interrupt table 88. module memory map offset (99) name 76543210
interrupt mo dule - irq mm912_637, rev. 3.0 freescale semiconductor 91 5.3.5.3.2 interrupt source register (int_src (lo)) 1 hti high temperature interrupt status 0 - no high temperature interrupt pending 1 - high temperature interrupt pending 0 uvi under-voltage interrupt pending or wake-up from cranking mode status 0 - no under-voltage interrupt pending or wake-up from cranking mode 1 - under-voltage interrupt pending or wake-up from cranking mode table 91. interrupt source register (int_src (lo)) offset (101 ) 0x09 access: user read 7 6 5 4 3 2 1 0 r 0 0 cal ltc cvmi rx tx err w notes 101.offset related to 0x0200 for blocking access and 0x300 fo r non blocking access within the global address space. table 92. interrupt source register (int_src (lo)) - register field descriptions field description 5 cal calibration request interrupt status 0 - no calibration request interrupt pending 1 - calibration request interrupt pending 4 ltc life time counter interrupt status 0 - no life time counter interrupt pending 1 - life time counter interrupt pending 3 cvmi current / voltage measurement interrupt status 0 - no current / voltage measurement interrupt pending 1 - current / voltage measurement interrupt pending 2 rx sci receive interrupt status 0 - no sci receive interrupt pending 1 - sci receive interrupt pending 1 tx sci transmit interrupt status 0 - no sci transmit interrupt pending 1 - sci transmit interrupt pending 0 err sci error interrupt status 0 - no sci transmit interrupt pending 1 - sci transmit interrupt pending table 90. interrupt source register (int_src (hi)) - register field descriptions field description
interrupt mo dule - irq mm912_637, rev. 3.0 freescale semiconductor 92 5.3.5.3.3 interrupt vect or register (int_vect) 5.3.5.3.4 interrupt mask re gister (int_msk (hi)) table 93. interrupt vector register (int_vect) offset (102 ) 0x0a access: user read 7 6 5 4 3 2 1 0 r 0 0 0 0 irq w notes 102.offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. table 94. interrupt vector register (int_ vect) - register field descriptions field description 4-0 irq represents the highest prioritized interrupt pending. see ta b l e 95 . if no interrupt is pending, the result will be 0. table 95. interrupt vector / priority irq description irq priority - no interrupt pending or wake-up from stop mode 0x00 - uvi under-voltage interrupt or wake-up from cranking mode 0x01 1 (highest) hti high temperature interrupt 0x02 2 lti lin driver over-temperature interrupt 0x03 3 ch0 tim channel 0 interrupt 0x04 4 ch1 tim channel 1 interrupt 0x05 5 ch2 tim channel 2 interrupt 0x06 6 ch3 tim channel 3 interrupt 0x07 7 tov tim timer overflow interrupt 0x08 8 err sci error interrupt 0x09 9 tx sci transmit interrupt 0x0a 10 rx sci receive interrupt 0x0b 11 cvmi acquisition interrupt 0x0c 12 ltc life time counter interrupt 0x0d 13 cal calibration request interrupt 0x0e 14 (lowest) table 96. interrupt mask regi ster (int_msk (hi)) offset (103 ) 0x0c access: user read/write 7 6 5 4 3 2 1 0 r tovm ch3m ch2m ch1m ch0m ltim htim uvim w reset 0 0 0 0 0 0 0 0 notes 103.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space.
mm912_637, rev. 3.0 freescale semiconductor 93 5.3.5.3.5 interrupt mask re gister (int_msk (lo)) table 97. interrupt mask register (int_msk (hi)) - register field descriptions field description 7 tovm timer overflow interrupt mask 0 - interrupt enabled 1 - interrupt disabled 6 ch3m timer channel 3 interrupt mask 0 - interrupt enabled 1 - interrupt disabled 5 ch2m timer channel 2 interrupt mask 0 - interrupt enabled 1 - interrupt disabled 4 ch1m timer channel 1 interrupt mask 0 - interrupt enabled 1 - interrupt disabled 3 ch0m timer channel 1 interrupt mask 0 - interrupt enabled 1 - interrupt disabled 2 ltim lin driver over-temperature interrupt mask 0 - interrupt enabled 1 - interrupt disabled 1 htim high temperature interrupt mask 0 - interrupt enabled 1 - interrupt disabled 0 uvim under-voltage interrupt mask 0 - interrupt enabled 1 - interrupt disabled table 98. interrupt mask register (int_msk (lo)) offset (104) 0x0d access: user read/write 7 6 5 4 3 2 1 0 r 0 0 calm ltcm cvmm rxm txm errm w reset 0 0 0 0 0 0 0 0 notes 104.offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 99. interrupt mask register (int_msk (lo)) - register field descriptions field description 5 calm calibration request interrupt mask 0 - interrupt enabled 1 - interrupt disabled 4 ltcm life time counter interrupt mask 0 - interrupt enabled 1 - interrupt disabled 3 cvmm current / voltage measurement interrupt mask 0 - interrupt enabled 1 - interrupt disabled
mm912_637, rev. 3.0 freescale semiconductor 94 2 rxm sci receive interrupt mask 0 - interrupt enabled 1 - interrupt disabled 1 txm sci transmit interrupt mask 0 - interrupt enabled 1 - interrupt disabled 0 errm sci error interrupt mask 0 - interrupt enabled 1 - interrupt disabled table 99. interrupt mask register (int_msk (lo)) - register field descriptions field description
current measurement - isense mm912_637, rev. 3.0 freescale semiconductor 95 5.4 current measurement - isense 5.4.1 introduction this chapter only gives a summary of the current sense module. refer to section 5.7, ?channel acquisition" for the complete description of all acquisition channels, in cluding the current measurement channel. 5.4.1.1 features ? dedicated 16 bit sigma delta ( ?? ) adc ? programmable gain amplifier (pga ) with 8 programmable gain factors ? gain control block (gcb) for automatic gain adjustment ? simultaneous sampling with voltage channel ? programmable gain and offset compensation ? optional chopper mode with moving average ? sinc3 + iir stage ? calibration mode to compute compensation buffers ? programmable low pass filter (lpf), configur ation shared with the voltage measurement channel ? optional shunt resistor sensing feature ? triggered sampling during low power mode with programmable wake-up conditions 5.4.1.2 block diagram figure 29. current measurement channel the battery current is measured by measuring the voltage drop v drop over an external shunt resistor, connected to isenseh and isensel. v drop , and is defined as the differential voltag e between the isensel and isenseh inputs (v drop =isensel-isenseh). a positive voltage drop means a positive current is flowing, and vice versa. if the gnd pin of the module is connected to isenseh, the measured current includes the su pply current of the mm912_637 (current flows back to negative battery pole ). if the gnd pin is connected to the i sensel input, the supply current of the mm912_637 is not measured. however, the voltage at the isenseh input could go below gnd (see max ratings). in this case, the current measurement sti ll functions as specified. pga esd battery minus pole chassis ground r shunt isensel isenseh vref compensation 24bit esd input swap pga auto zero gcb digital chopper decimation with iir lpf analog mcu
voltage measurement - vsense mm912_637, rev. 3.0 freescale semiconductor 96 5.5 voltage measurement - vsense 5.5.1 introduction this chapter only gives a summary of the voltage sense module. refer to section 5.7, ?channel acquisition" for the complete description of all acquisition channels, including the voltage measurement channel. 5.5.1.1 features ? dedicated 16 bit sigma delta ( ?? ) adc ? fixed high precision divider ? optional external voltage input ?vopt? ? simultaneous sampling with current channel ? programmable gain and offset compensation ? calibration mode to compute compensation buffers ? optional chopper mode with moving average ? sinc3 + iir stage ? programmable low pass filter (lpf), configur ation shared with current measurement channel 5.5.1.2 block diagram figure 30. voltage measurement channel the battery voltage is measured by default, via the vsense input. a high precision divider st age scales down the battery voltag e by a fixed factor k =1/28, to a voltage below the inter nal reference voltage of the sigma delta adc (vsense*k < v ref ). if an optional external voltage is measured, t he multiplexer (mux) is selected to feed the v opt input to the buffer. esd vopt vsense vref 16bit esd mux div28 div28 input swap digital chopper compensation lpf decimator with iir analog mcu
temperature measurement - tsense mm912_637, rev. 3.0 freescale semiconductor 97 5.6 temperature measurement - tsense 5.6.1 introduction this chapter only gives a summary of t he temperature sense module. refer to section 5.7, ?channel acquisition" for the complete description of all acquisition channels, incl uding the temperature measurement channel. 5.6.1.1 features ? internal on chip temperature sensor ? optional external temperat ure sensor input (vtemp) ? dedicated 16-bit sigma delta adc ? programmable gain and offset compensation ? optional external sensor supply (tsup) with selectable capacitor ? optional measurement during low power mode to trigger recalibration 5.6.1.2 block diagram figure 31. temperature measurement channel note to minimize ground shift effects while using the external sensor option, r2 must be placed as close to the agnd pin as possible. c tsup is optional. the supply output must be configured to operate with the capacitor. vtemp tsup agnd r1 r2 esd vref 16bit tsup mux input swap digital chopper compensation decimation internal tempsense c tsup r vtemp analog mcu
channel acquisition mm912_637, rev. 3.0 freescale semiconductor 98 5.7 channel acquisition 5.7.1 introduction this chapter documents the current, voltage, and temperature ac quisition flow. the chapter is structured in the following secti ons. ? section 5.7.2, ?channel structure overview" ? section 5.7.3, ?current and voltage measurement" ? section 5.7.3.1, ?shunt sense, pga, and gcb (current channel only)" ? section 5.7.3.2, ?volta ge sense multiplexer (voltage channel only)" ? section 5.7.3.3, ?sigma delta converter" ? section 5.7.3.4, ?compensation" ? section 5.7.3.5, ?iir / decimation / chopping stage" ? section 5.7.3.6, ?low pass filter" ? section 5.7.3.7, ?format and clamping" ? section 5.7.4, ?temperature measurement channel" ? section 5.7.4.1, ?compensation" ? section 5.7.5, ?calibration" ? section 5.7.6, ?memory map and registers" 5.7.2 channel structure overview the mm912_637 offers three parallel measurement channels. current, voltage, and temperature. the voltage channel is shared between the vsense and vopt voltage source, the temperature channel between etemp and itemp. figure 32. simplified measurement channel figure 33 shows an overview of the detailed dependencies between th e control and status registers and the channels. refer to the following sections of this chapter for details. i sd sinc3 +iir format & clamp 24 10 gain (igcx) offset (coc) 8 v sd sinc3 format & clamp 16 10 gain (vsgc) offset (voc) 8 t format & clamp 1 16 8 gain (itgc/ etgc) offset (itoc/ etoc) 8 pga sd lpf sinc1 lpf sinc1 1 1 sinc1 sinc3 +iir analog mcu
channel acquisition mm912_637, rev. 3.0 freescale semiconductor 99 figure 33. channel complete overview gain and offset compensation, sinc 3 filter, and iir filter block pga pga offset cal. g c b div28 div28 ahcr(m) opte(m) opene(m) cvmie(m) etmen(m) itmen(m) vmen(m) cmen(m) avrf pgag vmow etm itm vm cm cmow open etchop itchop vchop cchop vth w r/w r/w r/w r/w r/w r/w r/w r r r r r r r r r r r r r r calibration interrupt tcomp(m) ccomp(m) lpfen(m) etchop(m) itchop(m) cvchop(m) agen(m) r/w r/w r/w r/w r/w r/w r/w zero(m) ecap(m) tadcg(m) vadcg(m) cadcg(m) tden(m) vden(m) cden(m) r/w r/w r/w r/w r/w r/w r/w r/w dec[2:0] r/w bgadc[1:0] bgldo r/w r/w bg3en bg2en r r bg1en r igain[2:0] r/w d r/w etemp[15:0] r itemp[15:0] r curr[23:0] r volt[15:0] r lpfc[3:0] r/w tcmp[15:0] r/w thf[7:0] r/w cth[7:0] r/w dbt(m)[1:0] r/w iirc(m)[2:0] r/w pgaf(m) r/w ahth[30:0] r/w ahc[31:0] a0[15:0] r/w r a1[15:0] r/w a2[15:0] r/w a3[15:0] r/w a4[15:0] r/w a5[15:0] r/w a6[15:0] r/w a7[15:0] r/w a8[15:0] r/w a9[15:0] r/w a10[15:0] r/w a11[15:0] r/w a12[15:0] r/w a13[15:0] r/w a14[15:0] r/w a15[15:0] r/w 00b 5 0212 041 b 0812 0a4 4 0e3 5 1021 10e 4 1021 0e3 5 0a4 4 0812 041 b 0212 00b 5 0000 bgcal(m)[1:0] r/w pgaz(m) r/w pgao(m) r/w diagv(m) r/w diagi(m) r/w bgrf r pgaof r tmf[2:0] r/w tcmax[15:0] r/w tcmin[15:0] r/w voc[7:0] r/w 0000 0000 00 coc4..512[7:0] r/w 00 vsgc[9:0] r/w 200 igc4..512[9:0] r/w 200 pgaoc4..512[10:0] r/w 000 itoc[7:0] r/w 00 itgc[7:0] r/w 80 etoc[7:0] r/w 00 etgc[7:0] r/w 80 gain and offset compensation and sinc 3 filter esd tsup vtemp tsup mux itemp etemp 1 bit internal temp sensor isensel esd esd isenseh esd vsense vopt esd esd mux format & clamp vcomp(m) r/w adc ref adc ref chopper control chopper control temperature measurement control voltage measurement control chopper control 16 bit 1 bit 1 bit short short calibration request open test lpf current measurement control format & clamp sinc1 l=4 lpf format & clamp sinc1 l=4 =1 cvmi interrupt 1 0 1 0 pf[1:0] presc[15:0] r/w r/w prdf r apresc[12:0] r clock control calibration wake up ah threshold wake up current threshold wake up wake up control (low power mode only) calie(m) r/w low power current measurement result adc ref bg control diag diag short cal ref cal ref cal ref sinc1 l=2 16 bit 24 bit = ? 0xdac0 calf r gain and offset compensation, sinc 3 filter, and iir filter block
channel acquisition mm912_637, rev. 3.0 freescale semiconductor 100 5.7.3 current and voltage measurement to guarantee synchronous voltage and current acquisition, both channels are implemented equal in terms of digital signal conditioning and timing. the analog signal conditioning, before t he sigma delta converter, is di fferent to match the different sources. 5.7.3.1 shunt sense, pga, a nd gcb (current channel only) current channel specific analog signal conditioning. 5.7.3.1.1 shunt sense an optional current sense featur e is implemented to sense the presence of the current shunt resistor. setting the open bit (acq_ctl register), will activate the feature. the open bit (acq _sr register) will indicate the shunt resistor open. the sense feature will detect an open condition for a shunt resistance r shunt > ropen. 5.7.3.1.2 programmable gain amplifier (pga) to allow a wide range of current levels to be measured, a programmable gain amplifier is implemented. following the input chopper (see section 5.7.3.5, ?iir / decimation / chopping stage" ), the differential voltage is amplified by one of the 8 gains controlled by the gain control block. the pga has an internal offset compensation feature - see section 5.7.4.1, ?compensation" and section 5.7.5, ?calibration" for details. 5.7.3.1.3 gain cont rol block (gcb) to allow a transparent gain adjustment with minimum mcu load, an automatic gain c ontrol has been implemented. the absolute output of the pga is constantly compared with a programmable up and down threshold (acq_gcb register). the threshold is a d/a output according ta b l e 100 . once the programmed threshold is reached, the gain is adjusted to the next level. the currently active gain setting can be read in the igain[2:0] register. once the gain has been adjusted by the gcb, the pgag bit will be set. table 100. gain control block - register acq_gcb d[7:0] gcb high (up) threshold acq_gcb d[7:0] gcb low (down) threshold 0000xxxx 1/16 v ref xxxx0000 0 0001xxxx 2/16 v ref xxxx0001 1/16 v ref 0010xxxx 3/16 v ref xxxx0010 2/16 v ref 0011xxxx 4/16 v ref xxxx0011 3/16 v ref 0100xxxx 5/16 v ref xxxx0100 4/16 v ref 0101xxxx 6/16 v ref xxxx0101 5/16 v ref 0110xxxx 7/16 v ref xxxx0110 6/16 v ref 0111xxxx 8/16 v ref xxxx0111 7/16 v ref 1000xxxx 9/16 v ref xxxx1000 8/16 v ref 1001xxxx 10/16 v ref xxxx1001 9/16 v ref 1010xxxx 11/16 v ref xxxx1010 10/16 v ref 1011xxxx 12/16 v ref xxxx1011 11/16 v ref 1100xxxx 13/16 v ref xxxx1100 12/16 v ref 1101xxxx 14/16 v ref xxxx1101 13/16 v ref 1110xxxx 15/16 v ref xxxx1110 14/16 v ref 1111xxxx 16/16 v ref xxxx1111 15/16 v ref
channel acquisition mm912_637, rev. 3.0 freescale semiconductor 101 the automatic gain control can be disabl ed by clearing the agen bit. in this case, writing the igain[2:0] register will allow manual gain control. note the igain[2:0] regi ster content does determine the offset compensation register access, as there are 8 individual offset register bu ffers implemented, accessed through the same coc[7:0] register. 5.7.3.2 voltage sense multip lexer (voltage channel only) a multiplexer has been implemented to select between the vsen se or vopt voltage input. the opte bit controls the multiplexer. both input signals are divided by a fixed div28 divider. note there is no further state machine separation of the two voltage channels. the software has to assure all compensation regi sters are configured properly af ter changing the multiplexer. both voltage source conversion results will be stored in the same result register. the divided and multiplexed voltages will be routed through the optional chopper (see section 5.7.3.5, ?iir / decimation / chopping stage" ) before entering the sigma delta converter stage. 5.7.3.3 sigma delta converter 5.7.3.3.1 overview a high resolution adc is needed for current and battery volt age measurements of the mm912_637 . a second order sigma delta modulator based architecture is chosen. 5.7.3.4 compensation following the optional chopper stage, the sigma delta bit stream is first gain and then offset compensated using the compensati on registers. the compensation stages for both channels can be completely bypassed by clearing the ccomp / vcomp bits. 5.7.3.4.1 gain compensation table 101 shows the gain compensation register for the current an d voltage channel. at system startup, the factory trimmed values have to be copied into the vsgc and igcx registers (see section 6.2, ?ifr trimming content and location" ). note there are 8 individual gain compensation registers for the current measurement channels different pga gains with 8 individual gain trim values present in the ifr trimming flash. based on the voltage channel multiplexer confi guration, a different trim gain compensation value has to be used in the compensation regi ster. the compensation register content has to be updated when changing the multiplexer setting. table 101. gain compensation - voltage and current channel vsgc[9:0] igcx[9:0] voltage channel gain current channel gain 0x3ff 1.3174 1.7832 0x3fe 1.3169 1.7822 0x3fd 1.3164 1.7812 . . . . . .
channel acquisition mm912_637, rev. 3.0 freescale semiconductor 102 5.7.3.4.2 offset compensation table 102 shows the offset compensatio n register for the current and voltage chann el. at system startup, the factory trimmed values have to be copied into the voc and coc registers (see section 6.2, ?ifr trimming content and location" ). note based on the voltage channel multiplexer and co pper configuration, a different trim offset compensation value has to be used in the compensation register. the compensation register content has to be updated wh en changing the multiplexer setting. while there is only one offset compensation r egister voc[7:0] for th e voltage channel, there are 8 individual offset compensation regist ers for the current channel. the access happens through the coc[7:0] regist er mapped, based on the igai n[2:0] register content. 0x203 1.0694 1.2872 0x202 1.0689 1.2862 0x201 1.0684 1.2852 0x200 (default) 1.0679 1.2842 0x1ff 1.0674 1.2832 0x1fe 1.0669 1.2822 0x1fd 1.0664 1.2812 . . . . . . 0x002 0.8189 0.7862 0x001 0.8184 0.7852 0x000 0.8179 0.7842 table 102. offset compensation - voltage and current channel voc[7:0] coc[7:0] voltage channel offset (105) current channel offset (105) 0x7f +9.073 +15.092 0x7e +9.002 +14.974 0x7d +8.93 +14.855 . . . . . . 0x03 0.214 +0.357 0x02 0.143 +0.238 0x01 0.071 +0.119 0x00 (default) 0 0 0xff -0.071 -0.119 0xfe -0.143 -0.238 0xfd -0.214 -0.357 . . . . . . 0x82 -9.002 -14.974 0x81 -9.073 -15.092 table 101. gain compensation - voltage and current channel vsgc[9:0] igcx[9:0] voltage channel gain current channel gain
channel acquisition mm912_637, rev. 3.0 freescale semiconductor 103 5.7.3.5 iir / decimation / chopping stage 5.7.3.5.1 functional description the chopper frequency is set to one eight h of the decimator frequency (512 khz typ). on each phase, four decimation cycles are necessary to get a steady signal. the equation of the iir is y n+1 = ? .x n +(1- ? ).y n . the ? parameter can be configured by the iirc[2:0] register. see section 5.7.6.3.18, ?i and v chopper control register (acq_cvcr (lo))" . the decimation process is then completed by a programm able (dec[2:0]) sinc3 filter, which outputs a 0.5...8 ks/s signal. the modulated noise is removed by an averagi ng filter (sinc1; l=4), which has an infini te rejection at the chopping frequency. 5.7.3.5.2 latency and throughput ? the throughput is 512 khz/df with df configurable from 64 to 1024. ? the latency is given by (4+3*iir+3*avger+n_lpf)*df/512 khz where: ? iir=1 if iir is en abled (0 otherwise), ? avger=1 if the chopper mode is activated (0 otherwise), ? n_lpf is the lpf coefficient number. 5.7.3.6 low pass filter to achieve the required attenuation of the measured volta ge and current signals in the frequency domain, a programmable low-pass filter following the sinc3+iir filt er, is implemented for both channels with shared configuration registers to deliver the equivalent filtering. the following filter charac teristic is implemented: ?f pass = 100 hz (att100 hz) ?f stopp = 500 hz (att500 hz) the number of filter coefficients used ca n be programmed in the acq_lpfc[3:0] register. the filter can be bypassed completely clearing the lpfen bit. the filter uses an algorithmic and logic unit (alu) for calculat ing the filtered output data, depending on the incoming data st ream at ?data in? and the low-pass coefficients (a0...15) at the input ?coeff?, 16-bit width of each coefficient (see 5.7.6.3.22, ?low pass filter coefficient ax (lpf_ax (hi))" ). the filter structure calculates during on e cycle (tcyc=1/fadc) the filtered data output. 0x80 -9.145 -15.211 notes 105.sd input related (mv) table 102. offset compensation - voltage and current channel voc[7:0] coc[7:0] voltage channel offset (105) current channel offset (105)
channel acquisition mm912_637, rev. 3.0 freescale semiconductor 104 figure 34. fir structure z -1 unit delay is done at a programmable frequency, depending on the decimation factor programme d in the dec[2:0] register. see table 120 . note there is no decimation from sinc3 to the lp f output, lpf uses same output rate than decimator. it's therefore possible to select an output update rate inde pendent of the filter characteristic and bandwidth. the coefficient vector consists of 16*16-b it elements and is free programmable, the maximum response time for 16 coefficients structure is 16*1/output rate. the follo wing filter function can be realized. lp filter function eqn. 3 the coefficients aj are the elements of the coefficient vector and determine the filter function. m <= 16. it's possible to rea lize fir filter functions. a typical total frequency response of the decimator and the programmable lp filter is given in figure 35 . z-1 z-1 z-1 z-1 z-1 ?? a0 a1 + + a2 + a13 + a15 + a14 + ?? ?? x(n) y(n) z-1 z-1 z-1 z-1 z-1 ?? a0 a1 + + a2 + a13 + a15 + a14 + ?? ?? x(n) y(n) y(n) = a0.x(n)+a1.x(n-1)+a2.x(n-2)+a3.x(n-3)+a4.x(n-4)+a5.x(n-5)+a6.x(n-6)+a7.x(n-7) +a8.x(n-8)+a9.x(n-9)+a10.x(n-10)+a11.x(n-11)+a12.x(n-12)+a13.x(n-13)+a14.x(n-14)+a15.x(n-15) z -1 z -1 z -1 z -1 z -1 ? ? ? ? m i i i lp z a z h 0 * ) (
channel acquisition mm912_637, rev. 3.0 freescale semiconductor 105 figure 35. typical total filter response sinc3 (d=128), lp filter (fir type with 15 coefficients used) 5.7.3.7 format and clamping the output data stream is formatted into its final size fo r both channels (16-bit for voltage and 24-bit for current). the current result will contain the gain information as part of the result. see section 5.7.6.3.12, ?current measurement result (acq_curr1 / acq_curr0)" and section 5.7.6.3.13, ?voltage measurement result (acq_volt)" . both results are written into the corresponding result regist ers and will issue an irq if enabled. the internal voltage measurement results (no compensation acti ve) are clamped to maximum and minimum values of 0xffff and 0x0000 respectively. terminal voltages outside this range will result in the respective max or min clamped values. the internal current measurement results (no compensation ac tive) are clamped to maximum and minimum values of 0x0ffff and 0x10000 respectively. terminal voltages outside this range will result in the respective max or min clamped values. note both channels will perform synchronized conversions when enabled with a single write to the acq_ctl register. as the voltage channel is not active during low power mode, the synchronicity might not be given after wake-up, and has to be re-established by restarting both channels. entering low power mode with the current / temperature channel enabled will have the channel(s) remain active during low power mode. 10 1 00 1 ? 10 3 1 ? 10 4 100 80 60 40 20 0 0 100 ? gtot f () 1 0000 10 f
channel acquisition mm912_637, rev. 3.0 freescale semiconductor 106 5.7.4 temperature measurement channel the mm912_637 can measure the tem perature from an internal built-in temperature sensor, or from an external temperature sensor connected to the vtemp pin. the ex ternal temperature sensor is supplied vi a the tsup pin. the measurement channel is the same for the internal and external temperature sensor. the temperature measurement channel uses the same sigma de lta (sd) converter implementat ion as the current and voltage channel, followed by a fixed decimation (l=128). a selectable chopper mode is implemented to compensate for of fset errors. once the chopper is enabled, an average (sinc1, l=2) is active. once the measurement is enabled, the temperature result registers are updated with the channel update rate. when both measurements are enabled, bo th temperature sensors are measured succe ssively where the measurement is started with the internal sensor. the internal temperature measurement result (no compensati on active) of 0x0000 represents 0k, the maximum 0xffff = 523k (typ). the result data is stored into the result registers acq_itemp and acq_etemp (both 16-bit). during an over range event, the adc is limited to the maximum value. the result of the internal temper ature measurement is utilized to g enerate the calibration request. see section 5.7.5, ?calibration" . 5.7.4.1 compensation the compensation for the tem perature channels is implemented simila r to the current and voltage channel. table 103. gain compensation - temperature channel itgc[7:0] etgc[7:0] temperature channel gain compensation 0xff 1.124 0xfe 1.123 0xfd 1.122 . . . . 0x83 1.003 0x82 1.002 0x81 1.001 0x80 (default) 1.000 0x7f 0.999 0x7e 0.998 0x7d 0.997 . . . . 0x02 0.877 0x01 0.876 0x00 0.875
channel acquisition mm912_637, rev. 3.0 freescale semiconductor 107 note factory trimmed compensation values are only available for the internal temperature channel. 5.7.5 calibration to ensure the maximum precision of the current and voltage sense module, several stages of calibration are implemented to compensate temperature effects. the calibr ation concept combines the availability of flash and the temperat ure information to guarantee the measurement accuracy un der all functional conditions. the trimming and calibration procedures are split in three diff erent categories: power on-, calibration request-, and optional verification procedures. 5.7.5.1 system power on procedure several device parameters are guaranteed with full precision afte r system trimming only. during fi nal test of the device, trim values are computed, verified, and st ored into the system flash memory. to ensure optimum system performance, the following power on procedure has to be performed during power on. as the device is typically constantly powered during its operation, th is operation has to be performed typically one time only. during a system power loss or low power rese t condition, the applicati on software has to ensure t he procedure executes again. table 104. offset compensation - temperature channel (106) itoc[7:0] etoc[7:0] temperature channel offset compensation (107) 0x7f +9.689 0x7e +9.613 0x7d +9.537 . . . . 0x03 +0.229 0x02 +0.153 0x01 +0.076 0x00 (default) 0 0xff -0.076 0xfe -0.153 0xfd -0.229 . . . . 0x82 -9.613 0x81 -9.689 0x80 -9.766 notes 106.typical values based on default gain setting 107.sd input related (mv)
channel acquisition mm912_637, rev. 3.0 freescale semiconductor 108 figure 36. power on procedure 5.7.5.1.1 startup trimming to ensure all analog die modules are being trimmed properly, t he following flash information (located in the mcu ifr from 0x0_40d0 to 0x0_40d9) has to be copied to the analog die re gister 0xe0 to 0xe9. this trimming includes the band gap reference adjustment for the 3 system ba nd gap circuits, the lin slope adjustmen t (trim_lin), the lo w voltage threshold (trim_lvt), and the low power oscillator (trim_osc). see section 6, ?mm912_637 - trimming" . note the lposc[12:0] trim will adjust the low power o scillator to its specified accuracy. this will result in the dependent watchdog timing to be accurate after writing the trimming information. startup trimming bandgap trim (bg1,2,3) lin slope trim lvt trim lposc trim startup calibration current channel offset compensation procedure 2 vsense / vopt channel offset compensation 1 itemp channel offset compensation build gain compensation reference table build current channel gc look up table build vsense channel gc look up table build vopt channel gc look up table current / voltage channel gain comp. based on itemp and lookup table itemp channel gain compensation program calibration irq temperature thresholds power on procedure (one time only) 1 : based on first channel used 2 : in case copper mode is not used pga auto zero sequence
channel acquisition mm912_637, rev. 3.0 freescale semiconductor 109 5.7.5.1.2 gain compensation look up table in order to prepare the system for the optio nal calibration interrupt serv ice during operation, it is be beneficial to create a look up table for the voltage and current channel gain compensation over temperature. for all current and voltage channel gain buffers, there are corre sponding room temperature optimum trim values stored in the ifr flash. for hot (125 c) and cold (-40 c) temperature, the adjustment to wards the room value is stored. note: this table is partially populated for analog option 1 device s (populated from 0x0_40c0 to 0x0_40e1). only default (room temperature) gain compensation values applicable. for isense, see table 22 (igainerr). for vsense, see ta b l e 23 (vgainerr). table 105. gain compensation buffer optimum global address (ifron) offset byte description content hex dec 7 6 5 4 3 2 1 0 0x0_40c0 00 00 igc4[9:8] current channel gain (4) compensation - room temp 0x0_40c1 01 01 igc4[7:0] 0x0_40c2 02 02 igc8[9:8] current channel gain (8) compensation - room temp 0x0_40c3 03 03 igc8[7:0] 0x0_40c4 04 04 igc16[9:8] current channel gain (16) compensation - room temp 0x0_40c5 05 05 igc16[7:0] 0x0_40c6 06 06 igc32[9:8] current channel gain (32) compensation - room temp 0x0_40c7 07 07 igc32[7:0] 0x0_40c8 08 08 igc64[9:8] current channel gain (64) compensation - room temp 0x0_40c9 09 09 igc64[7:0] 0x0_40ca 0a 10 igc128[9:8] current channel gain (128) compensation - room temp 0x0_40cb 0b 11 igc128[7:0] 0x0_40cc 0c 12 igc256[9:8] current channel gain (256) compensation - room temp 0x0_40cd 0d 13 igc256[7:0] 0x0_40ce 0e 14 igc512[9:8] current channel gain (512) compensation - room temp 0x0_40cf 0f 15 igc512[7:0] 0x0_40de 1e 30 vsgc[9:8] vsense channel gain compensation - room temp 0x0_40df 1f 31 vsgc[7:0] 0x0_40e0 20 32 vogc[9:8] vopt channel gain compensation - room temp 0x0_40e1 21 33 vogc[7:0] 0x0_40ec 2c 44 comp_vsg_cold[7:0] vsense channel gain compensation - cold temp (108) 0x0_40ed 2d 45 comp_vsg_hot[7:0] vsense channel gain compensation - hot temp (108) 0x0_40ee 2e 46 comp_vog_cold[7:0] vopt channel gain compensation - cold temp (108) 0x0_40ef 2f 47 comp_vog_hot[7:0] vopt channel gain compensation - hot temp (108) 0x0_40f0 30 48 igc4_cold[7:0] current channel gain (4) compensation - cold temp (108) 0x0_40f1 31 49 igc4_hot[7:0] current channel gain (4) compensation - hot temp (108) 0x0_40f2 32 50 igc8_cold[7:0] current channel gain (8) compensation - cold temp (108) 0x0_40f3 33 51 igc8_hot[7:0] current channel gain (8) compensation - hot temp (108)
channel acquisition mm912_637, rev. 3.0 freescale semiconductor 110 to create the look up table, a linear interpolation of the gai n adjustment has to be done between the three given temperatures, based on the temperature step width specified (tcalstep). 0x0_40f4 34 52 igc16_cold[7:0] current channel gain (16) compensation - cold temp (108) 0x0_40f5 35 53 igc16_hot[7:0] current channel gain (16) compensation - hot temp (108) 0x0_40f6 36 54 igc32_cold[7:0] current channel gain (32) compensation - cold temp (108) 0x0_40f7 37 55 igc32_hot[7:0] current channel gain (32) compensation - hot temp (108) 0x0_40f8 38 56 igc64_cold[7:0] current channel gain (64) compensation - cold temp (108) 0x0_40f9 39 57 igc64_hot[7:0] current channel gain (64) compensation - hot temp (108) 0x0_40fa 3a 58 igc128_cold[7:0] current channel gain (128) compensation - cold temp (108) 0x0_40fb 3b 59 igc128_hot[7:0] current channel gain (128) compensation - hot temp (108) 0x0_40fc 3c 60 igc256_cold[7:0] current channel gain (256) compensation - cold temp (108) 0x0_40fd 3d 61 igc256_hot[7:0] current channel gain (256) compensation - hot temp (108) 0x0_40fe 3e 62 igc512_cold[7:0] current channel gain (512) compensation - cold temp (108) 0x0_40ff 3f 63 igc512_hot[7:0] current channel gain (512) compensation - hot temp (108) notes 108.7-bit character with bit 7 (msb) as sign (0 = ?+?; 1 = ?- ?) with the difference to the corresponding room temperature value (e.g. 10000010 = ?-2?). table 105. gain compensation buffer optimum global address (ifron) offset byte description content hexdec76543210
mm912_637, rev. 3.0 freescale semiconductor 111 figure 37. loop up table creation 5.7.5.1.3 startup calibration the power on trimming / calibration procedure is finalized by performing the start up calibration. 5.7.5.1.3.1 vsense / vopt ch annel offset compensation and itemp channel gain / offset compensation copying the default compensation values, according to table 106 , will establish the optimum offset compensation for the vsense and vopt channels, as well as the optimum gain and offset compensation for the in ternal temperature sensor. 5.7.5.1.3.2 pga au to zero sequence the following procedure has to be performed for the pg a (programmable gain ampl ifier) auto zero (az). 1. write a ?1? to the pgao bit and its mask in the comp_ctl register (0xa0) 2. approximately 6.5 ms later, pgaof will become set at to ?1? (flag needs to be polled) 3. exit the pgao mode by writing ?0 ? in pga0 and its mask being a ?1? 4. clear the pgaof flag by writing ?1? table 106. voltage / temp trim global address (ifron) offset byte description target register hex dec 7 6 5 4 3 2 1 0 name offset 0x0_40da 1a 26 voc_s[7:0] comp_vos 0xaa (109) 0x0_40db 1b 27 voc_o[7:0] comp_voo 0xaa (109) 0x0_40dc 1c 28 voc_s[7:0] (chopper mode) comp_vos_chop 0xaa (109) 0x0_40dd 1d 29 voc_o[7:0] (chopper mode) comp_voo_chop 0xaa (109) 0x0_40e2 22 34 ito[7:0] comp_ito 0xd0 0x0_40e3 23 35 itg[7:0] comp_itg 0xd1 notes 109.based on the selection of the voltage measurement sour ce (vsense or vopt) and the activation of chopper mode. room hot cold 0 +1 +2 -1 -2 +x -x
mm912_637, rev. 3.0 freescale semiconductor 112 note the new offset compensation data can be ob served in the (pgaoc4...512[10:0]) registers. the sequence will require 3352 clock cycles of the d2dfclk (512khz), typically 6.5 ms. 5.7.5.1.3.3 current and voltage channel ga in compensation based on itemp from look up table after the first reading of the temperatur e channel measurement, the current and voltage channel gain compensation buffers must be written with the corresponding look up table value (see section 5.7.5.1.2, ?gain com pensation look up table" ). 5.7.5.1.3.4 current channel offset co mpensation procedure (chopper off only) if the chopper feature is not used for t he current measurement channel, the offset s hould be compensated using the following procedure with the highest decimation selected and the lpf active. figure 38. current channel offset compensation sequence 5.7.5.1.3.5 program calibrat ion irq temperature thresholds to finalize the startup sequence, the new temperature limits must be programmed in to the calibration temperature limits (tcmax[15:0] and tcmin[ 15:0]), and the calibration request interrupt must be enabled. 5.7.5.2 calibration request procedure during normal system operation (in normal and low power mode), a calibration request interrupt / wake-up will indicate the device temperature changed outside the range for the programmed current and voltage channel gain compensation. during a calibration request interrupt (wake-up), the curren t and voltage channel gain compensation buffers have to be updated with the corres ponding values stored in the look up table created upon system start up (see section 5.7.5.1.2, ?gain compensation look up table" ). the the new temperature limits must be prog rammed into the calibrat ion temperature limits (tcmax[15:0] and tcmi n[15:0]) before leaving the interrupt service routine. 5.7.5.3 verification procedures as an optional feature, upon application r equirement, the proper function of the cu rrent and voltage measurement channels can be verified by connecting a special calibrat ion reference to the input of the channels. short pga inputs pgaz(m) = 1 start regular sd current channel conversion with compensation disabled (ccomp(m) = 0) wait for conversion complete irq and adjust offset compensation buffers with result.
mm912_637, rev. 3.0 freescale semiconductor 113 table 107 shows the location of the diagnostic reference measurements. note: this table is unpopulated for analog option 1 devices. 5.7.6 memory map and registers 5.7.6.1 overview this section provides a detailed descrip tion of the memory map and registers. 5.7.6.2 module memory map the memory map for the acqu isition, compensation, and lpf module is given in ta b l e 108 . table 107. diagnostic measurement flash location global address (ifron) offset byte description hex dec 7 6 5 4 3 2 1 0 0x0_40e4 24 36 bg3 diag measurement from vsense channel after cal at room 0x0_40e5 25 37 0x0_40e6 26 38 bg3 diag measurement from vopt channel after cal at room 0x0_40e7 27 39 0x0_40e8 28 40 bg3 diag measurement from i channel (gain4) at room 0x0_40e9 29 41 0x0_40ea 2a 42 connect calibration reference to channel inputs (diagi(m) = diagv(m) = 1) start regular sd conversion. wait for conversion complete irq. verify result based on the reference measurements disconnect calibration reference to channel inputs (diagi(m) = diagv(m) = 0)
mm912_637, rev. 3.0 freescale semiconductor 114 table 108. module memory map offset name 7 6 5 4 3 2 1 0 0x58 acq_ctl acquisition control register r 0 0 0 0 0 0 0 0 w ahcrm optem openem cvmiem etmenm itmenm vmenm cmenm r 0 opte opene cvmie etmen itmen vmen cmen w ahcr 0x5a acq_sr (hi) r avrf pgag vmow cmow etm itm vm cm acquisition status register w write 1 will clear the flags 0x5b acq_sr (lo) r open 0 0 vth etchop itchop vchop cchop acquisition status register w 0x5c acq_acc1 acquisition chain control 1 r 0 0 0 0 0 0 0 0 w tcompm vcompm ccomp m lpfenm etchop m itchop m cvchop m agenm r tcomp vcomp ccomp lpfen etchop itchop cvchop agen w 0x5e acq_acc0 acquisition chain control 0 r 0 0 0 0 0 0 0 0 w zerom ecapm tadcgm vadcgm cadcgm tdenm vdenm cdenm r zero ecap tadcg vadcg cadcg tden vden cden w 0x60 acq_dec r 0 0 0 0 0 dec[2:0] decimation rate w 0x61 acq_bgc r 0 0 bgadc[1:0] bgldo bg3en bg2en bg1en bandgap control w 0x62 acq_gain r 0 0 0 0 0 igain[2:0] pga gain w 0x63 acq_gcb r d[7:0] gcb threshold w 0x64 acq_itemp (hi) r itemp[15:8] internal temp. measurement result w 0x65 acq_itemp (lo) r itemp[7:0] internal temp. measurement result w 0x66 acq_etemp (hi) r eemp[15:8] external temp. measurement result w 0x67 acq_etemp (lo) r eemp[7:0] external temp. measurement result w 0x68 reserved r 0 0 0 0 0 0 0 0 w 0x69 acq_curr1 r curr[23:16] current measurement result w
mm912_637, rev. 3.0 freescale semiconductor 115 0x6a acq_curr0 current measurement result r curr[15:8] w r curr[7:0] w 0x6c acq_volt voltage measurement result r volt[15:8] w r volt[7:0] w 0x6e acq_lpfc r 0 0 0 0 lpfc[3:0] low pass filter coefficient number w 0x6f reserved r 0 0 0 0 0 0 0 0 w 0x70 acq_tcmp low power trigger current measurement period r tcmp[15:0] w r w 0x72 acq_thf r thf[7:0] low power current threshold filtering period w 0x73 reserved r 0 0 0 0 0 0 0 0 w 0x74 acq_cvcr (hi) r 0 0 0 0 0 0 0 0 i and v chopper control register w dbtm[1:0] iircm[2:0] pgafm 0x75 acq_cvcr (lo) r 0 0 dbt[1:0] iirc[2:0] pgaf i and v chopper control register w 0x76 acq_cth r cth[7:0] low power current threshold w 0x77 reserved r 0 0 0 0 0 0 0 0 w 0x78 acq_ahth1 (hi) r 0 low power ah counter threshold w ahth[30:16] 0x79 acq_ahth1 (lo) r low power ah counter threshold w 0x7a acq_ahth0 (hi) r ahth[15:0] low power ah counter threshold w 0x7b acq_ahth0 (lo) r low power ah counter threshold w 0x7c acq_ahc1 (hi) r ahc[31:24] low power ah counter w 0x7d acq_ahc1 (lo) r ahc[23:16] low power ah counter w table 108. module memory map offset name 76543210
mm912_637, rev. 3.0 freescale semiconductor 116 0x7e acq_ahc0 (hi) r ahc[15:8] low power ah counter w 0x7f acq_ahc0 (lo) r ahc[7:0] low power ah counter w 0x80 lpf_a0 (hi) r a0[15:0] a0 filter coeff w 0x81 lpf_a0 (lo) r a0 filter coeff w 0x82 lpf_a1 (hi) r a1[15:0] a1 filter coeff w 0x83 lpf_a1 (lo) r a1 filter coeff w 0x84 lpf_a2 (hi) r a2[15:0] a2 filter coeff w 0x85 lpf_a2 (lo) r a2 filter coeff w 0x86 lpf_a3 (hi) r a3[15:0] a3 filter coeff w 0x87 lpf_a3 (lo) r a3 filter coeff w 0x88 lpf_a4 (hi) r a4[15:0] a4 filter coeff w 0x89 lpf_a4 (lo) r a4 filter coeff w 0x8a lpf_a5 (hi) r a5[15:0] a5 filter coeff w 0x8b lpf_a5 (lo) r a5 filter coeff w 0x8c lpf_a6 (hi) r a6[15:0] a6 filter coeff w 0x8d lpf_a6 (lo) r a6 filter coeff w 0x8e lpf_a7 (hi) r a7[15:0] a7 filter coeff w 0x8f lpf_a7 (lo) r a7 filter coeff w 0x90 lpf_a8 (hi) r a8[15:0] a8 filter coeff w 0x91 lpf_a8 (lo) r a8 filter coeff w table 108. module memory map offset name 76543210
mm912_637, rev. 3.0 freescale semiconductor 117 0x92 lpf_a9 (hi) r a9[15:0] a9 filter coeff w 0x93 lpf_a9 (lo) r a9 filter coeff w 0x94 lpf_a10 (hi) r a10[15:0] a10 filter coeff w 0x95 lpf_a10 (lo) r a10 filter coeff w 0x96 lpf_a11 (hi) r a11[15:0] a11 filter coeff w 0x97 lpf_a11 (lo) r a11 filter coeff w 0x98 lpf_a12 (hi) r a12[15:0] a12 filter coeff w 0x99 lpf_a12 (lo) r a12 filter coeff w 0x9a lpf_a13 (hi) r a13[15:0] a13 filter coeff w 0x9b lpf_a13 (lo) r a13 filter coeff w 0x9c lpf_a14 (hi) r a14[15:0] a14 filter coeff w 0x9d lpf_a14 (lo) r a14 filter coeff w 0x9e lpf_a15 (hi) r a15[15:0] a15 filter coeff w 0x9f lpf_a15 (lo) r a15 filter coeff w 0xa0 comp_ctl compensation control register r 0 0 0 0 0 0 0 w bgcalm[1:0] pgazm pgaom diagvm diagim caliem r bgcal[1:0] pgaz pgao diagv diagi calie w 0xa2 comp_sr r 0 bgrf 0 pgaof 0 0 0 calf compensation status register w write 1 will clear the flags 0xa3 comp_tf r 0 0 0 0 0 tmf[2:0] temperature filtering period w 0xa4 comp_tmax max temp before recalibration r tcmax[15:0] w r w table 108. module memory map offset name 76543210
mm912_637, rev. 3.0 freescale semiconductor 118 0xa6 comp_tmin min temp before recalibration r tcmin[15:0] w r w 0xa8 reserved r 0 0 0 0 0 0 0 0 w 0xa9 reserved r 0 0 0 0 0 0 0 0 w 0xaa comp_vo r voc[7:0] offset voltage compensation w 0xab comp_io r coc[7:0] offset current compensation window w 0xac comp_vsg gain voltage comp. vsense channel r 0 0 0 0 0 0 vsgc[9:8] w r vsgc[7:0] w 0xae reserved r 0 0 0 0 0 0 0 0 w 0xaf reserved r 0 0 0 0 0 0 0 0 w 0xb0 comp_ig4 gain current compensation 4 r 0 0 0 0 0 0 igc4[9:8] w r igc4[7:0] w 0xb2 comp_ig8 gain current compensation 8 r 0 0 0 0 0 0 igc8[9:8] w r igc8[7:0] w 0xb4 comp_ig16 gain current compensation 16 r 0 0 0 0 0 0 igc16[9:8] w r igc16[7:0] w 0xb6 comp_ig32 gain current compensation 32 r 0 0 0 0 0 0 igc32[9:8] w r igc32[7:0] w 0xb8 comp_ig64 gain current compensation 64 r 0 0 0 0 0 0 igc64[9:8] w r igc64[7:0] w table 108. module memory map offset name 76543210
mm912_637, rev. 3.0 freescale semiconductor 119 0xba comp_ig128 gain current compensation 128 r 0 0 0 0 0 0 igc128[9:8] w r igc128[7:0] w 0xbc comp_ig256 gain current compensation 256 r 0 0 0 0 0 0 igc256[9:8] w r igc256[7:0] w 0xbe comp_ig512 gain current compensation 512 r 0 0 0 0 0 0 igc512[9:8] w r igc512[7:0] w 0xc0 comp_pgao4 offset pga compensation 4 r 0 0 0 0 0 pgaoc4[10:8] w r pgaoc4[7:0] w 0xc2 comp_pgao8 offset pga compensation 8 r 0 0 0 0 0 pgaoc8[10:8] w r pgaoc8[7:0] w 0xc4 comp_pgao16 offset pga compensation 16 r 0 0 0 0 0 pgaoc16[10:8] w r pgaoc16[7:0] w 0xc6 comp_pgao32 offset pga compensation 32 r 0 0 0 0 0 pgaoc32[10:8] w r pgaoc32[7:0] w 0xc8 comp_pgao64 offset pga compensation 64 r 0 0 0 0 0 pgaoc64[10:8] w r pgaoc64[7:0] w 0xca comp_pgao128 offset pga compensation 128 r 0 0 0 0 0 pgaoc128[10:8] w r pgaoc128[7:0] w 0xcc comp_pgao256 offset pga compensation 256 r 0 0 0 0 0 pgaoc256[10:8] w r pgaoc256[7:0] w table 108. module memory map offset name 76543210
mm912_637, rev. 3.0 freescale semiconductor 120 5.7.6.3 register descriptions this section consists of regist er descriptions in address order. each description includes a standard register diagram with an associated figure number. details of register bit and fi eld function follow the register diagrams, in bit order. 0xce comp_pgao512 offset pga compensation 512 r 0 0 0 0 0 pgaoc512[10:8] w r pgaoc512[7:0] w 0xd0 comp_ito r itoc[7:0] internal temp. offset compensation w 0xd1 comp_itg r itgc[7:0] internal temp. gain compensation w 0xd2 comp_eto r etoc[7:0] external temp. offset compensation w 0xd3 comp_etg r etgc[7:0] external temp. gain compensation w 0xd4 reserved r 0 0 0 0 0 0 0 0 w 0xd5 reserved r 0 0 0 0 0 0 0 0 w 0xd6 reserved r 0 0 0 0 0 0 0 0 w 0xd7 reserved r 0 0 0 0 0 0 0 0 w notes 110.offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. 111.register offset with the ?lo? address value not shown have to be accessed in 16bit mode. 8 bit access will not function. table 108. module memory map offset name 76543210
mm912_637, rev. 3.0 freescale semiconductor 121 5.7.6.3.1 acquisition cont rol register (acq_ctl) table 109. acquisition control register (acq_ctl) offset (112) , (113) 0x58 access: user read/write 15 14 13 12 11 10 9 8 r 0 0 0 0 0 0 0 0 w ahcrm optem openem cvmiem etmenm itmenm vmenm cmenm reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r 0 opte opene cvmie etmen itmen vmen cmen w ahcr reset 0 0 0 0 0 0 0 0 notes 112.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. 113.this register is 16-bit access only. table 110. acquisition control register ( acq_ctl) - register field descriptions field description 15 ahcrm ampere hour counter reset - mask 0 - writing the ahcr bit will have no effect 1 - writing the ahcr bit will be effective 14 optem optional voltage sense enable - mask 0 - writing the opte bit will have no effect 1 - writing the opte bit will be effective 13 openem enable shunt resistor open detection - mask 0 - writing the opene bit will have no effect 1 - writing the opene bit will be effective 12 cvmiem current / voltage measurement interrupt enable - mask 0 - writing the cvmie bit will have no effect 1 - writing the cvmie bit will be effective 11 etmenm external temperature measurement enable - mask 0 - writing the etmen bit will have no effect 1 - writing the etmen bit will be effective 10 itmenm internal temperature measurement enable - mask 0 - writing the itmen bit will have no effect 1 - writing the itmen bit will be effective 9 vmenm voltage measurement enable - mask 0 - writing the vmen bit will have no effect 1 - writing the vmen bit will be effective 8 cmenm current measurement enable - mask 0 - writing the cmen bit will have no effect 1 - writing the cmen bit will be effective 7 ahcr ampere hour counter reset, this write only bit will reset the acq_ahc register. 0 - no effect 1 - acq_ahc reset to 0x00000000 6 opte optional voltage sense enable (voltage channel multiplexer control) 0 - vsense routed to adc 1 - vopt routed to adc 5 opene enable shunt resistor open detection 0 - shunt resistor open detection disabled, the open bit must be ignored 1 - shunt resistor open detection enabled, open bit will indicate status
mm912_637, rev. 3.0 freescale semiconductor 122 5.7.6.3.2 acquisition status register (acq_sr (hi)) 4 cvmie current / voltage measurement interrupt enable 0 - current and voltage measurement interrupt disabled 1 - current and voltage measurement interrupt enabled 3 etmen external temperature measurement enable 0 - external temperature measurement disabled 1 - external temperature measurement enabled 2 itmen internal temperature measurement enable 0 - internal temperature measurement disabled 1 - internal temperature measurement enabled 1 vmen voltage measurement enable 0 - voltage measurement disabled 1 - voltage measurement enabled 0 cmen current measurement enable 0 - current measurement disabled 1 - current measurement enabled table 111. acquisition status register (acq_sr (hi)) offset (114 ) 0x5a access: user read/write 7 6 5 4 3 2 1 0 r avrf pgag vmow cmow etm itm vm cm w write 1 will clear the flags reset 0 0 0 0 0 0 0 0 notes 114.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. table 112. acquisition status register (acq _sr (hi)) - register field descriptions field description 7 avrf vdda low voltage reset flag. writing th is bit to logic 1 will clear the flag. 0 - n.a. 1 - last reset was caused by a low voltage condition at the vdda regulator. 6 pgag pga gain change flag (115) . writing this bit to l ogic 1 will clear the flag. 0 - pga gain has not changed since last flag clear 1 - pga gain has changed since last flag clear 5 vmow voltage measurement result overwritten (115) . writing this bit to logic 1 will clear the flag. 0 - voltage measurement result register volt[15:0] not overwritten (116) since last vmow flag clear 1 - voltage measurement result register volt[15:0] overwritten (116) since last vmow flag clear 4 cmow current measurement result overwritten (115) . writing this bit to l ogic 1 will clear the flag. 0 - current measurement result register curr[15:0] not overwritten (116) since last cmow flag clear 1 - current measurement result register curr[15:0] overwritten (116) since last cmow flag clear 3 etm end of measurement - external temperature (115) . writing this bit to logic 1 will clear the flag. 0 - no external temperature measur ement completed since last etm clear 1 - external temperature measurement completed since last etm clear 2 itm end of measurement - internal temperature (115) . writing this bit to l ogic 1 will clear the flag. 0 - no internal temperature measur ement completed since last itm clear 1 - internal temperature measurement completed since last itm clear table 110. acquisition control register (acq_ctl) - register field descriptions field description
mm912_637, rev. 3.0 freescale semiconductor 123 5.7.6.3.3 acquisition status register (acq_sr (lo)) 1 vm end of measurement - voltage. writing this bit to logic 1 will clear the flag. 0 - no voltage measurement completed since last vm clear 1 - voltage measurement completed since last vm clear 0 cm end of measurement - current. writing th is bit to logic 1 will clear the flag. 0 - no current measurement completed since last cm clear 1 - current measurement completed since last cm clear notes 115.no interrupts issued for those flags 116.overwritten - new result latched before previous result was read table 113. acquisition status register (acq_sr (lo)) offset (117 ) 0x5b access: user read 7 6 5 4 3 2 1 0 r open 0 0 vth etchop itchop vchop cchop w notes 117.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. table 114. acquisition status register (acq _sr (lo)) - register field descriptions field description 7 open shunt resistor open detection status (nor mal mode only, only functional if opene=1) 0 - shunt resistor detected 1 - shunt resistor disconnected 4 vth digital voltage high threshold reached 0 - voltage measurement result for vsense / vopt below v th (0xdac0: equivalent to 28 v at 0.5 mv lsb weighing) 1 - voltage measurement result for vsense / vopt above or equal v th (0xdac0: equivalent to 28 v at 0.5 mv lsb weighing) 3 etchop chopping active status - external temperature 0 - chopper for external temperature measurement disabled 1 - chopper for external temperature measurement enabled 2 itchop chopping active status - internal temperature 0 - chopper for internal temperature measurement disabled 1 - chopper for internal temperature measurement enabled 1 vchop chopping active status - voltage 0 - chopper for voltage measurement disabled 1 - chopper for voltage measurement enabled 0 cchop chopping active status - current 0 - chopper for current measurement disabled 1 - chopper for current measurement enabled table 112. acquisition status register ( acq_sr (hi)) - register field descriptions field description
mm912_637, rev. 3.0 freescale semiconductor 124 5.7.6.3.4 acquisition chai n control 1 (acq_acc1) table 115. acquisition chain control 1 (acq_acc1) offset (118) (119) 0x5c access: user read/write 15 14 13 12 11 10 9 8 r 0 0 0 0 0 0 0 0 w tcompm vcompm ccompm lpfenm etchopm itchopm cvchopm agenm reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r tcomp vcomp ccomp lpfen etchop itchop cvchop agen w reset 1 1 1 0 0 0 0 1 notes 118.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. 119.this register is 16 bit access only. table 116. acquisition chain co ntrol 1 (acq_acc1) - register field descriptions field description 15 tcompm temperature measurement channel - compensation enable - mask 0 - writing the tcomp bit will have no effect 1 - writing the tcomp bit will be effective 14 vcompm voltage measurement channel - compensation enable - mask 0 - writing the vcomp bit will have no effect 1 - writing the vcomp bit will be effective 13 ccompm current measurement channel - compensation enable - mask 0 - writing the ccomp bit will have no effect 1 - writing the ccomp bit will be effective 12 lpfenm lpf enable - mask 0 - writing the ccomp bit will have no effect 1 - writing the ccomp bit will be effective 11 etchopm chopping enable - external temperature measurement channel - mask 0 - writing the etchop bit will have no effect 1 - writing the etchop bit will be effective 10 itchopm chopping enable - internal temperature measurement channel - mask 0 - writing the itchop bit will have no effect 1 - writing the itchop bit will be effective 9 cvchopm chopping enable - voltage measurement channel - mask 0 - writing the cvchop bit will have no effect 1 - writing the cvchop bit will be effective 8 agenm automatic gain control enable - mask 0 - writing the agen bit will have no effect 1 - writing the agen bit will be effective 7 tcomp temperature measurement channel - compensation enable 0 - temperature measurement channel offset and gain compensation disabled 1 - temperature measurement channe l offset and gain compensation enabled 6 vcomp voltage compensation enable 0 - voltage measurement channel offs et and gain compensation disabled 1 - voltage measurement channel offs et and gain compensation enabled 5 ccomp current compensation enable 0 - current measurement channel of fset and gain compensation disabled 1 - current measurement channel offset and gain compensation enabled
mm912_637, rev. 3.0 freescale semiconductor 125 5.7.6.3.5 acquisition chai n control 0 (acq_acc0) 4 lpfen lpf enable 0 - low pass filter for current and voltage channel disabled 1 - low pass filter for current and voltage channel enabled 3 etchop chopping enable - external temperature 0 - chopper mode for external temperature measurement disabled 1 - chopper mode for external temperature measurement enabled 2 itchop chopping enable - internal temperature 0 - chopper mode for internal temperature measurement disabled 1 - chopper mode for internal temperature measurement enabled 1 cvchop chopping enable - voltage 0 - chopper mode for voltage measurement disabled 1 - chopper mode for voltage measurement enabled 0 agen automatic gain control enable 0 - automatic gain control disabled (manual gain control via igain[2:0]) 1 - automatic gain control enabled table 117. acquisition chain control 0 (acq_acc0) offset (120) , (121) 0x5e access: user read/write 15 14 13 12 11 10 9 8 r 0 0 0 0 0 0 0 0 w zerom ecapm tadcgm vadcgm cadcgm tdenm vdenm cdenm reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r zero ecap tadcg vadcg cadcg tden vden cden w reset 0 0 1 1 1 0 0 0 notes 120.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. 121.this register is 16 bit access only. table 118. acquisition chain co ntrol 0 (acq_acc0) - register field descriptions field description 15 zerom current and voltage sigma delta input short - mask 0 - writing the zero bit will have no effect 1 - writing the zero bit will be effective 14 ecapm tsup external capacitor - mask 0 - writing the ecap bit will have no effect 1 - writing the ecap bit will be effective 13 tadcgm temperature adc gain select - mask 0 - writing the tadcg bit will have no effect 1 - writing the tadcg bit will be effective 12 vadcgm voltage adc gain select - mask 0 - writing the vadcg bit will have no effect 1 - writing the vadcg bit will be effective table 116. acquisition chai n control 1 (acq_acc1) - register field descriptions field description
mm912_637, rev. 3.0 freescale semiconductor 126 5.7.6.3.6 decimation rate (acq_dec) 11 cadcgm current adc gain select - mask 0 - writing the cadcg bit will have no effect 1 - writing the cadcg bit will be effective 10 tdenm 100ns clock delay - internal temperature - mask 0 - writing the tden bit will have no effect 1 - writing the tden bit will be effective 9 vdenm 100ns clock delay - voltage - mask 0 - writing the vden bit will have no effect 1 - writing the vden bit will be effective 8 cdenm 100ns clock delay - current - mask 0 - writing the cden bit will have no effect 1 - writing the cden bit will be effective 7 zero current and voltage sigma delta input short (to perform offset compensation measurement) 0 - sigma delta inputs not shorted 1 - current and voltage sigma delta inputs shorted 6 ecap tsup external capacitor select 0 - tsup frequency compensation di sabled. no capacitor at pin. 0 - tsup frequency compensat ion enabled. capacitor c tsup allowed at pin. 5 tadcg temperature adc gain select; test purpose only, default value (1) must be used 0 - temperature adc - gain adjustment 1 - temperature adc - standard gain (default) 4 vadcg voltage adc gain select; test purpose only; default value (1) must be used 0 - voltage adc - gain adjustment 1 - voltage adc - standard gain (default) 3 cadcg current adc gain select; test purpose only; default value (1) must be used 0 - current adc - gain adjustment 1 - current adc - standard gain (default) 2 tden timing delay - temperature 0 - standard timing for temperature measurement channel 1 - additional sd converter input delay (typ. 100 ns) for temperature measurement channel 1 vden timing delay - voltage 0 - standard timing for voltage measurement channel 1 - additional sd converter input delay (typ. 100 ns) for voltage measurement channel 0 cden timing delay - current 0 - standard timing for current measurement channel 1 - additional sd converter input delay (typ. 100 ns) for current measurement channel table 119. decimation rate (acq_dec) offset (122) 0x60 access: user read/write 7 6 5 4 3 2 1 0 r 0 0 0 0 0 dec[2:0] w reset 0 0 0 0 0 1 0 0 notes 122.offset related to 0x0200 for blocki ng access and 0x300 for non blocking acce ss within the global address space. table 118. acquisition chai n control 0 (acq_acc0) - register field descriptions field description
mm912_637, rev. 3.0 freescale semiconductor 127 5.7.6.3.7 bandgap control (acq_bgc) table 120. decimation rate (acq_dec ) - register field descriptions field description 2-0 dec[2:0] decimation rate selection (combined decimation rate of firs t and second sinc3 decimator; fist decimator is fixed to d=8) 000 - d = 512 (channel output rate = 1.0 khz) 001 - d = 64 (channel output rate = 8.0 khz) 010 - d = 128 (channel output rate = 4.0 khz) 011 - d = 256 (channel output rate = 2.0 khz) 100 - d = 512 (channel output rate = 1.0 khz), (default) 101 - d = 1024 (channel output rate = 500 hz) 110 - d = 512 (channel output rate = 1.0 khz) 111 - d = 512 (channel output rate = 1.0 khz) table 121. bandgap co ntrol (acq_bgc) offset (123) 0x61 access: user read/write 7 6 5 4 3 2 1 0 r 0 0 bgadc bgldo bg3en bg2en bg1en w reset 0 0 0 1 1 0 0 0 notes 123.offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. table 122. bandgap control (acq_bgc) - register field descriptions field description 5-4 bgadc adc bandgap select 00 - n.a. (not allowed - vdda reset) 01 - bg1 reference selected for the ad converters (default) 10 - bg2 reference selected for the ad converters 11 - bg3 reference selected for the ad converters 3 bgldo ldo (low dropout regulator) bandgap select 0 - bg2 selected as voltage regulator reference 1 - bg1 selected as voltage regulator reference (default) 2 bg3en bandgap 3 status 0 - bandgap 3 disabled 1 - bandgap 3 enabled 1 bg2en bandgap 2 status 0 - bandgap 2 disabled 1 - bandgap 2 enabled 0 bg1en bandgap 1 status 0 - bandgap 1 disabled 1 - bandgap 1 enabled
mm912_637, rev. 3.0 freescale semiconductor 128 5.7.6.3.8 pga gain (acq_gain) 5.7.6.3.9 gcb threshold (acq_gcb) table 123. pga gain (acq_gain) offset (124) 0x62 access: user read/write 7 6 5 4 3 2 1 0 r 0 0 0 0 0 igain[2:0] w reset 0 0 0 0 0 0 0 0 notes 124.offset related to 0x0200 for blocki ng access and 0x300 for non blocking ac cess within the global address space. table 124. pga gain (acq_gain) - register field descriptions field description 2-0 igain[2:0] pga gain register - writing will select (manually override) the pga gain if the aut omatic gain control is disabled (agen=0). reading will return current gain setting (including the auto gain). the register content will also determine the current channel offset compensation buffer accessed through the coc[7:0] register. 000 - pga gain = 4 001 - pga gain = 8 010 - pga gain = 16 011 - pga gain = 32 100 - pga gain = 64 101 - pga gain = 128 110 - pga gain = 256 111 - pga gain = 512 table 125. gcb threshold (acq_gcb) offset (125) 0x63 access: user read/write 7 6 5 4 3 2 1 0 r d (hi) d (lo) w reset 0 0 0 0 0 0 0 0 notes 125.offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space. table 126. gcb threshold (acq_gcb) - register field descriptions field description 7-4 d[7:4] gain control block (gcb) - 4 bit gain ?up? threshold. see section 5.7.3.1.3, ?gain control block (gcb)" . 3-0 d[3:0] gain control block (gcb) - 4 bit gain ?down? threshold. see section 5.7.3.1.3, ?gain control block (gcb)" .
mm912_637, rev. 3.0 freescale semiconductor 129 5.7.6.3.10 internal temp. me asurement result (acq_itemp (hi) / acq_itemp (lo)) 5.7.6.3.11 external temp. m easurement result (acq_etemp (hi) / acq_etemp (lo)) table 127. internal temp. measurement result (acq_itemp (hi) / acq_itemp (lo)) offset (126) 0x64 / 0x65 access: user read 7 6 5 4 3 2 1 0 r itemp[15:8] w r itemp[7:0] w notes 126.offset related to 0x0200 for blocking access and 0x300 fo r non blocking access within the global address space. table 128. internal temp. measurement resu lt (acq_itemp (hi) / acq_itemp (l o)) - register field descriptions field description 15-0 itemp[15:0] internal temperature measurement - 16 bit adc result register (unsigned integer) table 129. external temp. measurement result (acq_etemp (hi) / acq_etemp (lo)) offset (127) 0x66 / 0x67 access: user read 7 6 5 4 3 2 1 0 r etemp[15:8] w r etemp[7:0] w notes 127.offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 130. external temp. measurement result (acq_etemp (hi) / acq_etemp (lo)) - register field descriptions field description 15-0 etemp[15:0] external temperature measurement - 16 bit adc result register (unsigned integer)
mm912_637, rev. 3.0 freescale semiconductor 130 5.7.6.3.12 current measurement r esult (acq_curr1 / acq_curr0) 5.7.6.3.13 voltage measure ment result (acq_volt) table 131. current measurement result (acq_curr1 / acq_curr0) offset (128) 0x69 (129) / 0x6a (130) access: user read 7 6 5 4 3 2 1 0 r curr[23:16] w r curr[15:8] w r curr[7:0] w notes 128.offset related to 0x0200 for blocki ng access and 0x300 for non blocking ac cess within the global address space. 129.0x69 for 8-bit access. 0x68 for 16-bit access. 130.this register is 16-bit access only. table 132. current measurement result (acq_curr1 / acq_curr0) - register field descriptions field description curr [23:0] two's complement 24-bit signed integer result register for the current measurement channel. 23-16 curr [23:16] current measurement - high byte result register, 8 or 16-bit read operation. 15-0 curr [15:0] current measurement - low word result register, 16-bit read operation only. table 133. voltage measurement result (acq_volt) offset (131) (132) 0x6c access: user read 7 6 5 4 3 2 1 0 r volt[15:8] w r volt[7:0] w notes 131.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. 132.this register is 16-bit access only. table 134. voltage measurement result (acq_v olt) - register field descriptions field description 15-0 volt[15:0] unsigned 16-bit integer result register for the voltage measurement channel.
mm912_637, rev. 3.0 freescale semiconductor 131 5.7.6.3.14 low pass filter co efficient number (acq_lpfc) 5.7.6.3.15 low power trigger current measurement period (acq_tcmp) note the cyclic acquisition period must be greater than the acquisition time. see section 5.7.3.5.2, ?laten cy and throughput" ? for estimation. a continuous acquisition is still possible by using tcmp=0. table 135. low pass filter coefficient number (acq_lpfc) offset (133) 0x6e access: user read/write 7 6 5 4 3 2 1 0 r 0 0 0 0 lpfc[3:0] w reset 0 0 0 0 1 1 1 0 notes 133.offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. table 136. low pass filter coefficient number (acq_lpfc) - register field descriptions field description 3-0 lpfc[3:0] low pass filter coefficient number. defi nes the highest coefficient number used. 0000 - lpf used with coefficient a0 0001 - lpf used with coefficient a0...a1 .... 1111 - lpf used with coefficient a0...a15 table 137. low power trigger current measurement period (acq_tcmp) offset (134) (135) 0x70 access: user read / write 7 6 5 4 3 2 1 0 r tcmp[15:8] w reset 0 0 0 0 0 0 0 0 r tcmp[7:0] w reset 0 0 0 0 0 0 0 0 notes 134.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. 135.this register is 16-bit access only. table 138. low power trigger current measurement peri od (acq_tcmp) - register field descriptions field description 15-0 tcmp[15:0] low power trigger current measurement peri od (trigger counter based on alfclk). see section 5.2.4.1.1, ?cyclic current acquisition / calibration temperature check" .
mm912_637, rev. 3.0 freescale semiconductor 132 5.7.6.3.16 low power current thresh old filtering pe riod (acq_thf) 5.7.6.3.17 i and v chopper cont rol register (acq_cvcr (hi)) table 139. low power current threshold filtering period (acq_thf) offset (136) 0x72 access: user read / write 7 6 5 4 3 2 1 0 r thf[7:0] w reset 0 0 0 0 0 0 0 0 notes 136.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within th e global address space. table 140. low power current threshold filtering peri od (acq_thf) - register field descriptions field description 7-0 thf[7:0] low power current threshold wake up filtering period. see section 5.2.4.1.1, ?cyclic current acquisition / calibration temperature check" . table 141. i and v chopper control register (acq_cvcr (hi)) offset (137) 0x74 access: user write 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 w dbtm iircm pgafm reset 0 0 0 0 0 0 0 0 notes 137.offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space. table 142. i and v chopper control register (acq _cvcr (hi)) - register field descriptions field description 5-4 dbtm[1:0] hold time after chopper swap - mask 0 - writing the dbt bits will have no effect 1 - writing the dbt bits will be effective 3-1 iircm[2:0] iir low pass filter configuration - mask 0 - writing the iirc bits will have no effect 1 - writing the iirc bits will be effective 0 pgafm pga fast mode enable - mask 0 - writing the pgaf bit will have no effect 1 - writing the pgaf bit will be effective
mm912_637, rev. 3.0 freescale semiconductor 133 5.7.6.3.18 i and v chopper cont rol register (acq_cvcr (lo)) note during low power mode: 0x15; (00010101b) is recommend for acq_cvcr (dbt =01, iirc = 010, pgaf = 1) 5.7.6.3.19 low power curre nt threshold (acq_cth) table 143. i and v chopper control register (acq_cvcr (lo)) offset (138) 0x75 access: user write 7 6 5 4 3 2 1 0 r 0 0 dbt iirc pgaf w reset 0 0 0 0 1 1 1 1 notes 138.offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. table 144. i and v chopper control register (acq _cvcr (lo)) - register field descriptions field description 5-4 dbt[1:0] hold time after chopper swap 00 - hold after swap disabled 01 - 3 x 64 khz cycles hold time for the sinc3-l8 10 - 4 x 64 khz cycles hold time for the sinc3-l8 11 - 5 x 64 khz cycles hold time for the sinc3-l8 3-1 iirc[2:0] iir low pass filter coefficient ( ?? 000 - 1/8 001 - 1/16 010 - 1/32 011 - 1/64 100 - 1/128 101 - iir disabled 110 - iir disabled 111 - iir disabled 0 pgaf pga fast mode enable 0 - pga capacitor swap disabled (slow mode). 1 - pga capacitors swapped during chopper table 145. low power current threshold (acq_cth offset (139) 0x76 access: user read / write 7 6 5 4 3 2 1 0 r cth[7:0] w reset 0 0 0 0 0 0 0 0 notes 139.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within th e global address space. table 146. low power current threshold (acq _cth - register field descriptions field description 7-0 cth[7:0] low power current threshold see section 5.2.4.1.1.1, ?current threshold wake-up" for details.
mm912_637, rev. 3.0 freescale semiconductor 134 5.7.6.3.20 low power ah counter threshol d (acq_ahth1 (hi) / acq_ahth1 (lo) / acq_ahth0 (hi) / acq_ahth0 (lo)) 5.7.6.3.21 low power ah count er (acq_ahc1 (hi) / acq_ahc1 (lo) / acq_ahc0 (hi) / acq_ahc0 (lo)) table 147. low power ah counter threshold (acq_ahth1 (hi) / acq_ahth1 (lo) / acq_ahth0 (hi) / acq_ahth0 (lo)) offset (140) 0x78 / 0x79 / 0x7a / 0x7b access: user read / write 7 6 5 4 3 2 1 0 r 0 w r w ahth[30:0] r w r w reset 0 0 0 0 0 0 0 0 notes 140.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. table 148. low power ah counter threshold (acq_ahth1 (hi) / acq_ahth1 (lo) / acq_ahth0 (hi) / acq_ahth0 (lo)) - register field descriptions field description 30-0 ahth[30:0] low power ah counter threshold. absolute (unsigned) 31-bit in teger. reading one 16-bit part of the register will buffer the second. reading the second will unlock the buffer. see section 5.2.4.1.1.2, ?current ampere hour threshold wake-up" . for details on the register. table 149. low power ah counter (acq _ahc1 (hi) / acq_ahc1 (lo) / acq_ahc0 (hi) / acq_ahc0 (lo)) offset (141) 0x7c / 0x7d / 0x7e / 0x7f access: user read 7 6 5 4 3 2 1 0 r ahc[31:0] w r ahc[23:16] w r ahc[15:8] w r ahc[7:0] w notes 141.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within th e global address space.
mm912_637, rev. 3.0 freescale semiconductor 135 5.7.6.3.22 low pass filter co efficient ax (lpf_ax (hi)) 5.7.6.3.23 low pass filter co efficient ax (lpf_ax (lo)) table 150. low power ah counter (acq_ahc1 (hi) / acq_ahc1 (lo) / acq_ahc0 (hi) / acq_ahc0 (lo)) - register field descriptions field description 31-0 ahc[31:0] low power ah counter (32-bit signed integer, two?s complement). reading one 16-bit part of the register will buffer the second. reading the second will unlock the buffer. see section 5.2.4.1.1.2, ?current ampere hour threshold wake-up" . table 151. low pass filter coefficient ax (lpf_ax (hi)) offset (142) 0x80...0x9e access: user read/write 7 6 5 4 3 2 1 0 r ax[15:8] w reset see ta b l e 154 notes 142.offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space. table 152. low pass filter coefficient ax (lpf_ax (lo)) offset (143) 0x81...0x9f access: user read/write 7 6 5 4 3 2 1 0 r ax[7:0] w reset see table 154 notes 143.offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 153. low pass filter coefficient ax - register field descriptions field description 15-0 ax[15:0] low pass filter coefficient value. x = 0...15. da ta format: msb = sign (?1? minus). [14:0] integer. table 154. low pass filter coefficient ax - reset values field reset value field reset value a0 0x00f5 a8 0x1021 a1 0x0312 a9 0x0e35 a2 0x051f a10 0x0b44 a3 0x0852 a11 0x0852 a4 0x0b44 a12 0x051f a5 0x0e35 a13 0x0312 a6 0x1021 a14 0x00f5 a7 0x10e5 a15 0x0000
mm912_637, rev. 3.0 freescale semiconductor 136 5.7.6.3.24 compensation cont rol register (comp_ctl) table 155. compensation contro l register (comp_ctl) offset (144) (145) 0xa0 access: user read/write 15 14 13 12 11 10 9 8 r 0 0 0 0 0 0 0 0 w bgcalm pgazm pgaom diagvm diagim caliem reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r bgcal pgaz pgao diagv diagi 0 calie w reset 1 0 0 0 0 0 0 0 notes 144.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. 145.this register is 16-bit access only. table 156. compensation control register (com p_ctl) - register field descriptions field description 15-14 bgcalm calibration band gap select - mask 0 - writing the corresponding bgcal bits will have no effect 1 - writing the corresponding bgcal bits will be effective 13 pgazm pga input zero - mask 0 - writing the pgaz bit will have no effect 1 - writing the pgaz bit will be effective 12 pgaom pga offset calibration - mask 0 - writing the pgao bit will have no effect 1 - writing the pgao bit will be effective 11 diagvm diagnostic mode voltage channel - mask 0 - writing the diagv bit will have no effect 1 - writing the diagv bit will be effective 10 diagim diagnostic mode current channel - mask 0 - writing the diagi bit will have no effect 1 - writing the diagi bit will be effective 8 caliem calibration irq enable - mask 0 - writing the calie bit will have no effect 1 - writing the calie bit will be effective 7-6 bgcal calibration band gap select 00 - bandgap disconnected from calibration 01 - bg1 selected as calibration reference 10 - bg2 selected as calibration reference (default) 11 - bg3 selected as calibration reference 5 pgaz pga input zero 0 - programmable gain amplifier inputs in normal operation 1 - programmable gain amplifier inputs shorted for calibration 4 pgao pga offset calibration start 0 - pga normal operation 1 - pga internal offset calibration start (pgaof will indicate calibration complete). pgaz has to be set to 1 during calibratio n. the bit will remain set after the calibration is complete. it has to be cleared by writing 0 before it can be set to start the next calibration. the current measurement channel has to be enabled (acq_ctl[cmen]=1) in order to perform the pga offset compensation.
mm912_637, rev. 3.0 freescale semiconductor 137 5.7.6.3.25 compensation stat us register (comp_sr) 5.7.6.3.26 temperature fi ltering period (comp_tf) 3 diagv diagnostic mode voltage channel 0 - calibration reference disconnected from the voltage channel input 1 - calibration reference connected to the voltage channel input for calibration. man ual conversion needed to measure reference 2 diagi diagnostic mode current channel 0 - calibration reference disconnected from the current channel input 1 - calibration reference connected to the current channel input for calibration. manual conversion needed to measure reference 0 calie calibration irq enable 0 - calibration request interrupt disabled 1 - calibration request interrupt enabled. a temperature ?out of calibration range? will cause a calibration interrupt request table 157. compensation status register (comp_sr) offset (146) 0xa2 access: user read/write 7 6 5 4 3 2 1 0 r 0 bgrf 0 pgaof 0 0 0 calf w write 1 will clear the flags and w ill start next calibration steps reset 0 0 0 0 0 0 0 0 notes 146.offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. table 158. compensation status register (comp_sr) - register field descriptions field description 6 bgrf band gap reference status flag 0 - indicates the reference bandgap has not been set / applied 1 - reference bandgap has been set. writing 1 will clear the flag 4 pgaof pga internal offset compensation complete flag 0 - pga offset compensation ongoing or not started since last flag clear 1 - pga offset compensation finished since la st flag clear. writing 1 will clear the flag 0 calf calibration request status flag 0 - no temperature out of range condition detected 1 - temperature out of range condition detected. writing 1 will clear the flag table 159. temperature filtering period (comp_tf) offset (147) 0xa3 access: user read / write 7 6 5 4 3 2 1 0 r 0 0 0 0 0 tmf[2:0] w reset 0 0 0 0 0 0 0 0 notes 147.offset related to 0x0200 for blocki ng access and 0x300 for non blocking ac cess within the global address space. table 156. compensation control register (c omp_ctl) - register field descriptions field description
mm912_637, rev. 3.0 freescale semiconductor 138 5.7.6.3.27 max temp. before recalibration (comp_tmax) 5.7.6.3.28 min temp. before recalibration (comp_tmin) table 160. temperature filtering period (c omp_tf) - register field descriptions field description 2-0 tmf[2:0] recalibration temperature filtering period. defines the num ber of measurements above / below the max / min thresholds that are required before a calibration request is detected. table 161. max temp. before recalibration (comp_tmax) offset (148) (149) 0xa4 access: user read/write 15 14 13 12 11 10 9 8 r tcmax[15:8] w reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r tcmax[7:0] w reset 0 0 0 0 0 0 0 0 notes 148.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. 149.this register is 16 bit access only. table 162. max temp. before recalibration (com p_tmax) - register field descriptions field description 15-0 tcmax[15:0] maximum temperature before recalibration. once the internal te mperature measurement result is above or equal to tcmax, the tmf filter counter is increased, if below, the counter is decreased. table 163. min temp. before recalibration (comp_tmin) offset (150) (151) 0xa6 access: user read/write 15 14 13 12 11 10 9 8 r tcmin[15:8] w reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r tcmin[7:0] w reset 0 0 0 0 0 0 0 0 notes 150.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. 151.this register is 16-bit access only.
mm912_637, rev. 3.0 freescale semiconductor 139 5.7.6.3.29 offset voltag e compensation (comp_vo) 5.7.6.3.30 offset current co mpensation window (comp_io) table 164. min temp. before recalibration (com p_tmin) - register field descriptions field description 15-0 tcmin[15:0] minimum temperature before recalibration. once the internal te mperature measurement result is below tcmin, the tmf filter counter is increased, if above or equal, the counter is decreased. table 165. offset voltage compensation (comp_vo) offset (152) 0xaa access: user read/write 7 6 5 4 3 2 1 0 r voc[7:0] w reset 0 0 0 0 0 0 0 0 notes 152.offset related to 0x0200 for blocki ng access and 0x300 for non blocking a ccess within the global address space. table 166. offset voltage compensation (com p_vo) - register field descriptions field description 7-0 voc[7:0] voltage offset compensation buffer. this register contains t he voltage channel offset compensation as an 8-bit signed char (two complement). 0x7f = max, 0x80 =min. table 167. offset current compensation window (comp_io) offset (153) 0xab access: user read/write 7 6 5 4 3 2 1 0 r coc[7:0] w reset 0 0 0 0 0 0 0 0 notes 153.offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 168. offset current compensation window (comp_io) - register field descriptions field description 7-0 coc[7:0] current offset compensation buffer window for the 8 current compensation values stored. the content of the igain[2:0] register will determine the compensation buffer accessed through the coc[7:0] register. this register contains the current channel offset compensation as 8-bit signed char (two complement). 0x7f = max, 0x80 =min.
mm912_637, rev. 3.0 freescale semiconductor 140 5.7.6.3.31 gain voltage comp. v sense channel (comp_vsg) 5.7.6.3.32 8 x gain current compensati on 4...512 (comp_ig4... comp_ig512) table 169. gain voltage comp. v sense channel (comp_vsg) offset (154) (155) 0xac access: user read/write 15 14 13 12 11 10 9 8 r 0 0 0 0 0 0 vsgc[9:8] w reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r vsgc[7:0] w reset 0 0 0 0 0 0 0 0 notes 154.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. 155.this register is 16 bit access only. table 170. gain voltage comp. v sense channel (comp_vsg) - register field descriptions field description 9-0 vsgc[9:0] voltage channel gain compensation buffer. this register cont ains the voltage channel gain co mpensation as 10-bit special coded value. refer to section 5.7.3.4, ?compensation" for details. table 171. 8 x gain current compensation 4...512 (comp_ig4... comp_ig512) offset (156) (157) 0xb0... 0xbe access: user read/write 15 14 13 12 11 10 9 8 r 0 0 0 0 0 0 igc4...512 (hi) [9:8] w reset 0 0 0 0 0 0 1 0 7 6 5 4 3 2 1 0 r igc4...512 (lo) [7:0] w reset 0 0 0 0 0 0 0 0 notes 156.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. 157.this register is 16 bit access only.
mm912_637, rev. 3.0 freescale semiconductor 141 5.7.6.3.33 8 x offset pga compensation (comp_pgao4 ??? comp_pgao512) table 172. 8 x gain current compensation 4...512 (comp_ig4 ? comp_ig512) - register field descriptions field description 9-0 igc4[9:0] igc8[9:0] igc16[9:0] igc32[9:0] igc64[9:0] igc128[9:0] igc256[9:0] igc512[9:0] individual current gain compensation buffers for the 8 gain c onfigurations. those registers contain the current channel gain compensation as 10-bit special coded value. refer to section 5.7.3.4, ?compensation" for details. table 173. 8 x offset pga compensati on (comp_pgao4... comp_pgao512) offset (158) (159) 0xc0... 0xce access: user read/write 15 14 13 12 11 10 9 8 r 0 0 0 0 0 pgaoc4...512 (hi) [10:8] w reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r pgaoc4...512 (lo) [7:0] w reset 0 0 0 0 0 0 0 0 notes 158.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. 159.this register is 16 bit access only. table 174. 8 x offset pga compensation (comp_pgao4. ..comp_pgao512) - register field descriptions field description 10-0 pgaoc4[10:0] pgaoc8[10:0] pgaoc16[10:0] pgaoc32[10:0] pgaoc64[10:0] pgaoc128[10:0] pgaoc256[10:0] pgaoc512[10:0] individual pga offset compensation buffers for the 8 gain configurations. those regist ers contain the pga offset compensation as 11-bit special coded value. refer to section 5.7.3.4, ?compensation" for details.
mm912_637, rev. 3.0 freescale semiconductor 142 5.7.6.3.34 internal temp. o ffset compensation (comp_ito) 5.7.6.3.35 internal temp. ga in compensation (comp_itg) 5.7.6.3.36 external temp. of fset compensation (comp_eto) table 175. internal temp. offset compensation (comp_ito) offset (160) 0xd0 access: user read/write 7 6 5 4 3 2 1 0 r itoc[7:0] w reset 0 0 0 0 0 0 0 0 notes 160.offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space. table 176. internal temp. offset compensation (comp_ito) - register field descriptions field description 7-0 itoc[7:0] internal temperature offset compensation buffer. this register contains the internal temperature offset compensation as 8-bit signed char (two complement). refer to section 5.7.3.4, ?compensation" for details. table 177. internal temp. gain compensation (comp_itg) offset (161) 0xd1 access: user read/write 7 6 5 4 3 2 1 0 r itgc[7:0] w reset 1 0 0 0 0 0 0 0 notes 161.offset related to 0x0200 for blocking access and 0x3 00 for non blocking access wi thin the global address space. table 178. internal temp. gain compensation (c omp_itg) - register field descriptions field description 7-0 itgc[7:0] internal temperature gain compensation buffer. this register contains the internal temperat ure gain compensation as 8-bit special coded value. refer to section 5.7.3.4, ?compensation" for details. table 179. external temp. offset compensation (comp_eto) offset (162 ) 0xd2 access: user read/write 7 6 5 4 3 2 1 0 r etoc[7:0] w reset 0 0 0 0 0 0 0 0 notes 162.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space.
mm912_637, rev. 3.0 freescale semiconductor 143 5.7.6.3.37 external temp. ga in compensation (comp_etg) table 180. external temp. offset compensation (c omp_eto) - register field descriptions field description 7-0 etoc[7:0] external temperature offset compensation buffer. this register contains the external temper ature offset compensation as 8-bit signed char (two complement). refer to section 5.7.3.4, ?compensation" for details. table 181. external temp. gain compensation (comp_etg) offset (163) 0xd3 access: user read/write 7 6 5 4 3 2 1 0 r etgc[7:0] w reset 1 0 0 0 0 0 0 0 notes 163.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within th e global address space. table 182. external temp. gain compensation (c omp_etg) - register field descriptions field description 7-0 etgc[7:0] external temperature gain compensation buffer. this register contains the external temperature gain compensation as 8-bit special coded value. refer to section 5.7.3.4, ?compensation" for details.
window watchdog mm912_637, rev. 3.0 freescale semiconductor 144 5.8 window watchdog the mm912_637 analog die includes a configurable window watchdog which is active in normal mode. the watchdog module is based on the low power oscillator (lpclk) to operate independently from the mcu based d2dclk clock. the watchdog timeout (t wdto ) can be configured between 4.0 ms and 2048 ms using the watchdog control register (wd_ctl). note as the watchdog timing is based on the lpclk, its accuracy is based on the trimming applied to the trim_osc register. the given timeout values are typical values only. during low power mode, the watchdog feature is not active, a d2d read during stop mode will have the wdoff bit set. after wake-up and transition to normal mode, the watchdog is reset to the same state as when following a power-on-reset (por). to clear the watchdog counter, a alternat ing write has to be performed to the watchdog rearm register (wd_rr). the first write after the wake-up or reset_a has been released has to be 0xaa, the next one has to be 0x55. after the wake-up or r eset_a has been released, there will be a standard (non window) watchdog active with a fixed timeout of t iwdto (t wdto = b100 = 256 ms). the watchdog window open (wdwo) bit is set during that time. figure 39. mm912_637 analog die watchdog operation to change from the standard initial watchdog to the window watch dog, the initial counter reset has to be performed by writing 0xaa to the watchdog rearm register (wd_rr) before t iwdto is reached. note an immediate trimming of the low power oscillator after reset release assures t iwdto being at the maximum accuracy. if the t iwdto timeout is reached with no counter reset or a value differ ent from 0xaa written to the wd_rr, a watchdog reset will occur. once entering window watchdog mode, the first half of the time, t wdto is forbidden for a counter reset. to reset the watchdog counter, a alternating write of 0x55 and 0xaa has to be performed wit hin the second half of the t wdto . a window open (wdwo) flag will indicate the current status of the window. a timeout or wrong value written to the wd_rr will force a watchdog reset. if the first write to the wd_ctl register is 000 (wd off), the wd will be disabled (164) . if a different cycle ti me is written or the wd is refreshed with the default window (100) unchanged, no furt her ?000? write will be effective (a change of cycle time would still be possible). notes 164.the watchdog can be enabled any time later. window watch dog window closed window watch dog window open standard initial watch dog (no window) t iwdto wd register write = 0x55 initial wd reg. write = 0xaa reset_a release window watch dog window closed window watch dog window open t wdto / 2 t wdto / 2 window wd timing (t wdto ) t wd register write = 0xaa (to be continued) analog mcu
window watchdog mm912_637, rev. 3.0 freescale semiconductor 145 5.8.1 memory map and registers 5.8.1.1 overview this section provides a detailed descripti on of the memory map and registers. 5.8.1.2 module memory map the memory map for the watchdog module is given in ta b l e 183 5.8.1.3 register descriptions this section consists of regist er descriptions in address order. each description includes a standard register diagram with an associated figure number. details of register bits and fi eld function follow the register diagrams, in bit order. table 183. module memory map offset name 7 6 5 4 3 2 1 0 0x10 wd_ctl watchdog control register r 0 0 0 0 0 0 0 0 w wdtst m wdtom[2:0] r wdtst 0 0 0 0 wdto[2:0] w 0x12 wd_sr r 0 0 0 0 0 0 wdoff wdwo watchdog status register w 0x13 reserved r 0 0 0 0 0 0 0 0 w 0x14 wd_rr r wdr[7:0] watchdog rearm register w 0x15 reserved r 0 0 0 0 0 0 0 0 w 0x16 reserved r 0 0 0 0 0 0 0 0 w 0x17 reserved r 0 0 0 0 0 0 0 0 w notes 165.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. 166.register offset with the ?lo? address value not shown have to be accessed in 16-bit mode. 8- bit access will not function.
window watchdog mm912_637, rev. 3.0 freescale semiconductor 146 5.8.1.3.1 watchdog cont rol register (wd_ctl) 5.8.1.3.2 watchdog stat us register (wd_sr) table 184. watchdog control register (wd_ctl) offset (167) , (168) 0x10 access: user write 15 14 13 12 11 10 9 8 r 0 0 0 0 0 0 0 0 w wdtstm wdtom reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r wdtst 0 0 0 0 wdto w reset 1 0 0 0 0 1 0 0 notes 167.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. 168.this register is 16 bit access only. table 185. watchdog control register (wd_ ctl) - register field descriptions field description 15 wdtstm watchdog test - mask 0 - writing the wdtst bit will have no effect 1 - writing the wdtst bit will be effective 10-8 wdtom[2:0] watchdog timeout - mask 0 - writing the wdto bits will have no effect 1 - writing the wdto bits will be effective 7 wdtst watchdog test this bit is implemented for test purpos e and has no function in normal mode. 2-0 wdto[2:0] watchdog timeout configuration - configuring the watchdog timeout duration t wdto . 000 - watchdog off 001 - 4.0 ms 010 - 16.0 ms 011 - 64.0 ms 100 - 256 ms (default) 101 - 512 ms 110 - 1024 ms 111 - 2048 ms table 186. watchdog status register (wd_sr) offset (169) 0x12 access: user read 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 wdoff wdwo w notes 169.offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
window watchdog mm912_637, rev. 3.0 freescale semiconductor 147 5.8.1.3.3 watchdog rear m register (wd_rr) table 187. watchdog status register (wd_sr) - register field descriptions field description 1 wdoff watchdog status - indicating the wa tchdog module being enabled/disabled 1 - watchdog off 0 - watchdog active 0 wdwo watchdog window status 1 - open - indicating the watchdog window is currently open for counter reset. 0 - closed - indicating the watchdog window is currently closed for counter reset. resetting the watchdog with the window closed will cause a watchdog - reset. table 188. watchdog rearm register (wd_rr) offset (170) 0x14 access: user read/write 7 6 5 4 3 2 1 0 r wdr w reset 0 0 0 0 0 0 0 0 notes 170.offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 189. watchdog rearm register (wd_ rr) - register field descriptions field description 7-0 wdr[7:0] watchdog rearm register- writing this register with the corr ect value (0xaa alternating 0x55) while the window is open will reset the watchdog counter. writing the register while the watchdog is dis abled will have no effect.
basic timer module - tim (tim16b4c) mm912_637, rev. 3.0 freescale semiconductor 148 5.9 basic timer module - tim (tim16b4c) 5.9.1 introduction 5.9.1.1 overview the basic timer consists of a 16-bit, software-programmabl e counter driven by a seven stage programmable prescaler. this timer can be used for many purposes, including input wa veform measurements while simultaneously generating an output waveform. pulse widths can vary from microseconds to many seconds. this timer contains four complete input capture/output compare channels [ioc 3:0]. the input capt ure function is used to detect a selected transition edge and record the time. the output compar e function is used for generat ing output signals or for timer software delays. full access for the counter registers or the input capture/output compare registers should take place in a16-bit word access. accessing high bytes and low bytes separately for all of these regi sters may not yield the same resu lt as accessing them in one word. 5.9.1.2 features the tim16b4c includes these distinctive features: ? four input capture/output compare channels. ? clock prescaler ? 16-bit counter 5.9.1.3 modes of operation the tim16b4c is driven by the d2dclk / 4 during normal mode and the alfclk during low power mode. 5.9.1.4 block diagram figure 40. timer block diagram for more information on the respective functional descriptions see section 5.9.4, ?functional description" of this chapter. prescaler 16-bit counter ioc1 ioc0 ioc2 ioc3 timer overflow interrupt registers d2dclk / 4 or alfclk input capture output compare input capture output compare input capture output compare input capture output compare channel 0 channel 1 channel 2 channel 3 timer channel 0 interrupt timer channel 3 interrupt analog mcu
basic timer module - tim (tim16b4c) mm912_637, rev. 3.0 freescale semiconductor 149 5.9.2 signal description 5.9.2.1 overview the tim16b4c module can be used as regular time base, or c an be internally routed to the ptb and lin module. refer to the corresponding sections for further details, see section 5.11, ?lin" and section 5.10, ?general purpose i/o - gpio" . in addition, the tim16b4c module is used during low power mode to det ermine the cyclic wake-up and current measurement timing ( section 5.2, ?analog die - power, clock and resets - pcr" ) 5.9.2.2 detailed signal descriptions 5.9.2.2.1 ioc3 ? input capture and output compare channel 3 this pin serves as the input capt ure or output compare for channel 3. 5.9.2.2.2 ioc2 ? input capture and output compare channel 2 this pin serves as the input capt ure or output compare for channel 2. 5.9.2.2.3 ioc1 ? input capture and output compare channel 1 this pin serves as the input capt ure or output compare for channel 1. 5.9.2.2.4 ioc0 ? input capture and output compare channel 0 this pin serves as the input capt ure or output compare for channel 0. 5.9.3 memory map and registers 5.9.3.1 overview this section provides a detailed description of all memory and registers. 5.9.3.2 module memory map the memory map for the tim16b4c module is given in ta b l e 190 . table 190. module memory map offset name 7 6 5 4 3 2 1 0 0x20 tios r 0 0 0 0 ios3 ios2 ios1 ios0 timer input capture/output compare select w 0x21 (172) cforc r 0 0 0 0 0 0 0 0 timer compare force register w foc3 foc2 foc1 foc0 0x22 oc3m r 0 0 0 0 oc3m3 oc3m2 oc3m1 oc3m0 output compare 3 mask register w 0x23 oc3d r 0 0 0 0 oc3d3 oc3d2 oc3d1 oc3d0 output compare 3 data register w
basic timer module - tim (tim16b4c) mm912_637, rev. 3.0 freescale semiconductor 150 0x24 (173) tcnt (hi) r tcnt timer count register w 0x25 (173) tcnt (lo) r timer count register w 0x26 tscr1 r ten 0 0 tffca 0 0 0 0 timer system control register 1 w 0x27 ttov r 0 0 0 0 tov3 tov2 tov1 tov0 timer toggle overflow register w 0x28 tctl1 r om3 ol3 om2 ol2 om1 ol1 om0 ol0 timer control register 1 w 0x29 tctl2 r edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a timer control register 2 w 0x2a tie r 0 0 0 0 c3i c2i c1i c0i timer interrupt enable register w 0x2b tscr2 r toi 0 0 0 tcre pr2 pr1 pr0 timer system control register 2 w 0x2c tflg1 r 0 0 0 0 c3f c2f c1f c0f main timer interrupt flag 1 w 0x2d tflg2 r tof 0 0 0 0 0 0 0 main timer interrupt flag 2 w 0x2e (174) tc0 (hi) r tc0 timer input capture/output compare register 0 w 0x2f (174) tc0 (lo) r timer input capture/output compare register 0 w 0x30 (174) tc1 (hi) r tc1 timer input capture/output compare register 1 w 0x31 (174) tc1 (lo) r timer input capture/output compare register 1 w 0x32 (174) tc2 (hi) r tc2 timer input capture/output compare register 2 w 0x33 (174) tc2 (lo) r timer input capture/output compare register 2 w 0x34 (174) tc3 (hi) r tc3 timer input capture/output compare register 3 w 0x35 (174) tc3 (lo) r timer input capture/output compare register 3 w table 190. module memory map offset name 76543210
basic timer module - tim (tim16b4c) mm912_637, rev. 3.0 freescale semiconductor 151 5.9.3.3 register descriptions this section consists of regist er descriptions in address order. each description includes a standard register diagram with an associated figure number. details of register bit and fi eld function follow the register diagrams, in bit order. 5.9.3.3.1 timer input capture /output compare select (tios) 5.9.3.3.2 timer compare force register (cforc) 0x36 (173) timtst r 0 0 0 0 0 0 tcbyp 0 timer test register w notes 171.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within th e global address space. 172.always reads $00. 173.only writable in special modes. (refer to the soc guide for different modes). 174.a write to these registers has no m eaning or effect during input capture. table 191. timer input capture/output compare select (tios) offset (175) 0x20 access: user read/write 7 6 5 4 3 2 1 0 r 0 0 0 0 ios3 ios2 ios1 ios0 w reset 0 0 0 0 0 0 0 0 notes 175.offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. table 192. tios - register field descriptions field description 3-0 ios[3-0] input capture or output compare channel configuration 0 - the corresponding channel ac ts as an input capture. 1 - the corresponding channel acts as an output compare. table 193. timer compare force register (cforc) offset (176) 0x21 access: user write 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 w foc3 foc2 foc1 foc0 reset 0 0 0 0 0 0 0 0 notes 176.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. table 194. cforc - register field descriptions field description 3-0 foc[3-0] force output compare action for channel 3-0 0 - force output compare action disabled. input c apture or output compare channel configuration 1 - force output compare action enabled table 190. module memory map offset name 76543210
basic timer module - tim (tim16b4c) mm912_637, rev. 3.0 freescale semiconductor 152 a write to this register with the corresponding (foc 3:0) data bit(s) set causes the action pr ogrammed for output compare on channel ?n? to occur immediately.the action taken is the same as if a successful comparison ha d just taken place with the tcn register, except the interr upt flag does not get set. note a successful channel 3 output compare overrides any channel 2:0 compare. if a forced output compare on any channel occurs at the sa me time as the successful output compare, then a forced output compare action will take pr ecedence and the interrupt flag will not get set. 5.9.3.3.3 output compare 3 mask register (oc3m) setting the oc3mn (n ranges from 0 to 2) will set the correspondi ng port to be an output port when the corresponding tiosn (n ranges from 0 to 2) bit is set to be an output compare. note a successful channel 3 output compare ov errides any channel 2:0 compares. for each oc3m bit that is set, the output compare action reflects the corresponding oc3d bit. 5.9.3.3.4 output compare 3 data register (oc3d) table 195. output compare 3 mask register (oc3m) offset (177) 0x22 access: user read/write 7 6 5 4 3 2 1 0 r 0 0 0 0 oc3m3 oc3m2 oc3m1 oc3m0 w reset 0 0 0 0 0 0 0 0 notes 177.offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 196. oc3m - register field descriptions field description 3-0 oc3m[3-0] output compare 3 mask ?n? channel bit 0 - does not set the corresponding port to be an output port 1 - sets the corresponding port to be an output port when th is corresponding tios bit is set to be an output compare table 197. output compare 3 data register (oc3d) offset (178) 0x23 access: user read/write 7 6 5 4 3 2 1 0 r 0 0 0 0 oc3d3 oc3d2 oc3d1 oc3d0 w reset 0 0 0 0 0 0 0 0 notes 178.offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space.
basic timer module - tim (tim16b4c) mm912_637, rev. 3.0 freescale semiconductor 153 note a channel 3 output compare will cause bits in th e output compare 3 data register to transfer to the timer port data register if the corresp onding output compare 3 mask register bits are set. 5.9.3.3.5 timer count register (tcnt) note the 16-bit main timer is an up counter. full a ccess to the counter register should take place in one clock cycle. a separate read/write for high bytes and low bytes will give a different result than accessing them as a word. the period of the first count after a write to the tcnt registers may be a different length, because th e write is not synchronized with the prescaler clock. table 198. oc3d - register field descriptions field description 3 oc3d3 output compare 3 data for channel 3 2 oc3d2 output compare 3 data for channel 2 1 oc3d1 output compare 3 data for channel 1 0 oc3d0 output compare 3 data for channel 0 table 199. timer count register (tcnt) offset (179) 0x24, 0x25 access: user read (anytime)/write (special mode) 15 14 13 12 11 10 9 8 r tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 tcnt9 tcnt8 w reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r tcnt7 tcnt6 tcnt5 tcnt4 tcnt3 tcnt2 tcnt1 tcnt0 w reset 0 0 0 0 0 0 0 0 notes 179.offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. table 200. tcnt - register field descriptions field description 15-0 tcnt[15-0] 16-bit timer count register
basic timer module - tim (tim16b4c) mm912_637, rev. 3.0 freescale semiconductor 154 5.9.3.3.6 timer system c ontrol register 1 (tscr1) 5.9.3.3.7 timer toggle on overflow register 1 (ttov) note tovn toggles the output compare pin on over flow. this feature only takes effect when the corresponding channel is configured for an output compare mode. wh en set, an overflow toggle on the output compare pin takes prece dence over forced output compare events. table 201. timer system control register 1 (tscr1) offset (180) 0x26 access: user read/write 7 6 5 4 3 2 1 0 r ten 0 0 tffca 0 0 0 0 w reset 0 0 0 0 0 0 0 0 notes 180.offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space. table 202. tscr1 - register field descriptions field description 7 ten timer enable 1 = enables the timer. 0 = disables the timer. (used for reducing power consumption). 4 tffca timer fast flag clear all 1 = for tflg1 register, a read from an input capture or a write to the output compare channel [tc 3:0] causes the corresponding channel flag, cnf, to be cleared. for tflg2 register, any access to t he tcnt register clears the tof flag. this has the advantage of eliminating software overhead in a separate clear sequence. extra care is required to avoid accidental flag clearing d ue to unintended accesses. 0 = allows the timer flag clearing. table 203. timer toggle on overflow register 1 (ttov) offset (181) 0x27 access: user read/write 7 6 5 4 3 2 1 0 r 0 0 0 0 tov3 tov2 tov1 tov0 w reset 0 0 0 0 0 0 0 0 notes 181.offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. table 204. ttov - register field descriptions field description 3-0 tov[3-0] toggle on overflow bits 1 = toggle output compare pin on overflow feature enabled. 0 = toggle output compare pin on overflow feature disabled.
basic timer module - tim (tim16b4c) mm912_637, rev. 3.0 freescale semiconductor 155 5.9.3.3.8 timer control register 1 (tctl1) note these four pairs of control bits are encoded to specify the output action to be taken as a result of a successful output compare on ?n ? channel. when either omn or oln, the pin associated with the corresponding channel becomes an output tied to its ioc. to enable output action by the omn and oln bits on a ti mer port, the corresponding bit in oc3m should be cleared. 5.9.3.3.9 timer control register 2 (tctl2) table 205. timer control register 1 (tctl1) offset (182) 0x28 access: user read/write 7 6 5 4 3 2 1 0 r om3 ol3 om2 ol2 om1 ol1 om0 ol0 w reset 0 0 0 0 0 0 0 0 notes 182.offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. table 206. tctl1 - register field descriptions field description 7,5,3,1 omn output mode bit 6,4,2,0 oln output level bit table 207. compare result output action omn oln action 0 0 timer disconnected from output pin logic 0 1 toggle ocn output line 1 0 clear ocn output line to zero 1 1 set ocn output line to one table 208. timer control register 2 (tctl2) offset (183) 0x29 access: user read/write 7 6 5 4 3 2 1 0 r edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a w reset 0 0 0 0 0 0 0 0 notes 183.offset related to 0x0200 for blocki ng access and 0x300 for non blocking ac cess within the global address space. table 209. tctl2 - register field descriptions field description edgnb,edgn a input capture edge control
basic timer module - tim (tim16b4c) mm912_637, rev. 3.0 freescale semiconductor 156 these four pairs of control bits configur e the input capture edge detector circuits. 5.9.3.3.10 timer interrupt enable register (tie) 5.9.3.3.11 timer system c ontrol register 2 (tscr2) table 210. edge detector circuit configuration edgnb edgna configuration 0 0 capture disabled 0 1 capture on rising edges only 1 0 capture on falling edges only 1 1 capture on any edge (rising or falling) table 211. timer interrupt enable register (tie) offset (184) 0x2a access: user read/write 7 6 5 4 3 2 1 0 r 0 0 0 0 c3i c2i c1i c0i w reset 0 0 0 0 0 0 0 0 notes 184.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within t he global address space. table 212. tie - register field descriptions field description 3-0 c[3-0]i input capture/output compare interrupt enable. 1 = enables corresponding interrupt flag (cnf of tflg1 register) to cause a hardware interrupt 0 = disables corresponding interrupt flag (cnf of tflg1 register) from causing a hardware interrupt table 213. timer system control register 2 (tscr2) offset (185) 0x2b access: user read/write 7 6 5 4 3 2 1 0 r toi 0 0 0 tcre pr2 pr1 pr0 w reset 0 0 0 0 0 0 0 0 notes 185.offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space. table 214. tie - register field descriptions field description 7 toi timer overflow interrupt enable 1 = hardware interrupt requested when tof flag set in tflg2 register. 0 = hardware interrupt request inhibited. 3 tcre tcre ? timer counter reset enable 1 = enables timer counter reset by a su ccessful output compare on channel 3 0 = inhibits timer counter reset and counter continues to run. 3-0 pr[2:0] timer prescaler select these three bits select the frequency of the timer pre scaler clock derived from the bus clock as shown in table 215 .
basic timer module - tim (tim16b4c) mm912_637, rev. 3.0 freescale semiconductor 157 note this mode of operation is similar to an up-counting modulus counter. if register tc3 = $0000 and tcre = 1, the ti mer counter register (tcnt) will stay at $0000 continuously. if register tc3 = $ffff and tcre = 1, tof will not be set when the timer counter register (tcnt) is reset from $ffff to $0000. the newly selected prescale factor will not take effect until the next synchronized edge, where all prescale counter stages equal zero. 5.9.3.3.12 main timer interrupt flag 1 (tflg1) note these flags are set when an input capture or output compare event occurs. flag set on a particular channel is cleared by writing a one to that corresponding cnf bit. writing a zero to cnf bit has no effect on its status. when tffca bit in tscr register is set, a read from an input capture or a write into an output compare channel will cause the corresponding channel flag cnf to be cleared. table 215. timer clock selection pr2 pr1 pr0 timer clock (186) 0 0 0 timerclk / 1 0 0 1 timerclk / 2 0 1 0 timerclk / 4 0 1 1 timerclk / 8 1 0 0 timerclk / 16 1 0 1 timerclk / 32 1 1 0 timerclk / 64 1 1 1 timerclk / 128 notes 186.timerclk = d2dclk/4 or alfclk table 216. main timer inte rrupt flag 1 (tflg1) offset (187) 0x2c access: user read/write 7 6 5 4 3 2 1 0 r 0 0 0 0 c3f c2f c1f c0f w reset 0 0 0 0 0 0 0 0 notes 187.offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 217. tflg1 - register field descriptions field description 3-0 c[3:0]f input capture/output compare channel flag. 1 = input capture or output compare event occurred 0 = no event (input capture or output compare event) occurred.
basic timer module - tim (tim16b4c) mm912_637, rev. 3.0 freescale semiconductor 158 5.9.3.3.13 main timer interrupt flag 2 (tflg2) note the tflg2 register indicates when an interrup t has occurred. writing a one to the tof bit will clear it. any access to tcnt will clear tof bit of tflg2 register if the tffca bit in tscr register is set. 5.9.3.3.14 timer input capture/outp ut compare regist ers (tc3 - tc0) table 218. main timer inte rrupt flag 2 (tflg2) offset (188) 0x2d access: user read/write 7 6 5 4 3 2 1 0 r tof 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 notes 188.offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space. table 219. tflg2 - register field descriptions field description 7 tof timer overflow flag 1 = indicates that an interrupt has occurred (set when 16-b it free-running timer counter overflows from $ffff to $0000) 0 = flag indicates an interrupt has not occurred. table 220. timer input capture/output compare register 0 (tc0) offset (189) 0x2e, 0x2f access: user read/write 15 14 13 12 11 10 9 8 r tc0_15 tc0_14 tc0_13 tc0_12 tc0_11 tc0_10 tc0_9 tc0_8 w reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r tc0_7 tc0_6 tc0_5 tc0_4 tc0_3 tc0_2 tc0_1 tc0_0 w reset 0 0 0 0 0 0 0 0 notes 189.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within th e global address space.
basic timer module - tim (tim16b4c) mm912_637, rev. 3.0 freescale semiconductor 159 table 221. timer input capture/output compare register 1(tc1) offset (190) 0x30, 0x31 access: user read/write 15 14 13 12 11 10 9 8 r tc1_15 tc1_14 tc1_13 tc1_12 tc1_11 tc1_10 tc1_9 tc1_8 w reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r tc1_7 tc1_6 tc1_5 tc1_4 tc1_3 tc1_2 tc1_1 tc1_0 w reset 0 0 0 0 0 0 0 0 notes 190.offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 222. timer input capture/output compare register 2(tc2) offset (191) 0x32, 0x33 access: user read/write 15 14 13 12 11 10 9 8 r tc2_15 tc2_14 tc2_13 tc2_12 tc2_11 tc2_10 tc2_9 tc2_8 w reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r tc2_7 tc2_6 tc2_5 tc2_4 tc2_3 tc2_2 tc2_1 tc2_0 w reset 0 0 0 0 0 0 0 0 notes 191.offset related to 0x0200 for blocki ng access and 0x300 for non blocking a ccess within the global address space. table 223. timer input capture/output compare register 3(tc3) offset (192) 0x34, 0x35 access: user read/write 15 14 13 12 11 10 9 8 r tc3_15 tc3_14 tc3_13 tc3_12 tc3_11 tc3_10 tc3_9 tc3_8 w reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r tc3_7 tc3_6 tc3_5 tc3_4 tc3_3 tc3_2 tc3_1 tc3_0 w reset 0 0 0 0 0 0 0 0 notes 192.offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 224. tcn - register field descriptions field description 15-0 tcn[15-0] 16 timer input capture/output compare registers
basic timer module - tim (tim16b4c) mm912_637, rev. 3.0 freescale semiconductor 160 note tread anytime. write anytime for output compar e function. writes to these registers have no effect during input capture. depending on the tios bit for the corresponding channel, these registers are used to latch the value of the free-running counter wh en a defined transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare. read/write access in byte mode for high byte should takes place before low byte otherwise it will give a different result. 5.9.4 functional description 5.9.4.1 general this section provides a complete functional description of the timer tim16b4c block. refer to the detailed timer block diagram in figure 41 as necessary. figure 41. detailed timer block diagram prescaler channel 0 ioc0 pin 16-bit counter logic pr[2:1:0] tc0 16-bit comparator tcnt(hi):tcnt(lo) interrupt logic tof toi c0f edge detect cxf channel3 tc3 16-bit comparator c3f ioc3 pin logic edge detect om:ol0 tov0 om:ol3 tov3 edg3a edg3b edg0b tcre clear counter cxi ch.3 compare ch.3 capture ioc0 pin ioc3 pin te ch. 0 compare ch. 0 capture edg0a channel 3 output compare ioc0 ioc3 d2d clock / 4 or alfclk tof c0f c3f
mm912_637, rev. 3.0 freescale semiconductor 161 5.9.4.2 prescaler the prescaler divides the bus clock by 1, 2, 4, 8,16, 32, 64, or 128. the prescaler select bits, pr[2:0], select the prescaler divisor. pr[2:0] are in the timer system control register 2 (tscr2). 5.9.4.3 input capture clearing the i/o (input/output) select bit, iosn, configures channel n as an input capture channel. the input capture function captures the time at which an external event occurs. when an ac tive edge occurs on the pin of an input capture channel, the timer transfers the value in the timer count er into the timer channel registers, tcn. the minimum pulse width for the input captur e input is greater than two bus clocks. an input captur e on channel n sets the cnf flag. the cni bit enables the cnf flag to generate interrupt requests. 5.9.4.4 output compare setting the i/o select bit, iosn, configures channel n as an output compare channel. the output compare function can generate a periodic pulse with a programmable polarity, duration, and fre quency. when the timer counter reaches the value in the channel registers of an output compare channel, the timer can set, clear, or toggle the channel pin. an output compare on channel n set s the cnf flag. the cni bit enables the cnf flag to generate interrupt requests. the output mode and level bits, omn and oln, select set, clear, toggle on output compare. clearing both omn and oln disconnects the pin from the output logic. setting a force output compare bit, focn, causes an output compare on channel n. a forced output compare does not set the channel flag. a successful output compare on channel 3 overrides output comp ares on all other output comp are channels. the output compare 3 mask register masks the bits in the output compare 3 data regi ster. the timer counter reset ena ble bit, tcre, enables channel 3 output compares to reset the timer counter.writing to the time r port bit of an output compare pin does not affect the pin sta te. the value written is stored in an internal latch. when the pin becomes available for general-purpose output, the last value wri tten to the bit appears at the pin. 5.9.5 resets 5.9.5.1 general the reset state of each individual bit is listed within the register description section 5.9.3, ?memory map and registers" , which details the registers and their bit-fields. 5.9.6 interrupts 5.9.6.1 general this section describes interrupts or iginated by the tim16b4c block. ta b l e 225 lists the interrupts generated by the tim16b4c to communicate with the mcu. 5.9.6.2 description of interrupt operation the tim16b4c uses a total of 5 interrupt vectors. the interrupt vector offsets and interrupt numbers are chip dependent. more information on interrupt vector offsets and interrupt numbers can be found in section 5.3, ?interrupt module - irq" . table 225. tim16b4c interrupts interrupt offset vector priority source description c[3:0]f - - - timer channel 3-0 active high timer channel interrupts 3-0 tof - - - timer overflow timer overflow interrupt
mm912_637, rev. 3.0 freescale semiconductor 162 channel [3:0] interrupt these active high outputs is asserted by the module to request a timer channel 3 ? 0 interrupt following an input capture or ou tput compare event on these channels [3-0]. for the interrupt to be asserted on a specific channel, the enable, cni bit of tie regis ter should be set. these in terrupts are serviced by the system controller. 5.9.6.2.1 timer overfl ow interrupt (tof) this active high output will be asserted by the module to req uest a timer overflow interrupt, following the timer counter overf low when the overflow enable bit (toi) bit of tflg2 register is set. th is interrupt is serviced by the system controller.
general purpose i/o - gpio mm912_637, rev. 3.0 freescale semiconductor 163 5.10 general purpose i/o - gpio 5.10.1 introduction the 3 general purpose i/os (ptb0...2) are multipurpose ports, making internal signals available externally and providing digita l inputs. l0 (ptb3) offers an additional wake-up on rising edge during low power mode. additional routing options allow connections to the lin, timer, and sci module. 5.10.2 features ? internal clamping structure to operate as high voltage input (ptb3/l0 only). ?5.0 v (vddx) digital port input/output (ptb3/l0 only as input) ? selectable internal pull-up (ptb3/l0 pull-down) resistor ? selectable wake-up input during low power mode (ptb3/l0 - rising edge only). ? selectable timer channel input / output ? selectable connection to lin / sci 5.10.3 block diagram figure 42. general purpose i/o - block diagram ptb3 / l0 ptbx puex vddx dirx (m) =1 linrx scitx tcomp3..0 wkup ptbxx lintx scirx tcap3..0 pdx ptb0..ptb2 (x = 2..0) lin timer3..0 sci internal wake-up rx tx rx tx ic oc ptwu tcap3..0 pd3 pde3 1 0 wake-up detection pe3 pex z z analog mcu
general purpose i/o - gpio mm912_637, rev. 3.0 freescale semiconductor 164 5.10.4 high voltage wake-up input - ptb3 / l0 to offer robust high voltage wake-up capabilities, the following structure is implemented for ptb3/l0. figure 43. l0 / ptb3 input structure (typical values indicated) note due the different implementation of the l0/pt b3, the ptwu bit needs to be set in the gpio_in3 register, to read the por t status pd3 during normal mode. 5.10.4.1 modes of operation the full gpio functionality is only available during normal mode. the only features in available in both low power modes is the ptb3/l0 external wake-up and the wake-up routing of the timer output compare. note tcomp3...0 needs to be configured to allow timer output compare interrupts to generate a system wake-up. 5.10.5 memory map and registers 5.10.5.1 overview this section provides a detailed descripti on of the memory map and registers. 5.10.5.2 module memory map the memory map for the gpio module is given in ta b l e 226 esd 47k 1k 47n 6v clamp 2k 100k 1p external components esd / clamp input buffer
general purpose i/o - gpio mm912_637, rev. 3.0 freescale semiconductor 165 table 226. module memory map offset (193) , (194) name 7 6 5 4 3 2 1 0 0x40 gpio_ctl gpio control register r 0 0 0 0 0 0 0 0 w dir2m dir1m dir0m pe3m pe2m pe1m pe0m r 0 dir2 dir1 dir0 pe3 pe2 pe1 pe0 w 0x42 gpio_puc r 0 0 0 0 pde3 pue2 pue1 pue0 gpio pull up configuration w 0x43 gpio_data r 0 0 0 0 pd3 pd2 pd1 pd0 gpio port data register w 0x44 gpio_in0 r 0 tcap3 tcap2 tcap1 tcap0 scirx lintx 0 port 0 input configuration w 0x45 gpio_out0 r wkup tcomp3 tcomp2 tcomp1 tcomp0 scitx linrx 0 port 0 output configuration w ptbx0 0x46 gpio_in1 r 0 tcap3 tcap2 tcap1 tcap0 scirx lintx 0 port 1 input configuration w 0x47 gpio_out1 r wkup tcomp3 tcomp2 tcomp1 tcomp0 scitx linrx 0 port 1 output configuration w ptbx1 0x48 gpio_in2 r 0 tcap3 tcap2 tcap1 tcap0 scirx lintx 0 port 2 input configuration w 0x49 gpio_out2 r wkup tcomp3 tcomp2 tcomp1 tcomp0 scitx linrx 0 port 2 output configuration w ptbx2 0x4a gpio_in3 r ptwu ptwu tcap3 tcap2 tcap1 tcap0 0 0 port 3 input configuration w 0x4b reserved r 0 0 0 0 0 0 0 0 w 0x4c reserved r 0 0 0 0 0 0 0 0 w 0x4d reserved r 0 0 0 0 0 0 0 0 w 0x4e reserved r 0 0 0 0 0 0 0 0 w 0x4f reserved r 0 0 0 0 0 0 0 0 w notes 193.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within th e global address space. 194.register offset with the ?lo? address value not shown have to be accessed in 16-bit mode. 8- bit access will not function.
general purpose i/o - gpio mm912_637, rev. 3.0 freescale semiconductor 166 5.10.5.3 register descriptions 5.10.5.3.1 gpio control register (gpio_ctl) table 227. gpio control register (gpio_ctl) offset (195) , (196) 0x40 access: user read/write 15 14 13 12 11 10 9 8 r 0 0 0 0 0 0 0 0 w dir2m dir1m dir0m pe3m pe2m pe1m pe0m reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r 0 dir2 dir1 dir0 pe3 pe2 pe1 pe0 w reset 0 0 0 0 0 0 0 0 notes 195.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. 196.those registers are 16-bit access only. table 228. gpio control register (gpio_ctl) field description 14 dir2m data direction ptb2 - mask 0 - writing the dir2 bit will have no effect 1 - writing the dir2 bit will be effective 13 dir1m data direction ptb1 - mask 0 - writing the dir1 bit will have no effect 1 - writing the dir1 bit will be effective 12 dir0m data direction ptb0 - mask 0 - writing the dir0 bit will have no effect 1 - writing the dir0 bit will be effective 11 pe3m port 3 enable - mask 0 - writing the pe3 bit will have no effect 1 - writing the pe3 bit will be effective 10 pe2m port 2 enable - mask 0 - writing the pe2 bit will have no effect 1 - writing the pe2 bit will be effective 9 pe1m port 1 enable - mask 0 - writing the pe1 bit will have no effect 1 - writing the pe1 bit will be effective 8 pe0m port 0 enable - mask 0 - writing the pe0 bit will have no effect 1 - writing the pe0 bit will be effective 6 dir2 data direction ptb2 0 - ptb2 configured as input 1 - ptb2 configured as output 5 dir1 data direction ptb1 0 - ptb1 configured as input 1 - ptb1 configured as output 4 dir0 data direction ptb0 0 - ptb0 configured as input 1 - ptb0 configured as output
general purpose i/o - gpio mm912_637, rev. 3.0 freescale semiconductor 167 5.10.5.3.2 gpio pull-up c onfiguration (gpio_puc) 3 pe3 port 3 enable (197) 0 - ptb3 disabled (z state) 1 - ptb3 enabled (i) 2 pe2 port 2 enable (197) 0 - ptb2 disabled (z state) 1 - ptb2 enabled (i/o) 1 pe1 port 1 enable (197) 0 - ptb1 disabled (z state) 1 - ptb1 enabled (i/o) 0 pe0 port 0 enable (197) 0 - ptb0 disabled (z state) 1 - ptb0 enabled (i/o) notes 197.the port logic is always enabled. setting pex will connect the logic to the port i/o buffers. table 229. gpio pull-up configuration (gpio_puc) offset (198) 0x42 access: user read/write 7 6 5 4 3 2 1 0 r 0 0 0 0 pde3 pue2 pue1 pue0 w reset 0 0 0 0 0 0 0 0 notes 198.offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 230. gpio pull-up configuration (gpio_puc) field description 3 pde3 ptb3 pull-down enable 0 - ptb3 pull-down disabled 1 - ptb3 pull-down enabled 2 pue2 ptb2 pull-up enable 0 - ptb2 pull-up disabled 1 - ptb2 pull-up enabled 1 pue1 ptb1 pull-up enable 0 - ptb1 pull-up disabled 1 - ptb1 pull-up enabled 0 pue0 ptb0 pull-up enable 0 - ptb0 pull-up disabled 1 - ptb0 pull-up enabled table 228. gpio control register (gpio_ctl) field description
general purpose i/o - gpio mm912_637, rev. 3.0 freescale semiconductor 168 5.10.5.3.3 gpio port data register (gpio_data) 5.10.5.3.4 port 0 input co nfiguration (gpio_in0) table 231. gpio port data register (gpio_data) offset (199) 0x43 access: user read 7 6 5 4 3 2 1 0 r 0 0 0 0 pd3 (200) pd2 pd1 pd0 w notes 199.offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. 200.due the different implementation of the l0/ptb3, ptwu needs to be set in the gpio_in3 to read the pd3 port status during no rmal mode. table 232. gpio port data register (gpio_data) field description 3 pd3 ptb3 data register a read returns the value of the ptb3 buffer. 2 pd2 ptb2 data register a read returns the value of the ptb2 buffer. 1 pd1 ptb1 data register a read returns the value of the ptb1 buffer. 0 pd0 ptb0 data register a read returns the value of the ptb0 buffer. table 233. port 0 input configuration (gpio_in0) offset (201) 0x44 access: user read/write 7 6 5 4 3 2 1 0 r 0 tcap3 tcap2 tcap1 tcap0 scirx lintx 0 w reset 0 0 0 0 0 0 0 0 notes 201.offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space. table 234. port 0 input conf iguration (gpio_in0) field description 6 tcap3 ptb0 - timer input capture channel 3 0 - ptb0 input buffer disconnected from timer channel 3 - input capture 1 - ptb0 input buffer routed to timer channel 3 - input capture 5 tcap2 ptb0 - timer input capture channel 2 0 - ptb0 input buffer disconnected from timer channel 2 - input capture 1 - ptb0 input buffer routed to timer channel 2 - input capture 4 tcap1 ptb0 - timer input capture channel 1 0 - ptb0 input buffer disconnected from timer channel 1 - input capture 1 - ptb0 input buffer routed to timer channel 1 - input capture 3 tcap0 ptb0 - timer input capture channel 0 0 - ptb0 input buffer disconnected from timer channel 0 - input capture 1 - ptb0 input buffer routed to timer channel 0 - input capture
general purpose i/o - gpio mm912_637, rev. 3.0 freescale semiconductor 169 5.10.5.3.5 port 0 output co nfiguration (gpio_out0) 2 scirx ptb0 - sci module rx input 0 - ptb0 input buffer disconnected from sci module rx input 1 - ptb0 input buffer routed to sci module rx input 1 lintx ptb0 - lin module tx input 0 - ptb0 input buffer disconnected from lin module tx input 1 - ptb0 input buffer routed to lin module tx input table 235. port 0 output configuration (gpio_out0) offset (202) 0x45 access: user read/write 7 6 5 4 3 2 1 0 r wkup tcomp3 tcomp2 tcomp1 tcomp0 scitx linrx 0 w ptbx0 reset 0 0 0 0 0 0 0 0 notes 202.offset related to 0x0200 for blocking access and 0x30 0 for non blocking access within the global address space. table 236. port 0 output configuration (gpio_out0) field description 7 wkup ptb0 - wake-up output 0 - internal wake-up signal disconnected from ptb0 output buffer or gate 1 - internal wake-up signal connected to ptb0 output buffer or gate 6 tcomp3 ptb0 - timer channel 3 - output compare output 0 - timer channel 3 - output compare disconnected from ptb0 output buffer or gate 1 - timer channel 3 - output compare connected to ptb0 output buffer or gate 5 tcomp2 ptb0 - timer channel 2 - output compare output 0 - timer channel 2 - output compare disconnected from ptb0 output buffer or gate 1 - timer channel 2 - output compare connected to ptb0 output buffer or gate 4 tcomp1 ptb0 - timer channel 1 - output compare output 0 - timer channel 1 - output compare disconnected from ptb0 output buffer or gate 1 - timer channel 1 - output compare connected to ptb0 output buffer or gate 3 tcomp0 ptb0 - timer channel 0 - output compare output 0 - timer channel 0 - output compare disconnected from ptb0 output buffer or gate 1 - timer channel 0 - output compare connected to ptb0 output buffer or gate 2 scitx ptb0 - sci tx output 0 - sci tx output disconnected from ptb0 output buffer or gate 1 - sci tx output connected to ptb0 output buffer or gate 1 linrx ptb0 - lin rx output 0 - lin rx output disconnected from ptb0 output buffer or gate 1 - lin rx output connected to ptb0 output buffer or gate 0 ptbx0 ptb0 - output buffer control 0 - ptb0 output buffer or gate input = 0 1 - ptb0 output buffer or gate input = 1 table 234. port 0 input configuration (gpio_in0) field description
general purpose i/o - gpio mm912_637, rev. 3.0 freescale semiconductor 170 5.10.5.3.6 port 1 input co nfiguration (gpio_in1) 5.10.5.3.7 port 1 output c onfiguration (gpio_out1) table 237. port 1 input configuration (gpio_in1) offset (203) 0x46 access: user read/write 7 6 5 4 3 2 1 0 r 0 tcap3 tcap2 tcap1 tcap0 scirx lintx w reset 0 0 0 0 0 0 0 0 notes 203.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. table 238. port 1 input configuration (gpio_in1) field description 6 tcap3 ptb1 - timer input capture channel 3 0 - ptb1 input buffer disconnected from timer channel 3 - input capture 1 - ptb1 input buffer routed to timer channel 3 - input capture 5 tcap2 ptb1 - timer input capture channel 2 0 - ptb1 input buffer disconnected from timer channel 2 - input capture 1 - ptb1 input buffer routed to timer channel 2 - input capture 4 tcap1 ptb1 - timer input capture channel 1 0 - ptb1 input buffer disconnected from timer channel 1 - input capture 1 - ptb1 input buffer routed to timer channel 1 - input capture 3 tcap0 ptb1 - timer input capture channel 0 0 - ptb1 input buffer disconnected from timer channel 0 - input capture 1 - ptb1 input buffer routed to timer channel 0 - input capture 2 scirx ptb1 - sci module rx input 0 - ptb1 input buffer disconnected from sci module rx input 1 - ptb1 input buffer routed to sci module rx input 1 lintx ptb1 - lin module tx input 0 - ptb1 input buffer disconnected from lin module tx input 1 - ptb1 input buffer routed to lin module tx input table 239. port 1 output configuration (gpio_out1) offset (204) 0x47 access: user read/write 7 6 5 4 3 2 1 0 r wkup tcomp3 tcomp2 tcomp1 tcomp0 scitx linrx 0 w ptbx1 reset 0 0 0 0 0 0 0 0 notes 204.offset related to 0x0200 for blocking access and 0x3 00 for non blocking access wi thin the global address space.
general purpose i/o - gpio mm912_637, rev. 3.0 freescale semiconductor 171 5.10.5.3.8 port 2 input co nfiguration (gpio_in2) table 240. port 1 output configuration (gpio_out1) field description 7 wkup ptb1 - wake-up output 0 - internal wake-up signal disconnected from ptb1 output buffer or gate 1 - internal wake-up signal connected to ptb1 output buffer or gate 6 tcomp3 ptb1 - timer channel 3 - output compare output 0 - timer channel 3 - output compare disconnected from ptb1 output buffer or gate 1 - timer channel 3 - output compare connected to ptb1 output buffer or gate 5 tcomp2 ptb1 - timer channel 2 - output compare output 0 - timer channel 2 - output compare disconnected from ptb1 output buffer or gate 1 - timer channel 2 - output compare connected to ptb1 output buffer or gate 4 tcomp1 ptb1 - timer channel 1 - output compare output 0 - timer channel 1 - output compare disconnected from ptb1 output buffer or gate 1 - timer channel 1 - output compare connected to ptb1 output buffer or gate 3 tcomp0 ptb1 - timer channel 0 - output compare output 0 - timer channel 0 - output compare disconnected from ptb1 output buffer or gate 1 - timer channel 0 - output compare connected to ptb1 output buffer or gate 2 scitx ptb1 - sci tx output 0 - sci tx output disconnected from ptb1 output buffer or gate 1 - sci tx output connected to ptb1 output buffer or gate 1 linrx ptb1 - lin rx output 0 - lin rx output disconnected from ptb1 output buffer or gate 1 - lin rx output connected to ptb1 output buffer or gate 0 ptbx1 ptb1 - output buffer control 0 - ptb1 output buffer or gate input = 0 1 - ptb1 output buffer or gate input = 1 table 241. port 2 input configuration (gpio_in2) offset (205) 0x48 access: user read/write 7 6 5 4 3 2 1 0 r 0 tcap3 tcap2 tcap1 tcap0 scirx lintx 0 w reset 0 0 0 0 0 0 0 0 notes 205.offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 242. port 2 input configuration (gpio_in2) field description 6 tcap3 ptb2 - timer input capture channel 3 0 - ptb2 input buffer disconnected from timer channel 3 - input capture 1 - ptb2 input buffer routed to timer channel 3 - input capture 5 tcap2 ptb2 - timer input capture channel 2 0 - ptb2 input buffer disconnected from timer channel 2 - input capture 1 - ptb2 input buffer routed to timer channel 2 - input capture 4 tcap1 ptb2 - timer input capture channel 1 0 - ptb2 input buffer disconnected from timer channel 1 - input capture 1 - ptb2 input buffer routed to timer channel 1 - input capture
general purpose i/o - gpio mm912_637, rev. 3.0 freescale semiconductor 172 5.10.5.3.9 port 2 output co nfiguration (gpio_out2) 3 tcap0 ptb2 - timer input capture channel 0 0 - ptb2 input buffer disconnected from timer channel 0 - input capture 1 - ptb2 input buffer routed to timer channel 0 - input capture 2 scirx ptb2 - sci module rx input 0 - ptb2 input buffer disconnected from sci module rx input 1 - ptb2 input buffer routed to sci module rx input 1 lintx ptb2 - lin module tx input 0 - ptb2 input buffer disconnected from lin module tx input 1 - ptb2 input buffer routed to lin module tx input table 243. port 2 output configuration (gpio_out2) offset (205) 0x49 access: user read/write 7 6 5 4 3 2 1 0 r wkup tcomp3 tcomp2 tcomp1 tcomp0 scitx linrx 0 w ptbx2 reset 0 0 0 0 0 0 0 0 notes 206.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. table 244. port 2 output configuration (gpio_out2) field description 7 wkup ptb2 - wake-up output 0 - internal wake-up signal disconnected from ptb2 output buffer or gate 1 - internal wake-up signal connected to ptb2 output buffer or gate 6 tcomp3 ptb2 - timer channel 3 - output compare output 0 - timer channel 3 - output compare disconnected from ptb2 output buffer or gate 1 - timer channel 3 - output compare connected to ptb2 output buffer or gate 5 tcomp2 ptb2 - timer channel 2 - output compare output 0 - timer channel 2 - output compare disconnected from ptb2 output buffer or gate 1 - timer channel 2 - output compare connected to ptb2 output buffer or gate 4 tcomp1 ptb2 - timer channel 1 - output compare output 0 - timer channel 1 - output compare disconnected from ptb2 output buffer or gate 1 - timer channel 1 - output compare connected to ptb2 output buffer or gate 3 tcomp0 ptb2 - timer channel 0 - output compare output 0 - timer channel 0 - output compare disconnected from ptb2 output buffer or gate 1 - timer channel 0 - output compare connected to ptb2 output buffer or gate 2 scitx ptb2 - sci tx output 0 - sci tx output disconnected from ptb2 output buffer or gate 1 - sci tx output connected to ptb2 output buffer or gate 1 linrx ptb2 - lin rx output 0 - lin rx output disconnected from ptb2 output buffer or gate 1 - lin rx output connected to ptb2 output buffer or gate 0 ptbx2 ptb2 - output buffer control 0 - ptb2 output buffer or gate input = 0 1 - ptb2 output buffer or gate input = 1 table 242. port 2 input configuration (gpio_in2) field description
mm912_637, rev. 3.0 freescale semiconductor 173 5.10.5.3.10 port 3 input configurati on (gpio_in3) table 245. port 3 input configuration (gpio_in3) offset (207) 0x4a access: user read/write 7 6 5 4 3 2 1 0 r ptwu tcap3 tcap2 tcap1 tcap0 0 0 0 w reset 0 0 0 0 0 0 0 0 notes 207.offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. table 246. port 3 input configuration (gpio_in3) field description 7 ptwu ptb3 wake-up 0 - ptb3 input buffer low power mode wake-up circuity disabled 1 - ptb3 input buffer low power mode wake-up circuity enabled 6 tcap3 ptb3 - timer input capture channel 3 0 - ptb3 input buffer disconnected from timer channel 3 - input capture 1 - ptb3 input buffer routed to timer channel 3 - input capture 5 tcap2 ptb3 - timer input capture channel 2 0 - ptb3 input buffer disconnected from timer channel 2 - input capture 1 - ptb3 input buffer routed to timer channel 2 - input capture 4 tcap1 ptb3 - timer input capture channel 1 0 - ptb3 input buffer disconnected from timer channel 1 - input capture 1 - ptb3 input buffer routed to timer channel 1 - input capture 3 tcap0 ptb3 - timer input capture channel 0 0 - ptb3 input buffer disconnected from timer channel 0 - input capture 1 - ptb3 input buffer routed to timer channel 0 - input capture
lin mm912_637, rev. 3.0 freescale semiconductor 174 5.11 lin 5.11.1 introduction the lin bus pin provides a physical layer for single-wire communication in automotive applications. the lin physical layer is designed to meet the lin physical layer version 2.0 / 2. 1 and j2602 specification, an d has the following features: ? lin physical layer 2.0 / 2.1 / j2602 compliant ? slew rate selection 20 kbit, 10 kbit, and fast mode (100 kbit) ? over-temperature shutdown - hti ? permanent pull-up in normal mode 30 k ? , 1.0 m ? in low power ? current limitation ? special j2602 compliant configuration ? direct rx / tx access ? optional external rx / tx access and routing to the timer input through ptbx the lin driver is a low side mosfet with current limitation and thermal shutdown. an in ternal pull-up resistor with a serial di ode structure is integrated, so no external pull-up components are required for the applicat ion in a slave node. the fall time from dominant to recessive and the rise time from recessive to dominant is controll ed. the symmetry between both slopes is guaranteed. 5.11.2 overview 5.11.2.1 block diagram figure 44 shows the basic function of the lin module. figure 44. lin module block diagram receiver wake-up filter otie (m) txdm (m) lvsd (m) en (m) srs (m)[1:0] ot hf uv rx tx fromptb ptb sci rx tx lin lgnd vsup r slave d ser over- temperature detection interrupt wake up rdy transmitter control under- voltage detection =1 fromsci tosci toptb 1 0 analog mcu
lin mm912_637, rev. 3.0 freescale semiconductor 175 5.11.2.2 lin pin the lin pin offers high susceptibility immunity level from exte rnal disturbance, guaranteeing communication during external disturbances. see section 4.8, ?electromagnetic compatibility (emc)" . 5.11.2.3 slew rate selection the slew rate can be selected for optimized operation at 10 kbit/s and 20 kbit/s as well as a fast baud rate (100 kbit) for test and programming. the slew rate can be adapted with the bits srs[1:0] in the lin control re gister (lin_ctl). the initial slew rate i s 20 kbit/s. 5.11.2.4 over-temperatur e shutdown (lin interrupt) the output low side fet (transmitter) is pr otected against over-temperature conditions . in an over-temperature condition, the transmitter will be shut down, and the to bi t in the lin control register (lin_ctl) is set as long as the condition is present. if the otiem bit is set in the lin status register (lin_sr), an interrupt irq wil l be generated. acknowledge the interrupt by writing a ?1? in the lin status register (lin_sr). to issue a new interrupt, the condition has to vanish and reoccur. the transmitter is automatically re-enabled once the ov er-temperature condition is gone and txd is high. 5.11.2.5 low power mode and wake-up feature during low power mode operation, the transmitter of the physical la yer is disabled. the receiver is still active and able to de tect wake-up events on the lin bus line. a dominant level longer than t propwl , followed by a rising edge will generate a wake -up event and be reported in the wake-up source register (wsr). 5.11.2.6 j2602 compliance a low voltage shutdown feature was implemented to allow contro lled lin driver behavior under low voltage conditions at vsup. if lvsd is set, once vsup is below the threshold vj2602h, t he lin transmitter is not turned dominant again. the condition is indicated by the uv flag. 5.11.2.7 transmit / rece iving line definition the lin module can be connected to the sci or ptb module, or can be directly controlled by the txdm / rx bit 5.11.2.8 transmitter enable / ready the lin transmitter must be enabled before transmission is possible (en). the rdy bit is set to 1 about 50 s after the lin transmitter is enabled. this is due to the initialization time for the lin transmitter, under some low voltage conditions. during this period (lin enabled to rdy = 1), the lin is forced to a recessive state. 5.11.3 memory map and registers 5.11.3.1 overview this section provides a detailed descripti on of the memory map and registers. 5.11.3.2 module memory map the memory map for the lin module is given in ta b l e 247
lin mm912_637, rev. 3.0 freescale semiconductor 176 5.11.3.3 register descriptions this section consists of regist er descriptions in address order. each description includes a standard register diagram with an associated figure number. details of the register bit and field function follow the regi ster diagrams, in bit order. 5.11.3.3.1 lin contro l register (lin_ctl) table 247. module memory map offset name 7 6 5 4 3 2 1 0 0x50 lin_ctl lin control register r 0 0 0 0 0 0 0 0 w otiem txdm lvsdm enm srsm r otie 0 0 txd lvsd en srs w 0x52 lin_sr (hi) r ot 0 hf 0 uv 0 0 0 lin status register w write 1 will clear the flags 0x53 lin_sr (lo) r rdy 0 0 0 0 0 rx tx lin status register w 0x54 lin_tx r 0 0 0 0 0 0 frompt b fromsc i lin transmit line definition w 0x55 lin_rx r 0 0 0 0 0 0 toptb tosci lin receive line definition w 0x56 reserved r 0 0 0 0 0 0 0 0 w 0x57 reserved r 0 0 0 0 0 0 0 0 w notes 208.offset related to 0x0200 for blocki ng access and 0x300 for non blocking ac cess within the global address space. 209.this register is 16-bit access only. table 248. lin control register (lin_ctl) offset (210) , (211) 0x50 access: user write 15 14 13 12 11 10 9 8 r 0 0 0 0 0 0 0 0 w otiem txdm lvsdm enm srsm reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 r otie 0 0 txd lvsd en srs w reset 0 0 0 0 0 0 0 0 notes 210.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. 211.this register is 16-bit access only.
lin mm912_637, rev. 3.0 freescale semiconductor 177 5.11.3.3.2 lin status register (lin_sr (hi)) table 249. lin control register (lin_ctl) - register field descriptions field description 15 otiem lin over-temperature interrupt enable - mask 0 - writing the otie bit will have no effect 1 - writing the otie bit will be effective 12 txdm in - direct transmitter control - mask 0 - writing the txd bit will have no effect 1 - writing the txd bit will be effective 11 lvsdm lin - low voltage shutdown disable (j2602 compliance control) - mask 0 - writing the lvsd bit will have no effect 1 - writing the lvsd bit will be effective 10 enm lin module enable - mask 0 - writing the en bit will have no effect 1 - writing the en bit will be effective 9-8 srsm[1:0] lin - slew rate select - mask 00,01,10 - writing the srs bits will have no effect 11 - writing the srs bits will be effective 7 otie lin over-temperature interrupt enable 0 - lin over-temperature interrupt disabled 1 - lin over-temperature interrupt enabled 4 txd in - direct transmitter control 0 - transmitter not controlled 1 - transmitter dominant 3 lvsd lin - low voltage shutdown disable (j2602 compliance control) 0 - lin will be remain in recessive state in case of v sup under-voltage condition 1 - lin will stay functional even with a v sup under-voltage condition 2 en lin module enable 0 - lin module disabled 1 - lin module enabled 1-0 srs[1:0] lin - slew rate select 00 - normal slew rate (20 kbit) 01 - slow slew rate (10.4 kbit) 10 - fast slew rate (100 kbit) 11 - normal slew rate (20 kbit) table 250. lin status register (lin_sr (hi)) offset (212) 0x52 access: user read/write 7 6 5 4 3 2 1 0 r ot 0 hf 0 uv 0 0 0 w write 1 will clear the flags reset 0 0 0 0 0 0 0 0 notes 212.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within th e global address space.
lin mm912_637, rev. 3.0 freescale semiconductor 178 5.11.3.3.3 lin status register (lin_sr (lo)) 5.11.3.3.4 lin transmit line definition (lin_tx) table 251. lin status register (lin_sr (hi)) - register field descriptions field description 7 ot lin over-temperature status. this bit is latched and has to be reset by writing 1 into ot bit. 0 - no lin over-temperature condition detected 1 - lin over-temperature condition detected 5 hf lin hf (high frequency) condition status indicating hf (dpi) di sturbance in the lin module. this bit is latched and has to be reset by writing 1 into hf bit. 0 - no lin hf (dpi) condition detected 1 - lin hf (dpi) condition detected 3 uv lin under-voltage status. this threshold is used for the j2602 feature as well. this bit is latched and has to be reset by writing 1 into uv bit. 0 - no lin under-voltage condition detected 1 - lin under-voltage condition detected table 252. lin status regi ster (lin_sr (lo)) offset (213) 0x53 access: user read 7 6 5 4 3 2 1 0 r rdy 0 0 0 0 0 rx tx w notes 213.offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space. table 253. lin status register (lin_sr (lo)) - register field descriptions field description 1 rdy transmitter ready status 0 - transmitter not ready 1 - transmitter ready 1 rx current rx status 0 - rx recessive 1 - rx dominant 0 tx current tx status 0 - tx recessive 1 - tx dominant table 254. lin transmit line definition (lin_tx) offset (214) 0x54 access: user read/write 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 fromptb fromsci w reset 0 0 0 0 0 0 0 0 notes 214.offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
lin mm912_637, rev. 3.0 freescale semiconductor 179 5.11.3.3.5 lin receive li ne definition (lin_rx) note in order to route the rx signal to the ti mer input capture, one of the ptbx must be configured as a pass through. table 255. lin transmit line definition (l in_tx) - register field descriptions field description 1 fromptb lin_tx internally routed from ptb. see section 5.10, ?general purpose i/o - gpio" for details. (215) 0 - lin transmitter disconnected from ptb module. 1 - lin transmitter connected to the ptb module. 0 fromsci lin_tx internally routed from sci (215) 0 - lin transmitter disconnected from sci module. 1 - lin transmitter connected to the sci module. notes 215.in case both, fromptb and fromsci are selected, the sci has priority and the ptb signal is i gnored. in any case, the signal is logically ored with the txd direct transmitter control. table 256. lin receive line definition (lin_rx) offset (216) 0x55 access: user read/write 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 toptb tosci w reset 0 0 0 0 0 0 0 0 notes 216.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within th e global address space. table 257. lin receive line definition (l in_rx) - register field descriptions field description 1 toptb lin_rx internally routed to ptb 0 - lin receiver disconnected from ptb module. 1 - lin receiver connected to the ptb module. 0 tosci lin_rx internally routed to sci 0 - lin receiver disconnected from sci module. 1 - lin receiver connected to the sci module.
mm912_637, rev. 3.0 freescale semiconductor 180 figure 45. definition of lin bus timing parameters
serial communication interface (s08sciv4) mm912_637, rev. 3.0 freescale semiconductor 181 5.12 serial communication interface (s08sciv4) 5.12.1 introduction 5.12.1.1 features features of sci module include: ? full-duplex, standard non-return-to-zero (nrz) format ? double-buffered transmitter and receiver with separate enables ? programmable baud rates (13-bit modulo divider) ? interrupt-driven or polled operation: ? transmit data register em pty and transmission complete ? receive data register full ? receive overrun, parity error, framing error, and noise error ? idle receiver detect ? active edge on receive pin ? break detect supporting lin ? hardware parity generation and checking ? programmable 8-bit or 9-bit character length ? receiver wake-up by idle-line or address-mark ? optional 13-bit break character generat ion / 11-bit break character detection ? selectable transmitter output polarity 5.12.1.2 modes of operation see section 5.12.3, ?functional description" , for details concerning sci operation in these modes: ? 8- and 9-bit data modes ? loop mode ? single-wire mode 5.12.1.3 block diagram figure 46 shows the transmitter portion of the sci. analog mcu
serial communication interface (s08sciv4) mm912_637, rev. 3.0 freescale semiconductor 182 figure 46. sci transmitter block diagram h 8 7 6 5 4 3 2 1 0 l scid ? tx buffer (write-only) internal bus stop 11-bit transmit shift register start shift direction lsb 1 ? baud rate clock parity generation transmit control shift enable preamble (all 1s) break (all 0s) sci controls txd txd direction to txd logic loop control to receive data in to txd tx interrupt request loops rsrc tie tc tdre m pt pe tcie te sbk t8 txdir load from scid txinv brk13
serial communication interface (s08sciv4) mm912_637, rev. 3.0 freescale semiconductor 183 figure 47 shows the receiver portion of the sci. figure 47. sci receiver block diagram h 8 7 6 5 4 3 2 1 0 l scid ? rx buffer (read-only) internal bus stop 11-bit receive shift register start shift direction lsb from rxd rate clock rx interrupt request data recovery divide 16 ? baud single-wire loop control wakeup logic all 1s msb from transmitter error interrupt request parity checking by 16 rdrf rie idle ilie or orie fe feie nf neie pf loops peie pt pe rsrc ilt rwu m lbkdif lbkdie rxedgif rxedgie active edge detect rxinv lbkde rwuid
serial communication interface (s08sciv4) mm912_637, rev. 3.0 freescale semiconductor 184 5.12.2 memory map and registers 5.12.2.1 overview this section provides a detailed descripti on of the memory map and registers. 5.12.2.2 module memory map the memory map for the s08sciv4 module is given in table 258 . 5.12.2.3 register definition the sci has eight 8-bit registers to control baud rate, select sci options, report sci status, and for transmit/receive data. 5.12.2.3.1 sci baud rate regist ers (scibd (hi), scibd (lo)) this pair of registers control the prescale divisor for sci baud rate generation. to update the 13-bit baud rate setting [sbr12:sbr0], first write to scibd (hi) to buffer the high half of the new value, and then write to scibd (lo). the working val ue in scibd (hi) does not change until scibd (lo) is written. scibdl is reset to a non-zero value, so after reset the baud ra te generator remains disabled until the first time the receiver or transmitter is enabled (re or te bits in scic2 are written to 1). table 258. module memory map offse name 7 6 5 4 3 2 1 0 0x18 scibd (hi) r lbkdie rxedgie 0 sbr12 sbr11 sbr10 sbr9 sbr8 sci baud rate register w 0x19 scibd (lo) r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 sci baud rate register w 0x1a scic1 r loops 0 rsrc m 0 ilt pe pt sci control register 1 w 0x1b scic2 r tie tcie rie ilie te re rwu sbk sci control register 2 w 0x1c scis1 r tdre tc rdrf idle or nf fe pf sci status register 1 w 0x1d scis2 r lbkdif rxedgif 0 rxinv rwuid brk13 lbkde raf sci status register 2 w 0x1e scic3 r r8 t8 txdir txinv orie neie feie peie sci control register 3 w 0x1f scid r r7 r6 r5 r4 r3 r2 r1 r0 sci data register w t7 t6 t5 t4 t3 t2 t1 t0 notes 217.offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space.
serial communication interface (s08sciv4) mm912_637, rev. 3.0 freescale semiconductor 185 table 259. sci baud rate register (scibd (hi)) offset (218) 0x18 access: user read/write 7 6 5 4 3 2 1 0 r lbkdie rxedgie 0 sbr12 sbr11 sbr10 sbr9 sbr8 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved notes 218.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within th e global address space. table 260. scibd (hi) field descriptions field description 7 lbkdie lin break detect interrupt enable (for lbkdif) 0 hardware interrupts from lbkdif disabled (use polling). 1 hardware interrupt requested when lbkdif flag is 1. 6 rxedgie rxd input active edge interrupt enable (for rxedgif) 0 hardware interrupts from rxedgif disabled (use polling). 1 hardware interrupt requested when rxedgif flag is 1. 4:0 sbr[12:8] baud rate modulo divisor ? the 13 bits in sbr[12:0] are referred to collecti vely as br, and they set the modulo divide rate for the sci baud rate generator. when br = 0, the sci baud rate generator is disabled to reduce supply current. when br = 1 to 8191, the sci baud rate = busclk/(64 ? br). see br bits in table 261 . table 261. sci baud rate register (scibdl) offset (219) 0x19 access: user read/write 7 6 5 4 3 2 1 0 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w reset 0 0 0 0 0 1 0 0 notes 219.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within th e global address space. table 262. scibdl field descriptions field description 7:0 sbr[7:0] baud rate modulo divisor ? these 13 bits in sbr[12:0] are referred to collectively as br, and they set the modulo divide rate for the sci baud rate generator. when br = 0, the sci baud rate generator is disabled to reduce supply current. when br = 1 to 8191, the sci baud rate = busclk/(64 ? br). see also br bits in ta b l e 259 .
serial communication interface (s08sciv4) mm912_637, rev. 3.0 freescale semiconductor 186 5.12.2.3.2 sci control register 1 (scic1) this read/write register is used to control various optional features of the sci system. table 263. sci control register 1 (scic1) offset (220) 0x1a access: user read/write 7 6 5 4 3 2 1 0 r loops 0 rsrc m 0 ilt pe pt w reset 0 0 0 0 0 0 0 0 notes 220.offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space. table 264. scic1 field descriptions field description 7 loops loop mode select ? selects between loop back modes and nor mal 2-pin full-duplex modes. when loops = 1, the transmitter output is internally connected to the receiver input. 0 normal operation ? rxd and txd use separate pins. 1 loop mode or single-wire mode where transmitter output s are internally connected to receiver input. (see rsrc bit.) rxd pin is not used by sci. 5 rsrc receiver source select ? this bit has no meaning or effect unless the loops bit is set to 1. when loops = 1, the receiver input is internally connected to the txd pin and rsrc determines whether this connection is also connected to the transmitter output. 0 provided loops = 1, rsrc = 0 selects internal loop back mode and the sci does not use the rxd pins. 1 single-wire sci mode where the txd pin is connec ted to the transmitter output and receiver input. 4 m 9-bit or 8-bit mode select 0 normal ? start + 8 data bits (lsb first) + stop. 1 receiver and transmitter use 9-bit data characters ? start + 8 data bits (lsb first) + 9th data bit + stop. 2 ilt idle line type select ? setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. refer to section 5.12.3.3.2.1, ?idle-line wake-up" for more information. 0 idle character bit count starts after start bit. 1 idle character bit count starts after stop bit. 1 pe parity enable ? enables hardware parity generati on and checking. when parity is enabled, the most significant bit (msb) of the data character (eighth or ninth data bit) is treated as the parity bit. 0 no hardware parity generation or checking. 1 parity enabled. 0 pt parity type ? provided parity is enabled (pe = 1), this bit selects even or odd parity. odd parity means the total number of 1s in the data character, including the parity bit, is odd. even pari ty means the total number of 1s in the data character, includ ing the parity bit, is even. 0even parity. 1 odd parity.
serial communication interface (s08sciv4) mm912_637, rev. 3.0 freescale semiconductor 187 5.12.2.3.3 sci control register 2 (scic2) this register can be read or written at any time. table 265. sci control register 2 (scic2) offset (221) 0x1b access: user read/write 7 6 5 4 3 2 1 0 r tie tcie rie ilie te re rwu sbk w reset 0 0 0 0 0 0 0 0 notes 221.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within th e global address space. table 266. scic2 field descriptions field description 7 tie transmit interrupt enable (for tdre) 0 hardware interrupts from tdre disabled (use polling). 1 hardware interrupt requested when tdre flag is 1. 6 tcie transmission complete interrupt enable (for tc) 0 hardware interrupts from tc disabled (use polling). 1 hardware interrupt requested when tc flag is 1. 5 rie receiver interrupt enable (for rdrf) 0 hardware interrupts from rdrf disabled (use polling). 1 hardware interrupt requested when rdrf flag is 1. 4 ilie idle line interrupt enable (for idle) 0 hardware interrupts from idle disabled (use polling). 1 hardware interrupt requested when idle flag is 1. 3 te transmitter enable 0 transmitter off. 1 transmitter on. te must be 1 in order to use the sci transmitter. when te = 1, the sci forces the txd pin to act as an output for the sci system. when the sci is configured for single-wire operation (loops = rsrc = 1), txdir controls the direction of traffic on the single sci communication line (txd pin). te also can be used to queue an idle character by writing te = 0 then te = 1 while a transmission is in progress. refer to section 5.12.3.2.1, ?send break and queued idle" for more details. when te is written to 0, the transmitter keeps control of t he port txd pin until any data, queued idle, or queued break charact er finishes transmitting before allowing the pin to revert to a general-purpose i/o pin. 2 re receiver enable ? when the sci receiver is off, the rxd pin reve rts to being a general-purpose port i/o pin. if loops = 1 the rxd pin reverts to being a general-purpose i/o pin even if re = 1. 0 receiver off. 1 receiver on. 1 rwu receiver wake-up control ? this bit can be written to 1 to place the sc i receiver in a standby state where it waits for automatic hardware detection of a selected wake-up condition. the wake-up condition is either an idle line between messages (wake = 0, idle-line wake-up), or a logic 1 in the mo st significant data bit in a character (wake = 1, address-mark wake-up). application software sets rwu and (normally) a selected hardware condition automatically clears rwu. refer to section 5.12.3.3.2, ?receiver wake-up operation" for more details. 0 normal sci receiver operation. 1 sci receiver in standby waiting for wake-up condition. 0 sbk send break ? writing a 1 and then a 0 to sbk queues a break charac ter in the transmit data stream. additional break characters of 10 or 11 (13 or 14 if brk13 = 1) bit times of logic 0 are queued as long as sbk = 1. depending on the timing of the set and clear of sbk relative to the information curr ently being transmitted, a sec ond break character may be queued before software clears sbk. refer to section 5.12.3.2.1, ?send break and queued idle" for more details. 0 normal transmitter operation. 1 queue break character(s) to be sent.
serial communication interface (s08sciv4) mm912_637, rev. 3.0 freescale semiconductor 188 5.12.2.3.4 sci status register 1 (scis1) this register has eight read-only status flags. writes have no effect. special software sequences (which do not involve writing to this register) are used to clear these status flags. table 267. sci status register 1 (scis1) offset (222) 0x1c access: user read/write 7 6 5 4 3 2 1 0 r tdre tc rdrf idle or nf fe pf w reset 1 1 0 0 0 0 0 0 = unimplemented or reserved notes 222.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within th e global address space. table 268. scis1 field descriptions field description 7 tdre transmit data register empty flag ? tdre is set out of reset and when a transmit data value transfers from the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. to clear tdre, read scis1 with tdre = 1 and then write to the sci data register (scid). 0 transmit data register (buffer) full. 1 transmit data register (buffer) empty. 6 tc transmission complete flag ? tc is set out of reset and when tdre = 1 and no data, preamble, or break character is being transmitted. 0 transmitter active (sending data, a preamble, or a break). 1 transmitter idle (transmi ssion activity complete). tc is cleared automatically by reading scis1 with tc = 1 and then doing one of the following three things: ? write to the sci data register (scid) to transmit new data ? queue a preamble by changing te from 0 to 1 ? queue a break character by writing 1 to sbk in scic2 5 rdrf receive data register full flag ? rdrf becomes set when a character transfers from the receive shifter into the receive data register (scid). to clear rdrf, read scis1 with rdrf = 1 and then read the sci data register (scid). 0 receive data register empty. 1 receive data register full. 4 idle idle line flag ? idle is set when the sci receive line becomes idle fo r a full character time afte r a period of activity. when ilt = 0, the receiver starts counting idle bit times after the start bit. so if the receive characte r is all 1s, these bit times and the stop bit time count toward the full character time of logi c high (10 or 11 bit times depending on the m control bit) needed for the receiver to detect an idle line. when ilt = 1, the receiver doesn?t start counting idle bi t times until after the stop bit. so the stop bit and any logic high bit times at the end of the previous charac ter do not count toward the full character time of logic high needed for the receiver to detect an idle line. to clear idle, read scis1 with idle = 1 and then read the sci data register (scid). after idle has been cleared, it cannot become set again until after a new character has been received and rdrf has been set. idle will get set only once even if the receive line remains idle for an extended period. 0 no idle line detected. 1 idle line was detected. 3 or receiver overrun flag ? or is set when a new serial character is ready to be transferred to the receive data register (buffer), but the previously received character has not been read from scid yet. in this case, the new character (and all associated error information) is lost because there is no room to move it into scid. to clear or, read scis1 with or = 1 and then read the sci data register (scid). 0 no overrun. 1 receive overrun (new sci data lost).
serial communication interface (s08sciv4) mm912_637, rev. 3.0 freescale semiconductor 189 5.12.2.3.5 sci status register 2 (scis2) this register has one read-only status flag. 2 nf noise flag ? the advanced sampling technique used in the receiv er takes seven samples during the start bit and three samples in each data bit and the stop bit. if any of these samples di sagrees with the rest of the samples within any bit time i n the frame, the flag nf will be set at the same time as the fl ag rdrf gets set for the character. to clear nf, read scis1 and then read the sci data register (scid). 0 no noise detected. 1 noise detected in the received character in scid. 1 fe framing error flag ? fe is set at the same time as rdrf when the receiver detects a logic 0 where the stop bit was expected. this suggests the receiver wa s not properly aligned to a character frame. to clear fe, read scis1 with fe = 1 and then read the sci data register (scid). 0 no framing error detected. this does not guarantee the framing is correct. 1 framing error. 0 pf parity error flag ? pf is set at the same time as rdrf when parity is enabled (pe = 1) and the parity bit in the received character does not agree with the expected parity value. to clear pf, read scis1 and then read the sci data register (scid). 0 no parity error. 1 parity error. table 269. sci status register 2 (scis2) offset (223) 0x1d access: user read/write 7 6 5 4 3 2 1 0 r lbkdif rxedgif 0 rxinv rwuid brk13 lbkde raf w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved notes 223.offset related to 0x0200 for blocki ng access and 0x300 for non blocking a ccess within the global address space. table 270. scis2 field descriptions field description 7 lbkdif lin break detect interrupt flag ? lbkdif is set when the lin break detect ci rcuitry is enabled and a lin break character is detected. lbkdif is cleared by writing a ?1? to it. 0 no lin break character has been detected. 1 lin break character has been detected. 6 rxedgif rxd pin active edge interrupt flag ? rxedgif is set when an active edge (falling if rxinv = 0, rising if rxinv=1) on the rxd pin occurs. rxedgif is cleared by writing a ?1? to it. 0 no active edge on the receive pin has occurred. 1 an active edge on the receive pin has occurred. 4 rxinv (224) receive data inversion ? setting this bit reverses the polarity of the received data input. 0 receive data not inverted 1 receive data inverted 3 rwuid receive wake up idle detect ? rwuid controls whether the idle character that wakes up the receiver sets the idle bit. 0 during receive standby state (rwu = 1), the idle bit does not get set upon detection of an idle character. 1 during receive standby state (rwu = 1), the idle bit gets set upon detection of an idle character. 2 brk13 break character generation length ? brk13 is used to select a longer transm itted break character length. detection of a framing error is not affected by the state of this bit. 0 break character is trans mitted with length of 10 bit times (11 if m = 1) 1 break character is trans mitted with length of 13 bit times (14 if m = 1) table 268. scis1 field descriptions field description
serial communication interface (s08sciv4) mm912_637, rev. 3.0 freescale semiconductor 190 when using an internal oscillator in a li n system, it is necessary to raise the brea k detection threshold by one bit time. unde r the worst case timing conditions allowed in lin, it is possible that a 0x00 data character can appear to be 10.26 bit times lon g at a slave which is running 14% faster than the master. this woul d trigger normal break detection circuitry, which is designed to detect a 10 bit break symbol. when the lbkde bit is set, framing e rrors are inhibited and the break detection threshold changes from 10 bits to 11 bits, preventing false detection of a 0x00 data character as a lin break symbol. 5.12.2.3.6 sci control register 3 (scic3) 1 lbkde lin break detection enable ? lbkde is used to select a longer break c haracter detection length. while lbkde is set, framing error (fe) and receive data register fu ll (rdrf) flags are prevented from setting. 0 break character detection enabled. 1 break character detection disabled. 0 raf receiver active flag ? raf is set when the sci receiver detects the beginning of a valid start bit, and raf is cleared automatically when the receiver detects an id le line. this status flag can be used to check whether an sci character is being received before instructing the mcu to go to stop mode. 0 sci receiver idle waiting for a start bit. 1 sci receiver active (rxd input not idle). notes 224.setting rxinv inverts the rxd input for all cases: data bits, start and stop bits, break, and idle. table 271. sci control register 3 (scic3) offset (225) 0x1e access: user read/write 7 6 5 4 3 2 1 0 r r8 t8 txdir txinv orie neie feie peie w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved notes 225.offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. table 272. scic3 field descriptions field description 7 r8 ninth data bit for receiver ? when the sci is configured for 9-bit data (m = 1), r8 can be thought of as a ninth receive data bit to the left of the msb of the buffered data in the scid register. when reading 9-bit data, read r8 before reading scid, because reading scid completes automatic flag clearing sequences, which could allow r8 and scid to be overwritten with new data. 6 t8 ninth data bit for transmitter ? when the sci is configured for 9-bit data (m = 1), t8 may be thought of as a ninth transmit data bit to the left of the msb of the data in the scid regi ster. when writing 9-bit data, the entire 9-bit value is transferre d to the sci shift register after scid is written, so t8 should be written (if it needs to change from its previous value) before sc id is written. if t8 does not need to change in the new value (such as when it is used to generate mark or space parity), it need not be written each time scid is written. 5 txdir txd pin direction in single-wire mode ? when the sci is configured for single-wire half-duplex operation (loops = rsrc = 1), this bit determines the dire ction of data at the txd pin. 0 txd pin is an input in single-wire mode. 1 txd pin is an output in single-wire mode. 4 txinv (226) transmit data inversion ? setting this bit reverses the pol arity of the transmitted data output. 0 transmit data not inverted 1 transmit data inverted table 270. scis2 field descriptions field description
serial communication interface (s08sciv4) mm912_637, rev. 3.0 freescale semiconductor 191 5.12.2.3.7 sci data register (scid) this register is actually two separate r egisters. reads return the c ontents of the read-only receiv e data buffer and writes go to the write-only transmit data buffer. reads and writes of this register are also in volved in the automatic flag clearing mechani sms for the sci status flags. 5.12.3 functional description the sci allows full-duplex, asynchronous, nrz serial commun ication among the mcu and remote devices, including other mcus. the sci comprises a baud rate generator, transmitter, and receiver block. the transmitter and receiver operate independently, although they use the same baud rate generator. du ring normal operation, the mcu monitors the status of the sci, writes the data to be transmitted, and processes received data. the following describes each of the blocks of the sci. 5.12.3.1 baud rate generation figure 48 shows the clock source for the sci ba ud rate generator is the d2d clock / 4. 3 orie overrun interrupt enable ? this bit enables the overrun flag (or) to generate hardware interrupt requests. 0 or interrupts disabled (use polling). 1 hardware interrupt requested when or = 1. 2 neie noise error interrupt enable ? this bit enables the noise flag (nf) to generate hardware interrupt requests. 0 nf interrupts disabled (use polling). 1 hardware interrupt requested when nf = 1. 1 feie framing error interrupt enable ? this bit enables the framing error flag (fe) to generate hardware interrupt requests. 0 fe interrupts disabled (use polling). 1 hardware interrupt requested when fe = 1. 0 peie parity error interrupt enable ? this bit enables the parity error flag (p f) to generate hardware interrupt requests. 0 pf interrupts disabled (use polling). 1 hardware interrupt requested when pf = 1. notes 226.setting txinv inverts the txd output for all cases: data bits, start and stop bits, break, and idle. table 273. sci data register (scid) offset (227) 0x1d access: user read/write 7 6 5 4 3 2 1 0 r r7 r6 r5 r4 r3 r2 r1 r0 w t7 t6 t5 t4 t3 t2 t1 t0 reset 0 0 0 0 0 0 0 0 notes 227.offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space. table 272. scic3 field descriptions (continued) field description
serial communication interface (s08sciv4) mm912_637, rev. 3.0 freescale semiconductor 192 figure 48. sci baud rate generation sci communications require the transmitter and receiver (which typically derive baud rates from independent clock sources) to use the same baud rate. allowed tolerance on this baud frequency depends on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is performed. the mcu resynchronizes to bit boundaries on every high-to-low trans ition, but in the worst case, there are no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is accumulated for the whole character time. for a freescale semiconductor sci system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about 4.5 percent for 8-bit data format and about 4.0 percent for 9-bi t data format. although baud rate modulo divider settings do not always produce baud rates that exactly matc h standard rates, it is normally possible to get within a few percent, which is acceptable for reliable communications. 5.12.3.2 transmitter functional description this section describes the overall block di agram for the sci transmitter, as well as specialized functions for sending break an d idle characters. the transmitter block diagram is shown in figure 46 . the transmitter output (txd) idle state defaults to logic high (t xinv = 0 following reset). the tr ansmitter output is inverted by setting txinv = 1. the transmitter is enabled by setting the te bit in scic2. this queues a preamble character that is one full character frame of the idle state. the trans mitter then remains idle until data is available in the transmit data buffer. progr ams store data into the transmit data buffer by writing to the sci data register (scid). the central element of the sci transmitter is the transmit shift register that is ei ther 10 or 11 bits long depending on the se tting in the m control bit. for the remainder of this section, we will assume m = 0, selecting the normal 8-bit data mode. in 8-bit data mode, the shift register holds a start bit, eight data bits, and a stop bit. when the transmit shift register is available for a new sci character, the value waiting in the transmi t data register is transferred to the shif t register (synchronized with the baud rat e clock) and the transmit data register empty (tdre) status flag is set to indicate another character may be written to the transmit dat a buffer at scid. if no new character is waiting in the tran smit data buffer after a stop bit is shif ted out the txd pin, t he transmitter sets th e transmit complete flag and enters an idle mode, with txd hi gh, waiting for more characters to transmit. writing 0 to te does not immediately release the pin to be a genera l purpose i/o pin. any transmit activity that is in progress must first be completed. this includes data characters in prog ress, queued idle characters, and queued break characters. 5.12.3.2.1 send break and queued idle the sbk control bit in scic2 is used to send break characters wh ich were originally used to gain the attention of old teletype receivers. break characters are a full character time of logic 0 (10 bit times including the start and stop bits). a longer bre ak of 13 bit times can be enabled by setting brk13 = 1. normally, a prog ram would wait for tdre to bec ome set to indicate the last character of a message has move d to the transmit shifter, then write 1 and then writ e 0 to the sbk bit. this action queues a br eak character to be sent as soon as the shifter is available. if sbk is still 1 when the queued break moves into the shifter (synchronized to the baud rate clock), an additional break char acter is queued. if the receiving device is another freescale semiconductor sci, the break characters will be received as 0s in all eight data bits and a framing error (fe = 1) occurs. when idle-line wake-up is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers. normally, a program would wait for tdre to become se t to indicate the last character of a message has moved to the transmit shifter, then write 0 and then write 1 to the te bit. this action queues an idle characte r to be sent as soon as the s hifter is available. as long as the characte r in the shifter does not finish while te = 0, the sci transmitter never actually releases control sbr12:sbr0 divide by tx baud rate rx sampling clock (16 ? baud rate) baud rate generator off if [sbr12:sbr0] = 0 d2d / 4 baud rate = d2dclk / 4 [sbr12:sbr0] ? 16 16 modulo divide by (1 through 8191)
serial communication interface (s08sciv4) mm912_637, rev. 3.0 freescale semiconductor 193 of the txd pin. if there is a possibility of the shifter finishing while te = 0, set the general-purpose i/o controls so the pin that is shared with txd is an output driving a logi c 1. this ensures that the txd line will lo ok like a normal idle line even if the sc i loses control of the port pin between writing 0 and then 1 to te. the length of the break character is affected by the brk13 and m bits as shown below. 5.12.3.3 receiver f unctional description in this section, the receiver block diagram ( figure 47 ) is used as a guide for the overall receiver functional description. the data sampling technique used to reconstruct receiver data is then descr ibed in more detail. finally, two variations of the receiver wake-up function are explained. the receiver input is inverted by setting rxinv = 1. the receiv er is enabled by setting the re bit in scic2. character frames consist of a start bit of logic 0, eight (or nine) data bits (lsb first), and a stop bit of logic 1. for information about 9-bi t data mode, refer to section 5.12.3.5.1, ?8- and 9-bit data modes" . for the remainder of this discussion, we assume the sci is configured for normal 8-bit data mode. after receiving the stop bit into the receive shifter, and provid ed the receive data register is not already full, the data cha racter is transferred to the receive data register and the receive data register full (rdrf) status flag is set. if rdrf was already set indicating the receive data register (buffer) was already full, the overrun (or) status flag is set and the new data is lost. b ecause the sci receiver is double-buffered, the program has one full char acter time after rdrf is set before the data in the receive d ata buffer must be read to avoid a receiver overrun. when a program detects that the receive data register is full (rdrf = 1), it gets the data from the receive data register by reading scid. the rdrf flag is cleared automatically by a 2-step sequen ce which is normally satisfied in the course of the user?s program that handles receive data. refer to section 5.12.3.4, ?interrupt s and status flags" for more details about flag clearing. 5.12.3.3.1 data sampling technique the sci receiver uses a 16 ? baud rate clock for sampling. the receiver starts by taking logic level samples at 16 times the baud rate to search for a falling edge on the rxd serial data input pin. a falling edge is defined as a logic 0 sample after three consecutive logic 1 samples. the 16 ? baud rate clock is used to divide the bit time into 16 segments labeled rt1 through rt16. when a falling edge is located, three more samples are taken at rt 3, rt5, and rt7 to make sure this was a real start bit and not merely noise. if at least two of these three samples are 0, the receiver assumes it is synch ronized to a receive character. the receiver then samples each bit time, including the start and stop bits, at rt8, rt9, and rt10 to determine the logic level for that bit. the logic level is in terpreted to be that of the majo rity of the samples taken during the bit time. in the case of th e start bit, the bit is assumed to be 0 if at least two of the samples at rt 3, rt5, and rt7 are 0 even if one or all of the samples taken at rt8, rt9, and rt10 are 1s. if any sample in any bit time (inc luding the start and stop bits) in a character frame fails to agre e with the logic level for that bit, the noise flag (nf) will be set when the received character is transferred to the receive da ta buffer. the falling edge detection logic continuously looks for fa lling edges, and if an edge is detected, the sample clock is resynchronized to bit times. this improves the reliability of t he receiver in the presence of noise or mismatched baud rates. i t does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame. in the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a falling edge is filled with three logic 1 samples so that a new st art bit can be detected almost im mediately. the receiver is i nhibited from receiving any new characters until the framing error flag is cleared. the receive shift register continues to function, bu t a complete character cannot transfer to th e receive data buffer if fe is still set. table 274. break character length brk13 m break character length 0 0 10 bit times 0 1 11 bit times 1 0 13 bit times 1 1 14 bit times
serial communication interface (s08sciv4) mm912_637, rev. 3.0 freescale semiconductor 194 5.12.3.3.2 receiver wake-up operation receiver wake-up is a hardware mechanism that allows an sci rece iver to ignore the characters in a message that is intended for a different sci receiver. in such a s ystem, all receivers evaluate the first character(s) of each message, and as soon as t hey determine the message is intended for a different receiver, they wr ite logic 1 to the receiver wake up (rwu) control bit in sci c2. when rwu bit is set, the status flags associated with the receiv er (with the exception of the id le bit, idle, when rwuid bit is set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant message characters. at the end of a message, or at the beginning of the next message, all re ceivers automatically force rwu to 0 so all receivers wake up in time to look at the first character(s) of the next message. 5.12.3.3.2.1 idle-line wake-up when wake = 0, the receiver is configured for idle-line wake-up. in this mode, rwu is cleared automatically when the receiver detects a full character time of the idle-line level. the m co ntrol bit selects 8-bit or 9-bit data mode that determines how ma ny bit times of idle are needed to constitute a full character time (10 or 11 bit times because of the start and stop bits). when rwu is one and rwuid is zero, the idle condition that wa kes up the receiver does not set the idle flag. the receiver wakes up and waits for the first data character of the next message which will set the rdrf fl ag and generate an interrupt if enabled. when rwuid is one, any idle condition sets the idle fl ag and generates an interrupt if enabled, regardless of whether rwu is zero or one. the idle-line type (ilt) control bit selects one of two ways to detect an idle line. when ilt = 0, the idle bit counter starts after the start bit so the stop bit and any logic 1s at the end of a charac ter count toward the full charac ter time of idle. when ilt = 1 , the idle bit counter does not start until after a stop bit time, so th e idle detection is not affected by the data in the last char acter of the previous message. 5.12.3.3.2.2 address-mark wake-up when wake = 1, the receiver is configured for address-mark wake-up. in this mode , rwu is cleared automatically when the receiver detects a logic 1 in the most significant bit of a received character (eighth bit in m = 0 mode and ninth bit in m = 1 mode). address-mark wake-up allows messages to contain idle characte rs but requires that the msb be reserved for use in address frames. the logic 1 msb of an address frame clears the rwu bit before the stop bit is received and sets the rdrf flag. in this case, the character with the msb set is received even though th e receiver was sleeping during most of this character time. 5.12.3.4 interrupts and status flags the sci system has three separate interrupt vectors to reduce the amount of softwa re needed to isolat e the cause of the interrupt. one interrupt vector is associated with the transmitter for tdre and tc events. another interrupt vector is associat ed with the receiver for rdrf, idle, rxedgif, and lbkdif events, and a third vector is used for or, nf, fe, and pf error conditions. each of these ten interrupt sources can be separate ly masked by local interrupt enable masks. the flags can still b e polled by software when the local masks are cleared to disable generation of hardware interrupt requests. the sci transmitter has two status flags that optionally can gene rate hardware interrupt requests. transmit data register empty (tdre) indicates when there is room in the transmit data buffer to write another transmit character to scid. if the transmit interrupt enable (tie) bit is set, a hardware interrupt will be requested whenever tdre = 1. transmit complete (tc) indicates that the transmitter is finished transmitting all data, preamble, and break charac ters and is idle with txd at the inactive lev el. this flag is often used in systems with modems to determine when it is safe to turn off the modem. if the transmit complete interrup t enable (tcie) bit is set, a hardware interrupt will be requested whenever tc = 1. instead of hardware interrupts, software polling may be used to monitor the tdre and tc status flags if the corresponding tie or tcie local interrupt masks are 0s. when a program detects that the receive data register is full (rdrf = 1), it gets the data from the receive data register by reading scid. the rdrf flag is cleared by reading scis1 while rdrf = 1 and then reading scid. when polling is used, this sequence is natur ally satisfied in the normal course of th e user program. if hardware interrupts are used, scis1 must be read in the interrupt se rvice routine (isr). normally, this is d one in the isr anyway to check for receive errors, so the sequence is automatically satisfied. the idle status flag includes logic that prevents it from getting set repeatedly w hen the rxd line remains idle for an extended period of time. idle is cleared by reading scis1 while idle = 1 and then reading scid. after idle has been cleared, it cannot become set again until the receiver has received at least one new character and has set rdrf.
serial communication interface (s08sciv4) mm912_637, rev. 3.0 freescale semiconductor 195 if the associated error was detected in the received character t hat caused rdrf to be set, the error flags ? noise flag (nf), framing error (fe), and parity error flag (pf) ? get set at th e same time as rdrf. these flags are not set in overrun cases. if rdrf was already set when a new character is ready to be transferred from the rece ive shifter to the receive data buffer, th e overrun (or) flag gets set instead the data along wi th any associated nf, fe, or pf condition is lost. at any time, an active edge on the rxd serial data input pin causes the rxedgif flag to set. the rxedgif flag is cleared by writing a ?1? to it. this function does depend on the receiver being enabled (re = 1). 5.12.3.5 additional sci functions the following sections describe additional sci functions. 5.12.3.5.1 8- and 9-bit data modes the sci system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the m control bit in scic1 . in 9-bit mode, there is a ninth data bit to the left of the msb of the sci data register. for the transmit data buffer, this bi t is stored in t8 in scic3. for the receiver, the ninth bit is held in r8 in scic3. for coherent writes to the tran smit data buffer, write to the t8 bit before writing to scid. if the bit value to be transmitted as the ni nth bit of a new character is the same as for the previous character, it is not nec essary to write to t8 again. when data is transfe rred from the transmit data buffer to the transmit shifter, the value in t8 is copied at the same time data is transferr ed from scid to the shifter. 9-bit data mode typically is used in conjunction with parity to allo w eight bits of data plus the parity in the ninth bit. or i t is used with address-mark wake-up so the ninth data bi t can serve as the wake-up bit. in custom protocols, the ninth bit can also serve as a software-controlled marker. 5.12.3.5.2 stop mode operation during all stop modes, clocks to the sci module are halted. in stop1 and stop2 modes, all sci register data is lost and must be re-initialized upon recovery from these two stop modes. no sci module registers are affected in stop3 mode. the receive input active edge detect circuit is still active in stop3 mode, but not in stop2. an active edge on the receive inp ut brings the cpu out of stop3 mode if th e interrupt is not masked (rxedgie = 1). note, because the clocks are halted, the sci module will resume op eration upon exit from stop (only in stop3 mode). software should ensure stop mode is not entered while there is a charac ter being transmitted out of or received into the sci module. 5.12.3.5.3 loop mode when loops = 1, the rsrc bit in the same register chooses between loop mode (rsrc = 0) or single-wire mode (rsrc = 1). loop mode is sometimes used to check software, independent of co nnections in the external system, to help isolate system problems. in this mode, the transmitter output is internally connected to the receiver input and the rxd pin is not used by the sci, so it reverts to a general purpose port i/o pin. 5.12.3.5.4 single-wire operation when loops = 1, the rsrc bit in the same register chooses between loop mode (rsrc = 0) or single-wire mode (rsrc = 1). single-wire mode is used to implement a half-duplex serial conne ction. the receiver is interna lly connected to the transmitter output and to the txd pin. the rxd pin is not us ed and reverts to a general-purpose port i/o pin. in single-wire mode, the txdir bit in scic3 controls the direction of serial data on the txd pin. when txdir = 0, the txd pin is an input to the sci receiver and the transmitter is temporarily disconnected from the txd pin so an external device can send serial data to the receiver. when txdir = 1, the txd pin is an output driven by the tr ansmitter. in single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characte rs that are sent out by the transmitter.
life time counter (ltc) mm912_637, rev. 3.0 freescale semiconductor 196 5.13 life time counter (ltc) 5.13.1 introduction the life time counter is implemented as flexible counter running in both, low power (stop and sleep) and normal modes. it is based on the alfclk clock featuring irq and wake up ca pabilities on the life time counter overflow. the wake up on overflow would be indicated in the pcr_sr register wultcf bit. 5.13.2 memory map and registers 5.13.2.1 overview this section provides a detailed descripti on of the memory map and registers. 5.13.2.2 module memory map the memory map for the ltc module is in table 275 5.13.2.3 register descriptions this section consists of regist er descriptions in address order. each description includes a standard register diagram with an associated figure number. details of register bit and fi eld function follow the register diagrams, in bit order. table 275. module memory map offset (228) name 7 6 5 4 3 2 1 0 0x38 ltc_ctl (hi) r 0 0 0 0 0 0 0 0 life time counter control register w ltciem ltcem 0x39 ltc_ctl (lo) r ltcie 0 0 0 0 0 0 ltce life time counter control register w 0x3a ltc_sr r ltcof 0 0 0 0 0 0 0 life time counter status register w 1 = clear 0x3b reserved r 0 0 0 0 0 0 0 0 w 0x3c ltc_cnt1 life time counter register r ltc[31:0] w r w 0x3e ltc_cnt0 life time counter register r w r w notes 228.offset related to 0x0200 for blocki ng access and 0x300 for non blocking a ccess within the global address space. analog mcu
mm912_637, rev. 3.0 freescale semiconductor 197 5.13.2.3.1 life time counter co ntrol register (ltc_ctl (hi)) 5.13.2.3.2 life time counter co ntrol register (ltc_ctl (lo)) table 276. life time counter control register (ltc_ctl (hi)) offset (229) 0x38 access: user write 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 w ltciem ltcem reset 0 0 0 0 0 0 0 0 notes 229.offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space. table 277. life time counter control register (ltc_ctl (hi)) - register field descriptions field description 0 ltcem life time counter enable mask 0 - writing the ltce bit will have no effect 1 - writing the ltce bit will be effective 7 ltciem life time counter interrupt enable mask 0 - writing the ltcie bit will have no effect 1 - writing the ltcie bit will be effective table 278. life time counter control register (ltc_ctl (lo)) offset (230) 0x39 access: user read/write 7 6 5 4 3 2 1 0 r ltcie 0 0 0 0 0 0 ltce w reset 0 0 0 0 0 0 0 0 notes 230.offset related to 0x0200 for blocking access and 0x300 for non blocking ac cess within the global address space. table 279. life time counter control register (ltc_ctl (lo)) - register field descriptions field description 0 ltce life time counter enable 1 - life time counter module enabled. counter will be incremented with based on the alfclk frequency. 0 - life time counter module disabl ed. counter content will remain. (231) 7 ltcie life time counter interrupt enable 1 - life time counter overflow will generate an interrupt request. 0 - life time counter overflow will not generate an interrupt request. notes 231.the first period after enable might be s horted due to the asynchronous clocks.
mm912_637, rev. 3.0 freescale semiconductor 198 5.13.2.3.3 life time counter status register (ltc_sr) 5.13.2.3.4 life time counter re gister (ltc_cnt1, ltc_cnt0) table 280. life time counter status register (ltc_sr) offset (232) 0x3a access: user read/write 7 6 5 4 3 2 1 0 r ltcof 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 notes 232.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within th e global address space. table 281. life time counter status register (ltc_sr) - register field descriptions field description 0 ltcof life time counter overflow flag . writing 1 will clear the flag. 1 - life time counter overflow detected. 0 - no life time counter overflow since last clear table 282. life time counter register (ltc_cnt1, ltc_cnt0) offset (233) , (234) 0x3c, 0x3e access: user read/write 7 6 5 4 3 2 1 0 r ltc[31:16] w r w r ltc[15:0] w r w reset 0 0 0 0 0 0 0 0 notes 233.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. 234.those registers are 16-bit access only. table 283. life time counter register (ltc_cnt 1, ltc_cnt0) - register field descriptions field description 0-31 ltc[31:0] life time counter register the two 16-bit words of the 32-bit life time counter regi ster represent the current counter status. whenever the microcontroller performs a reading operation on one of the 16bit registers, the life time counter is stopped until the remaining 16-bit register is read, to prevent loss of info rmation. after the second part is read, the ltc continues automatically. write operations should be performed with the life time counter disabled to prevent a loss of data.
die to die interface - target mm912_637, rev. 3.0 freescale semiconductor 199 5.14 die to die interface - target the d2d interface is the bus interface to the microcontroller. access to the mm912_637 analog die is controlled by the d2d interface module. this section describes the functionality of the die-to-die target block (d2d). 5.14.1 overview the d2d is the target for a data transfer from the target to t he initiator (mcu). the initiator provides a set of configuration registers and two memory mapped 256 byte address windows. when writing to a window a transaction is initiated sending a write command, followed by an 8-bit address and the data byte or word is received from the initiator. when reading from a window a transaction is received with the read command, followed by an 8-bit address. the target then responds with the data. the basic idea is that a peripheral located on the mm912_637 anal og die, can be addressed like an on-chip peripheral. figure 49. die to die interface features: ? software transparent register access to peripherals on the mm912_637 analog die ? 256 byte address window ? supports blocking read or write as we ll as non-blocking write transactions ? 8 bit physical bus width ? automatic synchronization of the target when initiator starts driving the interface clock ? generates transaction and error status as well as eot acknowledge ? providing single interrupt interface to d2d initiator 5.14.2 low power mode operation the d2d module is disabled in sleep and stop mode. in stop mode, the d2dint signal is used to wa ke-up a powered down mcu after re-enabling the d2d interface. as the mcu could wake-up without the mm912_637 analog die, a special command will be recognized as wake-up event during stop mode. see section 5.2, ?analog die - power, clock and resets - pcr" . 5.14.2.1 normal mode while in normal, d2dclk acts as an input only with pull pr esent. d2d[7:0] operates as input/output with pull-down always present. d2dint acts as an output only. 5.14.2.2 sleep mode / stop mode while in sleep mode, all interface data pins are pulled down to dgnd to reduce power consumption. command, address and data buffer internal read data bus internal write data bus internal address bus internal interrupt signal (int) d2dclk internal interrupt sources analog mcu
embedded microcontroller - overview mm912_637, rev. 3.0 freescale semiconductor 200 5.15 embedded microcontroller - overview 5.15.1 introduction the s12 central processing unit (cpu) offers 128 kb of flash memory and 6.0 kb of system sram, up to eight general purpose i/os, an on-chip oscillator and clock multiplier, one serial pe ripheral interface (spi), an interrupt module, and debug capabil ities via the on-chip debug module (dbg), in co mbination with the background debug mode (b dm) interface. additionally, there is a die-to-die initiator (d2di) which represents the communication interface to the companion (analog) die. 5.15.2 features this section describes the key features of the mm912_637 micro controller die. 5.15.2.1 chip-level features on-chip modules available within the fa mily include the following features: ? s12 cpu core (cpu12_v1) ? 128 kbyte on-chip flash with ecc ?4.0 kbyte on-chip data flash with ecc ?6.0 kbyte on-chip sram ? phase locked loop (ipll) frequency multiplier with internal filter ? 4.0?16 mhz amplitude controlled pierce oscillator ? 1.024 mhz internal rc oscillator ? one serial peripheral interface (spi) module ? on-chip voltage regulator (vreg) for regulation of input supply and all internal voltages ? die to die initiator (d2di) 5.15.3 module features the following sections provide more details of the modules implemented on the mc9s12i128. 5.15.3.1 s12 16-bit central processor unit (cpu) s12 cpu is a high-speed 16-bit processing unit: ? full 16-bit data paths supports efficient arithmetic operation and high speed math execution ? includes many single-byte inst ructions. this allows much more efficient use of rom space ? extensive set of indexed addr essing capabilit ies, including: ? using the stack pointer as an indexing register in all indexed operations ? using the program counter as an indexing regi ster in all but auto in crement/decrement mode ? accumulator offsets using a, b, or d accumulators ? automatic index predecrement, preincrement, postdecrement, and postincrement (by ?8 to +8) analog mcu
embedded microcontroller - overview mm912_637, rev. 3.0 freescale semiconductor 201 5.15.3.2 on-chip flash with ecc on-chip flash memory on the mm912_637 features the following: ? 128 kbyte of program flash memory ? 32 data bits plus 7 syndrome ecc (error correction code) bits allow single bit error correction and double fault detection ? erase sector size 512 bytes ? automated program and erase algorithm ? user margin level setting for reads ? protection scheme to prevent accidental program or erase ?4.0 kbyte data flash memory ? 16 data bits plus 6 syndrome ecc (error correction code) bits allow single bit error correction and double-bit error detection ? erase sector size 256 bytes ? automated program and erase algorithm ? user margin level setting for reads 5.15.3.3 on-chip sram ?6.0 kbytes of general purpose ram 5.15.3.4 main external oscillator (xosc) ? loop controlled pierce oscillator using a 4.0 mhz to 16 mhz crystal or resonator ? current gain control on amplitude output ? signal with low harmonic distortion ? low power ? good noise immunity ? eliminates need for external current limiting resistor ? transconductance sized for optimum start-up margin for typical crystals 5.15.3.5 internal rc oscillator (irc) ? trimmable internal reference clock ? frequency: 1.024 mhz 5.15.3.6 internal phase-locked-loop (ipll) ? phase-locked-loop clock frequency multiplier ? no external components required ? reference divider and multiplier allow large variety of clock rates ? automatic bandwidth control mode for low-jitter operation ? automatic frequency lock detector ? configurable option to spread spectrum for reduced emc radiation (frequency modulation) ? reference clock sources: ? external 4.0?16 mhz resonator/crystal (xosc) ? internal 1.024 mhz rc oscillator (irc)
embedded microcontroller - overview mm912_637, rev. 3.0 freescale semiconductor 202 5.15.3.7 system integrity support ? power-on reset (por) ? system reset generation ? illegal address detection with reset ? low voltage detection with interrupt or reset ? real time interrupt (rti) ? computer operating properly (cop) watchdog ? configurable as window cop for enhanced failure detection ? initialized out of reset using option bits located in flash memory ? clock monitor supervising the co rrect function of the oscillator 5.15.3.8 serial periphera l interface module (spi) ? configurable 8- or 16-bit data size ? full duplex or single-wire bidirectional ? double buffered transmit and receive ? master or slave mode ? msb-first or lsb-first shifting ? serial clock phase and polarity options 5.15.3.9 on-chip voltage regulator (vreg) ? linear voltage regulator with bandgap reference ? low voltage detect (lvd) with low voltage interrupt (lvi) ? power-on reset (por) circuit ? low voltage reset (lvr) 5.15.3.10 background debug (bdm) ? non-intrusive memory access commands ? supports in-circuit programming of on-chip nonvolatile memory 5.15.3.11 debugger (dbg) ? trace buffer with depth of 64 entries ? three comparators (a, b and c) ? comparator a compares the full address bus and full 16-bit data bus ? exact address or address range comparisons ? two types of comparator matches ? tagged: this matches just before a s pecific instruction begins execution ? force: this is valid on the first instruction boundary after a match occurs ? four trace modes ? four stage state sequencer 5.15.3.12 die to die initiator (d2di) ?up to 2.0 mbyte/s data rate ? configurable 4-bit or 8-bit wide data path
embedded microcontroller - overview mm912_637, rev. 3.0 freescale semiconductor 203 5.15.4 block diagram figure 50 shows a block diagram of the mc9s12i128 device. figure 50. mc9s12i128 block diagram 6.0 k bytes ram reset extal xtal 4.0 k bytes dataflash with ecc bkgd periodic interrupt clock monitor single-wire background test voltage regulator debug module interrupt module mosi ss sck miso spi selectable 4 or 8 bit wide die-to-die initiator 128 k bytes flash with ecc cpu12-v1 cop watchdog pll with frequency modulation option debug module 3 address breakpoints 1 data breakpoints 64 byte trace buffer reset generation and test entry pa3 pa0 pa1 pa2 porta pa4 pa5 synchronous serial if pd3 pd0 pd1 pd2 portd pd7 pd4 pd5 pd6 pc0 pc1 portc d2dclk d2dint d2d3 d2d0 d2d1 d2d2 d2d7 d2d4 d2d5 d2d6 input: 3.13 v ? 5.5 v outputs: 1.8 v core and 2.7 flash power supply: vddrx, vssrx: 3.13 v ?5.5v for regulator input, port a, port e, bkgd, test vddd2d, vssd2d: 2.5 v for ports c and d pa6 pa7 . pe0 pe1 porte amplitude controlled low power and reset
embedded microcontroller - overview mm912_637, rev. 3.0 freescale semiconductor 204 5.15.5 device memory map table 284 shows the device register memory map. note reserved register space shown in ta b l e 284 is not allocated to an y module. this register space is reserved for future use. writing to these locations have no effect. read access to these locations returns zero. table 284. device register memory map address module size (bytes) 0x0000?0x0009 pim (port integration module ) 10 0x000a?0x000b mmc (memory map control) 2 0x000c?0x000d pim (port integration module ) 2 0x000e?0x000f reserved 2 0x0010?0x0015 mmc (memory map control) 8 0x0016?0x0019 reserved 2 0x001a?0x001b device id register 2 0x001c?0x001e reserved 4 0x001f int (interrupt module) 1 0x0020?0x002f dbg (debug module) 16 0x0030?0x0033 reserved 4 0x0034?0x003f cpmu (clock and power management) 12 0x0040?0x00d7 reserved 152 0x00d8?0x00df d2di (die 2 die initiator) 8 0x00e0?0x00e7 reserved 32 0x00e8?0x00ef spi (serial peripheral interface) 8 0x00f0?0x00ff reserved 32 0x0100?0x0113 ftmrc control registers 20 0x0114?0x011f reserved 12 0x0120?0x017f pim (port integration module ) 96 0x0180?0x01ef reserved 112 0x01f0?0x01fc cpmu (clock and power management) 13 0x01fd?0x01ff reserved 3 0x0200-0x02ff d2di (die 2 die initiator, blocking access window) 256 0x0300?0x03ff d2di (die 2 die initiator, non-blocking write window) 256
embedded microcontroller - overview mm912_637, rev. 3.0 freescale semiconductor 205 figure 51 shows mm912_637 cpu and bdm local address translation to the global memory map. it indicates also the location of the internal resources in the memory map. the whole 256 k global memory space is visible through the p-flash window located in the 64 k local memory map located at 0x8000 - 0xbfff using th e ppage register. figure 51. mc9s12i128 global memory map 0x3_ffff ppage cpu and bdm local memory map global memory map 0xffff 0xc000 0x8000 p-flash window 0x3_4000 0x3_8000 0x3_c000 0x0_4000 0x0000 0x4000 0x0400 d-flash 4k bytes ram 6k bytes unpaged p-flash 0 p0 p1 p2 p3 0 0 0 0x1400 0x0_0000 ram 6k p-flash 0x0_8000 nvm resources 0x0_2800 0x3_0000 unpaged p-flash (ppage 0x0c) (ppage 0x0d) (ppage 0x0e) (ppage 0x0f) (ppages (ppage 0x01) (ppage 0x00) 0x0_4400 d-flash 0x0_5400 0x2800 page 0x0f unpaged p-flash page 0x0d unpaged p-flash page 0x0c registers registers 4* 16k pages nvm resources unpaged p-flash unpaged p-flash 0x08-0x0b) (ppages 0x02-0x07) unimplemented unimplemented 0x2_0000
embedded microcontroller - overview mm912_637, rev. 3.0 freescale semiconductor 206 5.15.6 part id assignments the part id is located in two 8-bit registers partidh and pa rtidl (addresses 0x001a and 0x001b). the read-only value is a unique part id for each revision of the chip. ta b l e 285 shows the assigned part id number and mask set number. the version id in ta b l e 285 is a word located in a flash information row. the version id number indicates a specific version of internal nvm controller. 5.15.7 system clock description refer to section 5.22, ?s12 clock, reset, and power management unit (s12cpmu)" for the system clock description. 5.15.8 modes of operation the mcu can operate in different modes. these are described in section 5.15.8.1, ?chip conf iguration summary" . the mcu can operate in different power m odes to facilitate power saving when full system performance is not required. these are described in section 5.15.8.2, ?low power operation" . some modules feature a software programmable option to freeze the module status while the background debug module is active to facilitate debugging. 5.15.8.1 chip configuration summary the different modes and the security state of the mcu affect the debug features (enabled or disabled). the operating mode out of reset is determined by the state of the modc signal during reset (see table 286 ). the modc bit in the mode register shows the cu rrent operating mode and provides limited mode s witching during operation. the state of the modc signal is latched into this bit on the rising edge of reset . 5.15.8.1.1 normal single-chip mode this mode is intended for normal device operation. the opcode from the on-chip memory is being executed after reset (requires the reset vector to be programmed correctly). the pr ocessor program is executed from internal memory. 5.15.8.1.2 special single-chip mode this mode is used for debugging single-chip operation, boot-st rapping, or security related operations. the background debug module bdm is active in this mode. the cpu executes a monito r program located in an on-chip rom. bdm firmware waits for additional serial commands through the bkgd pin. table 285. assigned part id numbers device mask set number part id (235) version id mm912_637 0m96x 0x3880 0x0000 notes 235.the coding is as follows: ? bit 15-12: major family identifier ? bit 11-6: minor family identifier ? bit 5-4: major mask set revision number including fab transfers ? bit 3-0: minor ? non full ? mask set revision table 286. chip modes chip modes modc normal single chip 1 special single chip 0
embedded microcontroller - overview mm912_637, rev. 3.0 freescale semiconductor 207 5.15.8.2 low power operation the mm912_637 has two static low-power modes pseudo stop and stop mode. for a detailed description refer to the s12cpmu section. 5.15.9 security the mcu security mechanism prevents unauthorized access to the flash memory. refer to section 5.20, ?mcu - security (s12xs9secv2)" , section 5.21.4.1, ?security" , and section 5.24.5, ?security" . resets and interrupts consult the s12 cpu manual and the s12sint section for information on exception processing. 5.15.9.1 resets table 287 lists all reset sources and the vector locations. resets are explained in detail in section 5.22, ?s12 clock, reset, and power management unit (s12cpmu)" . 5.15.9.2 interrupt vectors table 288 lists all interrupt sources and vectors in the de fault order of priority. the interrupt module (see section 5.17, ?mcu - interrupt module (s12sintv1)" ) provides an interrupt vector base register (ivbr) to relocate the vectors. table 287. reset sources and vector locations vector address reset source ccr mask local enable $fffe power-on reset (por) none none $fffe low voltage reset (lvr) none none $fffe external pin reset none none $fffe illegal address reset none none $fffc clock monitor reset none osce bit in cpmuosc register $fffa cop watchdog reset none cr[2:0] in cpmucop register table 288. interrupt vector locations (sheet 1 of 2) vector address (236) interrupt source ccr mask local enable wake-up from stop wake-up from wait vector base + $f8 unimplemented instruction trap none none - - vector base+ $f6 swi none none - - vector base+ $f4 d2di error interrupt x bit none yes yes vector base+ $f2 d2di external interrupt i bit d2dctl (d2die) yes yes vector base+ $f0 rti timeout interrupt i bit cpmuint (rtie) 3.22.6 interrupts vector base + $ee to vector base + $da reserved vector base + $d8 spi i bit spicr1 (spie, sptie) no yes vector base + $d6 to vector base + $ca reserved vector base + $c8 oscillator status interrupt i bit cpmuint (oscie) no no vector base + $c6 pll lock interrupt i bit cpmuint (lockie) no no vector base + $c4 to vector base + $bc reserved
embedded microcontroller - overview mm912_637, rev. 3.0 freescale semiconductor 208 5.15.9.3 effects of reset when a reset occurs, mcu registers and control bits are initializ ed. refer to the respective blo ck sections for register reset states. on each reset, the flash module executes a reset sequence to load flash c onfiguration registers. 5.15.9.3.1 flash configur ation reset sequence phase the flash module will hold cpu on each reset activity while loading flash module registers from the flash memory. if double faults are detected in the reset phase, flash module protection and security may be active on leaving reset. this is explained in more detail in the flash module, section 5.24.6, ?initialization" . 5.15.9.3.2 reset while flash command active if a reset occurs while any flash command is in progress, that command will be immediately aborted. the state of the word being programmed or the sector/block being erased is not guaranteed. 5.15.9.3.3 i/o pins refer to the pim section for reset confi gurations of all peripheral module ports. 5.15.9.3.4 memory the ram arrays are not initialized out of reset. 5.15.10 cop configuration the cop timeout rate bits cr[2:0] and t he wcop bit in the cpmucop register at address 0x003c are loaded from the flash register fopt. see ta b l e 289 and table 290 for coding. the fopt register is loaded fr om the flash configuration field byte at global address 0x3_ff0e during the reset sequence. vector base + $ba flash error i bit fercnfg (sfdie, dfdie) no no vector base + $b8 flash command i bit fcnfg (ccie) no yes vector base + $b6 to vector base + $8c reserved vector base + $8a low-voltage interrupt (lvi) i bit cpmuctrl (lvie) no yes vector base + $88 to vector base + $82 reserved vector base + $80 spurious interrupt ? none - - notes 236.16-bit vector address based table 289. initial cop rate configuration nv[2:0] in fopt register cr[2:0] in co pctl register 000 111 001 110 010 101 011 100 table 288. interrupt vector locations (sheet 2 of 2) vector address (236) interrupt source ccr mask local enable wake-up from stop wake-up from wait
embedded microcontroller - overview mm912_637, rev. 3.0 freescale semiconductor 209 100 011 101 010 110 001 111 000 table 290. initial wcop configuration nv[3] in fopt register wcop in copctl register 1 0 0 1 table 289. initial cop rate configuration nv[2:0] in fopt register cr [2:0] in copctl register
mcu - port integration module (9s12i128pimv1) mm912_637, rev. 3.0 freescale semiconductor 210 5.16 mcu - port integration module (9s12i128pimv1) 5.16.1 introduction the port integration module (pim) establishes the interf ace between the s12i128 peripheral modules spi and die-to-die interface module (d2di) to the i/o pins of the mcu. all port a and port e pins support general purpose i/o functionalit y, if not in use with other fu nctions. the pim controls the signal prioritization and multiplexing on shared pins. 5.16.1.1 overview figure 52 is a block diagram of th e port integration module. figure 52. port integration module - block diagram 5.16.1.2 features ? 8-pin port a associated with the spi module ? 2-pin port c used as d2di clock output and d2di interrupt input ? 8-pin port d used as 8 or 4 bit data i/o for the d2di module ? 2-pin port e associated with the cpmu osc module ? gpio function shared on port a and e pins ? pull-down devices on pc1 and pd7-0 if used as d2di inputs ? reduced drive capability on pc0 and pd7-0 on per pin basis the port integration module includes these distinctive registers: ? data registers for ports a and e when used as general purpose i/o ? data direction registers for ports a and e when used as general purpose i/o ? port input register on ports a and e ? reduced drive register on port c and d d2dclk d2dint d2ddat0 d2ddat1 d2di die-to-die if d2ddat2 d2ddat3 d2ddat4 d2ddat5 d2ddat6 d2ddat7 pd3 pd0 pd1 pd2 pd4 pd5 pd6 pd7 pc0 pc1 pe0 pe1 ddre porte cpmu osc extal xtal pa3 pa0 pa1 pa2 pa4 pa5 miso mosi sck ss spi synchronous serial if ddra porta pa6 pa7 analog mcu
mcu - port integration module (9s12i128pimv1) mm912_637, rev. 3.0 freescale semiconductor 211 5.16.2 external signal description this section lists and describes the signals that do connect off-chip. table 291 shows all the pins and their functions that are controlled by the port integration module. note if there is more than one function associated with a pin, the priority is indicated by the position in the table from top (highest priority) to bottom (lowest priority). 5.16.3 memory map and register definition this section provides a detailed description of all port integration module registers. 5.16.3.1 memory map table 291. pin functions and priorities port pin name pin function & priority i/o description pin function after reset a pa7 gpio i/o general-purpose i/o gpi pa6 gpio i/o general-purpose i/o pa5 gpio i/o general-purpose i/o pa4 gpio i/o general-purpose i/o pa3 ss i/o serial peripheral interface 0 slave select output in master mode, input in slave or master mode gpio i/o general-purpose i/o pa2 sck i/o serial peripheral interface 0 serial clock pin gpio i/o general-purpose i/o pa1 mosi i/o serial peripheral interface 0 master out/slave in pin gpio i/o general-purpose i/o pa0 miso i/o serial peripheral interface 0 master in/slave out pin gpio i/o general-purpose i/o e pe1 xtal - cpmu osc xtal pin gpi gpio i/o general-purpose i/o pe0 extal - cpmu osc extal pin gpio i/o general-purpose i/o table 292. pim register summary register name bit 7 6 5 4 3 2 1 bit 0 0x0000 porta r pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 w 0x0001 porte r 0 0 0 0 0 0 pe1 pe0 w 0x0002 ddra r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 w 0x0003 ddre r 0 0 0 0 0 0 ddre1 ddre0 w
mcu - port integration module (9s12i128pimv1) mm912_637, rev. 3.0 freescale semiconductor 212 5.16.3.2 port a data register (porta) read: anytime. ? write: anytime. 0x0004- 0x0009 reserved r 0 0 0 0 0 0 0 0 w 0x000c pucr r 0 bkpue 0 0 0 0 pdpee 0 w 0x000d rdriv r 0 0 0 0 rdpd rdpc 0 0 w 0x0120 ptia r ptia7 ptia6 ptia5 ptia4 ptia3 ptia2 ptia1 ptia0 w 0x0121 ptie r 0 0 0 0 0 0 ptie1 ptie0 w 0x0122- 0x017f reserved r 0 0 0 0 0 0 0 0 w = unimplemented or reserved table 293. port a data register (porta) address 0x0000 access: user read/write 7 6 5 4 3 2 1 0 r pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 w spi function ? ? ? ? ss sck mosi miso reset 0 0 0 0 0 0 0 0 table 294. porta register field descriptions field description 7?4 pa port a general purpose input/output data ?data register in / output mode the register bit is driven to the pin. if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buff ered and synchronized pin input state is read. 3 pa port a general purpose input/output data ?data register, spi ss input/output when not used with the alternative function , this pin can be used as general purpose i/o. in general purpose output mode the register bit is driven to the pin. if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buff ered pin input state is read. the spi function takes precedence over the general purpose i/o function if enabled. 2 pa port a general purpose input/output data ?data register, spi sck input/output when not used with the alternative function , this pin can be used as general purpose i/o. in general purpose output mode the register bit is driven to the pin. if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buff ered pin input state is read. the spi function takes precedence over the general purpose i/o function if enabled. table 292. pim register summary register name bit 7 6 5 4 3 2 1 bit 0
mcu - port integration module (9s12i128pimv1) mm912_637, rev. 3.0 freescale semiconductor 213 5.16.3.3 port e data register (porte) read: anytime. ? write: anytime. 1 pa port a general purpose input/output data ?data register, spi mosi input/output when not used with the alternative function , this pin can be used as general purpose i/o. in general purpose output mode the register bit is driven to the pin. if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buff ered pin input state is read. the spi function takes precedence over the general purpose i/o function if enabled. 0 pa port a general purpose input/output data ?data register, spi miso input/output when not used with the alternative function , this pin can be used as general purpose i/o. in general purpose output mode the register bit is driven to the pin. if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buff ered pin input state is read. the spi function takes precedence over the general purpose i/o function if enabled. table 295. port e data register (porte) address 0x0001 access: user read/write 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 pe1 pe0 w cpmu osc function ? ? ? ? ? ? xtal extal reset 0 0 0 0 0 0 0 0 table 296. porte register field descriptions field description 1 pe port e general purpose input/output data ?data register, cpmu osc xtal signal when not used with the alternative function , this pin can be used as general purpose i/o. in general purpose output mode the register bit is driven to the pin. if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buff ered pin input state is read. the cpmu osc function takes prec edence over the general purpose i/o function if enabled. 0 pe port e general purpose input/output data ?data register, cpmu osc extal signal when not used with the alternative function , this pin can be used as general purpose i/o. in general purpose output mode the register bit is driven to the pin. if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buff ered pin input state is read. the cpmu osc function takes prec edence over the general purpose i/o function if enabled. table 294. porta register field descriptions field description
mcu - port integration module (9s12i128pimv1) mm912_637, rev. 3.0 freescale semiconductor 214 5.16.3.4 port a data direction register (ddra) read: anytime. ? write: anytime. 5.16.3.5 port e data direction register (ddre) read: anytime. ? write: anytime. table 297. port a data direction register (ddra) address 0x0002 access: user read/write 7 6 5 4 3 2 1 0 r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 w reset 0 0 0 0 0 0 0 0 table 298. ddra register field descriptions field description 7?4 ddra port a data direction ? this bit determines whether the associated pin is an input or output. 1 associated pin is configured as output. 0 associated pin is configured as input. 3?0 ddra port a data direction ? this bit determines whether the associated pin is an input or output. depending on the configuration of the enabled spi the i/o state will be forced to input or output. in this case, the data direc tion bits will not change. 1 associated pin is configured as output. 0 associated pin is configured as input. table 299. port e data direction register (ddre) address 0x0003 access: user read/write 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 ddre1 ddre0 w reset 0 0 0 0 0 0 0 0 table 300. ddre register field descriptions field description 1?0 ddre port e data direction ? this bit determines whether the asso ciated pin is an input or output. the enabled cpmu osc function connects the associated pins directly to the oscillator module. in this case, the data direction bits will not change. 1 associated pin is configured as output. 0 associated pin is configured as input.
mcu - port integration module (9s12i128pimv1) mm912_637, rev. 3.0 freescale semiconductor 215 5.16.3.6 pull-up control register (pucr) read: anytime. ? write: anytime. 5.16.3.7 reduced drive register (rdriv) read: anytime. ? write: anytime. table 301. pull control register (pucr) address 0x000c access: user read/write 7 6 5 4 3 2 1 0 r 0 bkpue 0 0 0 0 pdpee 0 w reset 0 1 0 0 0 0 1 0 table 302. pucr register field descriptions field description 6 bkpue bkgd pin pull-up enable?enabl e pull-up devices on bkgd pin this bit configures whether a pull-up devi ce is activated, if the pin is used as input. this bit has no effect if the pin is used as output. out of reset the pull-up device is enabled. 1 pull-up device enabled. 0 pull-up device disabled. 1 pdpee pull-down port e enable?enable pull- down devices on all port e input pins this bit configures whether pull-down devices are activated, if the pins are used as inputs. this bit has no effect if the pins are used as outputs. out of reset the pull-down devices are enabled. if the cpmu osc function is active, the pull-down dev ices are disabled. in this case, the register bit will not change. 1 pull-down devices enabled. 0 pull-down devices disabled. table 303. reduced drive register (rdriv) address 0x000d access: user read/write 7 6 5 4 3 2 1 0 r 0 0 0 0 rdpd rdpc 0 0 w reset 0 0 0 0 0 0 0 0 table 304. rdriv register field descriptions field description 3 rdpd port d reduced drive ? select reduced drive for output pins this bit configures the drive strength of out put pins as either full or reduced. if a pi n is used as input, this bit has no eff ect. 1 reduced drive selected (1/5 of the full drive strength) 0 full drive strength enabled 2 rdpc port c reduced drive ? select reduced drive for d2dclk output pin this bit configures the drive strength of d2 dclk output pin as either full or reduced. 1 reduced drive selected (1/5 of the full drive strength) 0 full drive strength enabled
mcu - port integration module (9s12i128pimv1) mm912_637, rev. 3.0 freescale semiconductor 216 5.16.3.8 port a input register (ptia) read: anytime. ? write: unimplemented. writing to this register has no effect. 5.16.3.9 port e input register (ptie) read: anytime. ? write: unimplemented. writing to this register has no effect. table 305. port a input register (ptia) address 0x0120 access: user read 7 6 5 4 3 2 1 0 r ptia7 ptia6 ptia5 ptia4 ptia3 ptia2 ptia1 ptia0 w reset (237) u u u u u u u u notes 237.u = unaffected by reset table 306. ptia register field descriptions field description 7?0 ptia port a input data ? a read always returns the buffered input state of the associat ed pin. it can be used to detect ov erload or short-circuit condit ions on output pins. table 307. port e input register (ptie) address 0x0121 access: user read 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 ptie1 ptie0 w reset (238) u u u u u u u u notes 238.u = unaffected by reset table 308. ptie register field descriptions field description 1?0 ptie port e input data ? a read always returns the buffered input state of the associat ed pin. it can be used to detect ov erload or short-circuit condit ions on output pins.
mcu - port integration module (9s12i128pimv1) mm912_637, rev. 3.0 freescale semiconductor 217 5.16.4 functional description 5.16.4.1 registers 5.16.4.1.1 data register (portx) this register holds the value driven out to the pi n, if the pin is used as a general purpose i/o. writing to this register has only an effect on the pin, if the pin is used as gener al purpose output. when reading this address , the buffered and synchronized state of the pin is returned, if th e associated data direction register bit is set to ?0?. if the data direction register bits are set to logic level ?1?, the contents of the data regist er is returned. this is independ ent of any other configuration ( figure 53 ). 5.16.4.1.2 data direction register (ddrx) this register defines whether the pi n is used as an input or an output. if a peripheral module controls the pin the cont ents of the data direction register is ignored ( figure 53 ). 5.16.4.1.3 input register (ptix) this is a read-only register and always returns the buffered and synchronized state of the pin ( figure 53 ). figure 53. illustration of i/o pin functionality 5.16.4.1.4 reduced drive register (rdriv) if the pin is used as an output , this register allows the conf iguration of the drive strength. 5.16.4.1.5 pull device en able register (pucr) this register turns on a pull-up or pull-down device. it becomes active only if the pin is used as an input. portx ddrx output enable port enable 1 0 1 0 pin data out periph. data in module 1 0 synch. ptix
mm912_637, rev. 3.0 freescale semiconductor 218 5.16.4.2 ports 5.16.4.2.1 port a this port is associated with the spi. port a pins pa7-0 ca n be used for general purpose i/o and pa3-0 also with the spi subsystem. 5.16.4.2.2 port e this port is associated with the cpmu osc. port e pins pe1-0 can be used for general purpose or with the cpmu osc module. 5.16.5 initialization information 5.16.5.1 port data and data direction register writes writing ptx and ddrx in a word access is not recommended. when changing the register pins from inputs to outputs, the data may have extra transitions during the write access. initialize the port data register before enabling the outputs.
mcu - interrupt module (s12sintv1) mm912_637, rev. 3.0 freescale semiconductor 219 5.17 mcu - interrupt module (s12sintv1) 5.17.1 introduction the int module decodes the priori ty of all system exception requ ests and provides the applicab le vector for processing the exception to the cpu. the int module supports: ?i bit and x bit maskable interrupt requests ? a non-maskable unimplemented op-code trap ? a non-maskable software interrupt (swi) or background debug mode request ? three system reset vector requests ? a spurious interrupt vector each of the i bit maskable interrupt requests is assigned to a fixed priority level. 5.17.1.1 glossary table 309 contains terms and abbreviations used in the document. 5.17.1.2 features ? interrupt vector base register (ivbr) ? one spurious interrupt vector (at address vector base (239) + 0x0080). ? 2?58 i bit maskable interrupt vector requests (at addresses vector base + 0x0082?0x00f2) ?i bit maskable interrupts can be nested ?one x bit maskable interrupt vector request (at address vector base + 0x00f4) ? one non-maskable software interrupt request (swi) or ba ckground debug mode vector request (at address vector base + 0x00f6) ? one non-maskable unimplemented op-code trap (trap) vector (at address vector base + 0x00f8) ? three system reset vectors (a t addresses 0xfffa?0xfffe) ? determines the highest priority interrupt vector reques ts, drives the vector to the bus on cpu request ? wakes up the system from stop or wait mode when an appropriate interrupt request occurs notes 239.the vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (ivbr, use d as upper byte) and 0x00 (used as lower byte). table 309. terminology term meaning ccr condition code register (in the cpu) isr interrupt service routine mcu micro-controller unit analog mcu
mcu - interrupt module (s12sintv1) mm912_637, rev. 3.0 freescale semiconductor 220 5.17.1.3 modes of operation ?run mode this is the basic mode of operation. ? wait mode in wait mode, the clock to the int m odule is disabled. the int module is however capable of waking up the cpu from wait mode, if an interrupt occurs. refer to section 5.17.5.3, ?wake-up from stop or wait mode" ? for details ? stop mode in stop mode, the clock to the int module is disabled. t he int module is however capable of waking up the cpu from stop mode, if an interrupt occurs. refer to section 5.17.5.3, ?wake-up from stop or wait mode" ? for details ? freeze mode (bdm active) in freeze mode (bdm active), the interrupt vector base register is overridden internally. refer to section 5.17.3.1.1, ?interrupt vector base register (ivbr)" ? for details 5.17.1.4 block diagram figure 54 shows a block diagram of the int module. figure 54. int block diagram 5.17.2 external signal description the int module has no external signals. 5.17.3 memory map and register definition this section provides a detailed description of all registers accessible in the int module. 5.17.3.1 register descriptions this section describes in address order all the int registers and their individual bits. 5.17.3.1.1 interrupt vector base register (ivbr) wake-up ivbr interrupt requests interrupt requests cpu vector address peripheral to c p u priority decoder non i bit maskable channels i bit maskable channels
mcu - interrupt module (s12sintv1) mm912_637, rev. 3.0 freescale semiconductor 221 read: anytime. ? write: anytime. 5.17.4 functional description the int module processes all exception requests to be serviced by the cpu module. these exceptions include interrupt vector requests and reset vector requests. each of these exception types and their overall pr iority level is discussed in the followin g subsections. 5.17.4.1 s12s exception requests the cpu handles both reset requests and interrupt requests. a pr iority decoder is used to ev aluate the priority of pending interrupt requests. 5.17.4.2 interrupt prioritization the int module contains a priority decoder to determine the priority for all interrupt requests pending for the cpu. if more th an one interrupt request is pending, the interrupt request with the higher vector address wins the prioritization. the following conditions must be met for an i bit maskable interrupt request to be processed. 1. the local interrupt enabled bit in the peripheral module must be set. 2. the i bit in the condition code register (ccr) of the cpu must be cleared. 3. there is no swi, trap, or x bit maskable request pending. note all non i bit maskable interrupt requests always have higher priority than the i bit maskable interrupt requests. if the x bit in the ccr is cleared, it is possible to interrupt an i bit maskable interrupt by an x bit maskable interrupt. it is possible to nest non maskable interrupt requests, e.g., by nesting swi or trap calls. since an interrupt vector is only supplied at the time when the cpu requests it, it is possible that a higher priority interrup t request could override the original interrupt reque st that caused the cpu to request the vect or. in this case, the cpu will receive the highest priority vector and the system will process this interru pt request first, before the or iginal interrupt request is proc essed. if the interrupt source is unknown (for ex ample, in the case where an interrupt re quest becomes inactive after the interrupt ha s been recognized, but prior to the cpu vector request), the vector address supplied to t he cpu will default to that of the spuri ous interrupt vector. table 310. interrupt vector base register (ivbr) address: 0x001f 7 6 5 4 3 2 1 0 r ivb_addr[7:0] w reset 1 1 1 1 1 1 1 1 table 311. ivbr field descriptions field description 7?0 ivb_addr[7:0] interrupt vector base address bits ? these bits represent the upper byte of all vector addresses. out of reset, these bits are set to 0xff (i.e., vectors are located at 0xff80?0xfffe) to ensure compatibility to hcs12. note: a system reset will initialize the interrupt vector base regi ster with ?0xff? before it is used to determine the reset vector address. therefore, changing the ivbr has no ef fect on the location of the three reset vectors (0xfffa?0xfffe). note: if the bdm is active (i.e., the cpu is in the process of executing bdm firmware code), the contents of ivbr are ignored and the upper byte of the vector address is fi xed as ?0xff?. this is done to enable handling of all non-maskable interrupts in the bdm firmware.
mcu - interrupt module (s12sintv1) mm912_637, rev. 3.0 freescale semiconductor 222 note care must be taken to ensure that all inte rrupt requests remain active until the system begins execution of the applicable service routin e; otherwise, the exception request may not get processed at all or the result may be a spurious interrupt reque st (vector at address (vector base + 0x0080)). 5.17.4.3 reset exception requests the int module supports three system reset exception request types (refer to the clock and reset generator module for details): 1. pin reset, power-on reset or illegal address reset, low voltage reset (if applicable) 2. clock monitor reset request 3. cop watchdog reset request 5.17.4.4 exception priority the priority (from highest to lowest) and address of all excepti on vectors issued by the int modu le upon request by the cpu is shown in ta b l e 312 . 5.17.5 initialization/app lication information 5.17.5.1 initialization after a system reset, the software should: 1. initialize the interrupt vector base register, if the interrupt vector table is not located at the default location (0xff80?0xfff9). 2. enable i bit maskable interrupts by clearing the i bit in the ccr. 3. enable the x bit maskable interrupt by clearing the x bit in the ccr. table 312. exception vector map and priority vector address (240) source 0xfffe pin reset, power-on reset, illegal address reset, low voltage reset (if applicable) 0xfffc clock monitor reset 0xfffa cop watchdog reset (vector base + 0x00f8) unimplemented opcode trap (vector base + 0x00f6) software interrupt instruction (swi) or bdm vector request (vector base + 0x00f4) x bit maskable interrupt request (xirq or d2d error interrupt) (241) (vector base + 0x00f2) irq or d2d interrupt request (242) (vector base + 0x00f0?0x0082) device specific i bit maskable interru pt sources (priority determined by the low byte of the vector address, in descending order) (vector base + 0x0080) spurious interrupt notes 240.16-bit vector address based 241.d2d error interrupt on mcus featuring a d2d initiator module, otherwise xirq pin interrupt 242.d2d interrupt on mcus featuring a d2d initiator module, otherwise irq pin interrupt
mcu - interrupt module (s12sintv1) mm912_637, rev. 3.0 freescale semiconductor 223 5.17.5.2 interrupt nesting the interrupt request scheme makes it possible to nest i bit maskable interrupt requests handled by the cpu. i bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority. i bit maskable interrupt requests cannot be interrupted by other i bit maskable interrupt requests per default. in order to make an interrupt service routine (isr) interruptib le, the isr must explicitly clear the i bit in the ccr (cli). after clearing the i bit, other i bit maskable interrupt requests can interrupt the current isr. an isr of an interruptible i bit maskable interrupt request could basically look like this: 1. service interrupt, e.g., clear interrupt flags, copy data, etc. 2. clear i bit in the ccr by executing the in struction cli (thus allowing other i bit maskable interrupt requests) 3. process data 4. return from interrupt by executing the instruction rti 5.17.5.3 wake-up from stop or wait mode 5.17.5.3.1 cpu wake-up fr om stop or wait mode every i bit maskable interrupt request is capable of waking the mcu from stop or wait mode. to determine whether an i bit maskable interrupts is qualified to wake-up the cpu, the same co nditions as in normal run mode are applied during stop or wait mode: if the i bit in the ccr is set, all i bit maskable interrupts are masked from waking up the mcu. since there are no clocks running in stop mode, only interrupts which can be asse rted asynchronously can wake-up the mcu from stop mode. note the only asynchronously asserted, i bit maskable interrupt for the mm912_637 would be the ?d2d external interrupt?. the x bit maskable interrupt request can wake-up the mcu from stop or wait mode at anytime, ev en if the x bit in ccr is set. if the x bit maskable interrupt request is used to wake-up the m cu with the x bit in the ccr set, the associated isr is not cal led. the cpu then resumes program execution wit h the instruction following the wai or stop instruction. this features works the same rules as with any interrupt request, i.e. care must be ta ken that the x interrupt request used for wake-up remains active at least until the system begins exec ution of the instruction follow ing the wai or stop instructio n; otherwise, wake-up may not occur. note the only x bit maskable interrupt for the mm912_637 would be the d2d error interrupt. as the d2d initiator module is not active during stop and wait mode, no x bit maskable interrupt source is existing for the mm912_637.
memory map control (s12pmmcv1) mm912_637, rev. 3.0 freescale semiconductor 224 5.18 memory map control (s12pmmcv1) 5.18.1 introduction the s12pmmc module controls the access to all internal memories and peripherals for the cpu12 and s12sbdm module. it regulates access priorities and determines t he address mapping of the on-chip resources. figure 55 shows a block diagram of the s12pmmc module. 5.18.1.1 glossary 5.18.1.2 overview the s12pmmc connects the cpu12?s and the s12sbdm?s bus interfaces to the mcu?s on-chip resources (memories and peripherals). it arbitrates the bus accesse s and determines all of the mcu?s memory maps. furthermore, the s12pmmc is responsible for constraining memory accesses on secured devices and for selecting th e mcu?s functional mode. 5.18.1.3 features the main features of this block are: ? paging capability to support a global 256 kbyte memory address space ? bus arbitration between the masters cp u12, s12sbdm to different resources ? mcu operation mode control ? mcu security control ? separate memory map schemes for each master cpu12, s12sbdm ? generation of system reset when cpu12 accesses an unimp lemented address (i.e., an address which does not belong to any of the on-chip modules) in single-chip modes 5.18.1.4 modes of operation the s12pmmc selects the mcu?s functional mode. it also determines the devices behavior in secured and unsecured state. table 313. glossary of terms term definition local address address within the cpu12?s local address map ( figure 60 ) global address address within the global address map ( figure 60 ) aligned bus access bus access to an even address. misaligned bus access bus access to an odd address. ns normal single-chip mode ss special single-chip mode unimplemented address ranges address ranges which are not mapped to any on-chip resource. p-flash program flash d-plash data flash nvm non-volatile memory; p-flash or d-flash ifr nvm information row. refer to ftmrc block guide analog mcu
memory map control (s12pmmcv1) mm912_637, rev. 3.0 freescale semiconductor 225 5.18.1.4.1 functional modes two functional modes are implemented on devices of the s12i product family: ? normal single chip (ns) ? the mode used for running applications. ? special single chip mode (ss) ? a debug mode which causes the device to enter bdm active mode after each reset. peripherals may also provide special debug features in this mode 5.18.1.4.2 security s12i devices can be secured to prohibit external access to th e on-chip p-flash. the s12pmmc module determines the access permissions to the on-chip memories in secured and unsecured state. 5.18.1.5 block diagram figure 55 shows a block diagram of the s12pmmc. figure 55. s12pmmc block diagram 5.18.2 external signal description the s12pmmc uses two external pins to determi ne the devices operating mode: reset and modc ( ta b l e 314 ) see device user guide (dug) for the mapping of these signals to device pins. cpu bdm target bus controller dbg mmc address decoder & priority peripherals p-flash d-flash ram
memory map control (s12pmmcv1) mm912_637, rev. 3.0 freescale semiconductor 226 5.18.3 memory map and registers 5.18.3.1 module memory map a summary of the register s associated with the s12pmmc block is shown in ta b l e 315 . detailed descriptions of the registers and bits are given in the subsections that follow. 5.18.3.2 register descriptions this section consists of th e s12pmmc control register descriptions in address order. table 314. external system pins associated with s12pmmc pin name pin functions description reset ( see dug) reset the reset pin is used the select the mcu?s operating mode. modc ( see dug) modc the modc pin is captured at the rising edge of the reset pin. the captured value determines the mcu?s operating mode. table 315. mmc register table address register name bit 7 6 5 4 3 2 1 bit 0 0x000a reserved r 0 0 0 0 0 0 0 0 w 0x000b mode r modc 0 0 0 0 0 0 0 w 0x0010 reserved r 0 0 0 0 0 0 0 0 w 0x0011 direct r dp15 dp14 dp13 dp12 dp11 dp10 dp9 dp8 w 0x0012 reserved r 0 0 0 0 0 0 0 0 w 0x0013 reserved r 0 0 0 0 0 0 0 0 w 0x0014 reserved r 0 0 0 0 0 0 0 0 w 0x0015 ppage r 0 0 0 0 pix3 pix2 pix1 pix0 w = unimplemented or reserved
memory map control (s12pmmcv1) mm912_637, rev. 3.0 freescale semiconductor 227 5.18.3.2.1 mode register (mode) read: anytime. ? write: only if a transition is allowed (see figure 56 ). ? the modc bit of the mode register is used to select the mcu?s operating mode. figure 56. mode transition diagra m when mcu is unsecured table 316. mode register (mode) address: 0x000b 7 6 5 4 3 2 1 0 r modc 0 0 0 0 0 0 0 w reset modc (243) 0 0 0 0 0 0 0 = unimplemented or reserved notes 243.external signal (see table 314 ). table 317. mode field descriptions field description 7 modc mode select bit ? this bit controls the current operating mode during reset high (inactive). the external mode modc pin determines the operating mode during reset low (active). the state of the pin is regi stered into the respective register bit after the reset signal goes inactive (see figure 56 ). write restrictions exist to disall ow transitions between certain modes. figure 56 illustrates all allowed mode changes. attempting non authorized transitions will not change the mode bit, but it will bl ock further writes to the register bit except in special modes. write accesses to the mode register are blocked when the device is secured. normal single-chip 1 special single-chip 0 (ss) reset (ns) 1 0 1
memory map control (s12pmmcv1) mm912_637, rev. 3.0 freescale semiconductor 228 5.18.3.2.2 direct page register (direct) read: anytime. ? write: anytime in special ss, write-one in ns. this register determines the posit ion of the 256 byte direct page within the memo ry map.it is valid for both global and local mapping scheme. figure 57. direct address mapping example 1. this example demonstrates usage of the direct addressing mode movb #$80,direct ;set direct register to 0x80. write once only. ;global data accesses to the range 0xxx_80xx can be direct. ;logical data accesses to the range 0x80xx are direct. ldy <$00 ;load the y index register from 0x8000 (direct access). ;< operator forces direct access on some assemblers but in ;many cases assemblers are ?direct page aware? and can ;automatically select direct mode. table 318. direct register (direct) address: 0x0011 7 6 5 4 3 2 1 0 r dp15 dp14 dp13 dp12 dp11 dp10 dp9 dp8 w reset 0 0 0 0 0 0 0 0 table 319. direct field descriptions field description 7?0 dp[15:8] direct page index bits 15?8 ? these bits are used by the cpu when perform ing accesses using the direct addressing mode. these register bits form bits [15:8] of the local address (see figure 57 ). bit15 bit0 bit7 cpu address [15:0] bit8 dp [15:8]
memory map control (s12pmmcv1) mm912_637, rev. 3.0 freescale semiconductor 229 5.18.3.2.3 program page index register (ppage) read: anytime. ? write: anytime. these four index bits are used to map 16 kb blocks into the flash page window locat ed in the local (cpu or bdm) memory map, from address 0x8000 to address 0xbfff (see figure 58 ). this supports accessing up to 256 kb of flash (in the global map) within the 64 kb local map. the ppage index register is effectively us ed to construct paged flash addresses in the local map format. the cpu has special access to read and write this regist er directly during execution of call and rtc instructions. figure 58. ppage address mapping note writes to this register using the special a ccess of the call and rtc instructions will be complete before the end of the instruction execution. the fixed 16 kb page from 0x0000 to 0x3fff is the page number 0x0c. pa rts of this page are covered by registers, d-flash and ram space. see the soc guide for details. the fixed 16 kb page from 0x4000?0x7fff is the page number 0x0d. the reset value of 0x0e ensures that there is linear flash space available between addresses 0x0000 and 0xffff out of reset. the fixed 16 kb page from 0xc000-0xffff is the page number 0x0f. table 320. program page index register (ppage) address: 0x0030 7 6 5 4 3 2 1 0 r 0 0 0 0 pix3 pix2 pix1 pix0 w reset 0 0 0 0 1 1 1 0 table 321. ppage field descriptions field description 3?0 pix[3:0] program page index bits 3?0 ? these page index bits are used to select wh ich of the 256 p-flash or rom array pages is to be accessed in the program page window. bit14 bit0 address [13:0] ppage register [3:0] global address [17:0] bit13 bit17 address: cpu local address or bdm local address
memory map control (s12pmmcv1) mm912_637, rev. 3.0 freescale semiconductor 230 5.18.4 functional description the s12pmmc block performs several basic functions of the s12i sub-system operation: mcu operatio n modes, priority control, address mapping, select si gnal generation, and access limitations for t he system. each aspect is described in the following subsections. 5.18.4.1 mcu operating modes ? normal single chip mode this is the operation mode for running applicati on code. there is no external bus in this mode. ? special single chip mode this mode is generally used for debugging operation, boot- strapping or security related operations. the active background debug mode is in control of the cpu code execut ion and the bdm firmware is waiting for serial commands sent through the bkgd pin. 5.18.4.2 memory map scheme 5.18.4.2.1 cpu and bdm memory map scheme the bdm firmware lookup tables and bdm register memory loca tions share addresses with other modules; however they are not visible in the memory map during user?s code execution. the bdm memory resources are enabled only during the read_bd and write_bd access cycles to distinguish between accesses to the bdm memory area and accesses to the other modules. (refer to the bdm block guide for further details). when the mcu enters active bdm mode, th e bdm firmware look-up tables and the bdm registers become visible in the local memory map in the range 0xff00-0xffff (global address 0x3_ff00 - 0x3_ffff) and the cpu begins execution of firmware commands or the bdm begins execution of hardware comman ds. the resources which share memory space with the bdm module will not be visible in the memory map during active bdm mode. note that after the mcu enters active bdm mode the bdm firmw are look-up tables and the bdm registers will also be visible between addresses 0xbf00 and 0xbfff if the ppage register contains value of 0x0f. 5.18.4.2.1.1 expansion of the local address map 5.18.4.2.1.1.1 expansion of the cpu local address map the program page index register in s12pmmc allows accessing up to 256 kb of p-flash in the global memory map by using the four index bits (ppage[3:0]) to page 16x16 kb blocks into the program page window, located from addre ss 0x8000 to address 0xbfff in the local cpu memory map. the page value for the program page window is stored in the ppag e register. the value of the pp age register can be read or written by normal memory accesses as well as by the call and rtc instructions (see section 5.18.6.1, ?call and rtc instructions" ). control registers, vector space and parts of the on-chip memories are located in unpaged portions of the 64 kb local cpu address space. the starting address of an interrupt servic e routine must be located in unpaged memory unless the user is certain that the ppag e register will be set to the appropriate va lue when the service routine is called. howe ver an interrupt service routine can call other routines that are in paged memory. the upper 16 kb block of the local cpu memory space (0xc000?0xffff) is unpaged. it is recommended that all reset and interrupt vectors point to location s in this area or to the other unmapped pages sections of the local cpu memory map. 5.18.4.2.1.1.2 expansion of the bdm local address map ppage and bdmppr register is also used for the expansion of the bdm local address to the global address. these registers can be read and written by the bdm. the bdm expansion scheme is the sa me as the cpu expansion scheme.
memory map control (s12pmmcv1) mm912_637, rev. 3.0 freescale semiconductor 231 the four bdmppr program page index bits allow access to the full 256 kb address map that can be accessed with 18 address bits. the bdm program page index register (bdmppr) is used only when t he feature is enabled in bdm and, in the case the cpu is executing a firmware command which uses cpu instructions, or by a bdm hardware commands. see the bdm block guide for further details. (see figure 59 ). figure 59. bdmppr address mapping bdm hardware command bdm firmware command bit14 bit0 bdm local address [13:0] bdmppr register [3:0] global address [17:0] bit13 bit17 bit14 bit0 cpu local address [13:0] bdmppr register [3:0] global address [17:0] bit13 bit17
memory map control (s12pmmcv1) mm912_637, rev. 3.0 freescale semiconductor 232 figure 60. local to global address mapping 0x3_ffff ppage cpu and bdm local memory map global memory map 0xffff 0xc000 0x8000 p-flash window 0x3_4000 0x3_8000 0x3_c000 0x0_4000 0x0000 0x4000 0x0400 d-flash ram unpaged p-flash registers unpaged p-flash unpaged p-flash 0 p0 p1 p2 p3 0 0 0 0x1400 ramsize 0x0_0000 ram ramsize 10 *16k paged p-flash 0x0_8000 nvm resources registers ram_low unpaged p-flash 0x3_0000 unimplemented area unpaged p-flash unpaged p-flash (ppage 0x0c) (ppage 0x0d) (ppage 0x0e) (ppage 0x0f) unpaged p-flash or (ppage 0x02-0x0b)) (ppage 0x01) (ppage 0x00) unpaged p-flash 0x0_4400 d-flash 0x0_5400 nvm resources
memory map control (s12pmmcv1) mm912_637, rev. 3.0 freescale semiconductor 233 5.18.5 implemented memory in th e system memory architecture each memory can be implemented in its maximum allowed size. but some devices have been defined for smaller sizes, which means less implemented pages. all non implem ented pages are called unimplemented areas. ? registers has a fixed size of 1.0 kb, accessible via xbus0 ? sram has a maximum size of 11 kb, accessible via xbus0 ? d-flash has a fixed size of 4.0 kb accessible via xbus0 ? p-flash has a maximum size of 224 kb, accessible via xbus0 ? nvm resources (ifr) including d-flash have maximum size of 16 kb (ppage 0x01) 5.18.5.0.1 implemented memory map the global memory spaces reserved for the internal resource s (ram, d-flash, and p-flash) are not determined by the mmc module. size of the individual internal resources are however fi xed in the design of the device cannot be changed by the user. refer to the soc guide for further details. figure 61 and table 322 show the memory spaces occupied by the on-chip resources. note that the memory spaces have fixed top addresses. in single-chip modes accesses by the cpu12 (except for fi rmware commands) to any of the unimplemented areas (see figure 61 ) will result in an illegal access reset (system reset). bdm accesses to the uni mplemented areas are allowed but the data will be undefined. no misaligned word access from the bdm module will occur; these accesses are blocked in the bdm module (refer to bdm block guide). table 322. global implemented memory space internal resource bottom address top address registers 0x0_0000 0x0_03ff system ram ram_low = 0x0_4000 minus ramsize (244) 0x0_3fff d-flash 0x0_4400 0x0_53ff p-flash pf_low = 0x4_0000 minus flashsize (245) 0x3_ffff notes 244.ramsize is the hexadecimal va lue of ram size in bytes 245.flashsize is the hexadecimal value of flash size in bytes
memory map control (s12pmmcv1) mm912_637, rev. 3.0 freescale semiconductor 234 figure 61. implemented global address mapping 0x3_ffff ppage cpu and bdm local memory map global memory map 0xffff 0xc000 0x8000 p-flash window pf_low unpaged p-flash unpaged p-flash 0 p0 p1 p2 p3 0 0 0 pfsize unimplemented area p-flash 0x0000 0x4000 0x0400 d-flash ram unpaged p-flash registers 0x1400 ramsize 0x0_4000 0x0_0000 ram ramsize 0x0_8000 nvm resources registers ram_low unimplemented area (ppage 0x01) (ppage 0x00) 0x0_4400 d-flash 0x0_5400 nvm resources
memory map control (s12pmmcv1) mm912_637, rev. 3.0 freescale semiconductor 235 5.18.5.1 chip bus control the s12pmmc controls the address buses and the data buses that interface the bus masters (cpu12, s12sbdm) with the rest of the system (master buses). in additi on, the mmc handles all cpu read data bus swapping operations. all internal resources are connected to specific target buses (see figure 62 ). figure 62. s12i platform 5.18.5.1.1 master bus prioritization re garding access conflicts on target buses the arbitration scheme allows only one mast er to be connected to a target at any given time. the following rules apply when prioritizing accesses from different masters to the same target bus: ? cpu12 always has priority over bdm. ? bdm has priority over cpu12 when its access is stalled for more than 128 cycles. in the later case the cpu will be stalled after finishing the current operation and the bdm will gain access to the bus. 5.18.5.2 interrupts the mmc does not generate any interrupts. 5.18.6 initialization/app lication information 5.18.6.1 call and rtc instructions call and rtc instructions are uninterruptable cpu instructions that automate page switching in the program page window. the call instruction is similar to the jsr inst ruction, but the subroutine that is calle d can be located anywhere in the local addr ess space or in any flash or rom page visible through the prog ram page window. the call instruction calculates and stacks a return address, stacks the current ppage value and writes a ne w instruction-supplied value to the ppage register. the ppage value controls which of the 256 possible pages is visible through the 16 kbyte program page window in the 64 kbyte local cpu memory map. execution then begins at the address of the called subroutine. cpu bdm mmc ?crossbar switch? s12x0 xbus0 dbg s12x1 ipbi p-flash d-flash sram bdm resources peripherals
memory map control (s12pmmcv1) mm912_637, rev. 3.0 freescale semiconductor 236 during the execution of the call instruct ion, the cpu performs the following steps: 1. writes the current ppage value into an internal temporary register and writes the new instruction supplied ppage value into the ppage register 2. calculates the address of the next instruction after the call instruction (the return address) and pushes this 16-bit value onto the stack 3. pushes the temporarily stor ed ppage value onto the stack 4. calculates the effective address of the subroutine, refills the queue and begins ex ecution at the new address this sequence is uninterruptable. there is no need to inhibit in terrupts during the call instruction execution. a call instruct ion can be performed from any address to any other address in the local cpu memory space. the ppage value supplied by the instruction is part of the effe ctive address of the cpu. for all addressing mode variations (except indexed-indirect modes), the new page value is provided by an immediate operand in the instruction. in indexed indirect variations of the call instruction, a point er specifies memory locations where the ne w page value and the address of the called subroutine are stored. using indirect addressing for both the ne w page value and the address within the page allows usage of values calculated at run time, rather than immediate values that must be known at the time of assembly. the rtc instruction terminates subroutines invoked by a call instruction. the rtc instruction unstacks the ppage value and the return address and refills the queue. execution resume s with the next instruction after the call instruction. during the execution of an rtc instruct ion the cpu performs the following steps: 1. pulls the previously stored ppage value from the stack 2. pulls the 16-bit return address from the stack and loads it into the pc 3. writes the ppage value into the ppage register 4. refills the queue and resumes execution at the return address this sequence is uninterruptable. the rtc can be executed from anywhere in the local cpu memory space. the call and rtc instructions behave like jsr and rts instruction. however they require more execution cycles. usage of jsr/rts instructions is therefore recommended when possible, and call/rtc instructions shou ld only be used when needed. the jsr and rts instructions can be used to access subroutines that are already present in the local cpu memory map (i.e. in the same page in the program memory page window for example). ho wever calling a function located in a different page requires usage of the call instruction. the functi on must be terminated by the rtc instructio n. because the rtc instruction restores contents of the ppage register from the stack. functions terminated with the rtc instruction must be called using the call instruction, even when the correct page is al ready present in the memory map. this is to make sure that the correct ppage value will be present on the stack at the ti me of the rtc instruction execution.
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 237 5.19 mcu - debug module (s12sdbg) 5.19.1 introduction the s12sdbg module provides an on-chip trace buffer with flex ible triggering capability, to allow non-intrusive debug of application software. the s12sdbg module is optimized for s12scpudebugging. typically, the s12sdbg module is used in conjunction with the s12sbdm module, whereby the user configures the s12sdbg module for a debugging session over the bdm interface. once configured the s12sdbg module is armed, the device leaves bdm returning control to the user program, which is then m onitored by the s12sdbg module . alternatively the s12sdbg module can be configured over a seri al interface using swi routines. 5.19.1.1 glossary of terms cof: change of flow. change in the program flow due to a conditional branch, indexed jump or interrupt. bdm: background debug mode s12sbdm: background debug module dug: device user guide, describing the features of the device into which the dbg is integrated. word: 16-bit data entity data line: 20-bit data entity cpu: s12scpu module dbg: s12sdbg module por: power on reset tag: tags can be attached to cpu opcodes as they enter the instruction pipe. if the tagged opcode reaches the execution stage a tag hit occurs. 5.19.1.2 overview the comparators monitor the bus activity of the cpu module. a ma tch can initiate a state sequenc er transition. on a transition to the final state , bus tracing is triggered and/ or a breakpoint can be generated. independent of comparator matches a transition to final st ate with associated tracing and breakpoint can be triggered immediately by writing to the trig control bit. the trace buffer is visible through a 2-byte window in the re gister address map and can be read out using standard 16-bit word reads. tracing is disabled w hen the mcu system is secured. 5.19.1.3 features ? three comparators (a, b and c) ? comparators a compares the full address bus and full 16-bit data bus ? comparator a features a data bus mask register ? comparators b and c compare the full address bus only ? each comparator features selectio n of read or write access cycles ? comparator b allows selection of byte or word access cycles ? comparator matches can initiate state sequencer transitions ? three comparator modes ? simple address/data comparator match mode ? inside address range mode, addmin ? address ?? addmax ? outside address range match mode, address ?? addmin ? or address ? addmax ? two types of matches ? tagged ? this matches just before a specific instruction begins execution ? force ? this is valid on the first in struction boundary after a match occurs analog mcu
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 238 ? two types of breakpoints ? cpu breakpoint entering bdm on breakpoint (bdm) ? cpu breakpoint executing swi on breakpoint (swi) ? trigger mode independent of comparators ? trig immediate software trigger ? four trace modes ? normal: change of flow (cof) pc information is stored (see section 5.19.4.5.2.1, ?normal mode" ) for change of flow definition. ? loop1: same as normal but inhibits co nsecutive duplicate source address entries ? detail: address and data for all cycles except free cycles and opcod e fetches are stored ? compressed pure pc: all program counter addresses are stored ? 4-stage state sequencer for trace buffer control ? tracing session trigger linked to final state of state sequencer ? begin and end alignment of tracing to trigger 5.19.1.4 modes of operation the dbg module can be used in all mcu functional modes. during bdm hardware accesses and while the bdm module is active, cpu monitoring is disabl ed. when the cpu enters active bdm mode through a background command, the db g module, if already a rmed, remains armed. the dbg module tracing is disabled if the mcu is secure, however, breakpoints can still be generated. table 323. mode dependent restriction summary bdm enable bdm active mcu secure comparator matches enabled breakpoints possible tagging possible tracing possible x x 1 yes yes yes no 0 0 0 yes only swi yes yes 0 1 0 active bdm not possible when not enabled 1 0 0 yes yes yes yes 1 1 0 no no no no
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 239 5.19.1.5 block diagram figure 63. debug module block diagram 5.19.2 external signal description there are no external signals associated with this module. 5.19.3 memory map and registers 5.19.3.1 module memory map a summary of the registers associated with the dbg sub-block is shown in ta b l e 324 . detailed descriptions of the registers and bits are given in the subsections that follow. table 324. quick reference to dbg registers address name bit 7 6 5 4 3 2 1 bit 0 0x0020 dbgc1 r arm 0 0 bdm dbgbrk 0 comrv w trig 0x0021 dbgsr r (246) tbf 0 0 0 0 ssf2 ssf1 ssf0 w 0x0022 dbgtcr r 0 tsource 0 0 trcmod 0 talign w 0x0023 dbgc2 r 0 0 0 0 0 0 abcm w 0x0024 dbgtbh r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w cpu bus trace buffer bus interface transition match0 state comparator b comparator c comparator a state sequencer match1 match2 trace read trace data (dbg read data bus) control secure breakpoint requests comparator match control trigger tag & match control logic tags taghits state to cpu
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 240 5.19.3.2 register descriptions this section consists of the dbg control and trace buffer register descriptions in addr ess order. each comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002f in the dbg module register address map. when arm is set in dbgc1, the only bits in the dbg module registers that can be written are arm, trig, and comrv[1:0] 0x0025 dbgtbl r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0026 dbgcnt r tbf 0 cnt w 0x0027 dbgscrx r 0 0 0 0 sc3 sc2 sc1 sc0 w 0x0027 dbgmfr r 0 0 0 0 0 mc2 mc1 mc0 w 0x0028 (247) dbgactl r sze sz tag brk rw rwe ndb compe w 0x0028 (248) dbgbctl r sze sz tag brk rw rwe 0 compe w 0x0028 (249) dbgcctl r 0 0 tag brk rw rwe 0 compe w 0x0029 dbgxah r 0 0 0 0 0 0 bit 17 bit 16 w 0x002a dbgxam r bit 15 14 13 12 11 10 9 bit 8 w 0x002b dbgxal r bit 7 6 5 4 3 2 1 bit 0 w 0x002c dbgadh r bit 15 14 13 12 11 10 9 bit 8 w 0x002d dbgadl r bit 7 6 5 4 3 2 1 bit 0 w 0x002e dbgadhm r bit 15 14 13 12 11 10 9 bit 8 w 0x002f dbgadlm r bit 7 6 5 4 3 2 1 bit 0 w notes 246.this bit is visible at dbgcnt[7] and dbgsr[7] 247.this represents the contents if the comparator a control register is blended into this address 248.this represents the contents if the comparator b control register is blended into this address 249.this represents the contents if the comparator c control register is blended into this address table 324. quick reference to dbg registers address name bit 7 6 5 4 3 2 1 bit 0
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 241 5.19.3.2.1 debug contro l register 1 (dbgc1) read: anytime ? write: bits 7, 1, 0 anytime ? bit 6 can be written anytime but always reads back as 0. ? bits 4:3 anytime dbg is not armed. note when disarming the dbg by clearing arm with software, the contents of bits[4:3] are not affected by the write, since up until the write operation, arm = 1 preventing these bits from being written. these bits must be clea red using a second write if required. table 325. debug control register (dbgc1) address: 0x0020 7 6 5 4 3 2 1 0 r arm 0 0 bdm dbgbrk 0 comrv w trig reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 326. dbgc1 field descriptions field description 7 arm arm bit ? the arm bit controls whether the dbg module is armed. this bit can be set and cleared by user software and is automatically cleared on completion of a debug session, or if a breakpoint is generated with tracing not enabled. on setting this bit the state sequencer enters state1. 0 debugger disarmed 1 debugger armed 6 trig immediate trigger request bit ? this bit when written to 1 requests an immediate trigger independent of state sequencer status. when tracing is complete a forced breakpoint may be generated depending upon dbgbrk and bdm bit settings. this bit always reads back a 0. writing a 0 to this bit has no effec t. if the dbgtcr_tsource bit is cl ear no tracing is carried out. if tracing has already commenced using begin trigger alignment, it continues until the end of the tracing session as defined by the talign bit, thus trig has no affect. in secure mode, tr acing is disabled and writing to th is bit cannot initiate a traci ng session. the session is ended by setting trig and arm simultaneously. 0 do not trigger until the state sequencer enters the final state. 1 trigger immediately 4 bdm background debug mode enable ? this bit determines if a breakpoint caus es the system to enter background debug mode (bdm) or initiate a software interrupt (swi). if this bit is set but the bdm is not enabled by the enbdm bit in the bdm module, then breakpoints default to swi. 0 breakpoint to software interrupt if bdm inactive. otherwise no breakpoint. 1 breakpoint to bdm, if bdm enabl ed. otherwise breakpoint to swi 3 dbgbrk s12sdbg breakpoint enable bit ? the dbgbrk bit controls whether the de bugger will request a breakpoint on reaching the state sequencer final state. if tracing is enabled, the break point is generated on completion of the tracing session. if tracing is not enabled, the break point is generated immediately. 0 no breakpoint generated 1 breakpoint generated 1?0 comrv comparator register visibility bits ? these bits determine which bank of comparator register is visible in the 8-byte window of the s12sdbg module address map, located between 0x0028 to 0x002f. furthermore these bits determine which register is visible at the address 0x0027. see table 327 .
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 242 5.19.3.2.2 debug status register (dbgsr) read: anytime ? write: never table 327. comrv encoding comrv visible comparator visible register at 0x0027 00 comparator a dbgscr1 01 comparator b dbgscr2 10 comparator c dbgscr3 11 none dbgmfr table 328. debug status register (dbgsr) address: 0x0021 7 6 5 4 3 2 1 0 r tbf 0 0 0 0 ssf2 ssf1 ssf0 w reset por ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 329. dbgsr field descriptions field description 7 tbf trace buffer full ? the tbf bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. if this bit is set, then all 64 lines will be valid data, regardless of the value of db gcnt bits. the tbf bit is cleared when arm in dbgc1 is written to a one. the tbf is cleared by the power on reset initialization. other system generated resets have no affect on this bit this bit is also visible at dbgcnt[7] 2?0 ssf[2:0] state sequencer flag bits ? the ssf bits indicate in which state the state sequencer is currently in. during a debug session on each transition to a new state these bits are updated. if the debug session is ended by software clearing the arm bit, then these bits retain their value to reflect the last state of the state sequencer before disarming. if a debug session is ended by an internal event, then the state sequencer returns to state0 and t hese bits are cleared to indicate that state0 was entered durin g the session. on arming the module the state sequencer enters state1 and these bits are forced to ssf[2:0] = 001. see ta b l e 330 . table 330. ssf[2:0] ? state sequence flag bit encoding ssf[2:0] current state 000 state0 (disarmed) 001 state1 010 state2 011 state3 100 final state 101,110,111 reserved
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 243 5.19.3.2.3 debug trace c ontrol register (dbgtcr) read: anytime ? write: bit 6 only when dbg is neither secure nor armed.bits 3,2,0 anytime the module is disarmed. 5.19.3.2.4 debug control register2 (dbgc2) read: anytime ? write: anytime the module is disarmed this register configures the comparators for range matching. table 331. debug trace contro l register (dbgtcr) address: 0x0022 7 6 5 4 3 2 1 0 r 0 tsource 0 0 trcmod 0 talign w reset 0 0 0 0 0 0 0 0 table 332. dbgtcr field descriptions field description 6 tsource trace source control bit ? the tsource bit enables a tracing session giv en a trigger condition. if the mcu system is secured, this bit cannot be se t and tracing is inhibited. ? this bit must be set to read the trace buffer. 0 debug session without tracing requested 1 debug session with tracing requested 3?2 trcmod trace mode bits ? see section 5.19.4.5.2, ?trace modes" for detailed trace mode descriptions. in normal mode, change of flow information is stored. in loop1 mode, change of flow info rmation is stored but redundant entries into trace memory are inhibited. in detail mode, address and data for all memory and regi ster accesses is stored. in compressed pure pc mode the program counter value for each instruction executed is stored. see table 333 . 0 talign trigger align bit ? this bit controls whether the trigger is a ligned to the beginning or end of a tracing session. 0 trigger at end of stored data 1 trigger before storing data table 333. trcmod trace mode bit encoding trcmod description 00 normal 01 loop1 10 detail 11 compressed pure pc table 334. debug control register2 (dbgc2) address: 0x0023 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 abcm w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 244 5.19.3.2.5 debug trace buffer register (dbgtbh:dbgtbl) read: only when unlocked and unsecured and not armed and tsource set ? write: aligned word writes when disarmed unlock the trace bu ffer for reading but do not af fect trace buffer contents table 335. dbgc2 field descriptions field description 1?0 abcm[1:0] a and b comparator match control ? these bits determine the a and b comparator match mapping as described in ta b l e 336 . table 336. abcm encoding abcm description 00 match0 mapped to comparator a match: match1 mapped to comparator b match. 01 match 0 mapped to comparator a/b inside range: match1 disabled. 10 match 0 mapped to comparator a/b outside range: match1 disabled. 11 reserved (250) notes 250.currently defaults to comparator a, comparator b disabled table 337. debug trace buffer register (dbgtb) address: 0x0024, 0x0025 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w por x x x x x x x x x x x x x x x x other resets ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? table 338. dbgtb field descriptions field description 15?0 bit[15:0] trace buffer data bits ? the trace buffer register is a window through which the 20-bit wide data lines of the trace buffer may be read 16 bits at a time. each vali d read of dbgtb increments an internal trace buffer pointer which points to the next address to be read. when the arm bit is set the trace buffer is locked to prevent reading. the trace buffer can only be unlocke d for reading by writing to dbgtb with an aligned word write wh en the module is disarmed. the dbgtb register can be read only as an aligned word, any byte reads or misaligned access of these registers return a 0, and do not cause the trace buffer pointer to increment to the next trace buffer address. similarl y reads while the debugger is armed or with the tsource bit clear, return a 0, and do not affect the trace buffer pointer. t he por state is undefined. other resets do not affect the trace buffer contents.
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 245 5.19.3.2.6 debug count register (dbgcnt) read: anytime ? write: never 5.19.3.2.7 debug stat e control registers there is a dedicated control register for ea ch of the state sequencer states 1 to 3, th at determines if trans itions from that s tate are allowed, depending upon comparator matches or tag hits, and define the next state for the state sequencer following a match . the three debug state control registers are lo cated at the same address in the register address map (0 x0027). each register can be accessed using the comrv bits in dbgc1 to blend in the requ ired register. the comrv = 11 value blends in the match flag register (dbgmfr). table 339. debug count register (dbgcnt) address: 0x0026 7 6 5 4 3 2 1 0 r tbf 0 cnt w reset por ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 = unimplemented or reserved table 340. dbgcnt field descriptions field description 7 tbf trace buffer full ? the tbf bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. if this bit is set, then all 64 lines will be valid data, regardless of the value of db gcnt bits. the tbf bit is cleared when arm in dbgc1 is written to a one. the tbf is cleared by the power on reset initialization. other system generated resets have no affect on this bit this bit is also visible at dbgsr[7] 5?0 cnt[5:0] count value ? the cnt bits indicate the number of valid data 20-bit data lines stored in the trace buffer. table 341 shows the correlation between the cnt bits and the number of valid data lines in the trace buffer. when the cnt rolls over to zero, the tbf bit in dbgsr is set and incrementi ng of cnt will continue in end-trigger m ode. the dbgcnt register is cleared when arm in dbgc1 is written to a one. the dbgcnt register is clea red by power-on-reset initializati on but is not cleared by other system resets. thus should a reset occur during a debug session, the dbgcnt register still indicates after the reset, the number of valid trace buffer entries stored before the reset oc curred. the dbgcnt register is not decremented when reading from the trace buffer. table 341. cnt decoding table tbf cnt[5:0] description 0 000000 no data valid 0 000001 000010 000100 000110 ... 111111 1 line valid 2 lines valid 4 lines valid 6 lines valid ... 63 lines valid 1 000000 64 lines valid; if using begin trigger alignment, arm bit will be cleared and the tracing session ends. 1 000001 ... ... 111110 64 lines valid, oldest data has been overwritten by most recent data
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 246 5.19.3.2.7.1 debug state cont rol register 1 (dbgscr1) read: if comrv[1:0] = 00 ? write: if comrv[1:0] = 00 and dbg is not armed this register is visible at 0x 0027 only with comrv[1:0] = 00. t he state control register 1 sele cts the targeted next state whil e in state1. the matches refer to the match channels of the comparator match contro l logic, as depicted in figure 63 and described in section 5.19.3.2.8.1, ?debug comparator control register (dbgxctl)" . comparators must be enabled by setting the comparator enable bit in the asso ciated dbgxctl control register. table 342. state control register access encoding comrv visible state control register 00 dbgscr1 01 dbgscr2 10 dbgscr3 11 dbgmfr table 343. debug state control register 1 (dbgscr1) address: 0x0027 7 6 5 4 3 2 1 0 r 0 0 0 0 sc3 sc2 sc1 sc0 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 344. dbgscr1 field descriptions field description 3?0 sc[3:0] these bits select the targeted next state while in state1, based upon the match event. table 345. state1 sequencer next state selection sc[3:0] description (unspecified matches have no effect) 0000 any match to final state 0001 match1 to state3 0010 match2 to state2 0011 match1 to state2 0100 match0 to state2....... match1 to state3 0101 match1 to state3.........match0 to final state 0110 match0 to state2....... match2 to state3 0111 either match0 or match1 to state2 1000 reserved 1001 match0 to state3 1010 reserved 1011 reserved 1100 reserved 1101 either match0 or match2 to fi nal state........match1 to state2
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 247 the priorities described in table 378 dictate that in the case of simultaneous matc hes, a match leading to final state has priority followed by the match on the lower channel number (0,1,2). thus with sc[3:0]=1101, a simultane ous match0/match1 transitions to final state. 5.19.3.2.7.2 debug state cont rol register 2 (dbgscr2) read: if comrv[1:0] = 01 ? write: if comrv[1:0] = 01 and dbg is not armed this register is visible at 0x 0027 only with comrv[1:0] = 01. t he state control register 2 sele cts the targeted next state whil e in state 2. the matches refer to the ma tch channels of the comparator matc h control logic, as depicted in figure 63 and described in section 5.19.3.2.8.1, ?debug comparator control register (dbgxctl)" . comparators must be enabled by setting the comparator enable bit in the asso ciated dbgxctl control register. 1110 reserved 1111 reserved table 346. debug state control register 2 (dbgscr2) address: 0x0027 7 6 5 4 3 2 1 0 r 0 0 0 0 sc3 sc2 sc1 sc0 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 347. dbgscr2 field descriptions field description 3?0 sc[3:0] these bits select the targeted next state while in state 2, based upon the match event. table 348. state2 ?sequencer next state selection sc[3:0] description (unspecified matches have no effect) 0000 match0 to state1....... match2 to state3. 0001 match1 to state3 0010 match2 to state3 0011 match1 to state3....... match0 final state 0100 match1 to state1....... match2 to state3. 0101 match2 to final state 0110 match2 to state1..... match0 to final state 0111 either match0 or match1 to final state 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 either match0 or match1 to final state........match2 to state3 1101 reserved 1110 reserved 1111 either match0 or match1 to final state........match2 to state1 table 345. state1 sequencer next state selection sc[3:0] description (unspecified matches have no effect)
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 248 the priorities described in table 378 dictate that in the case of simultaneous matc hes, a match leading to final state has priority followed by the match on the lower channel number (0,1,2). 5.19.3.2.7.3 debug state cont rol register 3 (dbgscr3) read: if comrv[1:0] = 10 ? write: if comrv[1:0] = 10 and dbg is not armed this register is visible at 0x0027 only with comrv[1:0] = 10. the state control register three selects the targeted next state while in state 3. the matches refer to the match channels of the comparator match contro l logic, as depicted in figure 63 and described in section 5.19.3.2.8.1, ?debug comparator control register (dbgxctl)" . comparators must be enabled by setting the comparator enable bit in the asso ciated dbgxctl control register. the priorities described in ta b l e 378 dictate that in the case of simultaneous matches, a match leading to final state has priority, followed by the match on the lower channel number (0,1,2). table 349. debug state control register 3 (dbgscr3) address: 0x0027 7 6 5 4 3 2 1 0 r 0 0 0 0 sc3 sc2 sc1 sc0 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 350. dbgscr3 field descriptions field description 3?0 sc[3:0] these bits select the targeted next state while in state 3, based upon the match event. table 351. state3 ? sequencer next state selection sc[3:0] description (unspecified matches have no effect) 0000 match0 to state1 0001 match2 to state2........ match1 to final state 0010 match0 to final state....... match1 to state1 0011 match1 to final state....... match2 to state1 0100 match1 to state2 0101 match1 to final state 0110 match2 to state2........ match0 to final state 0111 match0 to final state 1000 reserved 1001 reserved 1010 either match1 or match2 to state1....... match0 to final state 1011 reserved 1100 reserved 1101 either match1 or match2 to final state....... match0 to state1 1110 match0 to state2....... match2 to final state 1111 reserved
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 249 5.19.3.2.7.4 debug match flag register (dbgmfr) read: if comrv[1:0] = 11 ? write: never dbgmfr is visible at 0x0027 only with comrv[ 1:0] = 11. it features 3 flag bits, each mapped directly to a channel. should a match occur on the channel during the debug session, then the corresponding flag is set and remains set until the next time the module is armed, by writing to the arm bit. thus the contents are retained after a debug session for evaluation purposes. these flags cannot be cleared by software. they are cleared only wh en arming the module. a set flag does not inhibit the setting of other flags. once a flag is set, further comparator matches on the same channel in the same session have no affect on that flag . 5.19.3.2.8 comparator register descriptions each comparator has a bank of registers that are visible thro ugh an 8-byte window in the dbg module register address map. comparator a consists of 8 register bytes (3 address bus compar e registers, two data bus compar e registers, two data bus mask registers, and a control registe r). comparator b consists of fo ur register bytes (three address bus compare registers and a con trol register). comparator c consists of fo ur register bytes (three address bus comp are registers and a control register). each set of comparator registers can be accessed using the comrv bits in the dbgc 1 register. unimplemented registers (e.g. comparator b data bus and data bus masking) read as zero and cannot be written. the control regist er for comparator b differs from those of comparators a and c. 5.19.3.2.8.1 debug comparator control register (dbgxctl) the contents of register bits 7 and 6 differ, depending upon whic h comparator registers are visibl e in the 8-byte window of the dbg module register address map. table 352. debug match flag register (dbgmfr) address: 0x0027 7 6 5 4 3 2 1 0 r 0 0 0 0 0 mc2 mc1 mc0 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 353. comparator register layout 0x0028 control read/write comparators a,b and c 0x0029 address high read/write comparators a,b and c 0x002a address medium read/write comparators a,b and c 0x002b address low read/write comparators a,b and c 0x002c data high comparator read/write comparator a only 0x002d data low comparator read/write comparator a only 0x002e data high mask read/write comparator a only 0x002f data low mask read/write comparator a only table 354. debug comparator control register dbgactl (comparator a) address: 0x0028 7 6 5 4 3 2 1 0 r sze sz tag brk rw rwe ndb compe w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 250 read: dbgactl if comrv[1:0] = 00 ? dbgbctl if comrv[1:0] = 01 ? dbgcctl if comrv[1:0] = 10 write: dbgactl if comrv[1: 0] = 00 and dbg not armed ? dbgbctl if comrv[1:0] = 01 and dbg not armed ? dbgcctl if comrv[1:0] = 10 and dbg not armed table 355. debug comparator control register dbgbctl (comparator b) address: 0x0028 7 6 5 4 3 2 1 0 r sze sz tag brk rw rwe 0 compe w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 356. debug comparator control register dbgcctl (comparator c) address: 0x0028 7 6 5 4 3 2 1 0 r 0 0 tag brk rw rwe 0 compe w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 357. dbgxctl field descriptions field description 7 sze (comparators a and b) size comparator enable bit ? the sze bit controls whether access size comparison is enabled for the associated comparator. this bit is ignored if the tag bit in the same register is set. 0 word/byte access size is not used in comparison 1 word/byte access size is used in comparison 6 sz (comparators a and b) size comparator value bit ? the sz bit selects either word or byte access size in comparison for the associated comparator. this bit is ignored if t he sze bit is cleared or if the tag bit in the same register is set. 0 word access size is compared 1 byte access size is compared 5 tag tag select ? this bit controls whether the comparator match has immediate effect, causing an immediate state sequencer transition or tag the opcode at the matched address. tagged opcodes trigger only if they reach the execution stage of the instruction queue. 0 allow state sequencer trans ition immediately on match 1 on match, tag the opcode. if the opcode is about to be executed allow a state sequencer transition 4 brk break ? this bit controls whether a comparator match term inates a debug session immediately, independent of state sequencer state. to generate an immediate breakpoint t he module breakpoints must be enabled using the dbgc1 bit dbgbrk. 0 the debug session termination is dependent upon t he state sequencer and trigger conditions. 1 a match on this channel terminates the debug session immediat ely; breakpoints if active are generated, tracing, if active, is terminated and the module disarmed. 3 rw read/write comparator value bit ? the rw bit controls whether read or wr ite is used in compare for the associated comparator. the rw bit is not used if rwe = 0. this bit is ignored if the tag bit in the same register is set. 0 write cycle is matched1read cycle is matched 2 rwe read/write enable bit ? the rwe bit controls whether read or wr ite comparison is enabled for the associated comparator.this bit is ignored if the tag bit in the same register is set 0 read/write is not used in comparison 1 read/write is used in comparison
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 251 table 358 shows the effect for rwe and rw on the comparison cond itions. these bits are ignored if the corresponding tag bit is set, since the match occurs bas ed on the tagged opcode reaching the exec ution stage of the instruction queue. 5.19.3.2.8.2 debug comparator ad dress high register (dbgxah) the dbgc1_comrv bits determine which comparator address regist ers are visible in the 8-byte window from 0x0028 to 0x002f, as shown in ta b l e 360 1 ndb (comparator a) not data bus ? the ndb bit controls whether the match occurs when the data bus matches the comparator register value or when the data bus differs from the register value. this bit is ignored if the tag bi t in the same register is set. this bit is only available for comparator a. 0 match on data bus equivalence to comparator register contents 1 match on data bus difference to comparator register contents 0 compe determines if comparator is enabled 0 the comparator is not enabled 1 the comparator is enabled table 358. read or write comparison logic table rwe bit rw bit rw signal comment 0 x 0 rw not used in comparison 0 x 1 rw not used in comparison 1 0 0 write data bus 1 0 1 no match 1 1 0 no match 1 1 1 read data bus table 359. debug comparator addre ss high regist er (dbgxah) address: 0x0029 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 bit 17 bit 16 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 360. comparator address register visibility comrv visible comparator 00 dbgaah, dbgaam, dbgaal 01 dbgbah, dbgbam, dbgbal 10 dbgcah, dbgcam, dbgcal 11 none notes 251.read: anytime. see table for visible register encoding. ? write: if dbg not armed. see table for visible register encoding. table 357. dbgxctl field descriptions (continued) field description
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 252 5.19.3.2.8.3 debug comparator address mid register (dbgxam) read: anytime. see ta b l e 360 for visible register encoding. ? write: if dbg not armed. see table 360 for visible register encoding. 5.19.3.2.8.4 debug comparator address low regi ster (dbgxal) read: anytime. see table for visible register encoding ? write: if dbg not armed. see table for visible register encoding table 361. dbgxah field descriptions field description 1?0 bit[17:16] comparator address high compare bits ? the comparator address high compare bits control whether the selected comparator compares the address bus bits [17:16] to a logic one or logic zero. 0 compare corresponding address bit to a logic zero 1 compare corresponding address bit to a logic one table 362. debug comparator address mid register (dbgxam) address: 0x002a 7 6 5 4 3 2 1 0 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 0 0 0 0 0 0 0 0 table 363. dbgxam field descriptions field description 7?0 bit[15:8] comparator address mid compare bits ? the comparator address mid compare bits control whether the selected comparator compares the address bus bits [15:8] to a logic one or logic zero. 0 compare corresponding address bit to a logic zero 1 compare corresponding address bit to a logic one table 364. debug comparator address low register (dbgxal) address: 0x002b 7 6 5 4 3 2 1 0 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 0 0 0 0 0 0 0 0 table 365. dbgxal field descriptions field description 7?0 bits[7:0] comparator address low compare bits ? the comparator address low compare bits control whether the selected comparator compares the address bus bi ts [7:0] to a logic one or logic zero. 0 compare corresponding address bit to a logic zero 1 compare corresponding address bit to a logic one
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 253 5.19.3.2.8.5 debug comparator data high register (dbgadh) read: if comrv[1:0] = 00 ? write: if comrv[1:0] = 00 and dbg not armed 5.19.3.2.8.6 debug comparator data low register (dbgadl) read: if comrv[1:0] = 00 ? write: if comrv[1:0] = 00 and dbg not armed table 366. debug comparator data high register (dbgadh) address: 0x002c 7 6 5 4 3 2 1 0 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 0 0 0 0 0 0 0 0 table 367. dbgadh field descriptions field description 7?0 bits[15:8] comparator data high compare bits ? the comparator data high compare bits control whether the selected comparator compares the data bus bits [15:8] to a logic one or logic zero. the comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. this register is available only for comparator a. data bus comparisons are only performed if the tag bit in dbgactl is clear. 0 compare corresponding data bit to a logic zero 1 compare corresponding data bit to a logic one table 368. debug comparator data low register (dbgadl) address: 0x002d 7 6 5 4 3 2 1 0 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 0 0 0 0 0 0 0 0 table 369. dbgadl field descriptions field description 7?0 bits[7:0] comparator data low compare bits ? the comparator data low compare bits control, whether the selected comparator compares the data bus bits [7:0] to a logic one or a logic zero . the comparator data compare bits are only used in comparison if the corresponding data mask bit is a logic 1. this register is available only for comparator a. data bus comparisons are onl y performed if the tag bit in dbgactl is clear 0 compare corresponding data bit to a logic zero 1 compare corresponding data bit to a logic one
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 254 5.19.3.2.8.7 debug comparator da ta high mask register (dbgadhm) read: if comrv[1:0] = 00 ? write: if comrv[1:0] = 00 and dbg not armed 5.19.3.2.8.8 debug comparator data low mask register (dbgadlm) read: if comrv[1:0] = 00 ? write: if comrv[1:0] = 00 and dbg not armed 5.19.4 functional description this section provides a complete functional description of the dbg module. if the part is in secure mode, the dbg module can generate breakpoints, but tracing is not possible. 5.19.4.1 s12sdbg operation arming the dbg module by setting arm in dbgc1 allows triggering the state sequencer, storing of data in the trace buffer, and generation of breakpoints to the cpu. the db g module is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace buffer. the comparators monitor the bus activity of the cpu. all comp arators can be configured to monitor address bus activity. comparator a can also be configured to monitor data bus activity and mask out individual data bus bits during a compare. table 370. debug comparator data high mask register (dbgadhm) address: 0x002e 7 6 5 4 3 2 1 0 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 0 0 0 0 0 0 0 0 table 371. dbgadhm field descriptions field description 7?0 bits[15:8] comparator data high mask bits ? the comparator data high mask bits contro l whether the selected comparator compares the data bus bits [15:8] to the corresponding comparator data compare bits. data bus comparisons are only performed if the tag bit in dbgactl is clear 0 do not compare corresponding data bit any value of corresponding data bit allows match. 1 compare corresponding data bit table 372. debug comparator data low mask register (dbgadlm) address: 0x002f 7 6 5 4 3 2 1 0 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 0 0 0 0 0 0 0 0 table 373. dbgadlm field descriptions field description 7?0 bits[7:0] comparator data low mask bits ? the comparator data low mask bits contro l whether the selected comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. data bus comparisons are only performed if the tag bit in dbgactl is clear 0 do not compare corresponding data bit. any value of corresponding data bit allows match 1 compare corresponding data bit
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 255 comparators can be configured to use r/w and word/byte access qualification in the comparison. a match with a comparator register value can initiate a state se quencer transition to another state (see figure 65 ). either forced or tagged matches are possible. using a forced match, a state sequencer transition can occur immediately on a successf ul match of system busses and comparator registers. while tagging at a comparator match, t he instruction opcode is tagged, and only if the instruction reache s the execution stage of the instru ction queue, can a state sequencer transition occu r. in the case of a tr ansition to final stat e, bus tracing is triggered, and/or a breakpoint can be generated. a state sequencer transition to final state (with associated break point, if enabled) can be initia ted by writing to the trig bi t in the dbgc1 control register. the trace buffer is visible through a 2-byte window in the regi ster address map and must be read out using standard 16-bit word reads. figure 64. dbg overview 5.19.4.2 comparator modes the dbg contains three comparat ors, a, b and c. each comp arator compares th e system address bus with the address stored in dbgxah, dbgxam, and dbgxal. furthermo re, comparator a also compares the data buses to the data stored in dbgadh, dbgadl and allows masking of individual data bus bits. all comparators are disabled in bdm and during bdm accesses. the comparator match control logic (see figure 64 ) configures comparators to monitor the buses for an exact address or an address range, whereby either an access inside or outside th e specified range generates a ma tch condition. the comparator configuration is controlled by the control register content s and the range control by the dbgc2 contents. a match can initiate a transition to another state sequencer state (see section 5.19.4.4, ?state sequence control" ? ). the comparator control register also allows the type of access to be included in the comp arison through the use of the rwe, rw, sze, and sz bits. the rwe bit controls wh ether read or write comparis on is enabled for the associated comparator and the rw bit selects either a read or write access for a valid match. sim ilarly the sze and sz bits allow the size of access (word or by te) to be considered in the compare. only comparators a and b feature sze and sz. the tag bit in each comparator control r egister is used to determine the match c ondition. by setting tag, the comparator qualifies a match with the output of opcode tracking logic, and a state sequencer transition occurs when the tagged instruction reaches the cpu execution stage. while tagging, the rw, rwe, sze, and sz bits and the comparator data registers are ignored; the comparator address register must be loaded with the exact opcode address. cpu bus trace buffer bus interface transition match0 state comparator b comparator c comparator a state sequencer match1 match2 trace read trace data (dbg read data bus) control secure breakpoint requests comparator match control trigger tag & match control logic tags taghits state to cpu
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 256 if the tag bit is clear (forced type match), a comparator ma tch is generated when the selected addre ss appears on the system address bus. if the selected address is an opc ode address, the match is generated when the opcode is fetched from the memory, which precedes the instruction exec ution by an indefinite number of cycles due to instruction pipelining. for a comparator matc h of an opcode at an odd address when tag = 0, the corresponding even address must be contained in the comparator register. thus for an opcode at odd address (n), the co mparator register must contain address (n?1). once a successful comparator match has occurred, the condit ion that caused the original ma tch is not verified again on subsequent matches. if a particular data value is verified at a given address, this address may not still contain that data val ue when a subsequent match occurs. match[0, 1, 2] map directly to comparators [a, b, c] respectively, except in range modes (see section 5.19.3.2.4, ?debug control register2 (dbgc2)" ). comparator channel priority rules are described in the priority section ( section 5.19.4.3.4, ?channel priorities" ) . 5.19.4.2.1 single addr ess comparator match with range comparisons disabled, the match condition is an ex act equivalence of address bus, with the value stored in the comparator address registers. further qualification of the type of access (r/w, word/byte) and data bus contents is possible, depending on comparator channel. 5.19.4.2.1.1 comparator c comparator c offers only address and direction (r/w) comparison . the exact address is compared, with the comparator address register loaded with address (n), a word access of addr ess (n?1) also accesses (n) but does not cause a match. 5.19.4.2.1.2 comparator b comparator b offers address, direction (r/w) and access size (wor d/byte) comparison. if the sze bit is set, the access size (wo rd or byte) is compared with the sz bit value such that only the s pecified size of access causes a match. if configured for a byte access of a particular address, a word access cove ring the same address does not lead to match. assuming the access direction is not qualified (rwe=0), for simplicity, the size access considerations are shown in ta b l e 375 . table 374. comparator c access considerations condition for valid match comp c address rwe rw examples read and write accesses of addr[n] addr[n] (252) 0 x ldaa addr[n] staa #$byte addr[n] write accesses of addr[n] addr[n] 1 0 staa #$byte addr[n] read accesses of addr[n] addr[n] 1 1 ldaa #$byte addr[n] notes 252.a word access of addr[n-1] also accesses addr[n] but does not generate a match. the comparator address register must contai n the exact address from the code. table 375. comparator b access size considerations condition for valid match comp b address rwe sze sz8 examples word and byte accesses of addr[n] addr[n] (253) 0 0 x movb #$byte addr[n] movw #$word addr[n] word accesses of addr[n] only addr[n] 0 1 0 movw #$word addr[n] ldd addr[n] byte accesses of addr[n] only addr[n] 0 1 1 movb #$byte addr[n] ldab addr[n] notes 253.a word access of addr[n-1] also accesses addr[n] but does not generate a match. the comparator address register must contai n the exact address from the code.
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 257 access direction can also be used to qualify a match for comparat or b in the same way, as described for comparator c in table 374 . 5.19.4.2.1.3 comparator a comparator a offers address, direction (r/w), access size (word/byte), and data bus comparison. table 376 lists access considerations with data bus comparison. on wo rd accesses, the data byte of the lower address is mapped to dbgadh. access direction can also be used to qualify a match fo r comparator a in the same way as described for comparator c in table 374 . 5.19.4.2.1.4 comparator a data bus comparison ndb dependency comparator a features an ndb c ontrol bit, which allows data bus comparators to be configured to either trigger on equivalence or trigger on difference. this allows monitoring of a difference in the contents of an address location from an expected value. when matching on an equivalence (ndb=0), each individual data bus bit position can be masked out by clearing the corresponding mask bit (dbgadhm/dbgadlm) so that it is ignored in the comparis on. a match occurs when all data bus bits with corresponding mask bits set are equivalent. if all mask regi ster bits are clear, then a match is based on the address bus only, the data bus is ignored. when matching on a difference, mask bits can be cleared to ignore bit positions. a match occurs when any data bus bit with corresponding mask bit set is different. clearing all mask bits causes all bits to be ignored and prevents a match because no difference can be detected. in this case, add ress bus equivalence does not cause a match. table 376. comparator a matches when accessing addr[n] sze sz dbgadhm, dbgadlm access dh=dbgadh, dl=dbgadl comment 0 x $0000 byte word no databus comparison 0 x $ff00 byte, data(addr[n])=dh ? word, data(addr[n])=dh, data(addr[n+1])=x match data(addr[n]) 0 x $00ff word, data(addr[n])=x, data(addr[n+1])=dl match data(addr[n+1]) 0 x $00ff byte, data(addr[n])=x, data(addr[n+1])=dl possible unintended match 0 x $ffff word, data(addr[n])=dh, data(addr[n+1])=dl match data(addr[n], addr[n+1]) 0 x $ffff byte, data(addr[n])=dh, data(addr[n+1])=dl possible unintended match 1 0 $0000 word no databus comparison 1 0 $00ff word, data(addr[n])=x, data(addr[n+1])=dl match only data at addr[n+1] 1 0 $ff00 word, data(addr[n])=dh, data(addr[n+1])=x match only data at addr[n] 1 0 $ffff word, data(addr[n])=dh, data(addr[n+1])=dl match data at addr[n] & addr[n+1] 1 1 $0000 byte no databus comparison 1 1 $ff00 byte, data(addr[n])=dh match data at addr[n] table 377. ndb and mask bit dependency ndb dbgadhm[n] / dbgadlm[n] comment 0 0 do not compare data bus bit. 0 1 compare data bus bit. match on equivalence. 1 0 do not compare data bus bit. 1 1 compare data bus bit. match on difference.
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 258 5.19.4.2.2 range comparisons using the ab comparator pair for a range comp arison, the data bus can also be used for qualification by using the comparator a data registers. furthermore, the dbgactl rw and rwe bits can be used to qualify the range comparison on either a read or a write access. the corresponding dbgbctl bits are ignored. the sze and sz control bits are ignored in range mode. the comparator a tag bit is used to tag range comparisons. the comparator b tag bit is ignored in range modes. for a range comparison using comparators a and b, both compea and compeb must be set; to disable range comparisons both must be cleared. the comparator a brk bit is used to for the ab range, the comparator b brk bi t is ignored in range mode. when configured for range comparisons and tagging, the ranges are accurate only to word boundaries. 5.19.4.2.2.1 inside range (compa_addr ? address ? compb_addr) in the inside range comparator mode, co mparator pair a and b can be configured fo r range comparisons. this configuration depends upon the control register (dbgc2). the match condition requires that a valid match for both comparators happens on the same bus cycle. a match condition on only one comparator is not valid. an aligned word access which straddles the range boundary is valid only if the al igned address is inside the range. 5.19.4.2.2.2 outside range (address < compa_addr or address > compb_addr) in the outside range comparator mode, comparator pair a and b can be configured for range comparisons. a single match condition on either of the comparators is recognized as valid. an aligned word access which straddles the range boundary is valid, only if the aligned address is outside the range. outside range mode in combination with tagging can be used to det ect, if the opcode fetches are from an unexpected range. in forced match mode, the outside range match would typically be acti vated at any interrupt vector fetch or register access. this can be avoided by setting the upper range limit to $3ffff or lower range limit to $00000 respectively. 5.19.4.3 match modes (forced or tagged) match modes are used as qualifiers for a state sequencer change of state. the comparator control register tag bits select the match mode. the modes are described in the following sections. 5.19.4.3.1 forced match when configured for forced matching, a comparator channel matc h can immediately initiate a transition to the next state sequencer state, whereby the corresponding fl ags in dbgsr are set. the state control register for the current state determines the next state. forced matches are typically generated 2-3 bus cycles after the final matching address bus cycle, independent o f comparator rwe/rw settings. furthermore, since opcode fetche s occur several cycles before the opcode execution, a forced match of an opcode address typically precedes a tagged match at the same address. 5.19.4.3.2 tagged match if a cpu taghit occurs, a transition to another state sequencer stat e is initiated and the corresponding dbgsr flags are set. f or a comparator related taghit to occur, the db g must first attach tags to instructions as they are fetched fr om memory. when the tagged instruction reaches the execution sta ge of the instruction queue, a taghit is gener ated by the cpu. this can initiate a state sequencer transition. 5.19.4.3.3 immediate trigger independent of comparator matches, it is possible to initiate a tracing session and/or breakpoint by writing to the trig bit in dbgc1. if configured for begin aligned tracing, this triggers th e state sequencer into the final state, if configured for end alignment, setting the trig bit disarms the module, ending t he session and issues a forced breakpoint request to the cpu. it is possible to set both trig and arm simultaneously to gener ate an immediate trigger, independe nt of the current state of arm.
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 259 5.19.4.3.4 channel priorities in case of simultaneous matches, the priority is resolved according to ta b l e 378 . the lower priority is suppressed. it is possible to miss a lower priority match, if it occurs simultaneous ly with a higher priority. the priorities described in table 378 dictate that in the case of simultaneous matches, the match pointing to final state has highest priority, followed by the lower channel numb er (0,1,2). 5.19.4.4 state sequence control figure 65. state sequencer diagram the state sequencer allows a defin ed sequence of events to provide a trigger point for tracing of data in the trace buffer. onc e the dbg module has been armed by setting the arm bit in the db gc1 register, the state 1 of th e state sequencer is entered. further transitions between the states are then controlled by the state control regist ers and channel matches. from final state , the only permitted transition is back to the disarmed state 0. tran sition between any of the states 1 to 3 is not restricted. e ach transition updates the ssf[2:0] flags in dbgsr accordingly to indicate the current state. alternatively, writing to the trig bit in dbgsc1, provid es an immediate trigger independent of comparator matches. independent of the state sequencer, each comparator channel can be individually configured to generate an immediate breakpoint when a match occurs, through the use of the brk bits in the dbgxctl registers. it is possible to generate an immediate breakpoint on selected channels, while a state sequenc er transition can be initiated by a match on other channels. if a debug session is ended by a match on a channel, the state sequ encer transitions through final state for a clock cycle to stat e 0. this is independent of tracing and brea kpoint activity, and with tracing and break points disabled, the state sequencer enter s state 0 and the debug module is disarmed. 5.19.4.4.1 final state on entering final state, a trigger may be issued to the trace buf fer according to the trace alignment control, as defined by th e talign bit (see section 5.19.3.2.3, ?debug trace control register (dbgtcr)" ? ). if the tsource bit in dbgtcr is clear, then the trace buffer is disabled and the transition to final stat e can only generate a breakpoint request. in this case or upon completion of a tracing session when tracing is enabled, the ar m bit in the dbgc1 register is cleared, returning the module to table 378. channel priorities priority source action highest trig enter final state channel pointing to final state transition to next state as defi ned by state control registers match0 (force or tag hit) transition to next state as defi ned by state control registers match1 (force or tag hit) transition to next state as defi ned by state control registers lowest match2 (force or tag hit) transition to next state as defi ned by state control registers state1 final state state3 arm = 1 session complete (disarm) state2 state 0 (disarmed) arm = 0 arm = 0 arm = 0
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 260 the disarmed state 0. if tracing is enabled, a breakpoint request can occur at the en d of the tracing session. if neither traci ng nor breakpoints are enabled, when the final state is reached, it returns automatically to state 0 and the debug module is disarmed. 5.19.4.5 trace buffer operation the trace buffer is a 64 lines deep by 20-bits wide ram array. t he dbg module stores trace information in the ram array in a circular buffer format. the system a ccesses the ram array through a register window (dbgtbh:dbgtbl) using 16-bit wide word accesses. after each complete 20-bit trace buffer line is read , an internal pointer into the ram increments so that the ne xt read receives fresh information. da ta is stored in the format shown in table 379 and ta b l e 375 . after each store the counter register dbgcnt is incremented. tracing of cpu activity is disabled when the bdm is active. reading the trace buffer while the dbg is armed, returns invalid data and t he trace buffer pointer is not incremented. 5.19.4.5.1 trace trigger alignment using the talign bit (see section 5.19.3.2.3, ?debug trace control register (dbgtcr)" ), it is possible to align the trigger with the end or the beginning of a tracing session. if end tracing is selected, tracing begins when the arm bit in dbgc1 is set and state1 is entered; the transition to final stat e signals the end of the tracing session. tracing with begin trigger starts at the opcode of the trigger. using end trigger or wh en the tracing is initia ted by writing to t he trig bit while configured for begin trigger, tracing starts in the second cycle afte r the dbgc1 write cycle. 5.19.4.5.1.1 storing with begin trigger storing with begin trigger, data is not stored in the trace buffer until the final state is entered. once the trigger condition is met, the dbg module remains armed until 64 lines are stored in the trac e buffer. if the trigger is at the address of the change-of-f low instruction, the change of flow associated with the trigger is st ored in the trace buffer. using begin trigger together with ta gging, if the tagged instruction is about to be executed, then the trace is started. upon completion of the tracing session, the break point is generated, thus the breakpoint does no t occur at the tagged instruction boundary. 5.19.4.5.1.2 storing with end trigger storing with end trigger, data is stored in the trace buffer until the final state is entered, at which point the dbg module becomes disarmed and no more data is stored. if the trigger is at the address of a c hange of flow instruction, the trigger even t is not stored in the trace buffer. 5.19.4.5.2 trace modes four trace modes are available. the mode is selected using the trcmod bits in t he dbgtcr register. tracing is enabled using the tsource bit in the dbgtcr re gister. the modes are described in the following subsections. 5.19.4.5.2.1 normal mode in normal mode, change of flow (cof) program counter (pc) addresses are stored. cof addresses are defined as follows: ? source address of taken conditional branches (long, short, bit-conditional, and loop primitives) ? destination address of indexed jmp, jsr, and call instruction ? destination address of rti, rts, and rtc instructions ? vector address of interrupts, except for bdm vectors lbra, bra, bsr, bgnd, as well as non-indexed jmp, jsr, and call instructions are not classified as change of flow and are not stored in the trace buffer. stored information includes the full 18-bit address bus and info rmation bits, which contains a source/destination bit to indica te whether the stored address was a so urce address or destination address.
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 261 note when a cof instruction with destination address is executed, the destination address is stored to the trace buffer on instruction comple tion, indicating the cof has taken place. if an interrupt occurs simultaneously, then the next in struction carried out is actually from the interrupt service routine. the instruction at the destination address of the original program flow gets executed after the interrupt service routine. in the following example, an irq interrupt occurs during execution of the indexed jmp at address mark1. the brn at the destination (s ub_1) is not executed until after the irq service routine, but the destination address is ente red into the trace buff er to indicate that the indexed jmp cof has taken place. ldx #sub_1 mark1 jmp 0,x ; irq interrupt occurs during execution of this mark2 nop ; sub_1 brn * ; jmp destination address trace buffer entry 1 ? ; rti destination address trace buffer entry 3 nop ; addr1 dbne a,part5 ; source address trace buffer entry 4 irq_isr ldab #$f0 ; irq vector $fff2 = trace buffer entry 2 stab var_c1 rti ; the execution flow taking into account the irq is as follows ldx #sub_1 mark1 jmp 0,x ; irq_isr ldab #$f0 ; stab var_c1 rti ; sub_1 brn * nop ; addr1 dbne a,part5 ; 5.19.4.5.2.2 loop1 mode loop1 mode, similarly to normal mode also stores only cof addre ss information to the trace buffer , it however allows the filter ing out of redundant information. the intent of loop1 mode is to prevent the trace buffer from being filled entirely with duplicate information from a looping construct, such as delays using the dbne instruction or pol ling loops using brset/brclr instructions. immediately after address information is placed in the trace buffer, the dbg module writes this value into a background register. this prevents consecutive duplicate address entries in the tr ace buffer resulting from repeated branches. loop1 mode only inhibits consecutive duplic ate source address entries that would typically be stored in most tight looping constructs. it does not inhibit repeated entri es of destination addresses or vector a ddresses, since repeat ed entries of these would most likely indicate a bug in the user?s c ode that the dbg module is designed to help find. 5.19.4.5.2.3 detail mode in detail mode, address and data for all memory and register accesse s is stored in the trace buffer. this mode is intended to supply additional information on indexed, indirect addressi ng modes where storing only the destination address would not provide all information required for a user to determine where th e code is in error. this mode also features information bit st orage to the trace buffer, for each address byte storage. the informati on bits indicate the size of access (word or byte) and the typ e of access (read or write). when tracing in detail mode, all cycles are traced except those when the cpu is either in a free or opcode fetch cycle.
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 262 5.19.4.5.2.4 compressed pure pc mode in compressed pure pc mode, the pc addresses of all exec uted opcodes, including where illegal opcodes are stored. a compressed storage format is used to increase the effective dept h of the trace buffer. this is achieved by storing the lower or der bits each time and using 2 information bits to indicate if a 64 byte boundary has been crossed, in which case the full pc is st ored. each trace buffer row consists of 2 information bits and 18 pc address bits note: when tracing is terminated using forced br eakpoints, latency in breakpoint generation means that opcodes following the opcode causing the breakpoi nt can be stored to the trace buffer. the number of opcodes is dependent on program flow. this can be avoided by using tagged breakpoints. 5.19.4.5.3 trace buffer organizati on (normal, loop1, detail modes) adrh, adrm, adrl denote address high, middle, and low byte respectively. the numerical suffix refers to the tracing count. the information format for loop1 and normal modes are identical. in detail mode, the address and data for each entry are stored on consecutive lines, thus the maximum number of entries is 32. in this case, dbgcnt bits are incremented twice, once for the address line, and once for the data line, on each trace buffer ent ry. in detail mode, cinf comprises of r/w and size access information (crw and csz respectively). single byte data accesses in detail mode are always stored to the low byte of the trace buffer (datal) and the high byte is cleared. when tracing word accesses, the byte at the lower add ress is always stored to trace buffer byte1 and the byte at the higher address is stored to byte0. 5.19.4.5.3.1 information bit organization the format of the bits is dependent upon the active trace mode as described by the following. 5.19.4.5.3.1.1 field2 bits in detail mode in detail mode, the csz and crw bits indicate the type of access being made by the cpu. table 379. trace buffer organization (normal, loop1, detail modes) mode entry number 4-bits 8-bits 8-bits field 2 field 1 field 0 detail mode entry 1 cinf1,adrh1 adrm1 adrl1 0 datah1 datal1 entry 2 cinf2,adrh2 adrm2 adrl2 0 datah2 datal2 normal/loop1 modes entry 1 pch1 pcm1 pcl1 entry 2 pch2 pcm2 pcl2 table 380. field2 bits in detail mode bit 3 bit 2 bit 1 bit 0 csz crw addr[17] addr[16]
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 263 5.19.4.5.3.1.2 field2 bits in normal and loop1 modes 5.19.4.5.4 trace buffer organizati on (compressed pure pc mode) table 381. field descriptions bit description 3 csz access type indicator ? this bit indicates if the access was a by te or word size when tracing in detail mode 0 word access 1 byte access 2 crw read write indicator ? this bit indicates if the corresponding stored address corresponds to a read or write access when tracing in detail mode. 0 write access 1 read access 1 addr[17] address bus bit 17 ? corresponds to system address bus bit 17. 0 addr[16] address bus bit 16 ? corresponds to system address bus bit 16. table 382. information bits pch bit 3 bit 2 bit 1 bit 0 csd cva pc17 pc16 table 383. pch field descriptions bit description 3 csd source destination indicator ? in normal and loop1 mode, this bit indicates if the corresponding stored address is a source or destination address. this bit has no meaning in compressed pure pc mode. 0 source address 1 destination address 2 cva vector indicator ? in normal and loop1 mode, this bit indicates if the corresponding stored address is a vector address. vector addresses are destination addresses, thus if cva is set, then the corresponding csd is also set. this bit has no meaning in compressed pure pc mode. 0 non-vector destination address 1 vector destination address 1 pc17 program counter bit 17 ? in normal and loop1 mode, this bit corresponds to program counter bit 17. 0 pc16 program counter bit 16 ? in normal and loop1 mode, this bit corresponds to program counter bit 16. table 384. trace buffer organization example (compressed purepc mode) mode line number 2-bits 6-bits 6-bits 6-bits field 3 field 2 field 1 field 0 compressed pure pc mode line 1 00 pc1 (initial 18-bit pc base address) line 2 11 pc4 pc3 pc2 line 3 01 0 0 pc5 line 4 00 pc6 (new 18-bit pc base address) line 5 10 0 pc8 pc7 line 6 00 pc9 (new 18-bit pc base address)
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 264 5.19.4.5.4.0.1 field3 bits in compressed pure pc modes each time pc[17:6] differs form the previ ous base pc[17:6], a new base address is stored. the base address zero value is the lowest address in the 64 address range. the first line of the trace buffer always gets a base pc address; this applies also on rollover. 5.19.4.5.5 reading data from trace buffer the data stored in the trace buffer can be read provided the dbg module is not armed, is configured for tracing (tsource bit is set), and the system not secured. when the arm bit is written to 1 the trace buffer, it is locked to prevent reading. the tr ace buffer can only be unlocked for reading by a single aligned word write to dbgtb when the module is disarmed. the trace buffer can only be read through the dbgtb register using aligned word reads. any byte or misaligned reads return 0 and does not cause the trace buffer pointer to increment to th e next trace buffer address. the trace buffer data is read out fi rst-in first-out. by reading cnt in dbgcnt, the number of valid lines can be determined. dbgcnt does not decrement as data is read. while reading, an internal pointer is used to determine the next line to be read. after a tracing session, the pointer points t o the oldest data entry. if no overflow has occurred, the pointer poin ts to line 0, otherwise it points to the line with the oldest e ntry. in compressed pure pc mode on rollover, the line with the oldest data entry may also contain newer data entries in fields 0 and 1. if rollover is indicated by the tbf bit, the line status must be decoded using the inf bits in field3 of that line. if both inf bits are clear, the line contains only entries from before the last rollover. ? if inf0=1, field 0 contains post rollover data but fields 1 and 2 contain pre rollover data. ? if inf1=1, fields 0 and 1 contain post rollover data but field 2 contains pre rollover data. the pointer is initialized by each aligned write to dbgtbh to point to the oldest data again. this enables an interrupted trace buffer read sequence to be easily restarted from the oldest data entry. the least significant word of line is read out first. this corresponds to the fields 1 and 0 of ta b l e 379 . the next word read returns field 2 in the least significant bi ts [3:0] and ?0? for bits [15:4]. reading the trace buffer while the dbg module is armed, retu rns invalid data and no shifting of the ram pointer occurs. 5.19.4.5.6 trace buffer reset state the trace buffer contents and dbgcnt bits are not initialized by a syst em reset. should a system reset occur, immediately before the reset occurred, the trace session information can be re ad out and the number of valid lines in the trace buffer is indicated by dbgcnt. the internal pointer to the current trace buffer address is in itialized by unlocking the trace buffer and points to the oldest valid data, even if a reset occurred during the tracing session. to read the trace buffer after a reset, tsource must be set, otherwise the trace buffer reads as all zeroes. generally , debugging occurrences of system resets are best handled usin g end trigger alignment, since the reset may occur before the trace trigger, which in the begin trigger alignment case, means no information would be stored in the trace buffer. the trace buffer contents and dbgcnt bits are undefined following a por. note an external pin reset that occurs simultaneous to a trace buffer entry can, in very few cases, lead to either that entry being corru pted, or the first entry of the session being corrupted. in such cases, the other contents of the trace buffer still contain valid tracing information. the case occurs wh en the reset assertion coincides with the trace buffer entry clock edge. table 385. compressed pure pc mode field 3 information bit encoding inf1 inf0 trace buffer row content 0 0 base pc address tb[17:0] contains a full pc[17:0] value 0 1 trace buffer[5:0] contain incremental pc relative to base address zero value 1 0 trace buffer[11:0] contain next 2 incremental pcs relative to base address zero value 1 1 trace buffer[17:0] contain next 3 incremental pcs relative to base address zero value
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 265 5.19.4.6 tagging a tag follows program information as it advances through the instruction queue. when a tagged instruction reaches the head of the queue, a tag hit occurs and can in itiate a state sequencer transition. each comparator control register features a tag bit, which co ntrols whether the comparator match causes a state sequencer transition immediately or tags the opcode at the matched add ress. if a comparator is enabled for tagged comparisons, the address stored in the comparator match address registers must be an opcode address. using begin trigger together with tagging, if the tagged instruct ion is about to be executed, th e transition to the next state sequencer state occurs. if the transition is to the final state, tracing is started. only upon co mpletion of the tracing sessio n can a breakpoint be generated. using end alignment, when the tagged instruction is about to be ex ecuted and the next transition is to final state, a breakpoint is generated immedi ately, before the tagged in struction is carried out. r/w monitoring, access size (sz) monitoring and data bus moni toring are not useful if tagging is selected, since the tag is attached to the opcode at the matched address and is not dependent on the data bus nor on ta type of access. these bits are ignored if tagging is selected. when configured for range comparisons and tagging, the ranges are accurate only to word boundaries. tagging is disabled when the bdm becomes active. 5.19.4.7 breakpoints it is possible to generate breakpoints from channel transitions to final state or use software to write to the trig bit in the dbgc1 register. 5.19.4.7.1 breakpoints from comparator channels breakpoints can be generated when the state sequencer transitions to the final state. if config ured for tagging, the breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue. if a tracing session is selected by the ts ource bit, breakpoints are requested when t he tracing session has completed. if begin aligned triggering is selected, the breakpoint is requ ested only on completion of the subsequent trace (see ta b l e 386 ). if no tracing session is selected, breakpoints are requested immediately. if the brk bit is set, the associated breakpoint is gener ated immediately independent of tracing trigger alignment. 5.19.4.7.2 breakpoints generated via the trig bit if a trig triggers occur, the final state is entered, where the tracing trigger alignment is defined by the talign bit. if a tr acing session is selected by the tsource bit, breakpoints are reque sted when the tracing session has completed. if begin aligned triggering is selected, the breakpo int is requested only on completion of the subsequent trace (see table 386 ). if no tracing session is selected, breakpoints are requested immediately. tr ig breakpoints are possible with a single write to dbgc1, setting arm and trig simultaneously. table 386. breakpoint setup for cpu breakpoints brk talign dbgbrk breakpoint alignment 0 0 0 fill trace buffer until trigger then disarm (no breakpoints) 0 0 1 fill trace buffer until trigger, then breakpoint request occurs 0 1 0 start trace buffer at trigger (no breakpoints) 0 1 1 start trace buffer at trigger a breakpoint request occurs when trace buffer is full 1 x 1 terminate tracing and generate break point immediately on trigger 1 x 0 terminate tracing immediately on trigger
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 266 5.19.4.7.3 breakpoint priorities if a trig trigger occurs after begin aligned tracing has alre ady started, then the trig no longer has an effect. when the associated tracing session is complete, the breakpoint occurs. similarly, if a trig is followed by a subsequent comparator channel match, it has no effect, si nce tracing has already started. if a forced swi breakpoint coincides with a bgnd in user code with bdm enabled, then the bdm is activated by the bgnd and the breakpoint to swi is suppressed. 5.19.4.7.3.1 dbg breakpoint prio rities and bdm interfacing breakpoint operation is dependent on the state of the bdm module . if the bdm module is active , the cpu is executing out of bdm firmware. comparator matches and associated breakpoint s are disabled. in addition, while executing a bdm trace command, tagging into bdm is disabled. if bdm is not active, th e breakpoint gives priority to bdm requests over swi requests if the breakpoint happens to coincide with a swi instruction in us er code. on returning from bdm, the swi from user code gets executed. bdm cannot be entered from a breakpoint unless the enable bit is set in the bdm. if entry to bdm via a bgnd instruction is attempted and the enable bit in the bdm is cleared, the cpu actually executes the bdm fi rmware code, checks the enable, and returns if enable is not set. if not serviced by the monito r, the breakpoint is re-asserted when the bdm returns to normal cpu flow. if the comparator r egister contents coincide with the swi/bdm vector ad dress, an swi in user code could coincide with a dbg breakpoint. the cpu ensures that bdm requests have a higher pr iority than swi requests. returning from the bdm/swi service routine, care must be taken to avoid a repeated breakpoint at the same address. should a tagged or forced breakpoint coincide with a bgnd in user code, the instruction that fo llows the bgnd instruction is th e first instruction executed when normal program execution resumes. note when program control returns from a tagged br eakpoint using an rti or bdm go command without program counter modification, it return s to the instruction whose tag generated the breakpoint. to avoid a repeated breakpoint at the same location, reconfigure the dbg module in the swi routine, if configured for an swi breakpoint, or over the bdm interface by executing a trace command before the go, to increment the prog ram flow past the tagged instruction. 5.19.5 application information 5.19.5.1 state machine scenarios defining the state control registers as scr1,scr2, scr3, and m0 ,m1,m2 as matches on channels 0, 1, 2 respectively. scr encoding supported by s12sdbgv1 are show n in black. scr encoding supported only in s12sdbgv2 are shown in red. for backwards compatibility the new scenarios use a 4th bit in each scr register. thus the existing encoding for scrx[2:0] is not changed. table 387. breakpoint mapping summary dbgbrk bdm bit (dbgc1[4]) bdm enabled bdm active breakpoint mapping 0 x x x no breakpoint 1 0 x 0 breakpoint to swi x x 1 1 no breakpoint 1 1 0 x breakpoint to swi 1 1 1 0 breakpoint to bdm
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 267 5.19.5.2 scenario 1 a trigger is generated if a given s equence of 3 code events is executed. figure 66. scenario 1 scenario 1 is possible with s12sdbgv1 scr encoding. 5.19.5.3 scenario 2 a trigger is generated if a given s equence of 2 code events is executed. figure 67. scenario 2a a trigger is generated if a given sequence of 2 code events is executed, whereby the first event is entry into a range (compa, compb configured for range mode). m1 is disabled in range modes. figure 68. scenario 2b a trigger is generated if a given sequence of 2 code events is ex ecuted, whereby the second event is entry into a range (compa, compb configured for range mode). figure 69. scenario 2c all 3 scenarios 2a, 2b, 2c are possible with the s12sdbgv1 scr encoding. state1 final state state3 state2 scr1=0011 scr2=0010 scr3=0111 m1 m2 m0 state1 final state state2 scr1=0011 scr2=0101 m1 m2 state1 final state state2 scr1=0111 scr2=0101 m01 m2 state1 final state state2 scr1=0010 scr2=0011 m2 m0
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 268 5.19.5.4 scenario 3 a trigger is generated immediately when one of up to 3 given events occurs. figure 70. scenario 3 scenario 3 is possible with s12sdbgv1 scr encoding. 5.19.5.5 scenario 4 trigger if a sequence of 2 events is carri ed out in an incorrect order. event a must be followed by event b, and event b must b e followed by event a. 2 consecutive occurr ences of event a without an intermediate event b causes a trigger. similarly 2 consecutive occurrences of event b without an intermediate event a causes a trigger. this is possible by using compa and compc to match on the same address as shown. figure 71. scenario 4a this scenario is currently not possible us ing 2 comparators only. s12sdbgv2 makes it possible with 2 comparators, state 3 allows a m0 to return to state 2, while a m2 leads to final state, as shown in figure 72 . figure 72. scenario 4b (with 2 comparators) the advantage of using only 2 channels is that range comparisons can now be included (channel0). this however violates the s12sdbgv1 specif ication, which states that a match leading to final state always has priority, in cas e of a simultaneous match, while priority is also given to the lowest channel number. for the s12sdbg, the corresponding cpu priority decoder is removed to support this, such that on si multaneous taghits, taghits pointing to final state have highest pr iority. state1 final state scr1=0000 m012 state1 state 3 final state state2 m0 m0 m2 m1 m1 m1 scr1=0100 scr2=0011 scr3=0001 state1 state 3 final state state2 m0 m01 m0 m2 m2 m2 scr1=0110 scr2= 1100 scr3= 1110 m1 disabled in range mode
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 269 if no taghit points to final state, then the lowest channel number has priority. with the above encoding fr om state3, the cpu a nd dbg would break on a simultaneous m0/m2. 5.19.5.6 scenario 5 trigger if following event a, event c precedes event b. i.e... the expected execution flow is a->b->c. figure 73. scenario 5 scenario 5 is possible with the s12sdbgv1 scr encoding. 5.19.5.7 scenario 6 trigger if event a occurs twice in succession before any of 2 ot her events (bc) occur. this scenario is not possible using the s12sdbgv1 scr encoding. s12sdbgv2 incl udes additions shown in red. the change in scr1 encoding also has the advantage that a state1->state3 transition using m0 is now possible. this is advantageous because range and data bus comparisons use channel 0 only. figure 74. scenario 6 5.19.5.8 scenario 7 trigger when a series of 3 events are executed out of order. s pecifying the event order as m1, m2, m0 to run in loops (120120120). any deviation from that order should trigger. this scenario is not possible using the s12sdbgv1 scr encoding, because or possibilities are very limited in the channel encoding. by adding or forks as shown in red, this scenario is possibl e. figure 75. scenario 7 state1 final state state2 scr1=0011 scr2=0110 m1 m0 m2 state1 final state state3 scr1= 1001 scr3= 1010 m0 m0 m12 state1 final state state3 state2 scr1= 1101 scr2= 1100 scr3= 1101 m1 m2 m12 m0 m02 m01
mcu - debug module (s12sdbg) mm912_637, rev. 3.0 freescale semiconductor 270 on simultaneous matches the lowest channel number has priority , so with this configuration the forking from state1 has the peculiar effect that a simultaneous match0 /match1 transitions to final state, but a simultaneous match2/match1transitions to state2. 5.19.5.9 scenario 8 trigger when a routine/event at m2 follows either m1 or m0. figure 76. scenario 8a trigger when an event m2 is followed by either an event m0 or event m1 figure 77. scenario 8b scenario 8a and 8b are possible with the s12sdbgv1 and s12sdbgv2 scr encoding. 5.19.5.10 scenario 9 trigger when a routine/event at a (m2) does not follow either b or c (m1 or m0) before they are executed again. this cannot be realized with the s12sdbgv1 scr encoding, due to or limitation s. by changing the scr2 encoding as shown in red this scenario becomes possible. figure 78. scenario 9 5.19.5.11 scenario 10 trigger if an event m0 occurs following up to two successive m2 events, without the resetting event m1. as shown, up to 2 consecutive m2 events are allowed, whereby a reset to state1 is po ssible, after either one or two m2 events. if an event m0 occ urs following the second m2, before m1 resets to state1, a trigge r is generated. configuring comp a and compc the same, it is possible to generate a breakpoint on the third cons ecutive occurrence of event m0 without a reset on m1. state1 final state state2 scr1=0111 scr2=0101 m01 m2 state1 final state state2 scr1=0010 scr2=0111 m2 m01 state1 final state state2 scr1=0111 scr2= 1111 m01 m01 m2
mm912_637, rev. 3.0 freescale semiconductor 271 figure 79. scenario 10a figure 80. scenario 10b scenario 10b shows the case that after m2, an m1 must occur before m0. starting from a particular point in code, event m2 must always be followed by m1 before m0. if after any m2 event, m0 occurs before m1, then a trigger is generated. state1 final state state3 state2 scr1=0010 scr2=0100 scr3=0010 m2 m2 m0 m1 m1 state1 final state state3 state2 scr1=0010 scr2=0011 scr3=0000 m2 m1 m0 m0
mcu - security (s12xs9secv2) mm912_637, rev. 3.0 freescale semiconductor 272 5.20 mcu - security (s12xs9secv2) 5.20.1 introduction this specification describes the fu nction of the security mechanism in the s12i chip family (9sec). note no security feature is absolutely secure. however, freescale?s strategy is to make reading or copying the flash and/or eeprom difficult for unauthorized users. 5.20.1.1 features the user must be reminded that pa rt of the security must lie with the applicati on code. an extreme example would be application code that dumps the contents of the internal memory. this woul d defeat the purpose of security. at the same time, the user may also wish to put a backdoor in the application program. an exampl e of this is the user downloads a security key through the sci , which allows access to a programming routine that updates parameters stored in another section of the flash memory. the security features of the s12i chip family (in secure mode) are: ? protect the content of non-volatile memo ries (flash, eeprom) ? execution of nvm commands is restricted ? disable access to internal memory via background debug module (bdm) 5.20.1.2 modes of operation table 388 gives an overview over availability of security relevant features in unsecure and secure modes. 5.20.1.3 securing the microcontroller once the user has programmed the flash and eeprom, the chip can be secured by progr amming the security bits located in the options/security byte in the flash memory array. these non- volatile bits will keep the device secured through reset and power-down. the options/security byte is located at addr ess 0xff0f (= global address 0x7f_ff0f) in the flash memory array. this byte can be erased and programmed like any other flash location. two bits of this byte are used for security (sec[1 :0]). on devices whic h have a memory page window, the flash options/security byte is also available at address 0xbf0f by selecting page 0x3f with the ppage register. the contents of this byte are copied into the flash security register (fsec) during a reset sequence. table 388. feature availability in unsecure and secure modes on s12xs unsecure mode secure mode ns ss nx es ex st ns ss nx es ex st flash array access ? ? 4 4 eeprom array access 4 4 4 4 nvm commands (254) 4 (254) (254) bdm 4 4 ? (255) dbg module trace 4 4 ? ? notes 254.restricted nvm command set only. refer to the nvm wrapper block guides for detailed information. 255.bdm hardware commands restricted to peripheral registers only. table 389. flash options/security byte 7 6 5 4 3 2 1 0 0xff0f keyen1 keyen0 nv5 nv4 nv3 nv2 sec1 sec0 analog mcu
mm912_637, rev. 3.0 freescale semiconductor 273 the meaning of the bits keyen[1:0] is shown in ta b l e 390 . refer to section 5.20.1.5.1, ?unsecurin g the mcu using the backdoor key access" for more information. the meaning of the security bits sec[1:0] is shown in table 391 . for security reasons, the state of device security is controlled by two bits. to put the device in unsecured mode, these bits must be programmed to sec[1:0] = ?10?. all other combinations put the device in a secured mode. the recommended value to put the de vice in secured state is the in verse of the unsecured state, i.e. sec[1:0] = ?01?. note refer to the flash block guide for actual secu rity configuration (in section ?flash module security?). 5.20.1.4 operation of the secured microcontroller by securing the device, unauthorized acce ss to the eeprom and flash memory content s can be prevented. however, it must be understood that the security of the e eprom and flash memory contents also depends on the design of the application program. for example, if the app lication has the capability of downloading code th rough a serial port and then executing that code (e.g. an application containing bootloader code), then this capability could potentially be used to read the eeprom and flash memory contents, even when t he microcontroller is in the secure state. in th is example, the security of the application c ould be enhanced by requiring a challenge/response auth entication before any code can be downloaded. secured operation has the following effects on the microcontroller: 5.20.1.4.1 normal singl e chip mode (ns) ? background debug module (bdm) operation is completely disabled. ? execution of flash and eeprom co mmands is restricted. refer to the nvm block guide for details. ? tracing code execution using the dbg module is disabled. 5.20.1.4.2 special si ngle chip mode (ss) ? bdm firmware commands are disabled. ? bdm hardware commands are restricted to the register space. ? execution of flash and eeprom co mmands is restricted. refer to the nvm block guide for details. ? tracing code execution using the dbg module is disabled. special single chip mode means bdm is active after reset. th e availability of bdm firmware commands depends on the security state of the device. the bdm secure firmware first performs a blank check of both the flash memory and the eeprom. if the blank check succeeds, security will be temporarily turned off and the state of the security bits in the appropriate flash memor y location can be changed. if the blank check fails, security will remain active, only the bdm hardware commands will be enabled, table 390. backdoor key access enable bits keyen[1:0] backdoor key access enabled 00 0 (disabled) 01 0 (disabled) 10 1 (enabled) 11 0 (disabled) table 391. security bits sec[1:0] security state 00 1 (secured) 01 1 (secured) 10 0 (unsecured) 11 1 (secured)
mm912_637, rev. 3.0 freescale semiconductor 274 and the accessible memory space is restricted to the peripheral register area. this will allow the bdm to be used to erase the eeprom and flash memory without giving access to their contents. after eras ing both flash memory and eeprom, another reset into special single chip mode will cause the blank check to succeed and the options/security byte can be programmed to ?unsecured? state via bdm. while the bdm is executing the blank check, the bdm interface is completely blocked, which means t hat all bdm commands are temporarily blocked. 5.20.1.5 unsecuring the microcontroller unsecuring the microcontroller can be done by three different methods: 1. backdoor key access 2. reprogramming the security bits 3. complete memory erase (special modes) 5.20.1.5.1 unsecuring the mcu using the backdoor key access in normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key access method. this method requires that: ? the backdoor key at 0xff00?0xff07 (= global addresse s 0x7f_ff00?0x7f_ff07) has been programmed to a valid value. ? the keyen[1:0] bits within the flash options/security byte select ?enabled?. ? in single chip mode, the application program programmed in to the microcontroller must be designed to have the capability to write to the backdoor key locations. the backdoor key values themselves would not normally be st ored within the application data, which means the application program would have to be designed to receive the backdoor key values from an external source (e.g. through a serial port). the backdoor key access method allows debugging of a secured mi crocontroller without having to erase the flash. this is particularly useful for failure analysis. note no word of the backdoor key is allowed to have the value 0x0000 or 0xffff. 5.20.1.6 reprogramming the security bits in normal single chip mode (ns), security can also be disabled by erasing and reprogramming the security bits within flash options/security byte to the unsecured va lue. because the erase oper ation will erase the entire sector from 0xfe00?0xffff (0x7f_fe00?0x7f_ffff), the backdoor key and the interrupt vect ors will also be erased; this method is not recommended for normal single chip mode. the application software can only erase and program the flash options/security byte if the flash secto r containing the flash options/securit y byte is not protected (see flash protection). flash protection is a useful means of preve nting this method. the microcontroller will enter the unsecured state after the next reset following the programming of the security bits to the unsecured value. this method requires that: ? the application software previously programmed into the mi crocontroller has been designed to have the capability to erase and program the flash optio ns/security byte, or security is first disa bled using the backdoor key method, allowing bdm to be used to issue commands to erase and program the flash options/security byte. ? the flash sector containing the flash options/security byte is not protected. 5.20.1.7 complete memory erase (special modes) the microcontroller can be unsecured in special modes by erasing the entire eeprom and flash memory contents. when a secure microcontroller is reset into special single chip mode (ss), the bdm firmware verifies whether the eeprom and flash memory are erased. if any eeprom or flash memory addr ess is not erased, only bdm hardware commands are enabled. bdm hardware commands can then be used to write to the eeprom and flash regist ers to mass erase th e eeprom and all flash memory blocks.
mm912_637, rev. 3.0 freescale semiconductor 275 when next resetting into special single chip mode, the bdm firmware will again verify whether all eeprom and flash memory are erased. this being the case, it will enable all bdm commands , allowing the flash options/security byte to be programmed to the unsecured value. the security bits sec[1:0] in the flash secu rity register will indicate the unsecure state following the n ext reset.
background debug module (s12sbdmv1) mm912_637, rev. 3.0 freescale semiconductor 276 5.21 background debug module (s12sbdmv1) 5.21.1 introduction this section describes the functionalit y of the background debug module (bdm) sub-block of the hcs12s core platform. the background debug module (bdm) sub-block is a single-wir e, background debug system, implemented in on-chip hardware for minimal cpu intervention. all interfac ing with the bdm is done via the bkgd pin. the bdm has enhanced capability for maintaining synchronization be tween the target and host while allowing more flexibility in clock rates. this includes a sync signal to determine the communication rate and a handshake signal to indicate when an operation is complete. th e system is backwards compatible to the bdm of the s12 family with t he following exceptions: ? taggo command not supported by s12sbdm ? external instruction tagging feat ure is part of the dbg module ? s12sbdm register map and register content modified ? family id readable from bdm rom at global address 0x3_ff0f in active bdm ? (value for devices with hcs12s core is 0xc2) ? clock switch removed from bdm (clksw bit removed from bdmsts register) 5.21.1.1 features the bdm includes these distinctive features: ? single-wire communication with host development system ? enhanced capability for allowing more flexibility in clock rates ? sync command to determine communication rate ? go_until(262) command ? hardware handshake protocol to increase the performance of the serial communication ? active out of reset in special single chip mode ? nine hardware commands using free cycles, if available, for minimal cpu intervention ? hardware commands not requiring active bdm ? 14 firmware commands execute from the standard bdm firmware lookup table ? software control of bdm operation during wait mode ? when secured, hardware commands are allowed to access the r egister space in special single chip mode, if the flash erase tests fail ? family id readable from bdm rom at global address 0x3_ff0f in active bdm ? (value for devices with hcs12s core is 0xc2) ? bdm hardware commands are operational until system stop mode is entered 5.21.1.2 modes of operation bdm is available in all operating modes, but must be e nabled before firmware commands ar e executed. some systems may have a control bit that allows suspending the function during background debug mode. 5.21.1.2.1 regular run modes all of these operations refer to the part in run mode and not be ing secured. the bdm does not pr ovide controls to conserve powe r during run mode. ? normal modes - general operation of the bdm is av ailable and operates the same in all normal modes ? special single chip mode - in special single chip mode, background operation is enabled and active out of reset. this allows programming a system with blank memory 5.21.1.2.2 secure mode operation if the device is in secure mode, the operati on of the bdm is reduced to a small subset of its regular run mode operation. secur e operation prevents access to flash other than allowing erasure. for more information, see section 5.21.4.1, ?security" . analog mcu
background debug module (s12sbdmv1) mm912_637, rev. 3.0 freescale semiconductor 277 5.21.1.2.3 low-power modes the bdm can be used until stop mode is entered. when cpu is in wait mode, a ll bdm firmware commands as well as the hardware background command cannot be used and are ignored. in this case, the cpu can not enter bdm active mode, and only hardware read and write commands are available. also, the cpu can not enter a low powe r mode (stop or wait) during bdm active mode. in stop mode, the bdm clocks are stopped. when bdm clocks are disabled and stop mode is exited, the bdm clocks will restart and bdm will have a soft reset (clearing the instruction regist er, any command in progress and disable the ack function). the bdm is now ready to receive a new command. 5.21.1.3 block diagram a block diagram of the bdm is shown in figure 81 . figure 81. bdm block diagram 5.21.2 external signal description a single-wire interface pin called the background debug interf ace (bkgd) pin is used to communicate with the bdm system. during reset, this pin is a mode select input which selects betwe en normal and special modes of operation. after reset, this pi n becomes the dedicated serial interface pin for the background deb ug mode. the communication rate of this pin is based on the settings for the vco clock (cpmusynr). the bdm clock frequen cy is always vco clock frequency divided by 8. after reset, the bdm clock is based on the reset values of the cpmusynr register (4.0 mhz). when modifying the vco clock, make sure that the communication rate is adapted accordingly, and a communication timeout (bdm soft reset) has occurred. 16-bit shift register bkgd host system serial interface data control register block register bdmsts instruction code and execution standard bdm firmware lookup table secured bdm firmware lookup table bus interface and control logic address data control clocks bdmact trace enbdm sdv unsec
background debug module (s12sbdmv1) mm912_637, rev. 3.0 freescale semiconductor 278 5.21.3 memory map and register definition 5.21.3.1 module memory map table 392 shows the bdm memory map when bdm is active. 5.21.3.2 register descriptions a summary of the registers associated with the bdm is shown in table 393 . registers are accessed by host-driven communications to the bdm hardware using read_bd and write_bd commands. table 392. bdm memory map global address module size (bytes) 0x3_ff00?0x3_ff0b bdm registers 12 0x3_ff0c?0x3_ff0e bdm firmware rom 3 0x3_ff0f family id (part of bdm firmware rom) 1 0x3_ff10?0x3_ffff bdm firmware rom 240 table 393. bdm register summary global address register name bit 7 6 5 4 3 2 1 bit 0 0x3_ff00 reserved r x x x x x x 0 0 w 0x3_ff01 bdmsts r enbdm bdmact 0 sdv trace 0 unsec 0 w z z 0x3_ff02 reserved r x x x x x x x x w 0x3_ff03 reserved r x x x x x x x x w 0x3_ff04 reserved r x x x x x x x x w 0x3_ff05 reserved r x x x x x x x x w 0x3_ff06 bdmccr r ccr7 ccr6 ccr5 ccr4 ccr3 ccr2 ccr1 ccr0 w 0x3_ff07 reserved r 0 0 0 0 0 0 0 0 w 0x3_ff08 bdmppr r bpae 0 0 0 bpp3 bpp2 bpp1 bpp0 w 0x3_ff09 reserved r 0 0 0 0 0 0 0 0 w 0x3_ff0a reserved r 0 0 0 0 0 0 0 0 w = unimplemented, reserved z = implemented (do not alter) x = indeterminate 0 = always read zero
background debug module (s12sbdmv1) mm912_637, rev. 3.0 freescale semiconductor 279 5.21.3.2.1 bdm status register (bdmsts) read: all modes through bdm operation when not secured write: all modes through bdm operation when not secured, but subject to the following: ? enbdm should only be set via a bdm hardware command if the bdm firmware commands are needed. (this does not apply in special single chip mode) ? bdmact can only be set by bdm hardware upon entry into bdm. it can only be cleared by the standard bdm firmware lookup table upon exit from bdm active mode ? all other bits, while writable via bdm hardware or stand ard bdm firmware write command s, should only be altered by the bdm hardware or the standard firmware lo okup table, as part of bdm command execution 0x3_ff0b reserved r 0 0 0 0 0 0 0 0 w table 394. bdm status register (bdmsts) register global address 0x3_ff01 7 6 5 4 3 2 1 0 r enbdm bdmact 0 sdv trace 0 unsec 0 w reset special single-chip mode 0 (256) 1 0 0 0 0 0 (257) 0 all other modes 0 0 0 0 0 0 0 0 = unimplemented, reserved z = implemented (do not alter) 0 = always read zero notes 256.enbdm is read as a 1 by a debugging environment in special singl e chip mode, when the device is either secured or not secur ed, but fully erased (flash). this is because the enbdm bit is set by the standard bdm firmware before a bdm command can be fully transmitted and executed. 257.unsec is read as a 1 by a debugging environment in special si ngle chip mode when the device is secured and fully erased, el se it is 0 and can only be read if not secure (see also bit description). table 395. bdmsts field descriptions field description 7 enbdm enable bdm ? this bit controls whether the bdm is enabled or di sabled. when enabled, bdm can be made active to allow firmware commands to be executed. when disabled, bdm cannot be made active but bdm hardware commands are still allowed. 0 bdm disabled 1 bdm enabled note: enbdm is set out of reset in special single chip mode. in spec ial single chip mode with the device secured, this bit will not be set until after the flash erase verify tests are complete. 6 bdmact bdm active status ? this bit becomes set upon entering bdm. the standard bdm firmware lookup table is then enabled and put into the memory map. bdmact is cleared by a carefully timed store instruction in the standard bdm firmware, as part of the exit sequence to return to user code and remove the bdm memory from the map. 0 bdm not active 1 bdm active table 393. bdm register summary (continued) global address register name bit 7654321bit 0 = unimplemented, reserved z = implemented (do not alter) x = indeterminate 0 = always read zero
background debug module (s12sbdmv1) mm912_637, rev. 3.0 freescale semiconductor 280 read: all modes through bdm operation when not secured write: all modes through bdm operation when not secured note when bdm is made active, the cpu stores the content of its ccr register in the bdmccr register. however, out of special single-chip reset, the bdmccr is set to 0xd8 and not 0xd0 which is the reset value of the ccr register in this cpu mode. out of reset in all other modes the bdmccr register is read zero. when entering background debug mode, the bdm ccr holding register is used to save the condition code register of the user?s program. it is also used for temporary st orage in the standard bdm firmware mode. the bdm ccr holding register can be written to modify the ccr value. 4 sdv shift data valid ? this bit is set and cleared by the bdm hardware. it is set after data has been transmitted as part of a bdm firmware or hardware read command, or after data has been received as part of a bdm firmware or hardware write command. it is cleared when the next bdm command has been received or bd m is exited. sdv is used by the standard bdm firmware to control program flow execution. 0 data phase of command not complete 1 data phase of command is complete 3 trace trace1 bdm firmware command is being executed ? this bit gets set when a bdm trace1 firmware command is first recognized. it will stay set until bdm firmware is exited by one of the following bdm commands: go or go_until(262) . 0 trace1 command is not being executed 1 trace1 command is being executed 1 unsec unsecure ? if the device is secured this bit is only writable in special single chip m ode from the bdm secure firmware. it is in a zero state as secure mode is entered so that the secu re bdm firmware lookup table is enabled and put into the memory map, overlapping the standard bdm firmware lookup table. the secure bdm firmware lookup table verifies that the on-chip flash is erased. this being the case, the unsec bit is set and the bdm program jumps to the start of the standard bdm firmwa re lookup table, and the secure bdm firmware lookup table is turned off. if the erase test fails, the unsec bit will not be asserted. 0 system is in a secured mode. 1 system is in a unsecured mode. note: when unsec is set, security is off and the user can change the state of the secure bits in the on-chip flash eeprom. note that if the user does not change the state of the bits to ?unsecured? mode, the system will be secured again when it is next taken out of reset. after reset, this bit has no m eaning or effect when the security byte in the flash eeprom is configured for unsecure mode. table 396. bdm ccr holding register (bdmccr) register global address 0x3_ff06 7 6 5 4 3 2 1 0 r ccr7 ccr6 ccr5 ccr4 ccr3 ccr2 ccr1 ccr0 w reset special single-chip mode 1 1 0 1 1 0 0 0 all other modes 0 0 0 0 0 0 0 0 table 395. bdmsts field descriptions (continued) field description
background debug module (s12sbdmv1) mm912_637, rev. 3.0 freescale semiconductor 281 5.21.3.2.2 bdm program page index register (bdmppr) read: all modes through bdm operation when not secured write: all modes through bdm operation when not secured 5.21.3.3 family id assignment the family id is an 8-bit value located in the bdm rom in acti ve bdm (at global address: 0x3_ff0f). the read-only value is a unique family id which is 0xc2 for devices with an hcs12s core. 5.21.4 functional description the bdm receives and executes commands from a host via a single wire serial interface. there are two types of bdm commands: hardware and firmware commands. hardware commands are used to read and write target system me mory locations and to enter active background debug mode. see section 5.21.4.3, ?bdm hardware commands" . target system memory includes all me mory that is accessible by the cpu. firmware commands are used to read and write cpu resour ces and to exit from active background debug mode. see section 5.21.4.4, ?standard bdm firmware commands" . the cpu resources referred to are the accumulator (d), x index register (x), y index register (y), sta ck pointer (sp), and program counter (pc). hardware commands can be executed at any time and in any mode, excluding a few exceptions as highlighted (see section 5.21.4.3, ?bdm hardware commands" ) and in secure mode (see section 5.21.4.1, ?security" ). bdm firmware commands can only be executed when th e system is not secure and is in active background debug mode (bdm). 5.21.4.1 security if the user resets in to special single chip mode with t he system secured, a secured mode bdm firmware lookup table is brought into the map overlapping a portion of the standard bdm firmware lo okup table. the secure bdm firm ware verifies that the on-chip flash eeprom is erased. this being the case, the unsec and en bdm bits will get set. the bdm program jumps to the start of the standard bdm firmware, the secured mode bdm firmware is turned off, and all bdm commands are allowed. if the flash does not verify as erased, the bdm firmware sets the enbdm bi t, without asserting unsec, and t he firmware enters a loop. this causes the bdm hardware commands to become enabled, but does not enable the firmware commands. this allows the bdm hardware to be used to erase the flash. table 397. bdm program page register (bdmppr) register global address 0x3_ff08 7 6 5 4 3 2 1 0 r bpae 0 0 0 bpp3 bpp2 bpp1 bpp0 w reset 0 0 0 0 0 0 0 0 = unimplemented, reserved table 398. bdmppr field descriptions field description 7 bpae bdm program page access enable bit ? bpae enables program page access for bdm hardware and firmware read/write instructions the bdm hardware commands used to access the bdm registers ( read_bd and write_bd ) can not be used for global accesses even if the bgae bit is set. 0 bdm program paging disabled 1 bdm program paging enabled 3?0 bpp[3:0] bdm program page index bits 3?0 ? these bits define the selected program page. for more detailed information regarding the program page window scheme, refer to the s12s_mmc block guide.
background debug module (s12sbdmv1) mm912_637, rev. 3.0 freescale semiconductor 282 bdm operation is not possible in any other mode than special si ngle chip mode when the device is secured. the device can only be unsecured via the bdm serial interface in special single chip mode. for more information regarding security, see the s12s_9sec block guide. 5.21.4.2 enabling and activating bdm the system must be in active bdm to execute standard bd m firmware commands. bdm can be activated only after being enabled. bdm is enabled by setting the enbdm bit in the bdm stat us (bdmsts) register. the enbdm bit is set by writing to the bdm status (bdmsts) register, via the single-wire interface, using a hardware command such as write_bd_byte . after being enabled, bdm is activated by one of the following (258) : ? hardware background command ? cpu bgnd instruction ? breakpoint force or tag mechanism (259) notes 258.bdm is enabled and active immediately out of special single-chip reset. 259.this method is provided by the s12s_dbg module. when bdm is activated, the cpu finishes executing the current instruction and then begins executing the firmware in the standard bdm firmware lookup table. when bdm is activated by a breakpoint, the type of breakpoint used determines if bdm becomes active before or after execution of the next instruction. note if an attempt is made to activate bdm before being enabled, the cpu resumes normal instruction execution after a brief dela y. if bdm is not enabled, any hardware background commands issued are ignored by the bdm and the cpu is not delayed. in active bdm, the bdm registers and standard bdm firmwar e lookup table are mapped to addresses 0x3_ff00 to 0x3_ffff. bdm registers are mapped to addresses 0x3_ff00 to 0x3_ff0b. the bdm uses these registers which are readable anytime by the bdm. however, these registers are not readable by user programs. when bdm is activated, while cpu executes code overlapping with the bdm firmware space, the saved program counter (pc) will be auto incremented by one from the bdm firmware, regard less of what caused the entry into bdm active mode (bgnd instruction, background command or breakpoints). in such ca ses, the pc must be set to the next valid address via a write_pc command, before executing the go command. 5.21.4.3 bdm hardware commands hardware commands are used to read and write target system me mory locations and to enter active background debug mode. target system memory includes all memory t hat is accessible by the cpu such as on-ch ip ram, flash, i/o and control registers. hardware commands are executed with mini mal or no cpu intervention, and do not require the system to be in active bdm for execution, although, they can st ill be executed in this mode. when executing a hardware command, the bdm sub-block waits for a free bus cycle, so the background access does not disturb the ru nning application program. if a free cycle is not found withi n 128 clock cycles, the cpu is momentarily frozen so the bdm can steal a cycle. when the bdm finds a free cycle, the operation does not intrude on normal cpu operation, provided it can be comp leted in a single cycle. however, if an operation requires multiple cycles, the cpu is frozen until the operation is complete, even though the bdm found a free cycle. the bdm hardware commands are listed in table 399 . the read_bd and write_bd commands allow access to the bdm register locations. these locations are not normally in the system memory map, but share addresses with the application in memory. to distinguish between physical memory locations that share the same address, bdm memo ry resources are enabled just for the read_bd and write_bd access cycle. this allows the bdm to access bdm locations unobtrusively, even if the addresses conflict with the application memory map.
background debug module (s12sbdmv1) mm912_637, rev. 3.0 freescale semiconductor 283 if enabled, ack will occur when data is ready for transmission for all bdm read commands, and will occur after the write is complete for all bdm write commands. 5.21.4.4 standard bdm firmware commands bdm firmware commands are used to access and manipulate cpu resources. the system must be in active bdm to execute standard bdm firmware commands. see section 5.21.4.2, ?enabling and activating bdm" . normal instruction execution is suspended while the cpu executes the firmware located in the standard bdm firmware lookup table. the hardware command background is the usual way to activate bdm. as the system enters active bdm, the standard bdm firmware lookup table, bdm r egisters become visible in the on-chip memory map at 0x3_ff00?0x3_ffff, and the cpu begins executing the standard bdm firmware. the standard bdm firmware watches for serial commands and executes them as they are received. the firmware commands are shown in ta b l e 400 . table 399. hardware commands command opcode (hex) data description background 90 none enter background mode if bdm is enabled. if enabled, an ack will be issued when the part enters active background mode. ack_enable d5 none enable handshake. issues an ack pul se after the command is executed. ack_disable d6 none disable handshake. this comm and does not issue an ack pulse. read_bd_byte e4 16-bit address 16-bit data out read from memory with standard bdm firmware lookup table in map. ? odd address data on low byte; even address data on high byte. read_bd_word ec 16-bit address 16-bit data out read from memory with standard bdm firmware lookup table in map. ? must be aligned access. read_byte e0 16-bit address 16-bit data out read from memory with standard bdm firmware lookup table out of map. ? odd address data on low byte; even address data on high byte. read_word e8 16-bit address 16-bit data out read from memory with standard bdm firmware lookup table out of map. must be aligned access. write_bd_byte c4 16-bit address 16-bit data in write to memory with standard bdm firmware lookup table in map. ? odd address data on low byte; even address data on high byte. write_bd_word cc 16-bit address 16-bit data in write to memory with standard bdm firmware lookup table in map. ? must be aligned access. write_byte c0 16-bit address 16-bit data in write to memory with standard bdm firmware lookup table out of map. ? odd address data on low byte; even address data on high byte. write_word c8 16-bit address 16-bit data in write to memory with standard bdm firmware lookup table out of map. ? must be aligned access. table 400. firmware commands command (260) opcode (hex) data description read_next (261) 62 16-bit data out increment x index register by 2 (x = x + 2), then read word x points to. read_pc 63 16-bit data out read program counter. read_d 64 16-bit data out read d accumulator. read_x 65 16-bit data out read x index register. read_y 66 16-bit data out read y index register. read_sp 67 16-bit data out read stack pointer. write_next 42 16-bit data in increment x index register by 2 (x = x + 2), then write word to location pointed to by x.
background debug module (s12sbdmv1) mm912_637, rev. 3.0 freescale semiconductor 284 5.21.4.5 bdm command structure hardware and firmware bdm commands start with an 8-bit opc ode followed by a 16-bit address and/or a 16-bit data word, depending on the command. all the read commands return 16 bits of data despite the byte or word implication in the command name. 8-bit reads return 16-bits of data, only one by te of which contains valid data. if reading an even address, the valid data will appear in the m sb. if reading an odd address, the valid data will appear in the lsb. 16-bit misaligned reads and writes are generally not allowed. if attempted by bdm hardware command, the bdm ignores the least significant bit of the address and assumes an even address from the remaining bits. for hardware data read commands, the external host must wait at least 150 bus clock cycles after sending the address before attempting to obtain the read data. this is to be certain that valid data is available in the bdm shift register, ready to be s hifted out. for hardware write commands, th e external host must wait 150 bus clock cycles after sending the data to be written, before attempting to send a new command. this is to avoid disturbing the bdm shift register before the write has been completed. the 150 bus clock cycle delay, in both cases, includes the maximum 128 cycle delay that can be incurred, as the bdm waits for a free cycle before stealing a cycle. the external host s hould wait at least 48 bus clock cycles after sending the command opcode and befo re attempting to obtain the read data for bdm firmware read commands. the 48 cycle wa it allows enough time for the requested data to be made available in the bdm shift register, ready to be shifted out. the external host must wait 36 bus clock cycles after sending the data to be written, before attempting to send a new command for bdm firmware write commands. this is to avoid disturbi ng the bdm shift register befor e the write has been completed. the external host should wait for at least for 76 bus clock cycles, after a trace1 or go command and before starting any new serial command. this is to allow the cp u to exit gracefully from the standard bd m firmware lookup table and resume execution of the user code. disturbing the bdm shift register prematurely may adversely affect the exit from the standard bdm firmware lookup table. write_pc 43 16-bit data in write program counter. write_d 44 16-bit data in write d accumulator. write_x 45 16-bit data in write x index register. write_y 46 16-bit data in write y index register. write_sp 47 16-bit data in write stack pointer. go 08 none go to user program. if enabled, ack will occur when leaving ac tive background mode. go_until (262) 0c none go to user program. if enabled, ack wi ll occur upon returning to active background mode. trace1 10 none execute one user instruction then return to active bdm. if enabled, ack will occur upon returning to active background mode. taggo -> go 18 none (previous enable tagging and go to user pr ogram.) this command will be deprecated and should not be used anymore. opcode will be executed as a go command. notes 260.if enabled, ack will occur when data is r eady for transmission for all bdm read commands, and will occur after the write is complete for all bdm write commands. 261.when the firmware command read_next or write_next is used to access the bdm address space, the bdm resources are accessed, rather than user code. wr iting bdm firmware is not possible. 262.system stop disables the ack function and ignored commands wi ll have no ack-pulse (e.g., cpu in stop or wait mode). the go_ until command will not get an acknowledge, if the cpu executes the wait or stop instruction before the ?until? condition (bdm active again) is reached (see section 5.21.4.7, ?serial interface hardware handshake protocol" last note). table 400. firmware commands command (260) opcode (hex) data description
background debug module (s12sbdmv1) mm912_637, rev. 3.0 freescale semiconductor 285 note if the bus rate of the target processor is unk nown or could be changing, it is recommended that the ack (acknowledge function) is used to indicate when an operation is complete. when using ack, the delay times are automated. figure 82 represents the bdm command structure. the command blocks illus trate a series of eight bit times, starting with a falling edge. the bar across the top of the blocks in dicates that the bkgd line idle s in the high state. the time for an 8-bit command is 8 ? 16 target clock cycles. (263) notes 263.target clock cycles are cycles measured using the tar get mcu?s serial clock rate. see section 5.21.4.6, ?bdm serial interface" and section 5.21.3.2.1, ?bdm status register (bdmsts)" for information on how seri al clock rate is selected. figure 82. bdm command structure 5.21.4.6 bdm serial interface the bdm communicates with external devices serially via the bkg d pin. during reset, this pin is a mode select input which selects between normal and special modes of operation. after reset, this pin becomes the dedicated serial interface pin for the bdm. the bdm serial interface is timed, based on the vco clock (refe r to the cpmu block guide for more details), which gets divided by 8. this clock will be referred to as t he target clock in the following explanation. the bdm serial interface uses a clocking scheme in which the external host generates a falling edge on the bkgd pin to indicate the start of each bit time. this falling edge is sent for every bi t whether data is transmitted or received. data is transferre d, most significant bit (msb) first, at 16 target clock cycles per bi t. the interface times out if 512 clock cycles occur between falli ng edges from the host. the bkgd pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. it is assumed that there is an external pull-up and drivers c onnected to bkgd do not typically drive the high level. since r-c rise time could be unacceptably long, the target system and host provide brief driv en-high (speedup) pulses to drive bkgd to a logic 1. the source of this speedup pulse is the host for transmit cases and the target for receive cases. the timing for host-to-target is shown in figure 83 , and that of target-to-host in figure 84 and figure 85 . all four cases begin when the host drives the bkgd pin low to generate a falling edge. since the host and target are op erating from separate clocks, it can take the target system up to one full clock cycle to recognize this edge. the target measures delays from this perceived hardware hardware firmware firmware go, 48-bc bc = bus clock cycles command address 150-bc delay next delay 8-bits at ~16 tc/bit 16-bits at ~16 tc/bit 16 bits at ~16 tc/bit command address data next data read write read write trace command next command data 76-bc delay next command 150-bc delay 36-bc delay command command command command data next command tc = target clock cycles
background debug module (s12sbdmv1) mm912_637, rev. 3.0 freescale semiconductor 286 start of the bit time, while the host measur es delays from the point it actually drov e bkgd low to start the bit up to one targ et clock cycle earlier. synchronization between the host and target is established in this manner at the start of every bit time. figure 83 shows an external host transmitting a logic 1 and transmit ting a logic 0 to the bkgd pin of a target system. the host is asynchronous to the target, so there is up to a one clock- cycle delay from the host-generated falling edge to where the targ et recognizes this edge as the beginning of the bit time. ten ta rget clock cycles later, the target senses the bit level on the bk gd pin. internal glitch detect logic requires the pin be driven high no later that eight target clock cycles after the falling edg e for a logic 1 transmission. since the host drives the high speedup pulses in these two ca ses, the rising edges look like digitally driven signals. figure 83. bdm host-to-target serial bit timing the receive cases are more complicated. figure 84 shows the host receiving a logic 1 from the target system. since the host is asynchronous to the target, there is up to one clock cycle delay from the host-generated falling edge on bkgd to the perceived start of the bit time in the target. the host holds the bkgd pin low long enough for the target to recognize it (at least two t arget clock cycles). the host must release the low drive before the ta rget drives a brief high speedup pulse seven target clock cycle s after the perceived start of the bit time. the host should sample the bit level about 10 target clock cycles after it started t he bit time. figure 84. bdm target-to-host seri al bit timing (logic 1) target senses bit 10 cycles synchronization uncertainty bdm clock (target mcu) host transmit 1 host transmit 0 perceived start of bit time earliest start of next bit high-impedance earliest start of next bit r-c rise 10 cycles 10 cycles host samples bkgd pin perceived start of bit time bkgd pin bdm clock (target mcu) host drive to bkgd pin target system speedup pulse high-impedance high-impedance
background debug module (s12sbdmv1) mm912_637, rev. 3.0 freescale semiconductor 287 figure 85 shows the host receiving a logic 0 from the target. since t he host is asynchronous to the target, there is up to a one clock cycle delay from the host-generated falling edge on bkgd to the start of the bit time as perceived by the target. the hos t initiates the bit time but the target finishes it. since the targ et wants the host to receive a l ogic 0, it drives the bkgd pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge. the host samples the bit level about 10 target clock cycles after starting the bit time. figure 85. bdm target-to-host seri al bit timing (logic 0) 5.21.4.7 serial interface hardware handshake protocol bdm commands that require cpu execution are ultimately treate d at the mcu bus rate. since the bdm clock source can be modified when changing the settings for the vco frequency (cpmusyn r), it is very helpful to provide a handshake protocol in which the host could determine when an issued command is ex ecuted by the cpu. the bdm clock frequency is always vco frequency divided by 8. the alternative is to always wait the am ount of time equal to the appropriate number of cycles at the slowest possible rate the clock could be running. this sub-section will describe the ha rdware handshake protocol. the hardware handshake protocol signals to the host controller when an issued comm and was successfully executed by the target. this protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the bkgd pin. th is pulse is generated by the target mcu when a command, i ssued by the host, has been successfully executed (see figure 86 ). this pulse is referred to as the ack pulse. after the ack pulse has finished: the host can start the bit retrieval if the last issued command was a read command, or start a new command if t he last command was a write command or a control command (background, go , go_until(262) or trace1 ). the ack pulse is not issued earlier than 32 serial clock cycles after the bdm command was issued. the end of the bdm command is assumed to be the 16th tick of the last bit. this minimum delay assures enough time for the host to perceive the ack pulse. note also that, there is no upper limit for the delay between the command and the related ack pulse, since t he command execution depends upon the cpu bus, which in some cases could be very slow due to long accesses taking place.this protocol allows a great flexibility for the pod designers, since it does not r ely on any accurate time measurement or short response time to any event in the serial communication. earliest start of next bit bdm clock (target mcu) host drive to bkgd pin bkgd pin perceived start of bit time 10 cycles 10 cycles host samples bkgd pin target system drive and speedup pulse speedup pulse high-impedance
background debug module (s12sbdmv1) mm912_637, rev. 3.0 freescale semiconductor 288 figure 86. target acknow ledge pulse (ack) note if the ack pulse was issued by the target, the host assumes the previous command was executed. if the cpu enters wait or stop prior to executing a hardware command, the ack pulse will not be issued meaning that the bdm command was not executed. after entering wait or stop mode, the bdm command is no longer pending. figure 87 shows the ack handshake protocol in a command level timing diagram. the read_byte instruction is used as an example. first, the 8-bit instruct ion opcode is sent by the host, followed by the address of the memory location to be read. th e target bdm decodes the instruction. a bus cycle is grabbed (f ree or stolen) by the bdm and it executes the read_byte operation. having retrieved the data, the bdm issues an ack pulse to the host controller, indicating that the addressed byte is ready to be retrieved. after detecting the ac k pulse, the host initiates the byte retrieva l process. note that data is sent in the form of a word, and the host needs to determine which is the appr opriate byte, based on whether the address was odd or even. figure 87. handshake protocol at command level differently from the normal bit transfer (w here the host initiates the transmission), the serial interface ack handshake pulse is initiated by the target mcu by issuing a negative edge on the bkgd pin. the hardware handshake protocol in figure 86 specifies the timing when the bkgd pin is being driven, so the host should fo llow this timing constraint to avoid the risk of an electric al conflict on the bkgd pin. note the only place the bkgd pin can hav e an electrical conflict is when one side is driving low and the other side is issuing a speedup pulse (high). other ?highs? are pulled rather than driven. the time of the speedup pulse can becom e lengthy at low rates, and so the potential conflict time becomes longer as well. 16 cycles bdm clock (target mcu) target transmits ack pulse high-impedance bkgd pin minimum delay from the bdm command 32 cycles earliest start of next bit speedup pulse 16th tick of the last command bit high-impedance read_byte bdm issues the bkgd pin byte address bdm executes the read_byte command host target host ta r g e t bdm decodes the command ack pulse (out of scale) host target (2) bytes are retrieved new bdm command
background debug module (s12sbdmv1) mm912_637, rev. 3.0 freescale semiconductor 289 the ack handshake protocol does not support nested ack pulses. if a bdm command is not acknowledge by an ack pulse, the host needs to abort the pending command first in order to be able to issue a new bdm command. when the cpu enters wait or stop while the host issues a hardware command (e.g., wr ite_byte), the target discards the incoming command due to the wait or stop being detected. therefore, the command is not a cknowledged by the target, which means that the ack pulse will not be issued. after a certain time the host (not aware of stop or wait) should decide to abort any possible pending ack pulse, to be sure a new command can be issued. the protocol provides a mechanism in which a comma nd, and its corresponding ack, can be aborted. note the ack pulse does not provide a timeout. this means for the go_until(262) command, it cannot be distinguished if a stop or wait has been executed (command discarded and ack not issued), or if the ?until? condition (bdm active) is just not reached yet. therefore, where the ack pulse of a command is not issued, the possible pending command should be aborted before issuing a new command. see the handshake abort procedure described in section 5.21.4.8, ?hardware handshake abort procedure" . 5.21.4.8 hardware handshake abort procedure the abort procedure is based on the sync command. to abort a command which had not issued the corresponding ack pulse, the host controller should generate a low pulse on the bkgd pin by driving it low for at least 128 serial clock cycles, and the n driving it high for one se rial clock cycle, providing a spee dup pulse. by detecting this long low pulse on the bkgd pin, the ta rget executes the sync protocol, see section 5.21.4.9, ?sync ? request timed reference pulse" , and assumes that the pending command, and therefore the related ack pulse , are being aborted. therefor e, after the sync protocol has been completed, the host is free to issue new bdm commands. for bdm firmware read or write commands, it ca n not be guaranteed that the pending command is aborted, when issuing a sync before the corr esponding ack pulse. there is a short latency time from the time the read or write access begins until it is finished and the corresponding ack pulse is issued. the latency time depends on the firmware read or write command that is issued and on the selected bus clock rate. when the sync command starts during this latency time, the read or write command will not be aborted, but the corresponding ack pulse will be aborted. a pending go , trace1 or go_until(262) command can not be aborted. only the co rresponding ack pulse can be aborted by the sync command. although it is not recommended, the host could abort a pending bdm command by issuing a low pulse on the bkgd pin, shorter than 128 serial clock cycles, which will not be interpreted as the sync command. the ack is actually aborted when a negative edge is perceived by the target in the bkgd pin. the short a bort pulse should have at least 4 clock cycles keeping the bkgd pin low, to allow the negative edge to be detected by the target . in this case, the target wi ll not execute the sync protocol, but the pending command will be aborted along wit h the ack pulse. the potential problem wit h this abort procedure is when there is a conflict between the ack pulse and the short abort pulse, where the target may not perceive the abort pulse. the worst cas e is when the pending command is a read command (i.e., read_byt e). if the abort pulse is not perceived by the target, the host will attempt to send a new command after the abort pulse was issu ed, while the target expects the host to retrieve the accessed memory byte. in this case, host and target will run out of sync hronism. however, if the command to be aborted is not a read command, the short abort pulse could be used. after a command is aborted, the target assumes the next negative edge, after the abort pulse, is the first bit of a new bdm command. note the details about the short abort pulse are being provided only as a reference for the reader to better understand the bdm internal behavior. it is not recommended that this procedure be used in a real application. since the host knows the target serial clock frequency, the sync command (used to abort a command) does not need to consider the lower possible target freque ncy. the host could issue a sync very close to the 128 serial clock cycl es length, providing a small overhead on the pulse length, to assure the sy nc pulse will not be misinterpreted by the target. see section 5.21.4.9, ?sync ? request timed reference pulse" . figure 88 shows a sync command being issued after a read_byte, which aborts the read_byte command. note that, after the command is aborted, a new command could be issued by the host computer.
background debug module (s12sbdmv1) mm912_637, rev. 3.0 freescale semiconductor 290 figure 88. ack abort procedure at the command level note figure 88 does not represent the signals in a true timing scale figure 89 shows a conflict between the ack pulse and the sync reques t pulse. this conflict coul d occur if a pod device is connected to the target bkgd pin and the ta rget is already in debug active mode. cons ider that the target cpu is executing a pending bdm command at the exact moment the pod is being connected to the bkgd pi n. in this case, an ack pulse is issued along with the sync command. in this case, there is an electr ical conflict between the ack speedup pulse and the sync pulse. since this is not a probable situation, the prot ocol does not prevent th is conflict from happening. figure 89. ack pulse and sync request conflict note this information is being provided so that the mcu integrator will be aware that such a conflict could occur. the hardware handshake protocol is enabled by the ack_enabl e and disabled by the ack_disable bdm commands. this provides backwards compatibility with the ex isting pod devices, which are not able to execute the hardware handshake protocol. it also allows for new pod devices supporting the hardware hands hake protocol, to freely comm unicate with the target device. if desired, without the need for waiting for the ack pulse. the commands are described as follows: ? ack_enable ? enables the hardware handshake protoc ol. the target will issue the ack pulse when a cpu command is executed by the cpu. the ack_enable co mmand itself also has the ack pulse as a response. ? ack_disable ? disables the ack pulse pr otocol the host needs to use the wors t case delay time at the appropriate places in the protocol. read_byte read_status bkgd pin memory address new bdm command new bdm command host target host target host target sync response from the target (out of scale) bdm decode and starts to execute the read_byte command read_byte cmd is aborted by the sync request (out of scale) bdm clock (target mcu) target mcu drives to bkgd pin bkgd pin 16 cycles speedup pulse high-impedance host drives sync to bkgd pin ack pulse host sync request pulse at least 128 cycles electrical conflict host and target drive to bkgd pin
background debug module (s12sbdmv1) mm912_637, rev. 3.0 freescale semiconductor 291 the default state of the bdm after reset is hardware handshake protocol disabled. all the read commands will ack (if enabled) when the data bus cycle has completed and the data is then ready for reading out by the bkgd serial pin. all the write commands will ack (if enabl ed) after the data has been received by the bdm through the bkgd serial pin, and when the data bus cycle is complete. see section 5.21.4.3, ?bdm hardware commands" and section 5.21.4.4, ?standard bdm firmware commands" for more information on the bdm commands. the ack_enable sends an ack pulse when the command has been co mpleted. this feature coul d be used by the host to evaluate if the target supports the hardware handshake protocol. if an ack pulse is issued in response to this command, the hos t knows that the target supports the hardware handshake protocol. if the target does not support the hardware handshake protocol the ack pulse is not issued. in this case, the ack_enable comma nd is ignored by the target since it is not recognized as a valid command. the background command issues an ack pulse when the cpu changes from normal to background mode. the ack pulse related to this command could be aborted using the sync command. the go command issues an ack pulse when the cpu exits from ba ckground mode. the ack pulse related to this command could be aborted using the sync command. the go_until(262) command is equivalent to a go command with excepti on that the ack pulse, in this case, is issued when the cpu enters into background mode. this command is an alternative to the go command and should be used when the host wants to trace if a breakpoint match occurs and causes the cpu to enter active background mode. note that the ack is issued whenever the cpu enters bdm, which could be caused by a breakpoint match or by a bgnd instruction being executed. the ack pulse related to this command could be aborted using the sync command. the trace1 command has the related ack pulse issued when the cpu enters background active mode after one instruction of the application program is executed. the ack pulse relat ed to this command could be aborted using the sync command. 5.21.4.9 sync ? request timed reference pulse the sync command is unlike other bdm commands, because the ho st does not necessarily know the correct communication speed to use for bdm communications until after it has analyzed the response to the sync command. to issue a sync command, the host should perform the following steps: 1. drive the bkgd pin low for at least 128 cycles at the lowe st possible bdm serial communication frequency (the lowest serial communication frequency is determined by the se ttings for the vco clock (cpmusynr). the bdm clock frequency is always vco clock frequency divided by 8.) 2. drive bkgd high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the host clock.) 3. remove all drive to the bkgd pin so it reverts to high-impedance. 4. listen to the bkgd pin for the sync response pulse. upon detecting the sync request from the hos t, the target performs the following steps: 1. discards any incomplete command received or bit retrieved. 2. waits for bkgd to return to a logic one. 3. delays 16 cycles to allow the host to stop driving the high speedup pulse. 4. drives bkgd low for 128 cycles at the cu rrent bdm serial communication frequency. 5. drives a one-cycle high speedup pulse to force a fast rise time on bkgd. 6. removes all drive to the bkgd pin so it reverts to high-impedance. the host measures the low time of this 128 cycle sync res ponse pulse and determines the correct speed for subsequent bdm communications. typically, the host can determine the correct co mmunication speed within a few pe rcent of the actual target speed, and the communication protocol can easi ly tolerate speed errors of several percent. as soon as the sync request is detected by the target, any pa rtially received command or bit retrieved is discarded. this is referred to as a soft-reset, equivalent to a time-out in the serial communication. af ter the sync response, the target will con sider the next negative edge (issued by the host) as the star t of a new bdm command or the start of new sync request. another use of the sync command pulse is to abort a pending ac k pulse. the behavior is exactly the same as in a regular sync command. note that one of the possible causes for a comm and to not be acknowledged by the target is a host-target synchronization problem. in this case, the command may not have been understood by the target, so an ack response pulse will not be issued.
background debug module (s12sbdmv1) mm912_637, rev. 3.0 freescale semiconductor 292 5.21.4.10 instruction tracing when a trace1 command is issued to the bdm in active bdm, the cpu exits the standard bdm firmware and executes a single instruction in the user code. once this ha s occurred, the cpu is forced to return to the standard bdm firmware, the bdm is acti ve, and ready to receive a new command. if the trace1 command is issued again, the next user instruction will be executed. this facilitates stepping or tracing through t he user code one instruction at a time. if an interrupt is pending when a trace1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. once back in standard bdm firmware execution, the program counter points to the first instruction in the interrupt service routine. be aware when tracing through the user code th at the execution of the user code is d one step by step, but peripherals are free running. hence possible timing relations between cpu code exec ution and occurrence of events of other peripherals no longer exist. do not trace the cpu instruction bgnd used for soft breakpoints. tracing over the bg nd instruction will result in a return addr ess pointing to bdm firmware address space. when tracing through user code which contains stop or wait inst ructions the following will happen when the stop or wait instruc tion is traced: the cpu enters stop or wait mode and the trace1 command can not be finished before leaving the low power mode. this is the case because bdm active mode can not be entered after the cpu executed the stop instruction. however, all bdm hardware commands except the background comm and are operational after tracing a stop or wait instruction, and still being in stop or wait mode. if system stop mode is entered (a ll bus masters are in stop mode), no bdm command is operational. as soon as stop or wait mode is ex ited, the cpu enters bdm active mode and the saved pc value points to the entry of the corresponding interrupt service routine. if the handshake feature is enabled, the corresponding ack pulse of the trace1 command will be discarded when tracing a stop or wait instruction. he nce, there is no ack pulse when bdm acti ve mode is entered as part of the trace1 command, after cpu exited from stop or wait mode. all vali d commands sent during cpu being in stop or wait mode or after cpu exited from stop or wait mo de will have an ack pulse. the handshake feature becomes disabled only when system stop mode has been reached. after a system stop mode, the handshake feature must be enabled again by sending the ack_enable command. 5.21.4.11 serial communication timeout the host initiates a host-to-target serial transmission by generat ing a falling edge on the bkgd pin. if bkgd is kept low for m ore than 128 target clock cycles, the target understands that a sync command was issued. in this case, the target will keep waiting for a rising edge on bkgd, to answer the sync request pulse. if the rising edge is not detected, the target will keep waiting forever without any timeout limit. consider now the case where the host returns bkgd to a logi c one before 128 cycles. this is interpreted as a valid bit transmission, and not as a sync request. the target will keep waiting for another falling edge, marking the start of a new bit. if, a new falling edge is not detected by the target within 512 clock cycles, since the last falling edge, a timeou t occurs and the current command is discarded without affecting memory or the operating mode of the mcu. this is referred to as a soft-reset. if a read command is issued, but the data is not retrieved within 512 serial clock cycles, a soft-reset will occur causing the command to be disregarded. the data is not available for retrieva l after the timeout has occurred. this is expected behavior if the handshake protocol is not enabled. to allow the data to be retrieved, even with a large clock frequency mismatch (between bdm and cpu) when the hardware handshake protocol is enabl ed, the timeout between a read command and the data retrieval is disabled. therefore, the host could wait for more then 512 serial clock cycles, and still be able to retrieve the data from an issued read command. however, once the handshake pulse (ack pu lse) is issued, the timeout fe ature is re-activated, meaning that the target wi ll timeout after 512 clock cycles. the ho st needs to retrieve the data with in a 512 serial clock cycles time frame after the ack pulse had been issued. after that period, the read command is discarded and the data is no longer available for retrieval. any negative edge in the bkgd pin after the timeou t period is considered to be a new command or a sync request. note that whenever a partially issued comm and, or partially retrieved data has occurr ed, the timeout in the serial communicatio n is active. this means that if a time frame higher than 512 seri al clock cycles is observed betw een two consecutive negative edg es and the command being issued or data being retrieved is not complete, a soft-reset will occur causing the partially received command or data retrieved to be disregarde d. the next negative edge in the bkgd pi n, after a soft-reset has occurred, is considered by the target as the start of a new bdm command, or the start of a sync request pulse.
s12 clock, reset, and power management unit (s12cpmu) mm912_637, rev. 3.0 freescale semiconductor 293 5.22 s12 clock, reset, and power management unit (s12cpmu) 5.22.1 introduction this specification describes the fu nction of the clock, reset, and power management unit (s12cpmu). ? the pierce oscillator (osclcp) provides a robust, low noise and low power external clock source. it is designed for optimal start-up margin with typical crystal oscillators ? the voltage regulator (ivreg) oper ates from the range 3.13 to 5.5 v. it provides all the required chip internal voltages and voltage monitors ? the phase locked loop (pll) provides a highly accurate frequency multiplier with internal filter ? the internal reference clock (irc1m) provides a1.0 mhz clock 5.22.1.1 features the pierce oscillator (osclcp) contains ci rcuitry to dynamically contro l current gain in the output amplitude. this ensures a signal with low harmonic distortion, low power, and good noise immunity. ? supports crystals or resonators from 4.0 to 16 mhz ? high noise immunity due to input hysteresis and spike filtering ? low rf emissions with peak-to- peak swing limited dynamically ? transconductance (gm) sized for optimum start-up margin for typical crystals ? dynamic gain control eliminates the nee d for external current limiting resistor ? integrated resistor eliminates th e need for external bias resistor ? low power consumption: oper ates from an internal 1.8 v (nominal) supply, amplitude control limits power the voltage regulator (ivreg) has the following features: ? input voltage range from 3.13 to 5.5 v ? low voltage detect (lvd) with low voltage interrupt (lvi) ? power-on reset (por) ? low voltage reset (lvr) the phase locked loop (pll) has the following features: ? highly accurate and phase locked frequency multiplier ? configurable internal filter for best stability and lock time ? frequency modulation for defined jitter and reduced emission ? automatic frequency lock detector ? interrupt request on entry or exit from locked condition ? reference clock either external (crystal) or internal square wave (1.0 mhz irc1m) based ? pll stability is sufficient for lin communica tion, even if using irc1 m as reference clock the internal reference clock (irc1m) has the following features: ? trimmable in frequency ? factory trimmed value for 1.0 mhz in flash memory, can be overwr itten by application if required other features of the s12cpmu include ? clock monitor to detect loss of crystal ? bus clock generator ? clock switch to select either pllclk or external crystal/resonator based bus clock ? pllclk divider to adjust system speed ? system reset generation from the following possible sources: ? power-on reset (por) ? low voltage reset (lvr) ? illegal address access ? cop timeout analog mcu
s12 clock, reset, and power management unit (s12cpmu) mm912_637, rev. 3.0 freescale semiconductor 294 ? loss of oscillation (clock monitor fail) ? external pin reset 5.22.1.2 modes of operation this subsection lists and briefly describes al l operating modes supported by the s12cpmu. 5.22.1.2.1 run mode the voltage regulator is in full performance mode (fpm). the phase locked loop (pll) is on. the internal reference clock (irc1m) is on. ? pll engaged internal (pei) ? this is the default mode afte r system reset and power-on reset. ? the bus clock is based on the pllclk. ? after reset the pll is configured for 64 mhz vcoclk op eration. post divider is 0x03, so pllclk is vcoclk divided by 4, that is 16 mhz and bus clock is 8.0 mhz. the pll can be re-configured for other bus frequencies. ? the reference clock for the pll (refclk) is based on internal reference clock irc1m ? pll engaged external (pee) ? the bus clock is based on the pllclk. ? this mode can be entered from default mo de pei by performing the following steps: ? configure the pll for desired bus frequency. ? program the reference divider (ref div[3:0] bits) to divide down oscillator frequency if necessary. ? enable the external oscillator (osce bit) ? pll bypassed external (pbe) ? the bus clock is based on the oscillator clock (oscclk). ? this mode can be entered from default mo de pei by performing the following steps: ? enable the external oscillator (osce bit) ? wait for oscillator to start up (uposc=1) ? select the oscillator clock (oscclk) as bus clock (pllsel=0). ? the pllclk is still on to filter possible spikes of the external oscillator clock. 5.22.1.2.2 wait mode for s12cpmu wait mode is the same as run mode. 5.22.1.2.3 stop mode this mode is entered by executing the cpu stop instruction. the voltage regulator is in reduced power mode (rpm). the phase locked loop (pll) is off. the internal reference clock (irc1m) is off. core clock, bus clock and bdm clock are stopped. depending on the setting of the pstp and the osce bit, stop mode can be differentiated between full stop mode (pstp = 0 or osce=0) and pseudo stop mode (pstp = 1 and osce=1). ? full stop mode (pstp = 0 or osce=0) ? the external oscillator (osclcp) is disabled. ? after wake-up from full stop mode the core clock and bus clock are running on pllclk (pllsel=1). after wake-up from full stop mode the cop and rti are running on ircclk (coposcsel=0, rtioscsel=0). ? pseudo stop mode (pstp = 1 and osce=1) ? the external oscillator (osclc p) continues to run. if the respective enabl e bits are set the cop and rti will continue to run. the clock configuration bits pllsel, coposcsel, rtioscsel are unchanged.
s12 clock, reset, and power management unit (s12cpmu) mm912_637, rev. 3.0 freescale semiconductor 295 note when starting up the external oscillator (either by programming osce bit to 1 or on exit from full stop mode with osce bit already 1), t he software must wait for a minimum time equivalent to the startup-time of the external oscillator t uposc before entering pseudo stop mode. 5.22.1.3 s12cpmu block diagram figure 90. block diagram of s12cpmu s12cpmu extal xtal system reset power-on detect pll lock interrupt mmc illegal address access cop timeout loop reference divider cop watchdog voltage vddrx internal reset generator divide by phase post divider 1,2,...,32 vcoclk eclk2x lockie irctrim[9:0] syndiv[5:0] lock refdiv[3:0] 2*(syndiv+1) pierce oscillator 4.0 mhz- osce ilaf porf divide by 2 eclk postdiv[4:0] power-on reset controlled locked loop with internal filter (pll) refclk fbclk reffrq[1:0] vcofrq[1:0] lock detect regulator 3.13 to 5.5v adaptive spike filter pllsel oscfilt[4:0] (to mscan) vssrx vss low voltage reset vddrx lvrf pllclk reference divide by 8 bdm clock clock (irc1m) clock monitor monitor fail real time interrupt (rti) rti interrupt pstp cpmurti oscillator status interrupt (osclcp) can_oscclk low voltage interrupt rticlk ircclk oscclk rtioscsel cpmucop copclk ircclk oscclk coposcsel to reset generator cop timeout pce pre uposc=0 sets pllsel bit vdd, vddf (core supplies) uposc reset oscie rtie lvds lvie low voltage interrupt vddrx uposc uposc=0 clears & oscclk divide by 4 ircclk (to lcd) oscbw (core clock) (bus clock) 16 mh
s12 clock, reset, and power management unit (s12cpmu) mm912_637, rev. 3.0 freescale semiconductor 296 figure 91 shows a block diagram of the osclcp. figure 91. osclcp block diagram 5.22.2 signal description this section lists and describes the signals that connect off chip. 5.22.2.1 reset pin reset is an active-low bidirectional pin. as an input, it initializ es the mcu asynchronously to a known start-up state. as an open-drain output, it indicates that an mcu-internal reset has been triggered. 5.22.2.2 extal and xtal these pins provide the interface for a crystal to control the inte rnal clock generator circuitry. extal is the external clock i nput or the input to the crystal oscillator amplifier. xtal is the output of the crystal oscillator amp lifier. the mcu internal oscclk is derived from the extal input frequency. if osce=0, the extal pi n is pulled down by an internal resistor of approximately 200 k ? , and the xtal pin is pulled down by an internal resistor of approximately 700 k ? . note freescale recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. lo op controlled circuit is not suited for overtone resonators and crystals. extal xtal gain control vdd = 1.8 v rf oscclk peak detector vss
s12 clock, reset, and power management unit (s12cpmu) mm912_637, rev. 3.0 freescale semiconductor 297 5.22.2.3 vss ? ground pin vss must be grounded. 5.22.2.4 vddrx, vssrx? regulator po wer input pin and pad supply pins vddrx is the power input of ivreg and the pa d positive supply pin. all currents source d into the regulator loads flow through this pin.the vddrx/vssx supply domain is m onitored by the low voltage reset circuit. an off-chip decoupling capacitor (100 nf...220 nf, x7r ceramic) between vddrx and vssx can further improv e the quality of this supply. 5.22.2.5 vdd ? internal regula tor output supply (core logic) node vdd is a device internal supply output of the voltage regu lator that provides the power supply for the core logic. this su pply domain is monitored by the low voltage reset circuit. 5.22.2.6 vddf ? internal regu lator output supply (nvm logic) node vddf is a device internal supply out put of the voltage regulator that provides the power supp ly for the nvm logic. this supply domain is monitored by the low voltage reset circuit 5.22.3 memory map and registers this section provides a detailed description of all registers accessible in the s12cpmu. 5.22.3.1 module memory map the s12cpmu registers are shown in ta b l e 401 . table 401. cpmu register summary address name bit 7 6 5 4 3 2 1 bit 0 0x0034 cpmu synr r vcofrq[1:0] syndiv[5:0] w 0x0035 cpmu refdiv r reffrq[1:0] 0 0 refdiv[3:0] w 0x0036 cpmu postdiv r 0 0 0 postdiv[4:0] w 0x0037 cpmuflg r rtif porf lvrf lockif lock ilaf oscif uposc w 0x0038 cpmuint r rtie 0 0 lockie 0 0 oscie 0 w 0x0039 cpmuclks r pllsel pstp 0 0 pre pce rti oscsel cop oscsel w 0x003a cpmupll r 0 0 fm1 fm0 0 0 0 0 w 0x003b cpmurti r rtdec rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 w = unimplemented or reserved
s12 clock, reset, and power management unit (s12cpmu) mm912_637, rev. 3.0 freescale semiconductor 298 5.22.3.2 register descriptions this section describes all the s12cpm u registers and their individual bits. address order is as listed in ta b l e 401 . 5.22.3.2.1 s12cpmu synthesi zer register (cpmusynr) the cpmusynr register controls the multiplication fa ctor of the pll and selects the vco frequency range. 0x003c cpmucop r wcop rsbck 0 0 0 cr2 cr1 cr0 w wrtmask 0x003d reservedc r 0 0 0 0 0 0 0 0 w 0x003e reservedc r 0 0 0 0 0 0 0 0 w 0x003f cpmu armcop r 0 0 0 0 0 0 0 0 w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x02f0 reserved r 0 0 0 0 0 0 0 0 w 0x02f1 cpmu lvctl r 0 0 0 0 0 lvds lvie lvif w 0x02f2 reserved r 0 0 w 0x02f3 reserved r 0 0 w 0x02f4 reserved r w 0x02f5 reserved r w 0x02f6 reservedc r 0 0 0 0 0 0 0 0 w 0x02f7 reserved r 0 0 0 0 0 0 0 0 w 0x02f8 cpmu irctrimh r tctrim[4:0] 0 irctrim[9:8] w 0x02f9 cpmu irctriml r irctrim[7:0] w 0x02fa cpmuosc r osce oscbw oscpins_ en oscfilt[4:0] w 0x02fb cpmuprot r 0 0 0 0 0 0 0 prot w 0x02fc reservedc r 0 0 0 0 0 0 0 0 w table 401. cpmu register summary address name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved
s12 clock, reset, and power management unit (s12cpmu) mm912_637, rev. 3.0 freescale semiconductor 299 read: anytime write: anytime if prot=0 (cpmuprot register) and pll sel=1 (cpmuclks register), el se write has no effect. note writing to this register clears the lock and uposc status bits. note f vco must be within the specified vco frequency lock range. bus frequency f bus must not exceed the specified maximum. the vcofrq[1:0] bits are used to configure the vco gain for optimal stability and lock time. for correct pll operation, the vcofrq[1:0] bits have to be selected according to the actual target vcoclk frequency, as shown in ta b l e 403 . setting the vcofrq[1:0] bits incorrectly can result in a non functi onal pll (no locking and/or insufficient stability). 5.22.3.2.2 s12cpmu reference di vider register (cpmurefdiv) the cpmurefdiv register provides a fine r granularity for the pll multiplier step s when using the external oscillator as reference. read: anytime write: anytime if prot=0 (cpmuprot register) and pll sel=1 (cpmuclks register), else write has no effect. note write to this register clears the lock and uposc status bits. table 402. s12cpmu synthesizer register (cpmusynr) 0x0034 7 6 5 4 3 2 1 0 r vcofrq[1:0] syndiv[5:0] w reset 0 1 0 1 1 1 1 1 table 403. vco clock frequency selection vcoclk frequency ranges vcofrq[1:0] 32 mhz <= f vco <= 48 mhz 00 48 mhz < f vco <= 64 mhz 01 reserved 10 reserved 11 table 404. s12cpmu reference divi der register (cpmurefdiv) 0x0035 7 6 5 4 3 2 1 0 r reffrq[1:0] 0 0 refdiv[3:0] w reset 0 0 0 0 1 1 1 1 f vco 2 f ref ? syndiv 1 + ?? ? = if pll has locked (lock=1)
s12 clock, reset, and power management unit (s12cpmu) mm912_637, rev. 3.0 freescale semiconductor 300 the reffrq[1:0] bits are used to configur e the internal pll filter for optimal stability and lock time. for correct pll operati on, the reffrq[1:0] bits have to be selected according to the actual refclk frequency as shown in ta b l e 405 . if irc1m is selected as refclk (osce=0) th e pll filter is fixed configured for the 1.0 mhz <= f ref <= 2.0 mhz range. the bits can still be written but will have no effect on the pll filter configuration. for osce=1, setting the reffrq[1:0] bits in correctly can result in a non functional pll (no locking and/or insufficient stabili ty). 5.22.3.2.3 s12cpmu post divide r register (cpmupostdiv) the postdiv register contro ls the frequency ratio between the vcoclk and the pllclk. read: anytime write: anytime if pllsel=1. else write has no effect. table 405. reference clock frequency selection if osc_lcp is enabled refclk frequency ranges (osce=1) reffrq[1:0] 1.0 mhz <= f ref <= 2.0 mhz 00 2.0 mhz < f ref <= 6.0 mhz 01 6.0 mhz < f ref <= 12.0 mhz 10 f ref >12.0 mhz 11 table 406. s12cpmu post divider register (cpmupostdiv) 0x0036 7 6 5 4 3 2 1 0 r 0 0 0 postdiv[4:0] w reset 0 0 0 0 0 0 1 1 = unimplemented or reserved f ref f osc refdiv 1 + ?? ------------------------------------- - = if osclcp is enabled (osce=1) if osclcp is disabled (osce=0) f ref f irc 1 m = f pll f vco postdiv 1 + ?? ------------------------------------------ - = if pll is locked (lock=1) if pll is not locked (lock=0) f pll f vco 4 --------------- = f bus f pll 2 ------------ - = if pll is selected (pllsel=1)
s12 clock, reset, and power management unit (s12cpmu) mm912_637, rev. 3.0 freescale semiconductor 301 5.22.3.2.4 s12cpmu flags register (cpmuflg) this register provides s12cpmu status bits and flags. read: anytime write: refer to each bit for individual write conditions table 407. s12cpmu flags register (cpmuflg) 0x0037 7 6 5 4 3 2 1 0 r rtif porf lvrf lockif lock ilaf oscif uposc w reset 0 (264) (265) 0 0 (266) 0 0 = unimplemented or reserved notes 264.1. porf is set to 1 when a power on reset occurs. unaffected by system reset. 265.2. lvrf is set to 1 when a low voltage reset occurs. unaffected by system reset. set by power on reset. 266.3. ilaf is set to 1 when an illegal address reset occu rs. unaffected by system reset. cleared by power on reset. table 408. cpmuflg field descriptions field description 7 rtif real time interrupt flag ? rtif is set to 1 at the end of the rti period. this flag can only be cleared by writing a 1. writing a 0 has no effect. if enabled (rtie=1), rtif causes an interrupt request. 0 rti timeout has not yet occurred. 1 rti timeout has occurred. 6 porf power on reset flag ? porf is set to 1 when a power on reset occurs. this flag can only be cleared by writing a 1. writing a 0 has no effect. 0 power on reset has not occurred. 1 power on reset has occurred. 5 lvrf low voltage reset flag ? lvrf is set to 1 when a low voltage reset occurs . this flag can only be cleared by writing a 1. writing a 0 has no effect. 0 low voltage reset has not occurred. 1 low voltage reset has occurred. 4 lockif pll lock interrupt flag ? lockif is set to 1 when lock status bit changes . this flag can only be cleared by writing a 1. writing a 0 has no effect.if enabled (lockie= 1), lockif causes an interrupt request. 0 no change in lock bit. 1 lock bit has changed. 3 lock lock status bit ? lock reflects the current state of pll lock condition. writes have no effect. while pll is unlocked (lock=0) f pll is f vco / 4 to protect the system from high core clock frequencies during the pll stabilization time t lock . 0 vcoclk is not within the desired tolerance of the target frequency. f pll = f vco /4. 1 vcoclk is within the desired tolerance of the target frequency. f pll = f vco /(postdiv+1). 2 ilaf illegal address reset flag ? ilaf is set to 1 when an illegal address reset o ccurs. refer to mmc chapter for details. this flag can only be cleared by writing a 1. writing a 0 has no effect. 0 illegal address reset has not occurred. 1 illegal address reset has occurred. 1 oscif oscillator interrupt flag ? oscif is set to 1 when uposc status bit changes. this flag can only be cleared by writing a 1. writing a 0 has no effect.if enabled (oscie=1 ), oscif causes an interrupt request. 0 no change in uposc bit. 1 uposc bit has changed. 0 uposc oscillator status bit ? uposc reflects the status of the oscillator. writes have no effect. while uposc=0 the oscclk going to the mscan module is off. entering full stop mode uposc is cleared. 0 the oscillator is off or oscillat ion is not qualified by the pll. 1 the oscillator is qualified by the pll.
s12 clock, reset, and power management unit (s12cpmu) mm912_637, rev. 3.0 freescale semiconductor 302 note the adaptive oscillator filter us es the vco clock as a referenc e to continuously qualify the external oscillator clock. as a result, the pl l is always active and a valid pll configuration is required for the system to work properly. furt hermore, the adaptive osci llator filter is used to determine the status of the external oscillat or (reflected in the uposc bit). since this function also relies on the vco clock, loosing pll lock status (lock=0, except for entering pseudo stop mode) means loosing the oscillator status information as well (uposc=0). 5.22.3.2.5 s12cpmu interrupt en able register (cpmuint) this register enables s12cpmu interrupt requests. read: anytime write: anytime 5.22.3.2.6 s12cpmu clock sele ct register (cpmuclks) this register controls s12cpmu clock selection. read: anytime write: 1. only possible if prot=0 (cpmuprot register) in all mcu modes (normal and special mode). 2. all bits in special mode (if prot=0). 3. pllsel, pstp, pre, pce, rtiosc sel: in normal mode (if prot=0). table 409. s12cpmu interrupt enable register (cpmuint) 0x0038 7 6 5 4 3 2 1 0 r rtie 0 0 lockie 0 0 oscie 0 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 410. crgint field descriptions field description 7 rtie real time interrupt enable bit 0 interrupt requests from rti are disabled. 1 interrupt will be requested whenever rtif is set. 4 lockie pll lock interrupt enable bit 0 pll lock interrupt requests are disabled. 1 interrupt will be requested whenever lockif is set. 1 oscie oscillator corrupt interrupt enable bit 0 oscillator corrupt interrupt requests are disabled. 1 interrupt will be requested whenever oscif is set. table 411. s12cpmu clock sele ct register (cpmuclks) 0x0039 7 6 5 4 3 2 1 0 r pllsel pstp 0 0 pre pce rti oscsel cop oscsel w reset 1 0 0 0 0 0 0 0 = unimplemented or reserved
mm912_637, rev. 3.0 freescale semiconductor 303 4. coposcsel: in normal mode (if prot=0) until cpmucop write once is taken. if coposcsel was cleared by uposc=0 (entering full stop mode with coposcsel=1 or insufficient oscclk quality), then coposcsel can be set again once. note after writing cpmuclks register, it is strongly recommended to read back cpmuclks register to make sure that write of pllsel, rtioscsel and coposcsel was successful. table 412. cpmuclks descriptions field description 7 pllsel pll select bit this bit selects the pllclk as source of the system clocks (cor e clock and bus clock). pllsel can only be set to 0, if uposc=1. uposc= 0 sets the pllsel bit. entering full stop mode sets the pllsel bit. 0 system clocks are derived from oscclk if oscillator is up (uposc=1, f bus = f osc / 2. 1 system clocks are derived from pllclk, f bus = f pll / 2. 6 pstp pseudo stop bit this bit controls the functionality of the oscillator during stop mode. 0 oscillator is disabled in stop mode (full stop mode). 1 oscillator continues to run in stop mode (p seudo stop mode), option to run rti and cop. note: pseudo stop mode allows for faster stop recovery and re duces the mechanical stress and aging of the resonator in case of frequent stop conditions at the expense of a slightly incr eased power consumption. note: when starting up the external oscillator (either by programmi ng osce bit to 1 or on exit from full stop mode with osce bit is already 1) the software must wait for a minimum time equivalent to the startup time of the external oscillator t uposc before entering pseudo stop mode. 3 pre rti enable during pseudo stop bit ? pre enables the rti during pseudo stop mode. 0 rti stops running during pseudo stop mode. 1 rti continues running during pseudo stop mode if rtioscsel=1. note: if pre=0 or rtioscsel=0 then the rti will go static while stop mode is active. the rti counter will not be reset. 2 pce cop enable during pseudo stop bit ? pce enables the cop during pseudo stop mode. 0 cop stops running during pseudo stop mode 1 cop continues running during pseudo stop mode if coposcsel=1 note: if pce=0 or coposcsel=0 then the cop will go static while stop mode is active . the cop counter will not be reset. 1 rtioscsel rti clock select ? rtioscsel selects the clock source to the rt i. either ircclk or oscclk. changing the rtioscsel bit re-starts the rti timeout period. rtioscsel can only be set to 1, if uposc=1. uposc= 0 clears the rtioscsel bit. 0 rti clock source is ircclk. 1 rti clock source is oscclk. 0 coposcsel cop clock select ? coposcsel selects the clock source to the cop. either ircclk or oscclk. changing the coposcsel bit re-starts the cop timeout period. coposcsel can only be set to 1, if uposc=1. uposc= 0 clears the coposcsel bit. 0 cop clock source is ircclk. 1 cop clock source is oscclk
mm912_637, rev. 3.0 freescale semiconductor 304 5.22.3.2.7 s12cpmu pll cont rol register (cpmupll) this register controls the pll functionality. read: anytime write: anytime if prot=0 (cpmuprot register) and pll sel=1 (cpmuclks register). el se write has no effect. note write to this register clears the lock and uposc status bits. note care should be taken to ensure that the bus frequency does not exceed the specified maximum when frequency modulation is enabled. note the frequency modulation (fm1 and fm0) can not be used if the adapti ve oscillator filter is enabled. 5.22.3.2.8 s12cpmu rti cont rol register (cpmurti) this register selects the timeout period for the real time interrupt. the clock source for the rti is either ircclk or oscclk depe nding on the setting of the rtioscsel bit. in stop mode with pstp=1 (pseudo stop mode) and rtioscsel=1 the rti continues to run, else the rti counter halts in stop mode. table 413. s12cpmu pll control register (cpmupll) 0x003a 7 6 5 4 3 2 1 0 r 0 0 fm1 fm0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 table 414. cpmupll field descriptions field description 5, 4 fm1, fm0 pll frequency modulation enable bits ? fm1 and fm0 enable frequency modulation on the vcoclk. this is to reduce noise emission. the modulation frequency is f ref divided by 16. see ta b l e 415 for coding. table 415. fm amplitude selection fm1 fm0 fm amplitude / f vco variation 0 0 fm off 0 1 ? 1% 1 0 ? 2% 1 1 ? 4%
mm912_637, rev. 3.0 freescale semiconductor 305 read: anytime write: anytime note a write to this register starts the rti timeout period. a change of the rtioscsel bit (writing a different value or loosing uposc status) re-starts the rti timeout period. table 416. s12cpmu rti control register (cpmurti) 0x003b 7 6 5 4 3 2 1 0 r rtdec rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 w reset 0 0 0 0 0 0 0 0 table 417. cpmurti field descriptions field description 7 rtdec decimal or binary divider select bit ? rtdec selects decimal or binary based prescaler values. 0 binary based divider value. see ta b l e 418 1 decimal based divi der value. see table 419 6?4 rtr[6:4] real time interrupt prescale rate select bits ? these bits select the prescale rate for the rti. see table 418 and ta b l e 419 . 3?0 rtr[3:0] real time interrupt modulus counter select bits ? these bits select the modulus count er target value to provide additional granularity. table 418 and table 419 show all possible divide values selectable by the cpmurti register . table 418. rti frequency divide rates for rtdec = 0 rtr[3:0] rtr[6:4] = 000 (off) 001 (2 10 ) 010 (2 11 ) 011 (2 12 ) 100 (2 13 ) 101 (2 14 ) 110 (2 15 ) 111 (2 16 ) 0000 ( ? 1) off (267) 2 10 2 11 2 12 2 13 2 14 2 15 2 16 0001 ( ? 2) off 2x2 10 2x2 11 2x2 12 2x2 13 2x2 14 2x2 15 2x2 16 0010 ( ? 3) off 3x2 10 3x2 11 3x2 12 3x2 13 3x2 14 3x2 15 3x2 16 0011 ( ? 4) off 4x2 10 4x2 11 4x2 12 4x2 13 4x2 14 4x2 15 4x2 16 0100 ( ? 5) off 5x2 10 5x2 11 5x2 12 5x2 13 5x2 14 5x2 15 5x2 16 0101 ( ? 6) off 6x2 10 6x2 11 6x2 12 6x2 13 6x2 14 6x2 15 6x2 16 0110 ( ? 7) off 7x2 10 7x2 11 7x2 12 7x2 13 7x2 14 7x2 15 7x2 16 0111 ( ? 8) off 8x2 10 8x2 11 8x2 12 8x2 13 8x2 14 8x2 15 8x2 16 1000 ( ? 9) off 9x2 10 9x2 11 9x2 12 9x2 13 9x2 14 9x2 15 9x2 16 1001 ( ? 10) off 10x2 10 10x2 11 10x2 12 10x2 13 10x2 14 10x2 15 10x2 16 1010 ( ? 11) off 11x2 10 11x2 11 11x2 12 11x2 13 11x2 14 11x2 15 11x2 16 1011 ( ? 12) off 12x2 10 12x2 11 12x2 12 12x2 13 12x2 14 12x2 15 12x2 16 1100 ( ? 13) off 13x2 10 13x2 11 13x2 12 13x2 13 13x2 14 13x2 15 13x2 16 1101 ( ? 14) off 14x2 10 14x2 11 14x2 12 14x2 13 14x2 14 14x2 15 14x2 16
mm912_637, rev. 3.0 freescale semiconductor 306 1110 ( ? 15) off 15x2 10 15x2 11 15x2 12 15x2 13 15x2 14 15x2 15 15x2 16 1111 ( ? 16) off 16x2 10 16x2 11 16x2 12 16x2 13 16x2 14 16x2 15 16x2 16 notes 267.denotes the default value out of reset.this value should be used to disable the rti to ensure future backwards compatibilit y. table 419. rti frequency divi de rates for rtdec=1 rtr[3:0] rtr[6:4] = 000 (1x10 3 ) 001 (2x10 3 ) 010 (5x10 3 ) 011 (10x10 3 ) 100 (20x10 3 ) 101 (50x10 3 ) 110 (100x10 3 ) 111 (200x10 3 ) 0000 ( ? 1) 1x10 3 2x10 3 5x10 3 10x10 3 20x10 3 50x10 3 100x10 3 200x10 3 0001 ( ? 2) 2x10 3 4x10 3 10x10 3 20x10 3 40x10 3 100x10 3 200x10 3 400x10 3 0010 ( ? 3) 3x10 3 6x10 3 15x10 3 30x10 3 60x10 3 150x10 3 300x10 3 600x10 3 0011 ( ? 4) 4x10 3 8x10 3 20x10 3 40x10 3 80x10 3 200x10 3 400x10 3 800x10 3 0100 ( ? 5) 5x10 3 10x10 3 25x10 3 50x10 3 100x10 3 250x10 3 500x10 3 1x10 6 0101 ( ? 6) 6x10 3 12x10 3 30x10 3 60x10 3 120x10 3 300x10 3 600x10 3 1.2x10 6 0110 ( ? 7) 7x10 3 14x10 3 35x10 3 70x10 3 140x10 3 350x10 3 700x10 3 1.4x10 6 0111 ( ? 8) 8x10 3 16x10 3 40x10 3 80x10 3 160x10 3 400x10 3 800x10 3 1.6x10 6 1000 ( ? 9) 9x10 3 18x10 3 45x10 3 90x10 3 180x10 3 450x10 3 900x10 3 1.8x10 6 1001 ( ? 10) 10 x10 3 20x10 3 50x10 3 100x10 3 200x10 3 500x10 3 1x10 6 2x10 6 1010 ( ? 11) 11 x10 3 22x10 3 55x10 3 110x10 3 220x10 3 550x10 3 1.1x10 6 2.2x10 6 1011 ( ? 12) 12x10 3 24x10 3 60x10 3 120x10 3 240x10 3 600x10 3 1.2x10 6 2.4x10 6 1100 ( ? 13) 13x10 3 26x10 3 65x10 3 130x10 3 260x10 3 650x10 3 1.3x10 6 2.6x10 6 1101 ( ? 14) 14x10 3 28x10 3 70x10 3 140x10 3 280x10 3 700x10 3 1.4x10 6 2.8x10 6 1110 ( ? 15) 15x10 3 30x10 3 75x10 3 150x10 3 300x10 3 750x10 3 1.5x10 6 3x10 6 1111 ( ? 16) 16x10 3 32x10 3 80x10 3 160x10 3 320x10 3 800x10 3 1.6x10 6 3.2x10 6 table 418. rti frequency divide rates for rtdec = 0 rtr[3:0] rtr[6:4] = 000 (off) 001 (2 10 ) 010 (2 11 ) 011 (2 12 ) 100 (2 13 ) 101 (2 14 ) 110 (2 15 ) 111 (2 16 )
mm912_637, rev. 3.0 freescale semiconductor 307 5.22.3.2.9 s12cpmu cop cont rol register (cpmucop) this register controls the cop (com puter operating properly) watchdog. the clock source for the cop is either ircc lk or oscclk depending on the setting of the coposcsel bit. in stop mode with pstp=1(pseudo stop mode), coposcsel=1 and pce=1 the cop cont inues to run, else the cop counter halts in stop mode. read: anytime write: 1. rsbck: anytime in special mode; write to ?1? but not to ?0? in normal mode 2. wcop, cr2, cr1, cr0: ? anytime in special mode, when wrtmask is 0, otherwise it has no effect ? write once in normal mode, when wr tmask is 0, otherwise it has no effect. ? writing cr[2:0] to ?000? has no effect, but counts for the ?write once? condition. ? writing wcop to ?0? has no effect, but counts for the ?write once? condition. when a non-zero value is loaded from flash to cr[2:0] the cop timeout period is started. a change of the coposcsel bit (writing a different value or loosing uposc status) re-starts the cop timeout period. in normal mode the cop timeout period is restar ted if either of these conditions is true: 1. writing a non-zero value to cr[2: 0] (anytime in special mode, once in normal mode) with wrtmask = 0. 2. writing wcop bit (anytime in special mode, once in normal mode) with wrtmask = 0. 3. changing rsbck bit from ?0? to ?1?. in special mode, any write access to cpmucop register restarts the cop timeout period. table 420. s12cpmu cop control register (cpmucop) 0x003c 7 6 5 4 3 2 1 0 r wcop rsbck 0 0 0 cr2 cr1 cr0 w wrtmask reset f 0 0 0 0 f f f after de-assert of system reset the values are automatically lo aded from the flash memory. see de vice specification for details . = unimplemented or reserved table 421. cpmucop fi eld descriptions field description 7 wcop window cop mode bit ? when set, a write to the cpmuarmcop register must occur in the last 25% of the selected period. a write during the first 75% of the selected period generates a cop reset. as long as all writes occur during this window, $55 can be written as often as desired. once $aa is written after t he $55, the timeout logic restarts and the user must wait until the next window before writing to cpmuarmcop. table 422 shows the duration of this window for the seven available cop rates. 0 normal cop operation 1 window cop operation 6 rsbck cop and rti stop in active bdm mode bit 0 allows the cop and rti to keep running in active bdm mode. 1 stops the cop and rti counters whenever the part is in active bdm mode.
mm912_637, rev. 3.0 freescale semiconductor 308 5.22.3.2.10 reserved register cpmutest0 note this reserved register is designed for factor y test purposes only, and is not intended for general user access. writing to this register when in special mode can alter the s12cpmu?s functionality. read: anytime write: only in special mode 5 wrtmask write mask for wcop and cr[2:0] bit ? this write-only bit serves as a mask fo r the wcop and cr[2:0] bits while writing the cpmucop register. it is intended for bdm writing the rsbck without changing the content of wcop and cr[2:0]. 0 write of wcop and cr[2:0] has an effect with this write of cpmucop 1 write of wcop and cr[2:0] has no effect with this write of cpmucop. (does not count for ?write once?.) 2?0 cr[2:0] cop watchdog timer rate select ? these bits select the cop timeout rate (see table 422 ). writing a nonzero value to cr[2:0] enables the cop counter and starts the timeout period. a cop counter timeout causes a system reset. this can be avoided by periodically (before ti meout) initializing the cop counter via the cpmuarmcop register. while all of the following four conditions are true the cr[2:0] , wcop bits are ignored and the cop operates at highest timeout period (2 24 cycles) in normal cop mode (window cop mode disabled): 1) cop is enabled (cr[2:0] is not 000) ? 2) bdm mode active ? 3) rsbck = 0 ? 4) operation in special mode table 422. cop watchdog rates cr2 cr1 cr0 copclk cycles to time-out (copclk is either ircclk or oscclk depending on the coposcsel bit) 0 0 0 cop disabled 0 0 1 2 14 0 1 0 2 16 0 1 1 2 18 1 0 0 2 20 1 0 1 2 22 1 1 0 2 23 1 1 1 2 24 table 423. reserved register (cpmutest0) 0x003d 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 421. cpmucop field descriptions (continued) field description
mm912_637, rev. 3.0 freescale semiconductor 309 5.22.3.2.11 reserved register cpmutest1 note this reserved register is designed for factor y test purposes only, and is not intended for general user access. writing to this register when in special mode can alter the s12cpmu?s functionality. read: anytime write: only in special mode 5.22.3.2.12 s12cpmu cop timer ar m/reset register (cpmuarmcop) this register is used to restart the cop timeout period. read: always reads $00 write: anytime when the cop is disabled (cr[2:0] = ?000?) writing to this register has no effect. when the cop is enabled by setting cr[2:0] nonzero, the following applies: writing any value other than $55 or $aa causes a cop rese t. to restart the cop timeou t period write $55 followed by a write of $aa. these writes do not need to occur back-to- back, but the sequence ($55, $a a) must be completed prior to cop end of timeout period to avoid a cop reset. sequences of $55 writes are allowed. when the wcop bit is set, $55 and $aa writes must be done in the last 25% of the sele cted timeout period; writing any value in the first 75% of the selected period will cause a cop reset. table 424. reserved register (cpmutest1) 0x003e 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 425. s12cpmu cpmuarmcop register 0x003f 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset 0 0 0 0 0 0 0 0
mm912_637, rev. 3.0 freescale semiconductor 310 5.22.3.2.13 low voltage cont rol register (cpmulvctl) the cpmulvctl register allows the configur ation of the low-voltage detect features. read: anytime write: lvie and lvif are write anytime, lvds is read only 5.22.3.2.14 reserved register cpmutest3 note this reserved register is designed for factor y test purposes only, and is not intended for general user access. writing to this register when in special mode can alter the s12cpmu?s functionality. read: anytime write: only in special mode table 426. low voltage control register (cpmulvctl) 0x02f1 7 6 5 4 3 2 1 0 r 0 0 0 0 0 lvds lvie lvif w reset 0 0 0 0 0 u 0 u the reset state of lvds and lvif depends on the external supplied vddxr level = unimplemented or reserved table 427. cpmulvctl field descriptions field description 2 lvds low-voltage detect status bit ? this read-only status bit reflects the voltage level on vddxr. writes have no effect. 0 input voltage vddxr is above level v lvid or rpm. 1 input voltage vddrx is below level v lvia and fpm. 1 lvie low-voltage interrupt enable bit 0 interrupt request is disabled. 1 interrupt will be requested whenever lvif is set. 0 lvif low-voltage interrupt flag ? lvif is set to 1 when lvds status bit changes. this flag can only be cleared by writing a 1. writing a 0 has no effect. if enabled (lvie = 1), lvif causes an interrupt request. 0 no change in lvds bit. 1 lvds bit has changed. table 428. reserved register (cpmutest3) 0x02f6 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved
mm912_637, rev. 3.0 freescale semiconductor 311 5.22.3.2.15 s12cpmu irc1m trim regist ers (cpmuirctrimh / cpmuirctriml) read: anytime write: anytime if prot=0 (cpmuprot register). else write has no effect note writes to these registers while pllsel=1 clears the lock and uposc status bits. table 430. s12cpmu irc1m trim high register (cpmuirctrimh) 0x02f8 15 14 13 12 11 10 9 8 r tctrim[4:0] 0 irctrim[9:8] w reset f f f f 0 0 f f after de-assert of system reset a factory programmed trim value is automatically loaded from the flash memory to provide trimme d internal reference frequency f irc1m_trim . table 431. s12cpmu irc1m trim low register (cpmuirctriml) 0x02f9 7 6 5 4 3 2 1 0 r irctrim[7:0] w reset f f f f f f f f after de-assert of system reset a factory programmed trim value is automatically loaded from the flash memory to provide trimme d internal reference frequency f irc1m_trim . table 432. cpmuirctrimh/l field descriptions field description 15-11 tctrim irc1m temperature coefficient trim bits trim bits for the temperature coefficient (tc) of the irc1m frequency. figure 93 shows the influence of the bits tctrim4:0] on the relationship between frequency and temperature. figure 93 shows an approximate tc variation, relative to the no minal tc of the irc1m (i.e. for tctrim[4:0]=0x00000 or 0x10000). 9-0 irctrim irc1m frequency trim bits ? trim bits for internal reference clock after system reset the factory programmed trim value is automatically loaded into these registers, resulting in a internal reference frequency f irc1m_trim . see device electrical char acteristics for value of f irc1m_trim . the frequency trimming consists of two different trimming methods: a rough trimming controlled by bits irctrim[9:6] c an be done with frequency leaps of about 6% in average. a fine trimming controlled by the bits ir ctrim[5:0] can be done with frequency leaps of about 0.3% (this trimming determines the precision of the frequency setting of 0.15%, i.e. 0.3% is the distance between two trimming values). figure 92 shows the relationship between the trim bits and the resulting irc1m frequency.
mm912_637, rev. 3.0 freescale semiconductor 312 figure 92. irc1m frequency trimming diagram figure 93. influence of tctrim[4:0] on the temperature coefficient note the frequency is not necessarily linear with th e temperature (in most cases it will not be). the above diagram is meant only to give the di rection (positive or negat ive) of the variation of the tc, relative to the nominal tc. setting tctrim[4:0] at 0x00000 or 0x10000 does not mean that the te mperature coefficient will be zero. these two combinations basica lly switch off the tc compensation module, which result in the nominal tc of the irc1m. table 433. tc trimming of the frequency of the irc1m tctrim[4:0] irc1m indicative relative tc variation irc1m indicative frequency drift for relative tc variation 00000 0 (nominal tc of the irc) 0% 00001 -0.27% -0.5% 00010 -0.54% -0.9% irctrim[9:0] $000 $1ff irctrim[9:6] irctrim[5:0] irc1m frequency (ircclk) 600 khz 1.5 mhz 1.0 mhz $3ff ...... $1ff frequency temperature t c t r i m [ 4 : 0 ] = 0 x 1 1 1 1 1 t c t r i m [ 4 : 0 ] = 0 x 0 1 1 1 1 - 40 c 150 c tctrim[4:0] = 0x10000 or 0x00000 (nominal tc) 0x00001 0x00010 0x00011 0x00100 0x00101 ... 0x01111 0x11111 ... 0x10101 0x10100 0x10011 0x10010 0x10001 tc increases tc decreases
mm912_637, rev. 3.0 freescale semiconductor 313 note since the irc1m frequency is not a linear fu nction of the temperature, but more like a parabola, the above relative variation is only an indication and should be considered with care. be aware that the output frequency varies with the tc trimming. a frequency trimming correction is therefore necessa ry. the values provided in ta b l e 433 are typical values at ambient temperature which can vary from device to device. 00011 -0.81% -1.3% 00100 -1.08% -1.7% 00101 -1.35% -2.0% 00110 -1.63% -2.2% 00111 -1.9% -2.5% 01000 -2.20% -3.0% 01001 -2.47% -3.4% 01010 -2.77% -3.9% 01011 -3.04 -4.3% 01100 -3.33% -4.7% 01101 -3.6% -5.1% 01110 -3.91% -5.6% 01111 -4.18% -5.9% 10000 0 (nominal tc of the irc) 0% 10001 +0.27% +0.5% 10010 +0.54% +0.9% 10011 +0.81% +1.3% 10100 +1.07% +1.7% 10101 +1.34% +2.0% 10110 +1.59% +2.2% 10111 +1.86% +2.5% 11000 +2.11% +3.0% 11001 +2.38% +3.4% 11010 +2.62% +3.9% 11011 +2.89% +4.3% 11100 +3.12% +4.7% 11101 +3.39% +5.1% 11110 +3.62% +5.6% 11111 +3.89% +5.9% table 433. tc trimming of the frequency of the irc1m tctrim[4:0] irc1m indicative relative tc variation irc1m indicative frequency drift for relative tc variation
mm912_637, rev. 3.0 freescale semiconductor 314 5.22.3.2.16 s12cpmu oscillat or register (cpmuosc) this register configures the external oscillator (osclcp). read: anytime write: anytime if prot=0 (cpmuprot register) and pll sel=1 (cpmuclks register), else write has no effect. note. write to this register clears the lock and uposc status bits. note. if the chosen vcoclk-to-oscclk ratio divided by two ((f vco / f osc )/2) is not an integer number, the filter can not be used and the oscfilt[4:0] bits must be set to 0. note the frequency modulation (fm1 and fm0) can not be used if the adapti ve oscillator filter is enabled. table 434. s12cpmu oscillator register (cpmuosc) 0x02fa 7 6 5 4 3 2 1 0 r osce oscbw oscpins_en oscfilt[4:0] w reset 0 0 0 0 0 0 0 0 table 435. cpmuosc fi eld descriptions field description 7 osce oscillator enable bit ? this bit enables the external oscillator (osclcp). the uposc status bit in the cpmuflg register indicates when the oscillation is stable and oscclk can be sele cted as bus clock or source of the cop or rti. a loss of oscillation will lead to a clock monitor reset. 0 external oscillator is disabled. ? refclk for pll is ircclk. 1 external oscillator is enabled .clock monitor is enabled. ? refclk for pll is external osci llator clock divided by refdiv. note: when starting up the external oscillator (either by programming osce bit to 1 or on exit from full stop mode with osce bit already 1) the software must wait for a minimum time e quivalent to the startup time of the external oscillator t uposc before entering pseudo stop mode. 6 oscbw oscillator filter bandwidth bit ? if the vcoclk frequency exceeds 25 mhz wide bandwidth must be selected. the oscillator filter is described in more detail in section 5.22.4.5.2, ?the adaptive oscillator filter" 0 oscillator filter bandwidth is narrow (window for expected oscclk edge is one vcoclk cycle). 1 oscillator filter bandwidth is wide (window fo r expected oscclk edge is three vcoclk cycles). 5 oscpins_en oscillator pins extal and xtal enable bit if osce=1 this read-only bit is set. it can only be cleared with the next reset. enabling the external oscillator reserves the extal and xtal pins exclusively for oscillator application. 0 extal and xtal pins are not reserved for oscillator. 1 extal and xtal pins exclusively reserved for oscillator. 4-0 oscfilt oscillator filter bits ? when using the oscillator a noise filter can be enabled, which filters noise from the incoming external oscillator clock and detects if the external oscillator clock is qualified or not (quality status shown by bit uposc). the vcoclk-to-oscclk ratio divided by two ((f vco / f osc )/2) must be an integer value. this value must be written to the oscfilt[4:0] bits to enable the adaptive oscillator filter. 0x0000 adaptive oscillator fi lter disabled, else adaptiv e oscillator filter enabled]
mm912_637, rev. 3.0 freescale semiconductor 315 5.22.3.2.17 s12cpmu protec tion register (cpmuprot) this register protects the following clock conf iguration registers from accidental overwrite: cpmusynr, cpmurefdiv, cpmuclks, cpmu pll, cpmuirctrimh /l, and cpmuosc read: anytime write: anytime 5.22.3.2.18 reserved register cpmutest2 note this reserved register is designed for factor y test purposes only, and is not intended for general user access. writing to this register when in special mode can alter the s12cpmu?s functionality. read: anytime write: only in special mode 5.22.4 functional description 5.22.4.1 phase locked loop wi th internal filter (pll) the pll is used to generate a high speed pllclk based on a low frequency refclk. the refclk is by default the ircclk which is trimmed to f irc1m_trim =1.0 mhz. if using the oscillator (osce=1) refclk will be based on oscclk. for increased flexibility, oscclk can be divided in a range of 1 to 16 to generate the reference frequency refclk using th e refdiv[3:0] bits. based on the syndiv[5:0] bits, the pll generates the vcoclk by multiplying the reference clock by a 2, 4, 6,... 126, 128. based on the postdiv[4:0] bits, the vcoclk can be divided in a range of 1,2, 3, 4, 5, 6,... to 32 to generate the pllclk. table 436. s12cpmu protection register (cpmuprot) 0x02fb 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 prot w reset 0 0 0 0 0 0 0 0 table 437. cpmuprot field description field description 0 clock configuration registers protection bit ? this bit protects the clock configur ation registers from accidental overwrite (see list of protected registers above). writing 0x26 to the cpmuprot register clears the prot bit, other write accesses set the prot bit. 0 protection of clock configuration registers is disabled. 1 protection of clock configuration registers is enabled. (see list of protected registers above) table 438. reserved register cpmutest2 0x02fc 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved
mm912_637, rev. 3.0 freescale semiconductor 316 . note although it is possible to set the dividers to command a very high clock frequency, do not exceed the specified bus frequency limit for the mcu. several examples of pll divider settings are shown in ta b l e 439 . the following rules help to achieve optimum stability and shortest lock time: ? use lowest possible f vco / f ref ratio (syndiv value). ? use highest possible refclk frequency f ref . the phase detector inside the pll compares the feedback clo ck (fbclk = vcoclk/(syndiv+1) with the reference clock (refclk = (irc1m or oscclk)/(refdiv+1)). correction pulses ar e generated based on the phase difference between the two signals. the loop filter alters the dc voltage on the internal fi lter capacitor, based on the width and direction of the correc tion pulse, which leads to a higher or lower vco frequency. the user must select the range of the refclk frequency (reffrq[1:0] bits) and the range of the vcoclk frequency (vcofrq[1:0] bits) to ensure that the correct pll loop bandwidth is set. the lock detector compares the frequencies of the fbclk and the refclk. therefore, the speed of the lock detector is directly proportional to the reference clock frequency. the circui t determines the lock condition based on this comparison. if pll lock interrupt requests are enabled, the software can wait for an interrupt request and for instance check the lock bit. if interrupt requests are disabled, software can poll the lock bit continuously (during pll start-up) or at periodic intervals. in either case, only when the lock bit is set, the vc oclk will have stabilized to the programmed frequency. ? the lock bit is a read-only indica tor of the locked state of the pll. ? the lock bit is set when the vco frequency is within the tolerance, ? lock , and is cleared when the vco frequency is out of the tolerance, ? unl . ? interrupt requests can occur if enabled (lockie = 1) when the lock condition changes, toggling the lock bit. table 439. examples of pll divider settings f osc refdiv[3:0] f ref reffrq[1:0] syndiv[5:0] f vco vcofrq[1:0] postdiv[4:0] f pll f bus off $00 1.0 mh z 00 $1f 64 mhz 01 $03 16 mhz 8.0 mhz off $00 1.0 mh z 00 $1f 64 mhz 01 $00 64 mhz 32 mhz off $00 1.0 mh z 00 $0f 32 mhz 00 $00 32 mhz 16 mhz 4.0 mh z $00 4.0 mh z 01 $03 32 mhz 01 $00 32 mhz 16 mhz f vco 2 f ref ? syndiv 1 + ?? ? = f ref f osc refdiv 1 + ?? ------------------------------------- - = if oscillator is enabled (osce=1) if oscillator is disabled (osce=0) f ref f irc 1 m = f pll f vco postdiv 1 + ?? ------------------------------------------ - = if pll is locked (lock=1) if pll is not locked (lock=0) f pll f vco 4 --------------- = f bus f pll 2 ------------ - = if pll is selected (pllsel=1)
mm912_637, rev. 3.0 freescale semiconductor 317 5.22.4.2 startup from reset an example of startu p of clock system from reset is given in figure 94 . figure 94. startup of clock system after reset 5.22.4.3 stop mode using pllclk as bus clock an example of what happens going into stop mode and exiting stop mode after an interrupt is shown in figure 95 . disable pll lock interrupt (lockie=0) before going into stop mode. figure 95. stop mode using pllclk as bus clock 5.22.4.4 full stop mode using os cillator clock as bus clock an example of what happens going into full stop mode an d exiting full stop mode after an interrupt is shown in figure 96 . disable pll lock interrupt (lockie=0) and oscillator status change interrupt (oscie=0) before going into full stop mode. system pllclk reset f vcorst cpu reset state vector fetch, program execution lock postdiv $03 (default target f pll =f vco /4 = 16mhz) f pll increasing f pll =16mhz t lock syndiv $1f (default target f vco =64mhz) $01 f pll =32 mhz example change of postdiv 768 cycles ) ( pllclk cpu lock t lock stop instruction execution interrupt continue execution wake-up t stp_rec
mm912_637, rev. 3.0 freescale semiconductor 318 figure 96. full stop mode using oscillator clock as bus clock 5.22.4.5 external oscillator 5.22.4.5.1 enabling the external oscillator an example of how to use the oscillator as bus clock is shown in figure 97 . figure 97. enabling the external oscillator cpu uposc t lock stop instruction execution interrupt continue execution wake-up t stp_rec core clock select oscclk as core/bus clock by writing pllsel to ?0? pllsel automatically set when go ing into full stop mode oscclk pllclk pllsel osce extal oscclk core enable external oscillator by writing osce bit to one. crystal/resonator starts oscillating uposc uposc flag is set upon successful start of oscillation select oscclk as core/bus cl ock by writing pllsel to zero clock based on pllclk based on oscclk
mm912_637, rev. 3.0 freescale semiconductor 319 5.22.4.5.2 the adaptive oscillator filter a spike in the oscillator clock can disturb the function of the modules driven by this clock. the adaptive oscillator filter includes two features: 1. filter noise (spikes) from the incoming external o scillator clock. the filter feature is illustrated in figure 98 . figure 98. noise filtered by the adaptive oscillator filter 2. detect severe noise disturbance on external oscillator clock which can not be filtered and indicate the critical situation to the software by clearing the uposc and lock status bi t and setting the oscif and lockif flag. an example for the detection of critical noise is illustrated in figure 99 . figure 99. critical noise detected by the adaptive oscillator filter note if the lock bit is clear due to severe noise di sturbance on the external oscillator clock, the pllclk is derived from the vco clock (with its actual frequency) divided by four (see section 5.22.3.2.3, ?s12cpmu post div ider register (cpmupostdiv)" ). the use of the filter function is only possible if the vcoclk-to-oscclk ratio divided by two ((f vco / f osc )/2) is an integer number. this integer value must be written to the oscfilt[4:0] bits. if enabled, the adaptive oscilla tor filter samples the incoming external osci llator clock signal (extal) with the vcoclk frequency. osce extal oscclk enable external oscillator crystal/resonator starts oscillating uposc osc configure the adaptive oscillator filter filt 0> 0 lock filtered filtered (filtered) osce extal oscclk enable external oscillator crystal/resonator starts oscillating uposc osc configure the adaptive oscillator filter filt 0> 0 lock (filtered) phase shift can not be filtered but detected
mm912_637, rev. 3.0 freescale semiconductor 320 using vcoclk, a time window is defined of which an edge of the oscclk is expected. in case of oscbw = 1, the width of this window is three vcoclk cycles, if t he oscbw = 0 it is one vcoclk cycle. the noise detection is active for certain combinations of oscfilt[4:0] and oscbw bit settings, as shown in ta b l e 440 . note if the vcoclk frequency is higher than 25 mhz the wide bandwidth must be selected (oscbw = 1). 5.22.4.6 system clock configurations 5.22.4.6.1 pll engaged internal mode (pei) this mode is the default mode afte r system reset or power-on reset. the bus clock is based on the pllclk, the reference clock for t he pll is internally generated (irc1m). the pll is configured to 64 mhz vcoclk with postdiv set to 0x03. if locke d (lock=1) this results in a pllclk of 16 mhz and a bus clock of 8.0 mhz. the pll can be re-configur ed to other bus frequencies. the clock sources for cop and rti are based on t he internal reference clock generator (irc1m). 5.22.4.6.2 pll engaged external mode (pee) in this mode, the bus clock is based on the pllclk as well (l ike pei). the reference clock for the pll is based on the external oscillator. the adaptive spike filter and detection logic which us es the vcoclk to filter and qualify the external oscillator c lock can be enabled. the clock sources for cop and rti can be based on the internal reference clock generator or on the external oscillator clock. this mode can be entered from default mo de pei by performing the following steps: 1. configure the pll for desired bus frequency. 2. optionally the adaptive spike filter and detection logic can be enabled by calculating the integer value for the oscfil[4:0] bits and setting the bandwidth (oscbw) accordingly. 3. enable the external oscillator (osce bit). 4. wait for the pll being locked (lock = 1) and the oscillator to start-up and additionally being qualified if the adaptive oscillator filter is enabled (uposc =1). 5. clear all flags in the cpmuflg register to be able to detect any future status bit change. 6. optionally status interrupts ca n be enabled (cpmuint register). since the adaptive oscillator filt er (adaptive spike filter and detection logic) uses the vcoclk to continuously filter and qua lify the external oscillator clock, losing pll lock status (lock=0), means losing the osci llator status information as well (uposc=0 ). the impact of losing the oscillator status in pee mode is as follows: ? the pllclk is derived from the vco clock (with its ac tual frequency) divided by fo ur until the pll locks again. application software needs to be prepared to deal with th e impact of losing the oscillator status at any time. table 440. noise detection settings oscfilt[4:0] oscbw detection filter 0 x disabled disabled 1 x disabled active 2 or 3 0 active active 1 disabled active >=4 x active active
mm912_637, rev. 3.0 freescale semiconductor 321 5.22.4.6.3 pll bypassed ex ternal mode (pbe) in this mode, the bus clock is based on the external oscillator clock. the reference clock for the pll is based on the external oscillator. the adaptive spike filter and det ection logic can be enabled which uses th e vcoclk to filter and qualify the extern al oscillator clock. the clock sources for cop and rti can be based on the internal reference clock generator or on the external oscillator clock. this mode can be entered from default mo de pei by performing the following steps: 1. make sure the pll configuration is valid. 2. optionally, the adaptive spik e filter and detection logic can be enabled by calculating the integer value for the oscfil[4:0] bits and setting the bandwidth (oscbw) accordingly. 3. enable the external oscillator (osce bit) 4. wait for the pll being locked (lock = 1) and the oscillator to start-up, and additionally be ing qualified if the adaptive oscillator filter is enabled (uposc=1). 5. clear all flags in the cpmuflg register to be able to detect any status bit change. 6. optionally status interrupts ca n be enabled (cpmuint register). 7. select the oscillator clock (oscclk) as bus clock (pllsel=0) since the adaptive oscillator filt er (adaptive spike filter and detection logic) uses the vcoclk to continuously filter and qua lify the external oscillator clock, losing pll lock status (lock=0) means losing the oscillator stat us information as well (uposc=0) . the impact of losing the oscillator status in pbe mode is as follows: ? pllsel is set automatically and the bus clock is switched back to the pllclk. ? the pllclk is derived from the vco clock (with its ac tual frequency) divided by fo ur until the pll locks again. application software needs to be prepared to deal with th e impact of loosing the oscillator status at any time. in the pbe mode, not every noise disturbance can be indi cated by bits lock and uposc (b oth bits are base d on the bus clock domain). there are clock disturbances possi ble, after which uposc and lock both stay asserted, while occasional pauses on the filtered oscclk and resulting bus clock occur. the adaptive sp ike filter is still functional and protects the bus clock fro m frequency overshoot due to spikes on the ex ternal oscillator clock. the filtered os cclk and resulting bus clock will pause unti l the pll has stabilized again. 5.22.5 resets 5.22.5.1 general all reset sources are listed in ta b l e 441 . refer to mcu specification for related vector addresses and priorities. 5.22.5.2 description of reset operation upon detection of any reset in ta b l e 441 , an internal circuit drives the reset pin low for 512 pllclk cycles. after 512 pllclk cycles, the reset pin is released. the reset generator of the s12cpm u waits for additional 256 pllclk cycles and then samples the reset pin to determine the originating source. ta b l e 442 shows which vector will be fetched. table 441. reset summary reset source local enable power-on reset (por) none low voltage reset (lvr) none external pin reset none illegal address reset none clock monitor reset osce bit in cpmuosc register cop reset cr[2:0] in cpmucop register
mm912_637, rev. 3.0 freescale semiconductor 322 note while system reset is asserted, th e pllclk runs with the frequency f vcorst . the internal reset of the mcu remains asserted while the reset generat or completes the 768 pl lclk cycles long reset sequence. in case the reset pin is externally driven low for more than these 768 pllclk cycles (external reset), the internal reset remains asserted longer. figure 100. reset timing 5.22.5.2.1 clock monitor reset when the external oscillator is enabled (osce=1), in case of a loss of oscillation or the oscillator frequency is below the fai lure assert frequency f cmfa (see device electrical characteristics for values), the s12cpmu generates a clock monitor reset. in full stop mode the external oscillator and the clock monitor are disabled. 5.22.5.2.2 computer operating properly watchdog (cop) reset the cop (free running watchdog timer) enables the user to che ck that a program is running and sequencing properly. when the cop is being used, software is responsible for keeping the cop fr om timing out. if the cop times out, it is an indication that the software is no longer being executed in the in tended sequence, and a cop reset is generated. the clock source for the cop is either ircclk or oscclk, depend ing on the setting of the coposcsel bit. in stop mode with pstp=1 (pseudo stop mode), coposcsel=1 and pce=1 the cop cont inues to run, else the cop counter halts in stop mode. three control bits in the cpmucop register allow selection of seve n cop timeout periods. table 442. reset vector selection sampled reset pin (256 cycles after release) oscillator monitor fail pending cop timeout pending vector fetch 1 0 0 por lvr illegal address reset external pin reset 1 1 x clock monitor reset 1 0 1 cop reset 0 x x por lvr illegal address reset external pin reset ) ( ) pllclk 512 cycles 256 cycles s12_cpmu drives possibly r eset driven low externally ) ( ( reset s12_cpmu releases f vcorst reset pin low reset pin f vcorst
mm912_637, rev. 3.0 freescale semiconductor 323 when cop is enabled, the program must write $55 and $aa (in this order) to the cpmuarmcop register during the selected timeout period. once this is done, the cop timeout period is restarted. if the program fails to do this and the cop times out, a cop reset is generated. also, if any value other than $55 or $aa is written, a cop reset is generated. windowed cop operation is enabled by setting wcop in the cpmucop register. in this mode , writes to the cpmuarmcop register to clear the cop timer must occur in the last 25% of the selected timeout period. a premature wr ite will immediately r eset the part. 5.22.5.3 power-on reset (por) the on-chip por circuitry detects when the internal supply vdd drops below an appropriate voltage level. the por is deasserted if the internal supply vdd exceeds an appropriate voltag e level (voltage levels are not specified in this document, because this internal supply is not visible on device pins). 5.22.5.4 low-voltage reset (lvr) the on-chip lvr circuitry detects when one of the supply voltages vdd, vddf, or vddx, drops below an appropriate voltage level. if lvr is deasserted, the mcu is fully operational at th e specified maximum speed. the lvr assert and deassert levels fo r the supply voltage vddx are v lvrxa and v lvrxd , and are specified in the device reference manual. 5.22.6 interrupts the interrupt/reset vectors requested by the s12cpmu are listed in table 443 . refer to mcu specification for related vector addresses and priorities. 5.22.6.1 description of interrupt operation 5.22.6.1.1 real time interrupt (rti) the clock source for the rti is either ircclk or oscclk, depen ding on the setting of the rtio scsel bit. in stop mode with pstp=1 (pseudo stop mode), rtioscsel=1 and pre=1 the rti continues to run, else the rti counter halts in stop mode. the rti can be used to generate hardware interrupts at a fixed pe riodic rate. if enabled (by setting rtie=1), this interrupt wi ll occur at the rate selected by the cpmurti register. at the end of the rti timeout period, the rtif flag is set to one and a new rti timeout period starts immediately. a write to the cpmurti register restarts the rti timeout period. 5.22.6.1.2 pll lock interrupt the s12cpmu generates a pll lock interrupt when the lock condition (lock status bit) of the pll changes, either from a locked state to an unlocked state, or vice versa. lock interrupts are lo cally disabled by setting the lockie bit to zero. the pll lock interrupt flag (lockif) is set to 1 when the lock condition has c hanged, and is cleared to 0 by writing a 1 to the lockif bit. table 443. s12cpmu interrupt vectors interrupt source ccr mask local enable rti timeout interrupt i bit cpmuint (rtie) pll lock interrupt i bit cpmuint (lockie) oscillator status interrupt i bit cpmuint (oscie) low voltage interrupt i bit cpmulvctl (lvie)
mm912_637, rev. 3.0 freescale semiconductor 324 5.22.6.1.3 oscillator status interrupt the adaptive oscillator filter co ntains two different features: 1. filters spikes of the external oscillator clock. 2. qualify the external oscillator clock. when the osce bit is 0, then uposc stays 0. when osce=1 and oscfilt = 0, then t he filter is transpar ent and no spikes are filtered. the uposc bit is then set after the lock bit is set. upon detection of a status change (uposc), where an unqualified oscillation becomes qu alified or vice versa, the oscif flag is set. going into full stop mode or disabling the oscillator can also cause a status change of uposc. since the adaptive oscillator filt er is based on the pllclk, any change in pll configuration or any other event which causes the pll lock status to be cleared, leads to a loss of the oscillator status information as well (uposc=0). oscillator status change interrupts are locally enabled with the oscie bit. note losing the oscillator st atus (uposc=0) affects the cl ock configuration of the system (268) . this needs to be addressed in application software. notes 268.for details refer to ? section 5.22.4.6, ?system clock configurations ? 5.22.6.1.4 low-voltage interrupt (lvi) in fpm, the input voltage vddxr is monito red. whenever vddxr drops below level v lvia , the status bit lvds is set to 1. when vddxr rises above level v lvid , the status bit lvds is cleared to 0. an interrupt, indicated by flag lvif = 1, is triggered by any change of the status bit lvds if interrupt enable bit lvie = 1. 5.22.7 initialization/app lication information 5.22.7.1 general initialization information usually applications run in mcu normal mode. it is recommended to write the cpmucop regi ster from the application program initialization routine after reset, regardless if the cop is used in the application, even if a configuration is loaded via the flash memory after reset. by doing a ?controlled? wri te access in mcu normal mode (with the right value for the app lication), the write once for the cop configuration bits (wcop,cr[2:0]) takes place, whic h protects these bits from further accidental change. if there is a pr ogram sequencing issue (code runaway), the cop configuration cannot be accidentally modified.
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 325 5.23 mcu - serial peripheral interface (s12spiv5) 5.23.1 introduction the spi module allows a duplex, synchronous, serial communica tion, between the mcu and peripheral devices. software can poll the spi status flags or the spi operation can be interrupt driven. 5.23.1.1 glossary of terms 5.23.1.2 features the spi includes these distinctive features: ? master mode and slave mode ? selectable 8 or 16-bit transfer width ? bidirectional mode ? slave select output ? mode fault error flag with cpu interrupt capability ? double-buffered data register ? serial clock with programmable polarity and phase ? control of spi operation during wait mode 5.23.1.3 modes of operation the spi functions in three modes: run, wait, and stop. ?run mode this is the basic mode of operation. ? wait mode spi operation in wait mode is a conf igurable low power mode, controlled by the spiswai bit located in the spicr2 register. in wait mode, if the spiswai bit is clear, the spi operates like in run mode. if the spiswai bit is set, the spi goes into a power conservative state, with the spi clock generat ion turned off. if the spi is configured as a master, any transmission in progress stops, but is resumed after cpu goes into run mode. if the spi is configured as a slave, reception and transmission of data continues, so t hat the slave stays synchronized to the master. ? stop mode the spi is inactive in stop mode for reduced power consumpti on. if the spi is configured as a master, any transmission in progress stops, but is resumed after cpu goes into run mo de. if the spi is configured as a slave, reception and transmission of data continues, so that the slave stays synchronized to the master. for a detailed description of operating modes, refer to section 5.23.4.7, ?low power mode options" . 5.23.1.4 block diagram figure 101 gives an overview on the spi architecture. the main parts of the spi are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic. table 444. term definition spi serial peripheral interface ss slave select sck serial clock mosi master output, slave input miso master input, slave output momi master output, master input siso slave input, slave output analog mcu
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 326 figure 101. spi block diagram 5.23.2 external signal description this section lists the name and description of all ports including inputs and outputs that do, or may, connect off chip. the sp i module has a total of four external pins. 5.23.2.1 mosi ? master out/slave in pin this pin is used to transmit data out of the spi module when it is conf igured as a master and receiv e data when it is configure d as slave. 5.23.2.2 miso ? master in/slave out pin this pin is used to transmit data out of the spi module when co nfigured as a slave and receive data when configured as master. spi control register 1 spi control register 2 spi baud rate register spi status register spi data register shifter port control logic mosi sck interrupt control spi msb lsb lsbfe=1 lsbfe=0 lsbfe=0 lsbfe=1 data in lsbfe=1 lsbfe=0 data out baud rate generator prescaler bus clock counter clock select sppr 3 3 spr baud rate phase + polarity control master slave sck in sck out master baud rate slave baud rate phase + polarity control control control cpol cpha 2 bidiroe spc0 2 shift sample clock clock modf spif sptef spi request interrupt ss
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 327 5.23.2.3 ss ? slave select pin this pin is used to output the select si gnal from the spi module to another peripheral , with which a data transfer is to take p lace when it is configured as a master, and is used as an input to receive the slave select signal when the spi is configured as a s lave. 5.23.2.4 sck ? serial clock pin in master mode, this is the synchronous output clock. in slave mode, this is the synchronous input clock. 5.23.3 memory map and register definition this section provides a detailed description of address space and registers used by the spi. 5.23.3.1 module memory map the memory map for the spi is given in ta b l e 445 . the address listed for each register is the sum of a base address and an address offset. the base address is defined at the soc level and t he address offset is defined at the module level. reads from the reserved bits return zeros and writes to the reserved bits have no effect. 5.23.3.2 register descriptions this section consists of regist er descriptions in address order. each description includes a standard register diagram with an associated figure number. details of register bit and fi eld function follow the register diagrams, in bit order. table 445. spi register summary register name bit 7 6 5 4 3 2 1 bit 0 0x00e8 spicr1 r spie spe sptie mstr cpol cpha ssoe lsbfe w 0x00e9 spicr2 r 0 xfrw 0 modfen bidiroe 0 spiswai spc0 w 0x00ea spibr r 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w 0x00eb spisr r spif 0 sptef modf 0 0 0 0 w 0x00ec spidrh r r15 r14 r13 r12 r11 r10 r9 r8 t15 t14 t13 t12 t11 t10 t9 t8 w 0x00ed spidrl r r7 r6 r5 r4 r3 r2 r1 r0 t7 t6 t5 t4 t3 t2 t1 t0 w 0x00ee reserved r w 0x00ef reserved r w = unimplemented or reserved
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 328 5.23.3.2.1 spi control register 1 (spicr1) read: anytime write: anytime table 446. spi control register 1 (spicr1) 0x00e8 7 6 5 4 3 2 1 0 r spie spe sptie mstr cpol cpha ssoe lsbfe w reset 0 0 0 0 0 1 0 0 table 447. spicr1 field descriptions field description 7 spie spi interrupt enable bit ? this bit enables spi interrupt requests , if spif or modf status flag is set. 0 spi interrupts disabled. 1 spi interrupts enabled. 6 spe spi system enable bit ? this bit enables the spi system and dedicates the spi port pins to spi system functions. if spe is cleared, spi is disabled and forced into idle st ate, status bits in spisr register are reset. 0 spi disabled (lower power consumption). 1 spi enabled, port pins are dedicated to spi functions. 5 sptie spi transmit interrupt enable ? this bit enables spi interrupt requests, if sptef flag is set. 0 sptef interrupt disabled. 1 sptef interrupt enabled. 4 mstr spi master/slave mode select bit ? this bit selects whether the spi operates in master or slave mode. switching the spi from master to slave or vice versa forces the spi system into idle state. 0 spi is in slave mode. 1 spi is in master mode. 3 cpol spi clock polarity bit ? this bit selects an inverted or non-inverted spi clock. to transmit data between spi modules, the spi modules must have identical cpol values. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 active-high clocks selected. in idle state sck is low. 1 active-low clocks selected. in idle state sck is high. 2 cpha spi clock phase bit ? this bit is used to select the spi clock forma t. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 sampling of data occurs at odd edges (1,3,5,...) of the sck clock. 1 sampling of data occurs at even edges (2,4,6,...) of the sck clock. 1 ssoe slave select output enable ? the ss output feature is enabled only in master mode, if modfen is set, by asserting the ssoe as shown in ta b l e 448 . in master mode, a change of this bit will abo rt a transmission in progress and force the spi system into idle state. 0 lsbfe lsb-first enable ? this bit does not affect the position of the msb and lsb in the data register. reads and writes of the data register always have the msb in the highest bit position. in master mode, a change of this bit will abort a transmission i n progress and force the spi system into idle state. 0 data is transferred most significant bit first. 1 data is transferred leas t significant bit first. table 448. ss input / output selection modfen ssoe master mode slave mode 0 0 ss not used by spi ss input 0 1 ss not used by spi ss input 1 0 ss input with modf feature ss input 1 1 ss is slave select output ss input
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 329 5.23.3.2.2 spi control register 2 (spicr2) read: anytime write: anytime; writes to the reserved bits have no effect table 449. spi control register 2 (spicr2) 0x00e9 7 6 5 4 3 2 1 0 r 0 xfrw 0 modfen bidiroe 0 spiswai spc0 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 450. spicr2 field descriptions field description 6 xfrw transfer width ? this bit is used for selecting the data transfer widt h. if 8-bit transfer width is selected, spidrl becomes the dedicated data register and spidrh is unused. if 16-bit transfer width is selected, spidrh and spidrl form a 16-bit data register. refer to section 5.23.3.2.4, ?spi status register (spisr)" for information about transmit/receive data handling and the interrupt flag clearing mechanism. in master mode, a change of this bit will abort a transmi ssion in progress and force the spi system into idle state. 0 8-bit transfer width (n = 8) (269) 1 16-bit transfer width (n = 16) (269) 4 modfen mode fault enable bit ? this bit allows the modf failure to be detec ted. if the spi is in master mode and modfen is cleared, then the ss port pin is not used by the spi. in slave mode, the ss is available only as an i nput regardless of the value of modfen. for an overview on the impact of the modfen bit on the ss port pin configuration, refer to table 448 . in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 ss port pin is not used by the spi. 1 ss port pin with modf feature. 3 bidiroe output enable in the bidirectional mode of operation ? this bit controls the mosi and miso output buffer of the spi, when in bidirectional mode of operation (spc0 is set). in master mode, this bit controls the output buffer of the mosi port, in slave mode it controls the output buffer of the miso port. in master mode, with spc0 set, a change of this bit will abort a transmission in progress and force the spi into idle state. 0 output buffer disabled. 1 output buffer enabled. 1 spiswai spi stop in wait mode bit ? this bit is used for power conservation while in wait mode. 0 spi clock operates normally in wait mode. 1 stop spi clock generation when in wait mode. 0 spc0 serial pin control bit 0 ? this bit enables bidirectional pin configurations as shown in table 451 . in master mode, a change of this bit will abort a transmission in progr ess and force the spi system into idle state. notes 269.n is used later in this document as a placeholder for the selected transfer width. table 451. bidirectional pin configurations pin mode spc0 bidiroe miso mosi master mode of operation normal 0 x master in master out bidirectional 1 0 miso not used by spi master in 1 master i/o slave mode of operation normal 0 x slave out slave in
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 330 5.23.3.2.3 spi baud rate register (spibr) read: anytime write: anytime; writes to the reserved bits have no effect the baud rate divisor equation is as follows: baudratedivisor = (sppr + 1) ? 2 (spr + 1) eqn. 4 the baud rate can be calculated with the following equation: baud rate = busclock / baudratedivisor eqn. 5 note for maximum allowed baud rates, refer to section 4.6.2.5, ?spi timing" of this data sheet. bidirectional 1 0 slave in mosi not used by spi 1 slave i/o table 452. spi baud rate register (spibr) 0x00ea 7 6 5 4 3 2 1 0 r 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 453. spibr field descriptions field description 6?4 sppr[2:0] spi baud rate preselection bits ? these bits specify the spi baud rates as shown in table 454 . in master mode, a change of these bits will abort a transmission in prog ress and force the spi system into idle state. 2?0 spr[2:0] spi baud rate selection bits ? these bits specify the spi baud rates as shown in table 454 . in master mode, a change of these bits will abort a transmi ssion in progress and force the spi system into idle state. table 454. example spi baud rate selection (25 mhz bus clock) sppr2 sppr1 sppr0 spr2 spr1 spr0 baud rate divisor baud rate 0 0 0 0 0 0 2 12.5 mbit/s 0 0 0 0 0 1 4 6.25 mbit/s 0 0 0 0 1 0 8 3.125 mbit/s 0 0 0 0 1 1 16 1.5625 mbit/s 0 0 0 1 0 0 32 781.25 kbit/s 0 0 0 1 0 1 64 390.63 kbit/s 0 0 0 1 1 0 128 195.31 kbit/s 0 0 0 1 1 1 256 97.66 kbit/s 0 0 1 0 0 0 4 6.25 mbit/s table 451. bidirectional pin configurations pin mode spc0 bidiroe miso mosi
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 331 0 0 1 0 0 1 8 3.125 mbit/s 0 0 1 0 1 0 16 1.5625 mbit/s 0 0 1 0 1 1 32 781.25 kbit/s 0 0 1 1 0 0 64 390.63 kbit/s 0 0 1 1 0 1 128 195.31 kbit/s 0 0 1 1 1 0 256 97.66 kbit/s 0 0 1 1 1 1 512 48.83 kbit/s 0 1 0 0 0 0 6 4.16667 mbit/s 0 1 0 0 0 1 12 2.08333 mbit/s 0 1 0 0 1 0 24 1.04167 mbit/s 0 1 0 0 1 1 48 520.83 kbit/s 0 1 0 1 0 0 96 260.42 kbit/s 0 1 0 1 0 1 192 130.21 kbit/s 0 1 0 1 1 0 384 65.10 kbit/s 0 1 0 1 1 1 768 32.55 kbit/s 0 1 1 0 0 0 8 3.125 mbit/s 0 1 1 0 0 1 16 1.5625 mbit/s 0 1 1 0 1 0 32 781.25 kbit/s 0 1 1 0 1 1 64 390.63 kbit/s 0 1 1 1 0 0 128 195.31 kbit/s 0 1 1 1 0 1 256 97.66 kbit/s 0 1 1 1 1 0 512 48.83 kbit/s 0 1 1 1 1 1 1024 24.41 kbit/s 1 0 0 0 0 0 10 2.5 mbit/s 1 0 0 0 0 1 20 1.25 mbit/s 1 0 0 0 1 0 40 625 kbit/s 1 0 0 0 1 1 80 312.5 kbit/s 1 0 0 1 0 0 160 156.25 kbit/s 1 0 0 1 0 1 320 78.13 kbit/s 1 0 0 1 1 0 640 39.06 kbit/s 1 0 0 1 1 1 1280 19.53 kbit/s 1 0 1 0 0 0 12 2.08333 mbit/s 1 0 1 0 0 1 24 1.04167 mbit/s 1 0 1 0 1 0 48 520.83 kbit/s 1 0 1 0 1 1 96 260.42 kbit/s 1 0 1 1 0 0 192 130.21 kbit/s 1 0 1 1 0 1 384 65.10 kbit/s 1 0 1 1 1 0 768 32.55 kbit/s 1 0 1 1 1 1 1536 16.28 kbit/s 1 1 0 0 0 0 14 1.78571 mbit/s 1 1 0 0 0 1 28 892.86 kbit/s 1 1 0 0 1 0 56 446.43 kbit/s table 454. example spi baud rate selection (25 mhz bus clock) (continued) sppr2 sppr1 sppr0 spr2 spr1 spr0 baud rate divisor baud rate
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 332 5.23.3.2.4 spi status register (spisr) read: anytime write: has no effect 1 1 0 0 1 1 112 223.21 kbit/s 1 1 0 1 0 0 224 111.61 kbit/s 1 1 0 1 0 1 448 55.80 kbit/s 1 1 0 1 1 0 896 27.90 kbit/s 1 1 0 1 1 1 1792 13.95 kbit/s 1 1 1 0 0 0 16 1.5625 mbit/s 1 1 1 0 0 1 32 781.25 kbit/s 1 1 1 0 1 0 64 390.63 kbit/s 1 1 1 0 1 1 128 195.31 kbit/s 1 1 1 1 0 0 256 97.66 kbit/s 1 1 1 1 0 1 512 48.83 kbit/s 1 1 1 1 1 0 1024 24.41 kbit/s 1 1 1 1 1 1 2048 12.21 kbit/s table 455. spi status register (spisr) 0x00eb 7 6 5 4 3 2 1 0 r spif 0 sptef modf 0 0 0 0 w reset 0 0 1 0 0 0 0 0 = unimplemented or reserved table 456. spisr field descriptions field description 7 spif spif interrupt flag ? this bit is set after received data has been transfer red into the spi data register. for information about clearing spif flag, refer to table 457 . 0 transfer not yet complete. 1 new data copied to spidr. 5 sptef spi transmit empty interrupt flag ? if set, this bit indicates that the transmi t data register is empty. for information about clearing this bit and placing data into the transmit data register, refer to table 458 . 0 spi data register not empty. 1 spi data register empty. 4 modf mode fault flag ? this bit is set if the ss input becomes low while the spi is conf igured as a master and mode fault detection is enabled, modfen bit of spicr2 register is set. refer to modfen bit description in section 5.23.3.2.2, ?spi control register 2 (spicr2)" ? . the flag is cleared automatically by a read of the spi status register (with modf set) followed by a write to the spi control register 1. 0 mode fault has not occurred. 1 mode fault has occurred. table 454. example spi baud rate selection (25 mhz bus clock) (continued) sppr2 sppr1 sppr0 spr2 spr1 spr0 baud rate divisor baud rate
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 333 5.23.3.2.5 spi data regist er (spidr = spidrh:spidrl) read: anytime; read data only valid when spif is set ? write: anytime table 457. spif interrupt flag clearing sequence xfrw bit spif interrupt flag clearing sequence 0 read spisr with spif == 1 then read spidrl 1 read spisr with spif == 1 then byte read spidrl (270) or byte read spidrh (271) byte read spidrl or word read (spidrh:spidrl) notes 270.data in spidrh is lost, in this case. 271.spidrh can be read repeatedly without any effect on spif. spif flag is cleared only by the read of spidrl after reading spi sr with spif == 1. table 458. sptef interrupt flag clearing sequence xfrw bit sptef interrup t flag clearing sequence 0 read spisr with sptef == 1 then write to spidrl (272) 1 read spisr with sptef == 1 then byte write to spidrl (272) (273) or byte write to spidrh (272) (274) byte write to spidrl (272) or word write to (spidrh:spidrl) (272) notes 272.any write to spidrh or spidrl with sptef == 0 is effectively ignored. 273.data in spidrh is undefined in this case. 274.spidrh can be written repeatedly without any effect on sptef. spt ef flag is cleared only by writing to spidrl after reading spisr with sptef == 1. table 459. spi data register high (spidrh) 0x00ec 7 6 5 4 3 2 1 0 r r15 r14 r13 r12 r11 r10 r9 r8 w t15 t14 t13 t12 t11 t10 t9 t8 reset 0 0 0 0 0 0 0 0 table 460. spi data register low (spidrl) 0x00ed 7 6 5 4 3 2 1 0 r r7 r6 r5 r4 r3 r2 r1 r0 w t7 t6 t5 t4 t3 t2 t1 t0 reset 0 0 0 0 0 0 0 0
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 334 the spi data register is both the input a nd output register for spi data. a write to this register allows data to be queued and transmitted. for an spi configured as a master, queued data is transmitted immediately after the previous transmission has completed. the spi transmitter empty flag spt ef in the spisr register indicates when the spi data register is ready to accept new data. received data in the spidr is valid when spif is set. if spif is cleared and data has been received, the received da ta is transferred from the receive shift register to the spidr and spif is set. if spif is set and not serviced, and a second data value has been received, the second received data is kept as valid data in the receive shift register unt il the start of another transmission. th e data in the spidr does not change. if spif is set and valid data is in the receive shift register , and spif is serviced before t he start of a third transmission, the data in the receive shift register is trans ferred into the spidr and spif remains set (see figure 102 ). if spif is set and valid data is in the receive shift register , and spif is serviced after the start of a third transmission, the data in the receive shift register has become invalid and is not transferred into the spidr (see figure 103 ). figure 102. reception with spif serviced in time figure 103. reception with spif serviced too late receive shift register spif spi data register data a data b data a data a received data b received data c data c spif serviced data c received data b = unspecified = reception in progress receive shift register spif spi data register data a data b data a data a received data b received data c data c spif serviced data c received data b lost = unspecified = reception in progress
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 335 5.23.4 functional description the spi module allows a duplex, synchronous, serial communica tion between the mcu and peripheral devices. software can poll the spi status flags or sp i operation can be interrupt driven. the spi system is enabled by se tting the spi enable (spe) bit in spi control register 1. while spe is set, the four associated spi port pins are dedicated to the spi function as: ? slave select ( ss ) ? serial clock (sck) ? master out/slave in (mosi) ? master in/slave out (miso) the main element of the spi system is the spi data register. the n-bit (275) data register in the master and the n-bit (275) data register in the slave are linked by the mosi and miso pins to form a distributed 2n-bit (275) register. when a data transfer operation is performed, this 2n-bit (275) register is serially shifted n (275) bit positions by the s-clock from the master, so data is exchanged between the master and the slave. data writ ten to the master spi data register beco mes the output data for the slave, and data read from the master spi data register after a transfer operation is the input data from the slave. notes 275.n depends on the selected transfer width, refer to section 5.23.3.2.2, ?spi control register 2 (spicr2)" a read of spisr with sptef = 1 followed by a write to spidr, puts data into the transmit data register. when a transfer is complete and spif is cleared, received data is moved into the receive data register. this data register acts as the spi receive data register for reads and as the spi trans mit data register for writes. a common spi da ta register address is shared for read ing data from the read data buffer and for writing data to the transmit data register. the clock phase control bit (cpha) and a clock polarity control bi t (cpol) in the spi control regi ster 1 (spicr1) select one of four possible clock formats to be used by the spi system. the cpol bit simply select s a non-inverted or inverted clock. the cpha bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered sck edges or on even numbered sck edges (see section 5.23.4.3, ?transmission formats" ). the spi can be configured to operate as a master or as a slave. when the mstr bit in spi control register1 is set, master mode is selected, when the mstr bit is clear, slave mode is selected. note a change of cpol or mstr bit while there is a received byte pending in the receive shift register will destroy the received byte and must be avoided. 5.23.4.1 master mode the spi operates in master mode when the ms tr bit is set. only a master spi module can initiate transmissions. a transmission begins by writing to the master spi data regi ster. if the shift register is empty, da ta immediately transfers to the shift regi ster. data begins shifting out on the mosi pin under the control of the serial clock. ? serial clock the spr2, spr1, and spr0 baud rate selection bits, in conjunction with the sppr2, sppr1, and sppr0 baud rate preselection bits in the spi baud rate register, control the baud rate generator and determine the speed of the transmission. the sck pin is the spi clock output. through the sck pin, the baud rate generator of the master controls the shift register of the slave peripheral. ? mosi, miso pin in master mode, the function of the serial data output pin (mosi) and the serial data input pin (miso) is determined by the spc0 and bidiroe control bits. ? ss pin if modfen and ssoe are set, the ss pin is configured as slave select output. the ss output becomes low during each transmission and is high when the spi is in idle state. if modfen is set and ssoe is cleared, the ss pin is configured as input for det ecting mode fault error. if the ss input becomes low, this indicates a mode fault error where another ma ster tries to drive the mosi and sck lines. in this case, the spi immediately switches to slave m ode, by clearing the mstr bit and also disables the slave output buffer miso (or siso in bidirectional mode ). the result is that all outputs are disabl ed and sck, mosi, and miso are inputs. if a transmission is in progress when the mode fault occurs, the tran smission is aborted and the spi is forced into idle state.
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 336 this mode fault error also sets the mode fault (modf) flag in the spi status register (spisr ). if the spi interrupt enable bit (spie) is set when the modf flag becomes set, then an spi interrupt sequence is also requested. when a write to the spi data register in the master occurs, there is a half sck-cycl e delay. after the delay, sck is started within the master. the rest of the transfer operation differs slightly, depending on the clock fo rmat specified by the spi clock phase bit, cpha, in spi control register 1 (see section 5.23.4.3, ?transmission formats" ) . note a change of the bits cpol, cpha, ssoe, lsbfe, xfrw, modfen, spc0, or bidiroe with spc0 set, sppr2-sppr0, and spr2-spr0 in master mode, will abort a transmission in progress and force the spi into idle state. the remote slave cannot detect this, therefore the master must ensure that the remote slave is returned to idle state. 5.23.4.2 slave mode the spi operates in slave mode when the mstr bit in spi control register 1 is clear. ? serial clock in slave mode, sck is the spi clock input from the master. ? miso, mosi pins in slave mode, the function of the se rial data output pin (miso) and serial data input pin (mosi) is determined by the spc0 bit and bidiroe bit in spi control register 2. ? ss pin the ss pin is the slave select input. before a data transmission occurs, the ss pin of the slave spi must be low. ss must remain low until the transmission is complete. if ss goes high, the spi is forced into idle state. the ss input also controls the se rial data output pin. if ss is high (not selected), t he serial data output pin is high impedance, and, if ss is low, the first bit in the spi data register is driven out of the serial data output pin. also, if the slave is not selected ( ss is high), then the sck input is ignored and no in ternal shifting of the spi shift register occurs. although the spi is capable of duplex operation, some spi per ipherals are capable of only receiving spi data in a slave mode. for these simpler devices, there is no serial data out pin. note when peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the sa me system slave?s serial data output line. as long as no more than one slave device driv es the system slave?s serial data output lin e, it is possible for several slaves t o receive the same transmission from a master , although the master would not receive retu rn information from all of the receiving slaves. if the cpha bit in spi control register 1 is clear, odd numbered edges on the sck in put cause the data at the serial data input pin to be latched. even numbered edges cause the value previously latched from the serial data input pin to shift into the lsb or msb of the spi shift register, depending on the lsbfe bit. if the cpha bit is set, even numbered edges on the sck input ca use the data at the serial data input pin to be latched. odd numbered edges cause the value previously latched from the serial data input pin to shift into the lsb or msb of the spi shift register, depending on the lsbfe bit. when cpha is set, the first edge is used to get the first data bi t onto the serial data output pin. when cpha is clear and the ss input is low (slave selected), the first bit of the spi dat a is driven out of the serial data output pin. after the nth (276) shift, the transfer is considered complete and the received data is transferred into the spi data register. to indicate transfer is complete, the s pif flag in the spi status register is set. notes 276.n depends on the selected transfer width, refer to section 5.23.3.2.2, ?spi control register 2 (spicr2)" note a change of the bits cpol, cpha, ssoe, lsbfe, modfen, spc0, or bidiroe with spc0 set in slave mode, will corrupt a transmission in progress and must be avoided.
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 337 5.23.4.3 transmission formats during an spi transmission, data is transmi tted (shifted out serially) and received (shifted in serially) simultaneously. the s erial clock (sck) synchronizes shif ting and sampling of the information on the two serial data lines. a slave select line allows sele ction of an individual slave spi device; slave devices that are no t selected do not interfere with spi bus activities. optionally, on a master spi device, the slave sele ct line can be used to indicate multiple-master bus contention. figure 104. master/slave transfer block diagram 5.23.4.3.1 clock phase and polarity controls using two bits in the spi control register 1, software select s one of four combinations of serial clock phase and polarity. the cpol clock polarity control bi t specifies an active high or low clock and has no significant effect on the transmission for mat. the cpha clock phase control bit selects one of tw o fundamentally different transmission formats. clock phase and polarity should be identical for the master spi dev ice and the communicating slave device. in some cases, the phase and polarity are changed between transmissions to allow a ma ster device to communicate with peripheral slaves having different requirements. 5.23.4.3.2 cpha = 0 transfer format the first edge on the sck line is used to clock the first data bi t of the slave into the master and the first data bit of the m aster into the slave. in some peripherals, the first bit of the slave?s data is available at the slave?s dat a out pin as soon as the slave is selected. in this format, the first sc k edge is issued a half cycle after ss has become low. a half sck cycle later, the second edge appears on the sck line. when this second edge occurs, the value previously latched from the serial data input pin is shifted into the l sb or msb of the shift register, depending on lsbfe bit. after this second edge, the next bit of the spi master data is tr ansmitted out of the serial data output pin of the master to t he serial input pin on the slave. this process continues for a total of 16 edges on the sck line, with data being latched on odd numbered edges and shifted on even numbered edges. data reception is double buffered. data is shifted serially in to the spi shift register during the transfer and is transferred to the parallel spi data register after the last bit is shifted in. after 2n (277) (last) sck edges: ? data that was previously in the master spi data register should now be in t he slave data register and the data that was in the slave data register should be in the master. ? the spif flag in the spi status register is set, indicating that the transfer is complete. notes 277.n depends on the selected transfer width, refer to section 5.23.3.2.2, ?spi control register 2 (spicr2)" figure 105 is a timing diagram of an spi transfer where cpha = 0. sck waveforms are shown for cpol = 0 and cpol = 1. the diagram may be interpreted as a master or slave timing diagram because the sck, miso , and mosi pins are connected directly between the master and the slave. the miso signal is the output from the slave and the mosi signal is the output from the master. the ss pin of the master must be either high or reconfig ured as a general purpose output not affecting the spi. shift register shift register baud rate generator master spi slave spi mosi mosi miso miso sck sck ss ss v dd
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 338 figure 105. spi clock format 0 (cp ha = 0), with 8-bit transfer width selected (xfrw = 0) t l begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb first (lsbfe = 0): lsb first (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 change o sel ss (i) mosi pin miso pin master only mosi/miso t t if next transfer begins here for t t , t l , t l minimum 1/2 sck t i t l t l = minimum leading time before the first sck edge t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time) t l , t t , and t i are guaranteed for the master mode and required for the slave mode. 1 2 34 56 78910111213141516 sck edge number end of idle state begin of idle state
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 339 figure 106. spi clock format 0 (cpha = 0), with 16-bit transfer width selected (xfrw = 1) in slave mode, if the ss line is not deasserted between the successive transmi ssions, then the content of the spi data register is not transmitted; inst ead the last received data is transmitted. if the ss line is deasserted for at least minimum idle time (half sck cycle) between successive transmissions, then the content of the spi data r egister is transmitted. in master mode, with slave select output enabled, the ss line is always deasserted and reasse rted between successive transfers for at least minimum idle time. 5.23.4.3.3 cpha = 1 transfer format some peripherals require the first sck edge before the first da ta bit becomes available at the data out pin, the second edge clocks data into the system. in this format , the first sck edge is issued by setting the cpha bit at the beginning of the n (278) -cycle transfer operation. notes 278.n depends on the selected transfer width, refer to section 5.23.3.2.2, ?spi control register 2 (spicr2)" the first edge of sck occurs immediately after the half sck clock cycle synchronization delay. this first edge commands the slave to transfer its first data bit to the serial data input pin of the master. a half sck cycle later, the second edge appears on the sck pin. this is the latching edge for both the master and slave. when the third edge occurs, the value previous ly latched from the serial data input pin is shifted into the lsb or msb of the s pi shift register, depending on lsbfe bit. after this edge, the next bit of the master data is coupled out of the serial data outp ut pin of the master to the serial input pin on the slave. this process continues for a total of n 4 edges on the sck line with data being latched on even numbered edges and shifting taking place on odd numbered edges. t l begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb first (lsbfe = 0) lsb first (lsbfe = 1) msb lsb lsb msb bit 13 bit 2 bit 14 bit 1 bit 12 bit 3 bit 11 bit 4 bit 5 change o sel ss (i) mosi pin miso pin master only mosi/miso t t if next transfer begins here for t t , t l , t l minimum 1/2 sck t i t l t l = minimum leading time before the first sck edge t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time) t l , t t , and t i are guaranteed for the master mode and required for the slave mode. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sck edge number end of idle state begin of idle state 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 bit 10 bit 9 bit 8 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 6 bit 5 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12bit 13 bit 14
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 340 data reception is double buffered, data is serially shifted in to the spi shift register durin g the transfer and is transferred to the parallel spi data register after the last bit is shifted in. after 2n 4 sck edges: ? data that was previously in the spi data register of the master is now in the data register of the slave, and data that was in the data register of the slave is in the master. ? the spif flag bit in spisr is set indi cating that the transfer is complete. figure 107 shows two clocking variations for cpha = 1. the diagram may be interpreted as a master or slave timing diagram, because the sck, miso, and mosi pins are connected directly between the master and th e slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the ss pin of the master must be either high or reconfigured as a general purpose output not affecting the spi. figure 107. spi clock format 1 (cpha = 1), with 8-bit transfer width selected (xfrw = 0) t l t t for t t , t l , t l minimum 1/2 sck t i t l if next transfer begins here begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb first (lsbfe = 0): lsb first (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 change o sel ss (i) mosi pin miso pin master only mosi/miso t l = minimum leading time before the first sck edge, not required for back-to-back transfers t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time), not required for back-to-back transfers 1 2 34 56 78910111213141516 sck edge number end of idle state begin of idle state
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 341 figure 108. spi clock format 1 (cpha = 1), with 16-bit transfer width selected (xfrw = 1) the ss line can remain active low between successive transfers (can be tied low at all times). this format is sometimes preferred in systems having a single fix ed master and a single slave th at drive the miso data line. ? back-to-back transf ers in master mode in master mode, if a transmission has completed and new data is available in the spi data register, this data is sent out immediately without a trailing and minimum idle time. the spi interrupt request flag ( spif) is common to both the master and slave modes. spif gets set one half sck cycle after the last sck edge. 5.23.4.4 spi baud rate generation baud rate generation consists of a series of divider stages. si x bits in the spi baud rate register (sppr2, sppr1, sppr0, spr2, spr1, and spr0) determine the divisor to the spi module clock which results in the spi baud rate. the spi clock rate is determin ed by the product of the value in the baud rate pres election bits (sppr2? sppr0) and the value in the baud rate selection bits (spr2?spr0). the module clock divisor equation is shown in equation 6 . baudratedivisor = (sppr + 1) ? 2 (spr + 1) eqn. 6 when all bits are clear (the default condit ion), the spi module clock is divided by 2. when the selection bits (spr2?spr0) are 001 and the presel ection bits (sppr2?sppr0) ar e 000, the module clock divisor becomes 4. when the selection bits are 010, the module clock divisor becomes 8, etc. when the preselection bits are 001, the divi sor determined by the selection bits is mu ltiplied by 2. when the preselection bits are 010, the divisor is multiplied by 3, etc. see table 454 for baud rate calculations for all bit conditions, based on a 25 mhz bus clock. the two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc. t l begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb first (lsbfe = 0) lsb first (lsbfe = 1) msb lsb lsb msb bit 13 bit 2 bit 14 bit 1 bit 12 bit 3 bit 11 bit 4 bit 5 change o sel ss (i) mosi pin miso pin master only mosi/miso t t if next transfer begins here for t t , t l , t l minimum 1/2 sck t i t l t l = minimum leading time before the first sc k edge, not required for back-to-back transfers t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time), not required for back-to-back transfers 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sck edge number end of idle state begin of idle state 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 bit 10 bit 9 bit 8 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 6 bit 5 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12bit 13 bit 14
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 342 the baud rate generator is activated only wh en the spi is in master mode and a serial transfer is taking place. in the other ca ses, the divider is disabled to decrease i dd current. note for maximum allowed baud rates, refer to section 4.6.2.5, ?spi timing" of this data sheet. 5.23.4.5 special features 5.23.4.5.1 ss output the ss output feature automatically drives the ss pin low during transmission, to select external devices and drives it high during idle to deselect exte rnal devices. when ss output is selected, the ss output pin is connected to the ss input pin of the external device. the ss output is available only in master mode during normal spi operation by asserting ssoe and modfen bit as shown in table 448 . the mode fault feature is disabled while ss output is enabled. note care must be taken when using the ss output feature in a mult imaster system because the mode fault feature is not available for detecting system errors between masters. 5.23.4.5.2 bidirectional mode (momi or siso) the bidirectional mode is selected when the spc0 bit is set in spi control register 2 (see table 461 ). in this mode, the spi uses only one serial data pin for the interface with external device(s) . the mstr bit decides which pin to use. the mosi pin becomes the serial data i/o (momi) pin for the master mode, and the mi so pin becomes serial data i/o (siso) pin for the slave mode. the miso pin in master mode and mosi pi n in slave mode are not used by the spi. the direction of each serial i/o pin depends on the bidiroe bit. if the pin is configured as an output, serial data from the sh ift register is driven out on the pi n. the same pin is also the serial input to the shift register. ? the sck is output for the master mode and input for the slave mode. ?the ss is the input or output for the master mode, and it is always the input for the slave mode. ? the bidirectional mode does not affect sck and ss functions. table 461. normal mode and bidirectional mode when spe = 1 master mode mstr = 1 slave mode mstr = 0 normal mode spc0 = 0 bidirectional mode spc0 = 1 spi mosi miso serial out serial in spi mosi miso serial in serial out spi momi serial out serial in bidiroe spi siso serial in serial out bidiroe
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 343 note in bidirectional master mode, with mode f ault enabled, both data pins miso and mosi can be occupied by the spi, though mosi is normally used for transmissions in bidirectional mode and miso is not used by the spi. if a mode fault occu rs, the spi is automatically switched to slave mode. in this case, miso becomes occupied by t he spi and mosi is not used. this must be considered, if the miso pin is used for another purpose. 5.23.4.6 error conditions the spi has one error condition: mode fault error 5.23.4.6.1 mode fault error if the ss input becomes low while the spi is configured as a master , it indicates a system error where more than one master may be trying to drive the mosi and sck lines simultaneously. this cond ition is not permitted in normal operation, the modf bit in the spi status register is set automati cally, provided the modfen bit is set. in the special case where the spi is in master mode and modfen bit is cleared, the ss pin is not used by the spi. in this special case, the mode fault error function is inhibited and modf remains cl eared. in case the spi system is configured as a slave, the ss pin is a dedicated input pin. mode fault error doesn?t occur in slave mode. if a mode fault error occurs, the spi is s witched to slave mode, with the exception that the slave outp ut buffer is disabled. s o sck, miso, and mosi pins are forced to be high-impedance inputs to avoid any possibility of co nflict with anot her output driver . a transmission in progress is aborted and the spi is forced into idle state. if the mode fault error occurs in the bidirectional mode for a spi system configured in master m ode, output enabl e of the momi (mosi in bidirectional mode) is cleared if it was set. no mode fault error occurs in the bidirectional mode for spi system configured in slave mode. the mode fault flag is cleared automatically by a read of the spi status register (with modf set) followed by a write to spi co ntrol register 1. if the mode fault flag is cleared, the spi becomes a normal master or slave again. note if a mode fault error occurs and a received data byte is pending in the receive shift register, this data byte will be lost. 5.23.4.7 low power mode options 5.23.4.7.1 spi in run mode in run mode with th e spi system enable (spe) bit in t he spi control register clear, the spi system is in a low-power, disabled state. spi registers remain acce ssible, but clocks to the core of this module are disabled. 5.23.4.7.2 spi in wait mode spi operation in wait mode depends upon the state of the spiswai bit in spi control register 2. ? if spiswai is clear, the spi operates normally when the cpu is in wait mode ? if spiswai is set, spi clock generation ceases and the spi module enters a power conservation state when the cpu is in wait mode. ? if spiswai is set and the spi is configured for master, any transmission and reception in progress stops at wait mode entry. the transmission and receptio n resumes when the spi exits wait mode. ? if spiswai is set and the spi is confi gured as a slave, any transmission and reception in progress continues if the sck continues to be driven from the master. this ke eps the slave synchronized to the master and the sck. ? if the master transmits several bytes while the slave is in wait mode, the slave will continue to send out bytes consistent with the operation m ode at the start of wait mode (i.e., if th e slave is currently sending its spidr to the master, it will continue to send the same byte. else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte).
mcu - serial peripheral interface (s12spiv5) mm912_637, rev. 3.0 freescale semiconductor 344 note care must be taken when expecting data from a master while the slave is in wait or stop mode. even though the shift register will continue to operate, t he rest of the spi is shut down (i.e., a spif interrupt will not be generated until exiting stop or wait mode). also, the byte from the shift register will not be copied into the spidr register until after the slave spi has exited wait or stop mode. in slave mode, a rece ived byte pending in the receive shift register will be lost when entering wait or stop mode. an spif flag and spidr copy is generated only if wait mode is entered or exited during a trans mission. if the slave enters wait mode in idle mode and exits wait mode in idle mode, neither a spif nor a spidr copy will occur. 5.23.4.7.3 spi in stop mode stop mode is dependent on the system. the spi enters stop mode when the module clock is disabled (held high or low). if the spi is in master mode and exchanging data when the cpu enters stop mode, the transmission is fr ozen until the cpu exits stop mode. after stop, data to and from the external spi is exc hanged correctly. in slave mode, the spi will stay synchronized with the master. the stop mode is not dependent on the spiswai bit. 5.23.4.7.4 reset the reset values of registers and signals are described in section 5.23.3, ?memory map and register definition" , which details the registers and their bit fields. ? if a data transmission occurs in slave mode after reset without a write to spidr, it will transmit garbage, or the data last received from the master before the reset. ? reading from the spidr after reset will always read zeros. 5.23.4.7.5 interrupts the spi only originates interrupt requests when the spi is enabled (spe bit in spicr1 set). the fo llowing is a description of h ow the spi makes a request and how the mcu should acknowledge that request. the interrupt vector offset and interrupt priority are chip dependent. the interrupt flags modf, spif, and sptef are lo gically ored to generate an interrupt request. 5.23.4.7.5.1 modf modf occurs when the master detects an error on the ss pin. the master spi must be co nfigured for the modf feature (see table 448 ). after modf is set, the current transfer is aborted a nd the following bit is changed: ms tr = 0, the master bit in spicr1 resets. the modf interrupt is refl ected in the status register modf flag. clearing the flag will also clear the interrupt. this interru pt will stay active while the modf flag is set. modf has an automatic clearing proce ss which is described in section 5.23.3.2.4, ?spi status register (spisr)" . 5.23.4.7.5.2 spif spif occurs when new data has been received and copied to the spi data register. after spif is set, it does not clear until it is serviced. spif has an automatic cleari ng process, which is described in section 5.23.3.2.4, ?spi status register (spisr)" . 5.23.4.7.5.3 sptef sptef occurs when the spi data register is ready to accept new data. after sptef is set, it d oes not clear until it is serviced . sptef has an automatic clearing pr ocess, which is described in section 5.23.3.2.4, ?spi status register (spisr)" .
128 kbyte flash module (s12ftmrc128k1v1) mm912_637, rev. 3.0 freescale semiconductor 345 5.24 128 kbyte flash module (s12ftmrc128k1v1) 5.24.1 introduction the ftmrc128k1 module implements the following: ? 128 kbytes of p-flash (program flash) memory ?4.0 kbytes of d-flash (data flash) memory the flash memory is ideal for single-supply applications allowin g for field reprogramming without requiring external high volta ge sources for program or erase operations. the flash module incl udes a memory controller that ex ecutes commands to modify flash memory contents. the user interface to the memory co ntroller consists of the indexed flash common command object (fccob) register which is written to with the command, global address, data, and any required command parameters. the memory controller must complete the exec ution of a command before the fccob regist er can be written to with a new command. caution a flash word or phrase must be in the eras ed state before being programmed. cumulative programming of bits within a flash word or phrase is not allowed. the flash memory may be read as bytes, aligned words, or misaligned words. read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. for flash memory, an erased bit reads 1 and a programmed bit reads 0. it is possible to read from p-flash memory while some comm ands are executing on d-flash memory. it is not possible to read from d-flash memory while a command is executing on p-fl ash memory. simultaneous p-flash and d-flash operations are discussed in section 5.24.4.4, ?allowed simultaneous p-flash and d-flash operations" . both p-flash and d-flash memories are im plemented with error correction codes (ecc) t hat can resolve single bit faults and detect double bit faults. for p-flash memory, the ecc implementa tion requires that programming be done on an aligned 8-byte basis (a flash phrase). since p-flash memory is always read by half-phrase, only one single bit fault in an aligned 4-byte half-phrase containing the byte or word accessed will be corrected. 5.24.1.1 glossary command write sequence ? an mcu instruction sequence to execute built-i n algorithms (including program and erase) on the flash memory. d-flash memory ? the d-flash memory constitutes the nonvolatile memory store for data. d-flash sector ? the d-flash sector is the smallest portion of the d-flash memory that can be erased. the d-flash sector consists of four 64-byte rows for a total of 256-bytes. nvm command mode ? an nvm mode using the cpu to setup the fccob register to pass parameters required for flash command execution. phrase ? an aligned group of four 16-bit words within the p-flash memory. each phrase includes two sets of aligned double words with each set, including 7 ecc bits for single bit fault correction and double bit fault detection within each double wor d. p-flash memory ? the p-flash memory constitu tes the main nonvolatile memo ry store for applications. p-flash sector ? the p-flash sector is the smallest portion of the p- flash memory that can be erased. each p-flash sector contains 512-bytes. program ifr ? nonvolatile information register located in the p-flash block that contains the device id, version id, and the program once field. analog mcu
128 kbyte flash module (s12ftmrc128k1v1) mm912_637, rev. 3.0 freescale semiconductor 346 5.24.1.2 features 5.24.1.2.1 p-flash features ? 128 kbytes of p-flash memory composed of one 128 kbyte flash block divided into 256 sectors of 512-bytes ? single bit fault correction and double bit fault detect ion within a 32-bit double wo rd during read operations ? automated program and erase algorithm with verify and generation of ecc parity bits ? fast sector erase and phrase program operation ? ability to read the p-flash memory while programming a word in the d-flash memory ? flexible protection scheme to prevent accide ntal program or erase of p-flash memory 5.24.1.2.2 d-flash features ?4.0 kbytes of d-flash memory composed of one 4.0 kbyte flash block divided into 16 sectors of 256-bytes ? single bit fault correction and double bit fault detection within a word during read operations ? automated program and erase algorithm with verify and generation of ecc parity bits ? fast sector erase and word program operation ? protection scheme to prevent accidental program or erase of d-flash memory ? ability to program up to four words in a burst sequence 5.24.1.2.3 other fl ash module features ? no external high-voltage power supply required for flash memory program and erase operations ? interrupt generation on flash command completion and flash error detection ? security mechanism to prevent unaut horized access to the flash memory 5.24.1.3 block diagram the block diagram of the flash module is shown in figure 109 . figure 109. ftmrc128k1 block diagram bus clock divider clock command interrupt request fclk protection security registers flash interface 16-bit internal bus sector 0 sector 1 sector 255 32kx39 p-flash error interrupt request cpu d-flash 2kx22 sector 0 sector 1 sector 15 scratch ram 384x16 memory controller
128 kbyte flash module (s12ftmrc128k1v1) mm912_637, rev. 3.0 freescale semiconductor 347 5.24.2 external signal description the flash module contains no signals that connect off-chip. 5.24.3 memory map and registers this section describes the memory map and registers for the fl ash module. read data from unimplemented memory space in the flash module is undefined. write access to unimplemented or reserved memory space in the flash module will be ignored by the flash module. 5.24.3.1 module memory map the s12 architecture places the p-flash memory betw een global addresses 0x2_0000 and 0x3_ffff, as shown in table 462 .the p-flash memory map is shown in figure 110 . the fprot register, described in section 5.24.3.2.9, ?p-flash prot ection register (fprot)" , can be set to protect regions in the flash memory from accidental program or erase. three se parate memory regions, one growing upward from global address 0x3_8000 in the flash memory (called the lower region), one gr owing downward from global address 0x3_ffff in the flash memory (called the higher region), and the remaining addresses in the flash memory, can be activated for protection . the flash memory addresses covered by these protec table regions are shown in the p-flash memory map. the higher address region is mainly targeted to hold the boot loader code since it covers the vector space. default protection settings as well as security information that allows the mcu to restrict access to the flas h module are stored in the flash configuration field as described in table 463 . table 462. p-flash memory addressing global address size (bytes) description 0x2_0000 ? 0x3_ffff 128 k p-flash block contains fl ash configuration field (see table 463 ) table 463. flash configuration field global address size (bytes) description 0x3_ff00-0x3_ff07 8 backdoor comparison key refer to section 5.24.4.5.11, ?verify backdoor access key command" , and section 5.24.5.1, ?unsecuring the mcu using backdoor key access" . 0x3_ff08-0x3_ff0b (279) 4 reserved 0x3_ff0c (279) 1 p-flash protection byte . refer to section 5.24.3.2.9, ?p-flash protection register (fprot)" . 0x3_ff0d (279) 1 d-flash protection byte . refer to section 5.24.3.2.10, ?d-flash protection register (dfprot)" . 0x3_ff0e (279) 1 flash nonvolatile byte refer to section 5.24.3.2.16, ?flash option register (fopt)" . 0x3_ff0f (279) 1 flash security byte refer to section 5.24.3.2.2, ?flash security register (fsec)" . notes 279.0x3ff08-0x3_ff0f form a flash phrase and must be programmed in a single command write sequence. each byte in the 0x3_ff08 - 0x3_ff0b reserved field should be programmed to 0xff.
128 kbyte flash module (s12ftmrc128k1v1) mm912_637, rev. 3.0 freescale semiconductor 348 figure 110. p-flash memory map table 464. program ifr fields global address size (bytes) field description 0x0_4000 ? 0x0_4007 8 reserved 0x0_4008 ? 0x0_40b5 174 reserved 0x0_40b6 ? 0x0_40b7 2 version id (280) 0x0_40b8 ? 0x0_40bf 8 reserved 0x0_40c0 ? 0x0_40ff 64 program once field. refer to section 5.24.4.5.6, ?program once command" . notes 280.used to track firmware patch versions, see section 5.24.4.2, ?ifr version id word" . flash configuration field 0x3_c000 flash protected/unprotected lower region 1.0, 2.0, 4.0, 8.0 kbytes 0x3_8000 0x3_9000 0x3_8400 0x3_8800 0x3_a000 p-flash end = 0x3_ffff 0x3_f800 0x3_f000 0x3_e000 flash protected/unprotected higher region 2.0, 4.0, 8.0, 16 kbytes flash protected/unprotected region 8.0 kbytes (up to 29 kbytes) 16 bytes (0x3_ff00 - 0x3_ff0f) flash protected/unprotected region 96 kbytes p-flash start = 0x2_0000 protection protection protection movable end fixed end fixed end
128 kbyte flash module (s12ftmrc128k1v1) mm912_637, rev. 3.0 freescale semiconductor 349 figure 111. d-flash and memory controller resource memory map 5.24.3.2 register descriptions the flash module contains a set of 20 control and status regist ers located between 0x0100 and 0x 0113. a summary of the flash module registers is given in ta b l e 466 with detailed descriptions in the following subsections. caution writes to any flash register must be avoided while a flash command is active (ccif=0) to prevent corruption of flash register contents and adversely affect memory controller behavior. table 465. d-flash and memory controller resource fields global address size (bytes) description 0x0_4000 ? 0x0_43ff 1,024 reserved 0x0_4400 ? 0x0_53ff 4,096 d-flash memory 0x0_5400 ? 0x0_57ff 1,024 reserved 0x0_5800 ? 0x0_5aff 768 memory controller scratch ram (ramon (281) = 1) 0x0_5b00 ? 0x0_5fff 1,280 reserved 0x0_6000 ? 0x0_67ff 2,048 reserved 0x0_6800 ? 0x0_7fff 6,144 reserved notes 281.mmcctl1 register bit d-flash memory 4.0 kbytes d-flash start = 0x0_4400 0x0_6000 d-flash end = 0x0_53ff p-flash ifr 1.0 kbyte 0x0_4000 reserved 1.0 kbyte scratch ram 768 bytes (ramon) ram end = 0x0_5aff ram start = 0x0_5800 reserved 6.0 kbytes reserved 2.0 kbytes reserved 1280 bytes 0x0_6800 0x0_7fff 0x0_40ff
128 kbyte flash module (s12ftmrc128k1v1) mm912_637, rev. 3.0 freescale semiconductor 350 table 466. ftmrc128k1 register summary address & name 7 6 5 4 3 2 1 0 0x0100 fclkdiv r fdivld fdivlck fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 w 0x0101 fsec r keyen1 keyen0 rnv5 rnv4 rnv3 rnv2 sec1 sec0 w 0x0102 fccobix r 0 0 0 0 0 ccobix2 ccobix1 ccobix0 w 0x0103 frsv0 r 0 0 0 0 0 0 0 0 w 0x0104 fcnfg r ccie 0 0 ignsf 0 0 fdfd fsfd w 0x0105 fercnfg r 0 0 0 0 0 0 dfdie sfdie w 0x0106 fstat r ccif 0 accerr fpviol mgbusy rsvd mgstat1 mgstat0 w 0x0107 ferstat r 0 0 0 0 0 0 dfdif sfdif w 0x0108 fprot r fpopen rnv6 fphdis fphs1 fphs0 fpldis fpls1 fpls0 w 0x0109 dfprot r dpopen 0 0 0 dps3 dps2 dps1 dps0 w 0x010a fccobhi r ccob15 ccob14 ccob13 ccob12 ccob11 ccob10 ccob9 ccob8 w 0x010b fccoblo r ccob7 ccob6 ccob5 ccob4 ccob3 ccob2 ccob1 ccob0 w 0x010c frsv1 r 0 0 0 0 0 0 0 0 w 0x010d frsv2 r 0 0 0 0 0 0 0 0 w 0x010e frsv3 r 0 0 0 0 0 0 0 0 w 0x010f frsv4 r 0 0 0 0 0 0 0 0 w 0x0110 fopt r nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 w 0x0111 frsv5 r 0 0 0 0 0 0 0 0 w 0x0112 frsv6 r 0 0 0 0 0 0 0 0 w 0x01103 frsv7 r 0 0 0 0 0 0 0 0 w = unimplemented or reserved
128 kbyte flash module (s12ftmrc128k1v1) mm912_637, rev. 3.0 freescale semiconductor 351 5.24.3.2.1 flash clock divi der register (fclkdiv) the fclkdiv register is used to control ti med events in program and erase algorithms. all bits in the fclkdiv register are readabl e, bit 7 is not writable, bit 6 is write- once-hi and controls the writability of th e fdiv field. caution the fclkdiv register must never be writte n to while a flash command is executing (ccif=0). the fclkdiv register is writable during the flash reset sequence even though ccif is clear. table 467. flash clock divi der register (fclkdiv) address: 0x0100 7 6 5 4 3 2 1 0 r fdivld fdivlck fdiv[5:0] w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 468. fclkdiv field descriptions field description 7 fdivld clock divider loaded 0 fclkdiv register has not been written since the last reset 1 fclkdiv register has been written since the last reset 6 fdivlck clock divider locked 0 fdiv field is open for writing 1 fdiv value is locked and cannot be changed. once the lock bit is set high, only reset can clear this bit and restore writabili ty to the fdiv field. 5?0 fdiv[5:0] clock divider bits ? fdiv[5:0] must be set to effectively divide busclk down to 1.0 mhz to control timed events during flash program and erase algorithms. table 469 shows recommended values for fdiv[5:0] based on the busclk frequency. refer to section 5.24.4.3, ?flash command operations" , for more information.
128 kbyte flash module (s12ftmrc128k1v1) mm912_637, rev. 3.0 freescale semiconductor 352 5.24.3.2.2 flash securi ty register (fsec) the fsec register holds all bits associated wi th the security of the mcu and flash module. all bits in the fsec register are readable, but not writable. during the reset sequence, the fsec register is loaded with the contents of the flash security byte in the flash configuration field at global address 0x3_ff0f located in p-flash memory (see ta b l e 463 ), as indicated by reset condition f in figure 470 . if a double bit fault is detected, while reading the p-flash phrase containing the flash security byte during the reset sequence, all bits in the fsec register will be set to leave the flash module in a secured state with backdoor key access disabled. table 469. fdiv values for various busclk frequencies busclk frequency (mhz) fdiv[5:0] busclk frequency (mhz) fdiv[5:0] min (282) max (283) min (282) max (283) 1.0 1.6 0x00 16.6 17.6 0x10 1.6 2.6 0x01 17.6 18.6 0x11 2.6 3.6 0x02 18.6 19.6 0x12 3.6 4.6 0x03 19.6 20.6 0x13 4.6 5.6 0x04 20.6 21.6 0x14 5.6 6.6 0x05 21.6 22.6 0x15 6.6 7.6 0x06 22.6 23.6 0x16 7.6 8.6 0x07 23.6 24.6 0x17 8.6 9.6 0x08 24.6 25.6 0x18 9.6 10.6 0x09 25.6 26.6 0x19 10.6 11.6 0x0a 26.6 27.6 0x1a 11.6 12.6 0x0b 27.6 28.6 0x1b 12.6 13.6 0x0c 28.6 29.6 0x1c 13.6 14.6 0x0d 29.6 30.6 0x1d 14.6 15.6 0x0e 30.6 31.6 0x1e 15.6 16.6 0x0f 31.6 32.6 0x1f notes 282.busclk is greater than this value. 283.busclk is less than or equal to this value. table 470. flash security register (fsec) address: 0x0101 7 6 5 4 3 2 1 0 r keyen[1:0] rnv[5:2] sec[1:0] w reset f f f f f f f f = unimplemented or reserved
128 kbyte flash module (s12ftmrc128k1v1) mm912_637, rev. 3.0 freescale semiconductor 353 the security function in the flash module is described in section 5.24.5, ?security" . 5.24.3.2.3 flash ccob inde x register (fccobix) the fccobix register is used to index the fccob register for flash memory operations. ccobix bits are readable and writable while remaining bits read 0 and are not writable. table 471. fsec field descriptions field description 7?6 keyen[1:0] backdoor key security enable bits ? the keyen[1:0] bits define the enabling of backdoor key access to the flash module as shown in table 472 . 5?2 rnv[5:2} reserved nonvolatile bits ? the rnv bits should remain in the erased state for future enhancements. 1?0 sec[1:0] flash security bits ? the sec[1:0] bits define the security state of the mcu as shown in table 473 . if the flash module is unsecured using backdoor key access , the sec bits are forced to 10. table 472. flash keyen states keyen[1:0] status of backdoor key access 00 disabled 01 disabled (284) 10 enabled 11 disabled notes 284.preferred keyen state to disable backdoor key access. table 473. flash security states sec[1:0] status of security 00 secured 01 secured (285) 10 unsecured 11 secured notes 285.preferred sec state to set mcu to secured state. table 474. fccob index register (fccobix) address: 0x0102 7 6 5 4 3 2 1 0 r 0 0 0 0 0 ccobix[2:0] w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 475. fccobix field descriptions field description 2?0 ccobix[1:0] common command register index ? the ccobix bits are used to select to which word of the fccob register array is being read or written. see section 5.24.3.2.11, ?flash common command object register (fccob)" for more details.
128 kbyte flash module (s12ftmrc128k1v1) mm912_637, rev. 3.0 freescale semiconductor 354 5.24.3.2.4 flash reserved0 register (frsv0) this flash register is re served for factory testing. all bits in the frsv0 register read 0 and are not writable. 5.24.3.2.5 flash configur ation register (fcnfg) the fcnfg register enables the flash command complete interrupt and forces ecc faults on flash array read access from the cpu. ccie, ignsf, fdfd, and fsfd bits are readable and writ able while remaining bits read 0 and are not writable. table 476. flash reserved0 register (frsv0) address: 0x0103 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 477. flash configuration register (fcnfg) address: 0x0104 7 6 5 4 3 2 1 0 r ccie 0 0 ignsf 0 0 fdfd fsfd w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 478. fcnfg field descriptions field description 7 ccie command complete interrupt enable ? the ccie bit controls interrupt generation when a flash command has completed. 0 command complete interrupt disabled 1 an interrupt will be requested whenever the cci f flag in the fstat register is set (see section 5.24.3.2.7, ?flash status register (fstat)" ) 4 ignsf ignore single bit fault ? the ignsf controls single bit fault reporting in the ferstat register (see section 5.24.3.2.8, ?flash error status register (ferstat)" ). 0 all single bit faults detected during array reads are reported 1 single bit faults detected during array reads are not repor ted and the single bit fault interrupt will not be generated 1 fdfd force double bit fault detect ? the fdfd bit allows the user to simula te a double bit fault during flash array read operations, and check the associated interrupt routine. the fdfd bit is cleared by writing a 0 to fdfd. the feccr registers will not be updated during the flash array read operation with fdfd set unless an actual double bit fault is detected. 0 flash array read operations will set the dfdif flag in the ferstat register only if a double bit fault is detected 1 any flash array read operation will force the df dif flag in the ferstat register to be set (see section 5.24.3.2.7, ?flash status register (fstat)" ) and an interrupt will be generated, as long as the dfdie interrupt enable in the fercnfg register is set (see section 5.24.3.2.6, ?flash error configuration register (fercnfg)" ) 0 fsfd force single bit fault detect ? the fsfd bit allows the user to simulate a single bit fault during flash array read operations, and check the associated interrupt routine. the fsfd bit is cleared by writing a 0 to fsfd. the feccr registers will not be updated during the flash array read operation with fsfd set unless an actual single bit fault is detected. 0 flash array read operations will set the sfdif flag in t he ferstat register only if a single bit fault is detected 1 flash array read operation will force the sfdif flag in the ferstat register to be set (see section 5.24.3.2.7, ?flash status register (fstat)" ), and an interrupt will be generated as long as the sfdie interrupt enable in the fercnfg register is set (see section 5.24.3.2.6, ?flash error configuration register (fercnfg)" )
mm912_637, rev. 3.0 freescale semiconductor 355 5.24.3.2.6 flash error confi guration register (fercnfg) the fercnfg register enables the flash error interrupts for the ferstat flags. all assigned bits in the fercnfg register are readable and writable. 5.24.3.2.7 flash status register (fstat) the fstat register reports the operat ional status of the flash module. ccif, accerr, and fpviol bits are readable and writable, mg busy and mgstat bits are readable but not writable, while remaining bits read 0 and are not writable. table 479. flash error configur ation register (fercnfg) address: 0x0105 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 dfdie sfdie w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 480. fercnfg field descriptions field description 1 dfdie double bit fault detect interrupt enable ? the dfdie bit controls interrupt generation when a double bit fault is detected during a flash block read operation. 0 dfdif interrupt disabled 1 an interrupt will be requested whenever the dfdif flag is set (see section 5.24.3.2.8, ?flash error status register (ferstat)" ) 0 sfdie single bit fault detect interrupt enable ? the sfdie bit controls interrupt generation when a single bit fault is detected during a flash block read operation. 0 sfdif interrupt disabled whenever the sfdif flag is set (see section 5.24.3.2.8, ?flash error status register (ferstat)" ) 1 an interrupt will be requested w henever the sfdif flag is set (see section 5.24.3.2.8, ?flash error status register (ferstat)" ) table 481. flash status register (fstat) address: 0x0106 7 6 5 4 3 2 1 0 r ccif 0 accerr fpviol mgbusy rsvd mgstat[1:0] w reset 1 0 0 0 0 0 0 (286) 0 (286) = unimplemented or reserved notes 286.reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see section 5.24.6, ?initialization" ).
mm912_637, rev. 3.0 freescale semiconductor 356 5.24.3.2.8 flash error status register (ferstat) the ferstat register reflects the error status of internal flash operations. all flags in the ferstat register are r eadable and only writable to clear the flag. table 482. fstat field descriptions field description 7 ccif command complete interrupt flag ? the ccif flag indicates that a flash co mmand has completed. the ccif flag is cleared by writing a 1 to ccif to launch a command and ccif wi ll stay low until command completion or command violation. 0 flash command in progress 1 flash command has completed 5 accerr flash access error flag ? the accerr bit indicates an il legal access has occurred to the flash memory caused by either a violation of the command write sequence (see section 5.24.4.3.2, ?command write sequence" ) or issuing an illegal flash command. while accerr is set, the ccif flag cannot be clear ed to launch a command. the accerr bit is cleared by writing a 1 to accerr. writing a 0 to the accerr bit has no effect on accerr. 0 no access error detected 1 access error detected 4 fpviol flash protection violation flag ?the fpviol bit indicates an attempt was made to program or erase an address in a protected area of p-flash or d-flash memory during a comm and write sequence. the fpviol bit is cleared by writing a 1 to fpviol. writing a 0 to the fpviol bit has no effect on f pviol. while fpviol is set, it is not possible to launch a command or start a command write sequence. 0 no protection violation detected 1 protection violation detected 3 mgbusy memory controller busy flag ? the mgbusy flag reflects the active state of the memory controller . 0 memory controller is idle 1 memory controller is busy exec uting a flash command (ccif = 0) 2 rsvd reserved bit ? this bit is reserved and always reads 0 . 1?0 mgstat[1:0] memory controller command completion status flag ? one or more mgstat flag bits are set if an error is detected during execution of a flash command or during the flash reset sequence. see section 5.24.4.5, ?flash command description" , and section 5.24.6, ?initialization" , for details. table 483. flash error status register (ferstat) address: 0x0107 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 dfdif sfdif w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved
mm912_637, rev. 3.0 freescale semiconductor 357 5.24.3.2.9 p-flash protec tion register (fprot) the fprot register defines which p-flash sectors are protected against program and erase operations. the (unreserved) bits of the fprot register are writable with the restriction that th e size of the protec ted region can only be increased (see section 5.24.3.2.9.1, ?p-flash protection restrictions" , and ta b l e 490 ). during the reset sequence, the fprot register is loaded with the contents of the p-flash protection byte in the flash configuration field at global address 0x 3_ff0c located in p-flash memory (see ta b l e 463 ), as indicated by reset condition ?f? in figure 485 . to change the p-flash protection that will be loaded during the reset sequenc e, the upper sector of the p-flash memory must be unprotected, then the p-flash protection byte must be reprogrammed. if a dou ble bit fault is detected while reading the p-flash phrase containing the p-flash protection byte during the reset sequence, the fpopen bit will be cleared and remaining bits in the fprot register will be set to leave the p-flash memory fully protected. trying to alter data in any protected area in the p-flash memory will result in a protection violation error and the fpviol bit will be set in the fstat register. the block erase of a p-flash block is not possible if any of the p-flash sectors contained in the same p-flash block are protected. table 484. ferstat field descriptions field description 1 dfdif double bit fault detect interrupt flag ? the setting of the dfdif flag indicates that a double bit fault was detected in the stored parity and data bits during a flash array read operation, or that a flash array read operation was attempted on a flash block that was under a flash command operation. (287) the dfdif flag is cleared by writing a 1 to dfdif. writing a 0 to dfdif has no effect on dfdif. 0 no double bit fault detected 1 double bit fault detected or an invalid flash array read operation attempted 0 sfdif single bit fault detect interrupt flag ? with the ignsf bit in the fcnfg register clear, the sfdif flag indicates that a single bit fault was detected in the stored pa rity and data bits during a flash array read operation, or that a flash array rea d operation was attempted on a flash block that was under a flash command operation. (287) the sfdif flag is cleared by writing a 1 to sfdif. writing a 0 to sfdif has no effect on sfdif. 0 no single bit fault detected 1 single bit fault detected and corrected or an invalid flash array read operation attempted notes 287.the single bit fault and double bit fault fl ags are mutually exclusive for parity er rors (an ecc fault occurrence can be ei ther single fault or double fault but never both). a simultaneous ac cess collision (read attempted while comm and running) is indicated when both sfd if and dfdif flags are high. table 485. flash protection register (fprot) address: 0x0108 7 6 5 4 3 2 1 0 r fpopen rnv6 fphdis fphs[1:0] fpldis fpls[1:0] w reset f f f f f f f f = unimplemented or reserved table 486. fprot field descriptions field description 7 fpopen flash protection operation enable ? the fpopen bit determines the protection function for program or erase operations as shown in table 487 , for the p-flash block. 0 when fpopen is clear, the fphdis and fpldis bits define unpr otected address ranges as specified by the corresponding fphs and fpls bits 1 when fpopen is set, the fphdis and fpldis bits enable prot ection for the address range specified by the corresponding fphs and fpls bits 6 rnv[6] reserved nonvolatile bit ? the rnv bit should remain in the erased state for future enhancements.
mm912_637, rev. 3.0 freescale semiconductor 358 all possible p-flash protection scenarios are shown in figure 112 . although the protection schem e is loaded from the flash memory at global address 0x3_ff0c during the reset sequence, it can be changed by the user. the p-flash protection scheme can be used by applications requiring reprogramming in single ch ip mode while providing as much protection as possible, if reprogramming is not required. 5 fphdis flash protection higher address range disable ? the fphdis bit determines whether there is a protected/unprotected area in a specific region of the p-flas h memory ending with global address 0x3_ffff. 0 protection/unprotection enabled 1 protection/unprotection disabled 4?3 fphs[1:0] flash protection higher address size ? the fphs bits determine the size of the protected/unprotected area in p-flash memory as shown in ta b l e 488 . the fphs bits can only be written to while the fphdis bit is set. 2 fpldis flash protection lower address range disable ? the fpldis bit determines whether there is a protected/unprotected area in a specific region of the p-flas h memory beginning with global address 0x3_8000. 0 protection/unprotection enabled 1 protection/unprotection disabled 1?0 fpls[1:0] flash protection lower address size ? the fpls bits determine the size of the protected/unprotected area in p-flash memory as shown in ta b l e 489 . the fpls bits can only be written to while the fpldis bit is set. table 487. p-flash protection function fpopen fphdis fpldis function (288) 1 1 1 no p-flash protection 1 1 0 protected low range 1 0 1 protected high range 1 0 0 protected high and low ranges 0 1 1 full p-flash memory protected 0 1 0 unprotected low range 0 0 1 unprotected high range 0 0 0 unprotected high and low ranges notes 288.for range sizes, refer to table 488 and table 489 . table 488. p-flash protection higher address range fphs[1:0] global address range protected size 00 0x3_f800?0x3_ffff 2.0 kbytes 01 0x3_f000?0x3_ffff 4.0 kbytes 10 0x3_e000?0x3_ffff 8.0 kbytes 11 0x3_c000?0x3_ffff 16 kbytes table 489. p-flash protection lower address range fpls[1:0] global address range protected size 00 0x3_8000?0x3_83ff 1.0 kbyte 01 0x3_8000?0x3_87ff 2.0 kbytes 10 0x3_8000?0x3_8fff 4.0 kbytes 11 0x3_8000?0x3_9fff 8.0 kbytes table 486. fprot field descriptions (continued) field description
mm912_637, rev. 3.0 freescale semiconductor 359 figure 112. p-flash protection scenarios 5.24.3.2.9.1 p-flash pr otection restrictions the general guideline is that p-flash protec tion can only be added and not removed. ta b l e 490 specifies all valid transitions between p-flash protection scenarios. any attempt to write an invalid scenario to the fprot register will be ignored. the contents of the fprot register reflect t he active protection scenario. see the fphs and fpls bit descriptions for additional restrictions. 7 6 5 4 fphs[1:0] fpls[1:0] 3 2 1 0 fphs[1:0] fpls[1:0] fphdis = 1 fpldis = 1 fphdis = 1 fpldis = 0 fphdis = 0 fpldis = 1 fphdis = 0 fpldis = 0 scenario scenario unprotected region protected region with size protected region protected region with size defined by fpls defined by fphs not defined by fpls, fphs 0x3_8000 0x3_ffff 0x3_8000 0x3_ffff flash start flash start fpopen = 1 fpopen = 0
mm912_637, rev. 3.0 freescale semiconductor 360 5.24.3.2.10 d-flash protec tion register (dfprot) the dfprot register defines which d-flash sectors are protected against progr am and erase operations. the (unreserved) bits of the dfprot regi ster are writable with the rest riction that protection can be added but not removed. writes must increase the dps value and the dpopen bit can only be written from a 1 (protection disabled) to a 0 (protection enabled). if the dpopen bit is set, the state of the dps bits is irrelevant. during the reset sequence, the dfprot register is loaded with the contents of the d-flash protection byte in the flash configuration field at global address 0x3_ff0d located in p-flash memory (see table 463 ) as indicated by reset condition f in figure 491 . to change the d-flash protec tion that will be loaded during the reset seq uence, the p-flash sector containing the d-flash protection byte must be unprotect ed, then the d-flash protection byte must be programmed. if a double bit fault is detected while reading the p-flas h phrase containing the d-flash protection byte during the reset sequence, the dpopen bit will be cleared and dps bits will be set to leave the d-flash memory fully protected. trying to alter data in any protected area in the d-flash memory will result in a protection violation error, and the fpviol bi t will be set in the fstat register. block erase of the d-flash memory is not possible if any of the d-flash sectors are protected. table 490. p-flash protection scenario transitions from protection scenario to protection scenario (289) 0 1 2 3 4 5 6 7 0 x x x x 1 x x 2 x x 3 x 4 x x 5 x x x x 6 x x x x 7 x x x x x x x x notes 289.allowed transitions marked with x, see figure 112 for a definition of the scenarios. table 491. d-flash protection register (dfprot) address: 0x0109 7 6 5 4 3 2 1 0 r dpopen 0 0 0 dps[3:0] w reset f 0 0 0 f f f f = unimplemented or reserved table 492. dfprot field descriptions field description 7 dpopen d-flash protection control 0 enables d-flash memory protection from program and er ase with protected address range defined by dps bits 1 disables d-flash memory prot ection from program and erase 3?0 dps[3:0] d-flash protection size ? the dps[3:0] bits determine the size of the protected area in the d-flash memory as shown in ta b l e 493 .
mm912_637, rev. 3.0 freescale semiconductor 361 5.24.3.2.11 flash common comman d object register (fccob) the fccob is an array of six words addressed via the ccobix in dex found in the fccobix regist er. byte wide reads and writes are allowed to the fccob register. 5.24.3.2.11.1 fccob - nvm command mode nvm command mode uses the indexed fccob register to provide a command code and its relevant parameters to the memory controller. the user first sets up all required fccob fields and then initiates the command?s execution by writing a 1 to the c cif bit in the fstat register (a 1 written by the user clears the ccif command completion flag to 0). when the user clears the ccif bit in the fstat register all fccob parameter fields are locke d and cannot be changed by the user until the command completes (as evidenced by the memory controller returning ccif to 1). so me commands return informati on to the fccob register array. the generic format for the fccob parameter fields in nvm command mode is shown in table 496 . the return values are available for reading after the ccif flag in the fstat register has been returned to 1 by the memory controller. writes to the unimplemented parameter fields (ccobix = 110 and ccobix = 111 ) are ignored with reads from these fields returning 0x0000. table 493. d-flash protection address range dps[3:0] global address range protected size 0000 0x0_4400 ? 0x0_44ff 256 bytes 0001 0x0_4400 ? 0x0_45ff 512 bytes 0010 0x0_4400 ? 0x0_46ff 768 bytes 0011 0x0_4400 ? 0x0_47ff 1024 bytes 0100 0x0_4400 ? 0x0_48ff 1280 bytes 0101 0x0_4400 ? 0x0_49ff 1536 bytes 0110 0x0_4400 ? 0x0_4aff 1792 bytes 0111 0x0_4400 ? 0x0_4bff 2048 bytes 1000 0x0_4400 ? 0x0_4cff 2304 bytes 1001 0x0_4400 ? 0x0_4dff 2560 bytes 1010 0x0_4400 ? 0x0_4eff 2816 bytes 1011 0x0_4400 ? 0x0_4fff 3072 bytes 1100 0x0_4400 ? 0x0_50ff 3328 bytes 1101 0x0_4400 ? 0x0_51ff 3584 bytes 1110 0x0_4400 ? 0x0_52ff 3840 bytes 1111 0x0_4400 ? 0x0_53ff 4096 bytes table 494. flash common command object high register (fccobhi) address: 0x010a 7 6 5 4 3 2 1 0 r ccob[15:8] w reset 0 0 0 0 0 0 0 0 table 495. flash common command object low register (fccoblo) address: 0x010b 7 6 5 4 3 2 1 0 r ccob[7:0] w reset 0 0 0 0 0 0 0 0
mm912_637, rev. 3.0 freescale semiconductor 362 table 496 shows the generic flash command format. the high byte of the first word in the ccob array contains the command code, followed by the parameters for this specific flash command. for details on the fccob settings required by each command, see the flash command descriptions in section 5.24.4.5, ?flash command description" . 5.24.3.2.12 flash reserved1 register (frsv1) this flash register is re served for factory testing. all bits in the frsv1 register read 0 and are not writable. 5.24.3.2.13 flash reserved2 register (frsv2) this flash register is re served for factory testing. all bits in the frsv2 register read 0 and are not writable. table 496. fccob - nvm command mode (typical usage) ccobix[2:0] byte fccob parameter fields (nvm command mode) 000 hi fcmd[7:0] defining flash command lo 6?h0, global address [17:16] 001 hi global address [15:8] lo global address [7:0] 010 hi data 0 [15:8] lo data 0 [7:0] 011 hi data 1 [15:8] lo data 1 [7:0] 100 hi data 2 [15:8] lo data 2 [7:0] 101 hi data 3 [15:8] lo data 3 [7:0] table 497. flash reserved1 register (frsv1) address: 0x010c 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 498. flash reserved2 register (frsv2) address: 0x010d 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved
mm912_637, rev. 3.0 freescale semiconductor 363 5.24.3.2.14 flash reserved3 register (frsv3) this flash register is re served for factory testing. all bits in the frsv3 register read 0 and are not writable. 5.24.3.2.15 flash reserved4 register (frsv4) this flash register is re served for factory testing. all bits in the frsv4 register read 0 and are not writable. 5.24.3.2.16 flash option register (fopt) the fopt register is the flash option register. all bits in the fopt register are readable but are not writable. during the reset sequence, the fopt register is loaded from the flash nonvolatile byte in the flash configuration field, at glo bal address 0x3_ff0e located in p-flash memory (see table 463 ), as indicated by reset condition f in figure 501 . if a double bit fault is detected while reading the p-flash phrase containing th e flash nonvolatile byte during the reset sequence, all bits in the fopt register will be set. table 499. flash reserved3 register (frsv3) address: 0x010e 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 500. flash reserved4 register (frsv4) address: 0x010f 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 501. flash option register (fopt) address: 0x0110 7 6 5 4 3 2 1 0 r nv[7:0] w reset f f f f f f f f = unimplemented or reserved table 502. fopt field descriptions field description 7?0 nv[7:0] nonvolatile bits ? the nv[7:0] bits are available as nonvolatile bits. refer to the devic e user guide for proper use of the nv bits.
mm912_637, rev. 3.0 freescale semiconductor 364 5.24.3.2.17 flash reserved5 register (frsv5) this flash register is re served for factory testing. all bits in the frsv5 register read 0 and are not writable. 5.24.3.2.18 flash reserved6 register (frsv6) this flash register is re served for factory testing. all bits in the frsv6 register read 0 and are not writable. 5.24.3.2.19 flash reserved7 register (frsv7) this flash register is re served for factory testing. all bits in the frsv7 register read 0 and are not writable. 5.24.4 functional description 5.24.4.1 modes of operation the ftmrc128k1 module provides t he modes of operation, as shown in table 506 . the operating mode is determined by module-level inputs and affects the fclkdiv, fcnfg, and df prot registers, scratch ram writes, and the command set availability (see ta b l e 508 ). table 503. flash reserved5 register (frsv5) address: 0x0111 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 504. flash reserved6 register (frsv6) address: 0x0112 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved table 505. flash reserved7 register (frsv7) address: 0x0113 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved
mm912_637, rev. 3.0 freescale semiconductor 365 5.24.4.2 ifr version id word the version id word is stored in the ifr at addre ss 0x0_40b6. the contents of the word are defined in table 507 . vernum: version number. the first version is number 0b_0001 with both 0b_0000 and 0b_1111 meaning ?none?. 5.24.4.3 flash command operations flash command operations are used to modify flash memory contents. the next sections describe: ? how to write the fclkdiv register that is used to generate a time base (fclk) derived from busclk for flash program and erase command operations ? the command write sequence used to set fl ash command parameters and launch execution ? valid flash commands available for execution 5.24.4.3.1 writing the fclkdiv register prior to issuing any flash program or erase command after a rese t, the user is required to write the fclkdiv register to divide busclk down to a target fclk of 1.0 mhz. ta b l e 469 shows recommended values for the fdiv field based on busclk frequency. note programming or erasing the flash memory cannot be performed if the bus clock runs at less than 0.8 mhz. setting fdiv too high can destroy the flash memory due to overstress. setting fdiv too low can result in incomplete programming or erasur e of the flash memory cells. when the fclkdiv register is writ ten, the fdivld bit is set automatically. if th e fdivld bit is 0, the fclkdiv register has not been written since the last reset. if th e fclkdiv register has not been written, any flash program or erase command loaded during a command write sequence will not execute and the accerr bit in the fs tat register will set. 5.24.4.3.2 command write sequence the memory controller will launch all valid flas h commands entered usi ng a command write sequence. before launching a command, the accerr and fpviol bits in the fstat register must be clear (see section 5.24.3.2.7, ?flash status register (fstat)" ) and the ccif flag should be tested to determine the status of the curre nt command write sequence. if ccif is 0, the previous comm and write sequence is still active and a new co mmand write sequence cannot be started, and all writes to the fccob register are ignored. caution writes to any flash register must be avoided while a flash command is active (ccif=0) to prevent corruption of flash register contents and memory controller behavior. table 506. modes and mode control inputs operating mode ftmrc input mmc_mode_ss_t2 normal: 0 special: 1 table 507. ifr version id fields [15:4] [3:0] reserved vernum
mm912_637, rev. 3.0 freescale semiconductor 366 5.24.4.3.2.1 defin e fccob contents the fccob parameter fields must be loaded with all required para meters for the flash command being executed. access to the fccob parameter fields is controlled via the ccobix bits in the fccobix register (see section 5.24.3.2.3, ?flash ccob index register (fccobix)" ). the contents of the fccob parameter fields are transferred to the memory controller when the user clears the ccif command completion flag in the fstat register (wri ting 1 clears the ccif to 0). the ccif flag will remain clear until the flash command has completed. upon completion, the memory controller will return ccif to 1 and the fccob register will be used to communicate any results. the flow for a gen eric command write s equence is shown in figure 113 . figure 113. generic flash command write sequence flowchart write to fccobix register write: fstat register (to launch command) clear ccif 0x80 clear accerr/fpviol 0x30 write: fstat register yes no access error and protection violation read: fstat register start check fccob accerr/ fpviol set? exit write: fclkdiv register read: fclkdiv register yes no fdiv correct? no bit polling for command completion check yes ccif set? to identify specific command parameter to load. write to fccob register to load required command parameter. yes no more parameters? availability check results from previous command note: fclkdiv must be set after each reset read: fstat register no yes ccif set? no yes ccif set? clock divider value check read: fstat register
mm912_637, rev. 3.0 freescale semiconductor 367 5.24.4.3.3 valid flash module commands 5.24.4.3.4 p-flash commands table 509 summarizes the valid p-flash commands along with the ef fects of the commands on the p-flash block and other resources within the flash module. table 508. flash commands by mode fcmd command unsecured secured ns (290) ss (291) ns (292) ss (293) 0x01 erase verify all blocks ? ? ? ? 0x02 erase verify block ? ? ? ? 0x03 erase verify p-flash section ? ? ? 0x04 read once ? ? ? 0x06 program p-flash ? ? ? 0x07 program once ? ? ? 0x08 erase all blocks ? ? 0x09 erase flash block ? ? ? 0x0a erase p-flash sector ? ? ? 0x0b unsecure flash ? ? 0x0c verify backdoor access key ? ? 0x0d set user margin level ? ? ? 0x0e set field margin level ? 0x10 erase verify d-flash section ? ? ? 0x11 program d-flash ? ? ? 0x12 erase d-flash sector ? ? ? notes 290.unsecured normal single chip mode. 291.unsecured special single chip mode. 292.secured normal single chip mode. 293.secured special single chip mode. table 509. p-flash commands fcmd command function on p-flash memory 0x01 erase verify all blocks verify that all p-flash (and d-flash) blocks are erased. 0x02 erase verify block verify that a p-flash block is erased. 0x03 erase verify p-flash section verify that a given number of words st arting at the address provided are erased. 0x04 read once read a dedicated 64-byte field in the nonvolatile in formation register in p-flash block that was previously programmed using the program once command. 0x06 program p-flash program a phrase in a p-flash block. 0x07 program once program a dedicated 64-byte field in the nonvolatile information register in p-flash block that is allowed to be programmed only once. 0x08 erase all blocks erase all p-flash ( and d-flash) blocks. an erase of all flash blocks is only possible when the fpldis, fphdis, and fpopen bits in the fprot register and the dpopen bit in the dfprot register are set prior to launching the command. 0x09 erase flash block erase a p-flash (or d-flash) block. an erase of the full p-flash block is only possi ble when fpldis, fphdis and fpopen bits in the fprot register are set prior to launching the command.
mm912_637, rev. 3.0 freescale semiconductor 368 5.24.4.3.5 d-flash commands table 510 summarizes the valid d-flash commands along with the effects of the commands on the d-flash block. 5.24.4.4 allowed simultaneous p-flash and d-flash operations only the operations marked ?ok? in ta b l e 511 are permitted to be run simultaneously on the program flash and data flash blocks. some operations cannot be executed simultaneously bec ause certain hardware resources are shared by the two memories. the priority has been placed on permitting program fl ash reads while program and erase operations execute on the data flash, providing read (p-flash) while write (d-flash) functionality. 0x0a erase p-flash sector erase all bytes in a p-flash sector. 0x0b unsecure flash supports a method of releasing mcu security by erasing all p-flash (and d-flash) blocks and verifying that all p-flash (a nd d-flash) blocks are erased. 0x0c verify backdoor access key supports a method of releasing mcu security by verifying a set of security keys. 0x0d set user margin level specifies a user margin read level for all p-flash blocks. 0x0e set field margin level specifies a field margin read level for all p-flash blocks (special modes only). table 510. d-flash commands fcmd command function on d-flash memory 0x01 erase verify all blocks verify that all d-flash (and p-flash) blocks are erased. 0x02 erase verify block verify that the d-flash block is erased. 0x08 erase all blocks erase all d-flash (and p-flash) blocks. an erase of all flash blocks is only possible when the fpldis, fphdis, and fpopen bits in the fprot register and the dpopen bit in the dfprot register are set prior to launching the command. 0x09 erase flash block erase a d-flash (o r p-flash) block. an erase of the full d-flash block is only possibl e when dpopen bit in the dfprot register is set prior to launching the command. 0x0b unsecure flash supports a method of releasing mcu security by erasing all d-flash (and p-flash) blocks and verifying that all d-flash ( and p-flash) blocks are erased. 0x0d set user margin level specifies a user margin read level for the d-flash block. 0x0e set field margin level specifies a field margin read level for the d-flash block (special modes only). 0x10 erase verify d-flash section verify that a given number of words starting at the address provided are erased. 0x11 program d-flash program up to four words in the d-flash block. 0x12 erase d-flash sector erase all bytes in a sector of the d-flash block. table 511. allowed p-flash and d-flash simultaneous operations data flash program flash read margin read (294) program sector erase mass erase (296) read ok ok ok margin read (294) ok (295) program sector erase ok table 509. p-flash commands fcmd command function on p-flash memory
mm912_637, rev. 3.0 freescale semiconductor 369 5.24.4.5 flash command description this section provides details of all available flash commands launched by a command write sequence. the accerr bit in the fstat register will be set during the comm and write sequence if any of the following illegal steps are performed, causing the command not to be processed by the memory controller: ? starting any command write sequence that programs or eras es flash memory before initializing the fclkdiv register ? writing an invalid command as part of the command write sequence ? for additional possible errors, refer to the error handling table provided for each command if a flash block is read during execution of an algorithm (ccif = 0) on that same block, the r ead operation will return invalid data. if the sfdif or dfdif flags were not prev iously set when the invalid read operation occurred, both the sfdif and dfdif flags will be set. if the accerr or fpviol bits are set in the fstat register, th e user must clear these bits bef ore starting any command write sequence (see section 5.24.3.2.7, ?flash status register (fstat)" ). caution a flash word or phrase must be in the eras ed state before being programmed. cumulative programming of bits within a flash word or phrase is not allowed. 5.24.4.5.1 erase verify all blocks command the erase verify all blocks command will verify t hat all p-flash and d-flash blocks have been erased. upon clearing ccif to launch the erase verify all blocks comm and, the memory controller will verify that the entire flash memory space is erased. the ccif flag will set afte r the erase verify all bl ocks operation has completed. mass erase (296) ok notes 294.a ?margin read? is any read after executing the margin setting commands ?set user margin level?, or ?set field margin level? with anything but the ?normal? level specified. 295.see the note on margin settings in section 5.24.4.5.12, ?set user margin level command" and section 5.24.4.5.13, ?set field margin level command" . 296.the ?mass erase? operations are commands ?erase all blocks? and ?erase flash block?. table 512. erase verify all blocks command fccob requirements ccobix[2:0] fccob parameters 000 0x01 not required table 513. erase verify all blocks command error handling register error bit error condition fstat accerr set if ccobix[2:0]!= 000 at command launch fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 511. allowed p-flash and d-flash simultaneous operations data flash program flash read margin read (294) program sector erase mass erase (296)
mm912_637, rev. 3.0 freescale semiconductor 370 5.24.4.5.2 erase verify block command the erase verify block command allows the user to verify t hat an entire p-flash or d-flash block has been erased. the fccob upper global address bits determine which block must be verified. upon clearing ccif to launch the erase veri fy block command, the memory controller will verify that the selected p-flash or d-flash block is erased. the ccif flag will set afte r the erase verify block operation has completed. 5.24.4.5.3 erase verify p- flash section command the erase verify p-flash section command will verify that a section of code in the p- flash memory is erased. the erase verify p-flash section command defines the starting point of the code to be verified and the number of phrases. upon clearing ccif to launch the erase verify p-flash section co mmand, the memory controller will verify the selected section of flash memory is erased. the ccif flag will set after the erase verify p- flash section operation has completed. table 514. erase verify block command fccob requirements ccobix[2:0] fccob parameters 000 0x02 global address [17:16] of the flash block to be verified . table 515. erase verify block command error handling register error bit error condition fstat accerr set if ccobix[2:0]!= 000 at command launch set if an invalid global address [17:16] is supplied fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 516. erase verify p-flash section command fccob requirements ccobix[2:0] fccob parameters 000 0x03 global address [17:16] of a p-flash block 001 global address [15:0] of the first phrase to be verified 010 number of phrases to be verified table 517. erase verify p-flash section command error handling register error bit error condition fstat accerr set if ccobix[2:0]!= 010 at command launch set if command not available in current mode (see table 508 ) set if an invalid global address [17:0] is supplied set if a misaligned phrase address is supplied (global address [2:0]!= 000) set if the requested section crosses a 128 kbyte boundary fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read
mm912_637, rev. 3.0 freescale semiconductor 371 5.24.4.5.4 read once command the read once command provides read access to a reserved 64-by te field (8 phrases) located in the nonvolatile information register of p-flash. the read once field is pr ogrammed using the program once command described in section 5.24.4.5.6, ?program once command" . the read once command must not be executed fr om the flash block containing the program once reserved field to avoid code runaway. upon clearing ccif to launch the read once command, a read once phrase is fetched and stored in the fccob indexed register. the ccif flag will set after the read once operation has completed. valid phrase index values for the read once command range from 0x0000 to 0x0007. duri ng execution of the read on ce command, any attempt to read addresses within p-flash block will return invalid data. 5.24.4.5.5 program p-flash command the program p-flash operation will program a previously erased phrase in the p-flash memory using an embedded algorithm. caution a p-flash phrase must be in the erased state before being programmed. cumulative programming of bits within a flash phrase is not allowed. table 518. read once command fccob requirements ccobix[2:0] fccob parameters 000 0x04 not required 001 read once phrase index (0x0000 - 0x0007) 010 read once word 0 value 011 read once word 1 value 100 read once word 2 value 101 read once word 3 value table 519. read once command error handling register error bit error condition fstat accerr set if ccobix[2:0]!= 001 at command launch set if command not available in current mode (see table 508 ) set if an invalid phrase index is supplied fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 520. program p-flash command fccob requirements ccobix[2:0] fccob parameters 000 0x06 global address [17:16] to identify p-flash block 001 global address [15:0] of phrase location to be programmed (297) 010 word 0 program value 011 word 1 program value 100 word 2 program value 101 word 3 program value notes 297.global address [2:0] must be 000
mm912_637, rev. 3.0 freescale semiconductor 372 upon clearing ccif to launch the program p- flash command, the memory controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. the ccif flag will set after the program p-flash operation has completed. 5.24.4.5.6 program once command the program once command restricts programming to a reserved 64-b yte field (8 phrases) in the nonvolatile information register located in p-flash. the program once reserved field can be read using the read once command as described in section 5.24.4.5.4, ?read once command" . the program once command must only be issued once, since the nonvolatile information register in p-flash cannot be erased. the program once command must not be executed from the flash block containing the program once reserved field to avoid code runaway. upon clearing ccif to launch the program once command, the memo ry controller first verifies that the selected phrase is erased. if erased, then the selected phrase will be programmed and then verified with read back. the ccif flag will remain clea r, setting only after the program once operation has completed. the reserved nonvolatile information register accessed by the program once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed. valid phrase index values for the program once command range from 0x0000 to 0x0007. during execution of the program once command, any attempt to read addresses within p-flash will return invalid data. table 521. program p-flash command error handling register error bit error condition fstat accerr set if ccobix[2:0]!= 101 at command launch set if command not available in current mode (see table 508 ) set if an invalid global address [17:0] is supplied set if a misaligned phrase address is supplied (global address [2:0]!= 000) fpviol set if the global address [17:0] points to a protected area mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 522. program once command fccob requirements ccobix[2:0] fccob parameters 000 0x07 not required 001 program once phrase index (0x0000 - 0x0007) 010 program once word 0 value 011 program once word 1 value 100 program once word 2 value 101 program once word 3 value
mm912_637, rev. 3.0 freescale semiconductor 373 5.24.4.5.7 erase all blocks command the erase all blocks operation will erase the entire p-flash and d-flash memory space. upon clearing ccif to la unch the erase all blocks command, the memory controller will erase the entire flash memory space and verify that it is erased. if the memo ry controller verifies that the entire flas h memory space was properly erased, securit y will be released. during the execution of th is command (ccif=0) the user must not write to any flash module register. the ccif flag will set after the erase all blocks operation has completed. 5.24.4.5.8 erase flash block command the erase flash block operation will erase a ll addresses in a p-flash or d-flash block. upon clearing ccif to launch the erase flash block command, the memory controller will erase the selected flash block and verify that it is erased. the ccif flag will set after the erase flash block operation has completed. table 523. program once command error handling register error bit error condition fstat accerr set if ccobix[2:0]!= 101 at command launch set if command not available in current mode (see table 508 ) set if an invalid phrase index is supplied set if the requested phrase has already been programmed (298) fpviol none mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation notes 298.if a program once phrase is initially programmed to 0xf fff_ffff_ffff_ffff, the program once command will be allowed to execute again on that same phrase. table 524. erase all blocks co mmand fccob requirements ccobix[2:0] fccob parameters 000 0x08 not required table 525. erase all blocks command error handling register error bit error condition fstat accerr set if ccobix[2:0]!= 000 at command launch set if command not available in current mode (see table 508 ) fpviol set if any area of the p-flash or d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 526. erase flash block command fccob requirements ccobix[2:0] fccob parameters 000 0x09 global address [17:16] to identify flash block 001 global address [15:0] in flash block to be erased
mm912_637, rev. 3.0 freescale semiconductor 374 5.24.4.5.9 erase p-flash sector command the erase p-flash sector operation will er ase all addresses in a p-flash sector. upon clearing ccif to launch the erase p-flash sector command, the memory controller will eras e the selected flash sector and then verify that it is erased. the ccif flag will be set after the erase p-flash sector operation has completed. 5.24.4.5.10 unsecure flash command the unsecure flash command will erase the entire p-flash and d-flash memory space and, if the erase is successful, will release security. upon clearing ccif to launch the unsecure flash command, the memory controller will erase the entire p-flash and d-flash memory space and verify that it is erased. if the memory contro ller verifies that the entire flash memory space was properly erased, security will be released. if the erase verify is not successful, the unsecure flash operation sets mgstat1 and terminates without changing the security state. during the execut ion of this command (ccif=0) the user must not write to any flash module register. the ccif flag is set after the unsecure flash operation has completed. table 527. erase flash block command error handling register error bit error condition fstat accerr set if ccobix[2:0]!= 001 at command launch set if command not available in current mode (see table 508 ) set if an invalid global address [17:16] is supplied set if the supplied p-flash address is not phr ase-aligned or if the d-flash address is not word-aligned fpviol set if an area of the selected flash block is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 528. erase p-flash sector command fccob requirements ccobix[2:0] fccob parameters 000 0x0a global address [17:16] to identify p-flash block to be erased 001 global address [15:0] anywhere with in the sector to be erased. refer to section 5.24.1.2.1, ?p-flash features" for the p-flash sector size. table 529. erase p-flash sector command error handling register error bit error condition fstat accerr set if ccobix[2:0]!= 001 at command launch set if command not available in current mode (see table 508 ) set if an invalid global address [17:16] is supplied set if a misaligned phrase address is supplied (global address [2:0]!= 000) fpviol set if the selected p-flash sector is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 530. unsecure flash command fccob requirements ccobix[2:0] fccob parameters 000 0x0b not required
mm912_637, rev. 3.0 freescale semiconductor 375 5.24.4.5.11 verify back door access key command the verify backdoor access key command will only execute if it is enabled by the keyen bits in the fsec register (see table 472 ). the verify backdoor access key comm and releases security if user-suppli ed keys match those stored in the flash security bytes of the flash configuration field (see table 463 ). the verify backdoor access key command must not be executed from the flash block containing the backdoor comparison key to avoid code runaway. upon clearing ccif to launch the verify backdoor access ke y command, the memory controller will check the fsec keyen bits to verify that this command is enabled. if not enabled, th e memory controller sets the acce rr bit in the fstat register an d terminates. if the command is enabled, the memory controller compares the key provided in fccob to the backdoor comparison key in the flash configuration field with key 0 compared to 0x3_ ff00, etc. if the backdoor keys ma tch, security will be release d. if the backdoor keys do not match, security is not released and all future attempts to execute the verify backdoor access key command are aborted (set accerr) until a re set occurs. the ccif flag is set after the verify backdoor access key operation has completed. 5.24.4.5.12 set user margin level command the set user margin level command causes the memory controller to set the margin level for future read operations of the p-flash or d-flash block. table 531. unsecure flash command error handling register error bit error condition fstat accerr set if ccobix[2:0]!= 000 at command launch set if command not available in current mode (see table 508 ) fpviol set if any area of the p-flash or d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 532. verify backdoor access key command fccob requirements ccobix[2:0] fccob parameters 000 0x0c not required 001 key 0 010 key 1 011 key 2 100 key 3 table 533. verify backdoor access key command error handling register error bit error condition fstat accerr set if ccobix[2:0]!= 100 at command launch set if an incorrect backdoor key is supplied set if backdoor key access has not been enabled (keyen[1:0]!= 10, see section 5.24.3.2.2 ) set if the backdoor key has mismatched since the last reset fpviol none mgstat1 none mgstat0 none
mm912_637, rev. 3.0 freescale semiconductor 376 upon clearing ccif to launch the set user margin level command, the memory controller will set the user margin level for the targeted block and then set the ccif flag. note when the d-flash block is target ed, the d-flash user margin levels are applied only to the d-flash reads. however, when the p-flash block is targeted, the p-flas h user margin levels are applied to both p-flash and d-flash reads. it is not possible to apply user margin levels to the p-flash block only. valid margin level settings for the set user margin level command are defined in ta b l e 535 . note user margin levels can be used to check that flash memory cont ents have adequate margin for normal level read operations. if unexpected results are encountered when checking flash memory contents at user margin leve ls, a potential loss of information has been detected. 5.24.4.5.13 set field margin level command the set field margin level command, valid in special modes only, causes the memory controller to set the margin level specified for future read operations of the p-flash or d-flash block. table 534. set user margin level command fccob requirements ccobix[2:0] fccob parameters 000 0x0d global address [17:16] to identify the flash block 001 margin level setting table 535. valid set user margin level settings ccob (ccobix=001) level description 0x0000 return to normal level 0x0001 user margin-1 level (299) 0x0002 user margin-0 level (300) notes 299.read margin to the erased state 300.read margin to the programmed state table 536. set user margin level command error handling register error bit error condition fstat accerr set if ccobix[2:0]!= 001 at command launch set if command not available in current mode (see table 508 ) set if an invalid global address [17:16] is supplied set if an invalid margin level setting is supplied fpviol none mgstat1 none mgstat0 none
mm912_637, rev. 3.0 freescale semiconductor 377 upon clearing ccif to launch the set field margin level comma nd, the memory controller will se t the field margin level for the targeted block and then set the ccif flag. note when the d-flash block is targeted, the d-flash field margin levels are applied only to the d-flash reads. however, when the p-flash block is targeted, the p-flash field margin levels are applied to both p-flash and d-flash reads. it is not possible to apply field margin levels to the p-flash block only. valid margin level settings for the set field margin level command are defined in table 538 . caution field margin levels must only be used during verify of the initial factory programming. note field margin levels can be used to check that flash memory contents have adequate margin for data retention at the normal level settin g. if unexpected results are encountered when checking flash memory contents at field marg in levels, the flash memory contents should be erased and reprogrammed. 5.24.4.5.14 erase verify d- flash section command the erase verify d-flash section command will verify that a sect ion of code in the d-flash is erased. the erase verify d-flash section command defines the starting point of the data to be verified and the number of words. table 537. set field margin level command fccob requirements ccobix[2:0] fccob parameters 000 0x0e global address [17:16] to identify the flash block 001 margin level setting table 538. valid set field margin level settings ccob (ccobix=001) level description 0x0000 return to normal level 0x0001 user margin-1 level (301) 0x0002 user margin-0 level (302) 0x0003 field margin-1 level (301) 0x0004 field margin-0 level (302) notes 301.read margin to the erased state 302.read margin to the programmed state table 539. set field margin level command error handling register error bit error condition fstat accerr set if ccobix[2:0]!= 001 at command launch set if command not available in current mode (see table 508 ) set if an invalid global address [17:16] is supplied set if an invalid margin level setting is supplied fpviol none mgstat1 none mgstat0 none
mm912_637, rev. 3.0 freescale semiconductor 378 upon clearing ccif to launch the erase verify d-flash section command, the memory c ontroller will verify the selected section of d-flash memory is erased. the ccif flag will set after the erase verify d-flash sect ion operation has completed. 5.24.4.5.15 program d-flash command the program d-flash operation programs one to four previously erased words in the d-flash block. the program d-flash operation will confirm that the targeted location(s) were successfully programmed upon completion. caution a flash word must be in the erased state before being programmed. cumulative programming of bits within a flash word is not allowed. upon clearing ccif to launch the program d-flash command, the user-supplied words will be transferred to the memory controller and be programmed if the area is unprotected. the ccobix index value at program d-flash command launch determines how many words will be programmed in the d-flash block. the ccif flag is set when the operation has completed. table 540. erase verify d-flash sect ion command fccob requirements ccobix[2:0] fccob parameters 000 0x10 global address [17:16] to identify the d-flash block 001 global address [15:0] of the first word to be verified 010 number of words to be verified table 541. erase verify d-flash section command error handling register error bit error condition fstat accerr set if ccobix[2:0]!= 010 at command launch set if command not available in current mode (see ta b l e 508 ) set if an invalid global address [17:0] is supplied set if a misaligned word address is supplied (global address [0]!= 0) set if the requested section breaches the end of the d-flash block fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 542. program d-flash command fccob requirements ccobix[2:0] fccob parameters 000 0x11 global address [17:16] to identify the d-flash block 001 global address [15:0] of word to be programmed 010 word 0 program value 011 word 1 program value, if desired 100 word 2 program value, if desired 101 word 3 program value, if desired
mm912_637, rev. 3.0 freescale semiconductor 379 5.24.4.5.16 erase d-flash sector command the erase d-flash sector operat ion will erase all addresses in a sector of the d-flash block. upon clearing ccif to launch the erase d-fl ash sector command, the memory controll er will erase the selected flash sector and verify that it is erased. the ccif flag will set af ter the erase d-flash sector operation has completed. 5.24.4.6 interrupts the flash module can generate an interrupt when a flash command operation has completed, or when a flash command operation has detected an ecc fault. table 543. program d-flash command error handling register error bit error condition fstat accerr set if ccobix[2:0] < 010 at command launch set if ccobix[2:0] > 101 at command launch set if command not available in current mode (see table 508 ) set if an invalid global address [17:0] is supplied set if a misaligned word address is supplied (global address [0]!= 0) set if the requested group of words breaches the end of the d-flash block fpviol set if the selected area of the d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 544. erase d-flash sector command fccob requirements ccobix[2:0] fccob parameters 000 0x12 global address [17:16] to identify d-flash block 001 global address [15:0] anywhere with in the sector to be erased. see section 5.24.1.2.2, ?d-flash features" for d-flash sector size. table 545. erase d-flash sector command error handling register error bit error condition fstat accerr set if ccobix[2:0]!= 001 at command launch set if command not available in current mode (see table 508 ) set if an invalid global address [17:0] is supplied set if a misaligned word address is supplied (global address [0]!= 0) fpviol set if the selected area of the d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 546. flash interrupt sources interrupt source interrupt flag local enable global (ccr) mask flash command complete ccif (fstat register) ccie (fcnfg register) i bit ecc double bit fault on flash read dfdif (ferstat register) dfdie (fercnfg register) i bit ecc single bit fault on flash read sfdif (ferstat register) sfdie (fercnfg register) i bit
mm912_637, rev. 3.0 freescale semiconductor 380 note vector addresses and their relative interrupt priority are determined at the mcu level. 5.24.4.6.1 description of fl ash interrupt operation the flash module uses the ccif flag in combination with the ccie interrupt enable bit to generate the flash command interrupt request. the flash module uses the dfdif and sfdif flags in combination with the dfdie and sfdie interrupt enable bits to generate the flash error interrupt request. for a detailed de scription of the register bits involved, refer to section 5.24.3.2.5, ?flash configurati on register (fcnfg)" , section 5.24.3.2.6, ?flash error conf iguration register (fercnfg)" , section 5.24.3.2.7, ?flash status register (fstat)" , and section 5.24.3.2.8, ?flash error st atus register (ferstat)" . the logic used for generating the flash module interrupts is shown in figure 114 . figure 114. flash module interrupts implementation 5.24.4.7 wait mode the flash module is not affected if the mc u enters wait mode. the flash module can recover the mcu from wait via the ccif interrupt (see section 5.24.4.6, ?interrupts" ). 5.24.4.8 stop mode if a flash command is active (ccif = 0) when the mcu requests stop mode, the current flash op eration will be completed before the cpu is allowed to enter stop mode. 5.24.5 security the flash module provides security informati on to the mcu. the flash security state is defined by the sec bits of the fsec register (see table 473 ). during reset, the flash module initializes the fsec register using data read from the security byte of the flash configuration field at global address 0x3_ff0f. th e security state out of reset can be permanently changed by programming the security byte, assuming that the mcu is star ting from a mode where the necessa ry p-flash erase and program commands are available, and that the upper region of the p-flash is unprotected. if the flash security byte is successfully programmed, its new value will take affect after the next mcu reset. the following subsections describe these security-related subjects: ? unsecuring the mcu using backdoor key access ? unsecuring the mcu in special single chip mode using bdm ? mode and security effects on flash command availability 5.24.5.1 unsecuring the mcu using backdoor key access the mcu may be unsecured by using the backdoor key access fe ature, which requires knowle dge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x3_ff00-0x 3_ff07). if the keyen[1:0] bits are in the enabled state (see section 5.24.3.2.2, ?flash security register (fsec)" ), the verify backdoor access key command (see flash error interrupt request ccif ccie dfdif dfdie sfdif sfdie flash command interrupt request
mm912_637, rev. 3.0 freescale semiconductor 381 section 5.24.4.5.11, ?verify backdoor access key command" ) allows the user to present four prospective keys for comparison to the keys stored in the flash memory vi a the memory controller. if the keys presented in the verify backdoor access key command match the backdoor keys stored in the flash memory, the sec bits in the fsec register (see ta b l e 473 ) will be changed to unsecure the mcu. key values of 0x0000 and 0xffff are not permitted as backdoor keys. while the verify backdoor access key command is active, p-flash memory, and d-flash memory will not be available for read access and will return invalid data. the user code stored in the p- flash memory must have a method of receiving t he backdoor keys from an external stimulus. this external stimulus would typically be through one of the on-chip serial ports. if the keyen[1:0] bits are in the enabled state (see section 5.24.3.2.2, ?flash secu rity register (fsec)" ), the mcu can be unsecured by the backdoor key access sequence described below: 1. follow the command sequence for the verify backdoor access key command as explained in section 5.24.4.5.11, ?verify backdoor access key command" 2. if the verify backdoor access key comm and is successful, the mcu is unsecured and the sec[1:0] bits in the fsec register are forced to the unsecure state of 10 the verify backdoor access key command is monitored by the me mory controller and an illegal key will prohibit future use of the verify backdoor access key command. a reset of the mcu is the on ly method to re-enable the verify backdoor access key command. the security as defined in the flash security byte (0x3_ff0f) is not changed by using the verify backdoor access key command sequence. the backdoor keys stored in addresses 0x3_ff00-0x3_ff07 are unaffected by the verify backdoor access key command sequence. the verify backdoor access key command sequence has no effect on the program and erase protections defined in the flas h protection register, fprot. after the backdoor keys have been correctly matched, the m cu will be unsecured. after the mcu is unsecured, the sector containing the flash security byte can be erased and the flash security byte can be reprogrammed to the unsecure state, if desired. in the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x3_ff00-0x3_ff07 in the fl ash configuration field. 5.24.5.2 unsecuring the mcu in sp ecial single chip mode using bdm a secured mcu can be unsecured in special single chip mode by using the following method to erase the p-flash and d-flash memory: 1. reset the mcu into special single chip mode 2. delay while the bdm executes the erase verify all blocks command write sequence to check if the p-flash and d-flash memories are erased 3. send bdm commands to disable protec tion in the p-flash and d-flash memory 4. execute the erase all blocks command write sequence to erase the p-flash and d-flash memory 5. after the ccif flag sets to indicate th at the erase all blocks operation has comple ted, reset the mcu in to special single chip mode 6. delay while the bdm executes the erase verify all blo cks command write sequence to verify that the p-flash and d-flash memory are erased if the p-flash and d-flash memory are verified as erased, t he mcu will be unsecured. all bdm commands will now be enabled and the flash security byte may be programmed to the unsecure state by continuing with the following steps: 7. send bdm commands to execute the program p-flash command write sequence to program the flash security byte to the unsecured state 8. reset the mcu 5.24.5.3 mode and security eff ects on flash command availability the availability of flash module commands depends on the mcu operating mode and security state as shown in ta b l e 508 . 5.24.6 initialization on each system reset the flash module executes a reset s equence which establishes initial values for the flash block configuration parameters, the fprot and df prot protection registers, and the fopt and fsec registers. the flash module reverts to using built-in default values that leave the module in a fully protected and secured st ate if errors are encountered during
mm912_637, rev. 3.0 freescale semiconductor 382 execution of the reset sequence. if a double bit fault is detect ed during the reset sequence, both mgstat bits in the fstat register will be set. ccif remains clear throughout the reset se quence. the flash module holds off all cpu access for the initial portion of the rese t sequence. while flash memory reads and access to most flash regi sters are possible when the hold is removed, writes to the fccobix, fccobhi, and fccoblo registers are ignored. comple tion of the reset sequence is marked by setting ccif high which enables writes to the fccobix, fccobhi, and fc coblo registers to launch any available flash command. if a reset occurs while any flash command is in progress, that command will be immediately aborted. the state of the word being programmed or the sector/block being erased is not guaranteed.
mcu - die-to-die initiator (d2div1) mm912_637, rev. 3.0 freescale semiconductor 383 5.25 mcu - die-to-die initiator (d2div1) 5.25.0.1 acronyms and abbreviations table 547 contains sample acronyms and abbr eviations used in this document. 5.25.0.1.1 glossary table 548 shows a glossary of the major terms used in this document. 5.25.1 introduction this section describes the functi onality of the die-to-die (d2div1) initiator block especially designed for low cost connection s between a microcontroller die (interface initiator) and an anal og die (interface target) located in the same package. the d2di block ? realizes the initiator part of the d2d interface, including supervision and error interrupt generation ? generates the clock for this interface ? disables/enables the interrupt from the d2d interface 5.25.1.1 overview the d2di is the initiator for a data tran sfer to and from a target, typically loca ted on another die in the same package. it pr ovides a set of configuration registers and two memory mapped 256 byte address windows. wh en writing to a window a transaction is initiated, sending a write command followed, by an 8-bit address and the data byte or word to the target. when reading from a window, a transaction is initiated, sendi ng a read command, followed by an 8-bit address to the target. the target then respond s with the data. the basic idea is that a peripheral located on anot her die, can be addressed like an on-chip peripheral, except for a small transaction delay. table 547. acronyms and abbreviated terms term meaning d2d die-to-die table 548. glossary term definition active low the signal is asserted when it changes to logic-level zero. active high the signal is asserted when it changes to logic-level one. asserted discrete signal is in active logic state. customer the end user of an soc design or device. eot end of transaction negated a discrete signal is in inactive logic state. pin external physical connection. revision revised or new version of a document. revisions produce versio ns; there can be no ?rev 0.0.? signal electronic construct whose state or change in state conveys information. transfer a read or write on the cpu bus following the ip-bus protocol. transaction command, address and if required data sent on the d2d interfac e. a transaction is finished by the eot acknowledge cycle. version particular form or variation of an earlier or original document. analog mcu
mcu - die-to-die initiator (d2div1) mm912_637, rev. 3.0 freescale semiconductor 384 figure 115. die-to-die initiato r (d2di) block diagram 5.25.1.2 features the main features of this block are ? software transparent, memory mapped access to peripherals on target die ? 256 byte address window ? supports blocking read or write as we ll as non-blocking write transactions ? scalable interface clock divide by 1, 2, 3 and 4 of bus clock ? clock halt on system stop ? configurable for 4- or 8-bit wide transfers ? configurable timeout period ? non-maskable interrupt on transaction errors ? transaction status and error flags ? interrupt enable for receiving interrupt (from d2d target) 5.25.1.3 modes of operation 5.25.1.3.1 d2di in stop/wait mode the d2di stops working in stop/wait mode. the d2dclk signal as well as the data signals used are driven low (only after the end of the current high phase, as defined by d2dclkdiv). waking from stop/wait mode, the d2dclk line starts clocki ng again and the data lines will be driven low until the first transaction starts. stop and wait mode are entered by different cpu instructions. in the wait mode the behavior of the d2di can be configured (d2dswai). every (enabled) interrupt can be used to leave the stop and wait mode. d2dclk d2ddat[7:0] /n n=1 ? 8 bus clock d2dint d2dcw address and data buffer d2die address bus write data bus read data bus d2dinti d2derr_int xfr_wait d2dif d2dclkdiv
mcu - die-to-die initiator (d2div1) mm912_637, rev. 3.0 freescale semiconductor 385 5.25.1.3.2 d2di in special modes the mcu can enter a special mode (used for test and debugging purposes as well as programming the flash). in the d2di, the ?write-once? feature is disabled . see the mcu description for details. 5.25.2 external signal description the d2di optionally uses 6 or 10 port pins. the functions of t hose pins depends on the settings in the d2dctl0 register, when the d2di module is enabled. 5.25.2.1 d2dclk when the d2di is enabled, this pin is the clock output. this signa l is low if the initiator is disabled, in stop mode or in wai t mode (with d2dswai asserted), ot herwise it is a continuos clock. this pin ma y be shared with general purpose functionality if the d2di is disabled. 5.25.2.2 d2ddat[7:4] when the d2di is enabled and the interface connection width d2dcw is set to be 8-bit wide, those lines carry the data bits 7:4 acting as outputs or inputs. when they act as inputs pull-down elements are enabled. if the d2di is disabled or if the interfac e connection width is set as 4-bit wide, the pins may be shared with general purpose pin functionality. 5.25.2.3 d2ddat[3:0] when the d2di is enabled those lines carry the data bits 3:0 acting as outputs or inputs. when they act as inputs pull-down elements are enabled. if the d2di is disabled the pins and may be shared with general purpose pin functionality. 5.25.2.4 d2dint the d2dint is an active input interrupt input driven by the ta rget device. the pin has an active pull-down device. if the d2di is disabled, the pin may be shared with general purpose pin functionality. see the port interface module (pim) guid e for details of the gpio function. 5.25.3 memory map and register definition 5.25.3.1 memory map the d2di memory map is split into three sections. 1. an eight byte set of control registers 2. a 256 byte window for blocking transactions 3. a 256 byte window for non-blocking transactions table 549. signal properties name primary (d2den=1) i/o secondary (d2den=0) reset comment pull down d2ddat[7:0] bidirectional data lines i/o gpio 0 driven low if in stop mode active (303) d2dclk interface clock signal o gpio 0 low if in stop mode ? d2dint active high interrupt i gpio ? ? active (304) notes 303.active if in input state, only if d2den=1 304.only if d2den=1
mcu - die-to-die initiator (d2div1) mm912_637, rev. 3.0 freescale semiconductor 386 see the chapter ?device memory map? for the regi ster layout (distribut ion of these sections). figure 116. d2di top level memory map a summary of the registers associat ed with the d2di block is shown in table 550 . detailed descriptions of the registers and bits are given in the subsections that follow. table 550. d2di register summary offset register name bit 7 6 5 4 3 2 1 bit 0 0x0 d2dctl0 r d2den d2dcw d2dswai 0 0 0 d2dclkdiv[1:0] w 0x1 d2dctl1 d2die 0 0 0 timeout[3:0] 0x2 d2dstat0 r errif ackerf cnclf timef terrf parf par1 par0 w 0x3 d2dstat1 d2dif d2dbsy 0 0 0 0 0 0 0x4 d2dadrhi r rwb sz8 0 nblk 0 0 0 0 w 0x5 d2dadrlo r adr[7:0] w 0x6 d2ddatahi r data[15:8] w 0x7 d2ddatalo r data[7:0] w = unimplemented or reserved 8 byte control registers 256 byte window blocking access 256 byte window non-blocking write d2dregs d2dblk d2dnblk
mcu - die-to-die initiator (d2div1) mm912_637, rev. 3.0 freescale semiconductor 387 5.25.3.2 register definition 5.25.3.3 d2di control register 0 (d2dctl0) this register is used to enable and configure the interface wid th, the wait behavior and the frequency of the interface clock. the clock divider will provide the waveforms as shown in figure 117 . the duty cycle of the clock is not always 50%, the high cycle is shorter than 50% or equal but never longer, since this is beneficial for the transaction speed. figure 117. interface clock waveforms for various d2dclkdiv encoding table 551. d2di control register 0 (d2dctl0) offset 0x0 access: user read/write 7 6 5 4 3 2 1 0 r d2den d2dcw d2dswai 0 0 0 d2dclkdiv[1:0] w reset 0 0 0 0 0 0 0 0 table 552. d2dctl0 register field descriptions field description 7 d2den d2di enable ? enables the d2di module. this bit is write-once in normal mode and can always be written in special modes. 0 d2di initiator is disabled. no lines are not us ed, the pins have their gp io (secondary) function. 1 d2di initiator is enabled. after setting d2den=1 the d2ddat[7:0] (or [3:0], see d2dcw) lines are driven low with the idle command; the d2dclk is driven by the divided bus clock. 6 d2dcw d2d connection width ? sets the number of data lines used by the interf ace. this bit is write-once in normal modes and can always be written in special modes. 0 lines d2ddat[3:0] are used for four line data transfer. d2ddat[7:4] are unused. 1 all eight interface lines d2ddat [7:0] are used for data transfer. 5 d2dswai d2d stop in wait ? controls the wait behavior. this bit can be written at any time. 0 interface clock continues to run if the cpu enters wait mode 1 interface clock stops if the cpu enters wait mode. 4:2 reserved, should be written to 0 to ensure compatib ility with future versions of this interface. 1:0 d2dclkdiv interface clock divider ? determines the frequency of the interface cloc k. these bits are write-once in normal modes and can be always written in special modes. see figure 117 for details on the clock waveforms 00 encoding 0. bus clock divide by 1. 01 encoding 1. bus clock divide by 2. 10 encoding 2. bus clock divide by 3. 11 encoding 3. bus clock divide by 4. 00 01 10 11 bus clock
mcu - die-to-die initiator (d2div1) mm912_637, rev. 3.0 freescale semiconductor 388 5.25.3.4 d2di control register 1 (d2dctl1) this register is used to enable the d2 di interrupt and set number of d2dclk cycl es before a timeout error is asserted. note ?write-once? means that after writing d2dcnt l0.d2den=1 the write accesses to these bits have no effect. 5.25.3.5 d2di status register 0 (d2dstat0) this register reflects the st atus of the d2di transactions. table 553. d2di control register 1 (d2dctl1) offset 0x1 access: user read/write 7 6 5 4 3 2 1 0 r d2die 0 0 0 timout[3:0] w reset 0 0 0 0 0 0 0 0 table 554. d2dctl1 register field descriptions field description 7 d2die d2d interrupt enable ? enables the external interrupt 0 external interrupt is disabled 1 external interrupt is enabled 6:4 reserved, should be written to 0 to ensure compatib ility with future versions of this interface. 3:0 timout time-out setting ? defines the number of d2dclk cycles to wait after th e last transaction cycle unti l a timeout is asserted. in case of a timeout the timef flag in the d2dstat0 register will be set. these bits are write-once in normal modes and can always be written in special modes. 0000 the acknowledge is expected directly after the last tr ansfer, i.e. the target must not insert a wait cycle. 0001 - 1111: the target may insert up to timout wait states before acknowl edging a transaction until a timeout is asserted table 555. d2di status register 0 (d2dstat0) offset 0x2 access: user read/write 7 6 5 4 3 2 1 0 r errif ackerf cnclf timef terrf parf par1 par0 w reset 0 0 0 0 0 0 0 0 table 556. d2di status regist er 0 field descriptions field description 7 errif d2di error interrupt flag ? this status bit indicates that the d2d initia tor has detected an error c ondition (summary of the following five flags).this interrupt is not locally maskable. write a 1 to clear the flag. writing a 0 has no effect. 0 d2di has not detected an error during a transaction. 1 d2di has detected an error during a transaction. 6 ackerf acknowledge error flag ? this read-only flag indicates that in the ack nowledge cycle not all data inputs are sampled high, indicating a potential broken wire. this flag is cleared when t he errif bit is cleared by writing a 1 to the errif bit. 5 cnclf cnclf ? this read-only flag indicates the initiator has canceled a transaction and replaced it by an idle command due to a pending error flag (errif). this flag is cleared when the e rrif bit is cleared by writing a 1 to the errif bit. 4 timef time out error flag ? this read-only flag indicates the initiator has detected a time-out error. this flag is cleared when the errif bit is cleared by writing a 1 to the errif bit.
mcu - die-to-die initiator (d2div1) mm912_637, rev. 3.0 freescale semiconductor 389 5.25.3.6 d2di status register 1 (d2dstat1) this register holds the status of th e external interrupt pin and an indica tor about the d2di transaction status. 5.25.3.7 d2di address buffer register (d2dadr) this read-only register contains information about the ongoing d2d interface transaction. the re gister content will be updated when a new transaction starts. in error cases the user can track back, which transaction failed. 3 terrf transaction error flag ? this read-only flag indicates the initiator has det ected the error signal during the acknowledge cycle of the transaction. this flag is cleared when the errif bit is cleared by writing a 1 to the errif bit. 2 parf parity error flag ? this read-only flag indicates the initiator has detected a pa rity error. parity bits[1:0] contain further information. this flag is cleared when the errif bit is cleared by writing a 1 to the errif bit. 1 par1 parity bit ? p[1] as received by the d2di 0 par0 parity bit ? p[0] as received by the d2di table 557. d2di status register 1 (d2dstat1) offset 0x3 access: user read 7 6 5 4 3 2 1 0 r d2dif d2dbsy 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 table 558. d2dstat1 register field descriptions field description 7 d2dif d2d interrupt flag ? this read-only flag reflects the status of the d2 dint pin. the d2d interrupt flag can only be cleared by a target specific interrupt acknowledge sequence. 0 external interrupt is negated 1 external interrupt is asserted 6 d2dbsy d2d initiator busy ? this read-only status bit indica tes that a d2d transaction is ongoing. 0 d2d initiator idle. 1 d2d initiator transaction ongoing. 5:0 reserved, should be masked to ensure compatibilit y with future versions of this interface. table 559. d2di address buffer register (d2dadr) offset 0x4/0x5 access: user read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r rwb sz8 0 nblk 0 0 0 0 adr[7:0] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 556. d2di status register 0 field descriptions (continued) field description
mcu - die-to-die initiator (d2div1) mm912_637, rev. 3.0 freescale semiconductor 390 5.25.3.8 d2di data buffe r register (d2ddata) this read-only register contains information about the ongoing d2d interface transaction. fo r a write transaction, the data becomes valid at the begin of the transaction. for a read tr ansaction, the data will be updated during the transaction and is finalized when the transaction is acknowledged by the target. in error cases, the user can track back what has happened. both d2ddata and d2dadr can be read with byte accesses. 5.25.4 functional description 5.25.4.1 initialization out of reset the interface is disabled. t he interface must be initializ ed by setting the interface clock speed, the timeout val ue, the transfer width and finally enabling the interface. this should be done using a 16-bit write or if using 8-bit write d2dctl1 mus t be written before d2d2ctl0.d2den=1 is written. once it is enabled in normal modes, only a reset can disable it again (write-once feature). 5.25.4.2 transactions a transaction on the d2d interface is triggered by writing to either the 256 byte address window or reading from the address window (see staa/ldaa 0/1 in the next figure). depending on which address window is used, a blocking or a non-blocking transaction is performed. the address for the transaction is the 8-bit wide window relative address. the data width of the cpu table 560. d2di address buffer register bit descriptions field description 15 rwb transaction read-write direction ? this read-only bit reflects the direction of the transaction 0 write transaction 1 read transaction 14 sz8 transaction size ? this read-only bit reflects the data size of the transaction 0 16-bit transaction. 1 8-bit transaction. 13 reserved, should be masked to ensure compatibilit y with future versions of this interface. 12 nblk transaction mode ? this read-only bit reflects the mode of the transaction 0 blocking transaction. 1 non-blocking transaction. 11:8 reserved, should be masked to ensure compatibilit y with future versions of this interface. 7:0 adr[7:0] transaction address ? those read-only bits contai n the address of the transaction table 561. d2di data buffer register (d2ddata) offset 0x6/0x7 access: user read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r data15:0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 562. d2di data buffer register bit descriptions field description 15:0 data transaction data ? those read-only bits contain the data of the transaction
mcu - die-to-die initiator (d2div1) mm912_637, rev. 3.0 freescale semiconductor 391 read or write instructions dete rmines if 8-bit or 16-bit wide data are transfe rred. there is always only one transaction active . figure 118 shows the various types of transactions explained in more detail below. for all 16-bit read/write accesses of the cpu the a ddresses are assigned according the big-endian model: ? word [15:8]: addr word[7:0]: addr+1 ? addr: byte-address (8 bit wide) inside the blocking or non-blo cking window, as provided by the cpu and transferred to the d2d target word: cpu data, to be transferred from/to the d2d target the application must care for the stretched cpu cycles (limited by the timout value, caus ed by blocking or consecutive accesses), which could affect time limits, including cop (com puter operates properly) supervision. the stretched cpu cycles cause the ?cpu halted? phases (see figure 118 ). figure 118. blocking and non-blocking transfers. 5.25.4.2.1 blocking writes when writing to the address window associated with blocking transact ions, the cpu is held until the transaction is completed, before completing the instruction. figure 118 shows the behavior of the cpu for a bl ocking write transaction shown in the following example. staa blk_window+offs0 ; write0 8- bit as a blocking transaction ldaa #byte1 staa blk_window+offs1 ; write1 is executed after write0 transaction is completed nop blocking writes should be used when clearing interrupt flags, located in the target or other writes which require that the oper ation at the target, is completed before pr oceeding with the cpu instruction stream. 5.25.4.3 non-blocking writes when writing to the address window associated with non-blocking transactions, the cpu can continue before the transaction is completed. however, if there was an ongoing transaction when doing the 2nd write, the cpu is held until the first one is completed, and before executing the 2nd one. figure 118 shows the behavior of the cpu for a blocking write transaction shown in the following example. staa nonblk_window+offs 0; write 8-bit as a blocking transaction ldaa #byte1 ; load next byte staa nonblk_window+of fs1; executed right after the first nop as the figure illustrates, non-blocking writes have a performa nce advantage, but care must be ta ken that the following instruct ions are not affected by the change in the target caused by the previous transaction. staa 0 ldaa # staa 1 write transaction 0 write transaction 1 staa 0 ldaa # staa 1 write transaction 0 write transaction 1 nop nop cpu halted cpu halted cpu halted blocking write non-blocking write ldaa 0 ldaa 1 transaction 0 transaction 1 cpu halted cpu halted nop blocking read staa mem cpu activity cpu activity cpu activity d2d activity d2d activity d2d activity
mcu - die-to-die initiator (d2div1) mm912_637, rev. 3.0 freescale semiconductor 392 5.25.4.4 blocking read when reading from the address window associated with blocking transact ions, the cpu is held until the data is returned from the target, before completi ng the instruction. figure 118 shows the behavior of the cpu for a bl ocking read transaction shown in the following example. ldaa blk_window+offs0 ; read 8-bit as a blocking transaction staa mem ; store result to local memory ldaa blk_window+offs1 ; read 8-bit as a blocking transaction 5.25.4.5 non-blocking read read access to the non-blocking window is reserved for futu re use. when reading from t he address window associated with non-blocking writes, the read returns an all 0s data byte or word. this behavior can change in future revisions. 5.25.4.6 transfer width 8-bit wide writes or reads are translated into 8-bit wide interf ace transactions. 16-bit wide, al igned writes or reads are tran slated into a16-bit wide interface transactions. 16 -bit wide, misaligned writes or reads are split up into two consecutive 8-bit trans actions with the transaction on the odd address first followed by the tr ansaction on the next higher even address. due to the much more complex error handling (by the mcu), misaligned 16-bit transfers should be avoided. 5.25.4.7 error conditions and handling faults since the s12 cpu (as well as the s08) does not provide a me thod to abort a transfer once started, the d2di asserts a d2derrint. the errif flag is set in the d2dstat0 register. de pending on the error condition, further error flags will be set, as described below. the content of the address and data buffers are frozen and all transactions will be replaced by an idle command, until the error flag is cleared. if an error is detected during the read transaction of a read-modify-write instructio n, or a non-blocking write transaction was followed by another write or read transaction, the second transaction is cancelled. the cnclf is set in the d2dstat0 register to indicate that a tr ansaction has been cancelled. the d2derrint handler can read the address and data buffer register to assess the error situat ion. any further transaction will be replaced by idle until the errif is cleared. 5.25.4.7.1 missing acknowledge if the target detects a wrong command, it will not send back an a cknowledge. the same situation occurs if the acknowledge is corrupted. the d2di detects this missing acknowledge after t he timeout period configured in the timout parameter of the d2dctl1 register. in case of a timeout, the errif and the timef flags in the d2dstat0 register will be set. 5.25.4.7.2 parity error in the final acknowledge cycle of a transaction, the target sends two parity bits. if this parity does not match the parity cal culated by the initiator, the errif and the parf flags in the d2dstat0 register will be set. the par[1:0] bits contain the parity value received by the d2di. 5.25.4.7.3 error signal during the acknowledge cycle the target can signal a target specif ic error condition. if the d2di finds the error signal assert ed during a transaction, the errif and the terrf flags in the d2dstat0 register will be set.
mcu - die-to-die initiator (d2div1) mm912_637, rev. 3.0 freescale semiconductor 393 5.25.4.8 low power mode options 5.25.4.8.1 d2di in run mode in run mode, with the d2 d interface enable (d2den) bit in th e d2d control register 0 clear, th e d2di system is in a low-power, disabled state. d2d registers remain accessible, but clocks to the core of this module are disabled. on d2d lines the gpio function is activated. 5.25.4.8.2 d2di in wait mode d2di operation in wait mode depends upon the stat e of the d2dswai bit in d2d control register 0. ? if d2dswai is clear, the d2di operates no rmally when the cpu is in the wait mode ? if d2dswai is set and the cpu enters the wait mode, any pending transmission is completed. when the d2dclk output is driven low then the clock generat ion is stopped, all internal clocks to the d2di module are stopped as well and the module enters a power saving state. 5.25.4.8.3 d2di in stop mode if the cpu enters the stop mode, the d2 di shows the same behavior as for the wa it mode with an activated d2dswai bit. 5.25.4.8.4 reset in case of reset any transaction is immediat ely stopped and the d2di module is disabled. 5.25.4.8.5 interrupts the d2di only originates interrupt requests when d2di is enabled (d2die bit in d2dctl0 set). there are two different interrupt requests from the d2d module. the interrupt vector offset and interrupt priority are chip dependent. 5.25.4.8.5.1 d2d external interrupt this is a level sensitive active high external interrupt driven by the d2dint input. this interrupt is enabled if the d2die bit in the d2dctl1 register is set. the interrupt must be cleared using an target specific clea ring sequence. the status of the d2d input pin can be observed by reading the d2dif bit in the d2dstat1 register. the d2dinit signal is also asserted in the wait an d stop mode; it can be used to leave these modes. figure 119. d2d external interrupt scheme 5.25.4.8.5.2 d2d error interrupt those d2d interface specific interrupts ar e level sensitive and are all cleared by wr iting a 1 to the errif flag in the d2dstat 0 register. this interrupt is not locally maskable and should be tied to the highest possible interrupt level in the system, on a n s12 architecture to the xirq. see the chapter ?v ectors? of the mcu description for details. d2die d2dint d2dinti to read data bus (d2dstat1.d2dif)
mcu - die-to-die initiator (d2div1) mm912_637, rev. 3.0 freescale semiconductor 394 figure 120. d2d internal interrupts 5.25.5 initialization information during initialization, the transfer width, clock divider, and timeout value must be set according to the capabilities of the ta rget device before starting any transaction. se e the d2d target specification for details. 5.25.6 application information 5.25.6.1 entering low power mode the d2di module is typically used on a microcontroller alon g with an analog companion device containing the d2d target interface and supplying the power. interface specification does not provide special wires for signalling low power modes to the target device. the cpu should determine when it is time to en ter one of the above power modes.the basic flow is as follows: 1. cpu determines there is no more work pending. 2. cpu writes a byte to a register on the analog die using blocking write configuring which mode to enter. 3. analog die acknowledges that write sending back an acknowledge symbol on the interface. 4. cpu executes wait or stop command. 5. analog die can enter low power mode - (s12 needs some more cycles to stack data!) ; example shows s12 code sei ; disable interrupts during test ; check is there is work pending? ; if yes, branch off and re-enable interrupt ; else ldaa #stop_entry staa mode_reg ; store to the analog die mode reg (use blocking write here) cli ; re-enable right befo re the stop instruction stop ; stack and turn off all clocks inc. interface clock for wake-up from stop the basic flow is as follows: 1. analog die detects a wake-up condition e.g. on a switch input or start bit of a lin message. 2. analog die exits voltage regulator low power mode. 3. analog die asserts the interrupt signal d2dint. 4. cpu starts clock generation. 5. cpu enters interrupt handler routine. 6. cpu services interrupt and acknowle dges the source on the analog die. note entering stop mode or wait mode with d2dswai asserted, the clock will complete the high duty cycle portion and settle at a low level. ackerf cnclf timef terrf parf errif d2den d2derrint 1
mm912_637 - trimming mm912_637, rev. 3.0 freescale semiconductor 395 6 mm912_637 - trimming 6.1 introduction to ensure the high precision requirements over a wide temperature an d lifetime range, the mm912_ 637 uses several trimming and calibration techniques. due to the advantage of the flash te chnology available in the microc ontroller die, several factory trimmed values can be used to in crease the overall device accuracy. trimming will use factory measured and calculat ed values stored in the microcontroller irf (information register) to be loaded into specific registers in the mcu and analog die at system power up. calibration would be done during operation of the system using internal references or specif ic measurement procedures. as calibration is an essential part of the signal acquisition, see section 5.7.5, ?calibration" as part of section 5.7, ?channel acquisition" . note the mm912_637 trimming is primarily used to achieve the specified analog die parameters. the only valid trimming of the mcu die, the internal oscillator trimming (icg) will be automatically stored into the mcu tr imming register during power up. see section 5.22.3.2.15, ?s12cpmu irc1m tr im registers (cpmuirctrimh / cpmuirctriml)" . 6.2 ifr trimming content and location all device trimming information are stored in the mcu information register (ifr) located at the following address. see also section 5.24, ?128 kbyte flash module (s12ftmrc128k1v1)" . note the program once reserved field can be read using the read once command as described in section 5.24.4.5.4, ?read once command" . 6.2.1 ifr - trimming content for analog die functionality the following table shows the details of the 64 byte (0x0_ 40c0 ? 0x0_40ff) program once field content used to store the analog die trimming information. refer to section 5.24.4.5.4, ?read once command" , for access instructions. table 563. ifr location global address (ifron) size (bytes) field description 0x0_4000 ? 0x0_4007 8 unique device id 0x0_4008 ? 0x0_40b5 174 reserved 0x0_40b6 ? 0x0_40b7 2 version id (305) 0x0_40b8 ? 0x0_40bf 8 reserved 0x0_40c0 ? 0x0_40ff 64 analog die trimming information (program once field) notes 305.used to track firmware patch versions, see section 5.24.4.2, ?ifr version id word" .
mm912_637 - trimming mm912_637, rev. 3.0 freescale semiconductor 396 table 564. analog die trimming information global address (ifron) offset byte description target register hex dec 7 6 5 4 3 2 1 0 name offset 0x0_40c0 00 00 igc4[9:8] comp_ig4 (hi) 0xb0 0x0_40c1 01 01 igc4[7:0] comp_ig4 (lo) 0x0_40c2 02 02 igc8[9:8] comp_ig8 (hi) 0xb2 0x0_40c3 03 03 igc8[7:0] comp_ig8 (lo) 0x0_40c4 04 04 igc16[9:8] comp_ig16 (hi) 0xb4 0x0_40c5 05 05 igc16[7:0] comp_ig16 (lo) 0x0_40c6 06 06 igc32[9:8] comp_ig32 (hi) 0xb6 0x0_40c7 07 07 igc32[7:0] comp_ig32 (lo) 0x0_40c8 08 08 igc64[9:8] comp_ig64 (hi) 0xb8 0x0_40c9 09 09 igc64[7:0] comp_ig64 (lo) 0x0_40ca 0a 10 igc128[9:8] comp_ig128 (hi) 0xba 0x0_40cb 0b 11 igc128[7:0] comp_ig128 (lo) 0x0_40cc 0c 12 igc256[9:8] comp_ig256 (hi) 0xbc 0x0_40cd 0d 13 igc256[7:0] comp_ig256 (lo) 0x0_40ce 0e 14 igc512[9:8] comp_ig512 (hi) 0xbe 0x0_40cf 0f 15 igc512[7:0] comp_ig512 (lo) 0x0_40d0 10 16 tcibg2[2:0] slpbg[2:0] trim_bg0 (hi) 0xe0 0x0_40d1 11 17 ibg2[2:0] ibg1[2:0] trim_bg0 (lo) 0xe1 0x0_40d2 12 18 ubg 3 dbg 3 tcbg2[2:0] tcbg1[2:0] trim_bg1 (hi) 0xe2 0x0_40d3 13 19 slpbg[2:0] trim_bg1 (lo) 0xe3 0x0_40d4 14 20 v1p2bg2[3:0] v1p2bg1[3:0] trim_bg2 (hi) 0xe4 0x0_40d5 15 21 v2p5bg2[3:0] v2p5bg1[3:0] trim_bg2 (lo) 0xe5 0x0_40d6 16 22 lin trim_lin 0xe6 0x0_40d7 17 23 lvt trim_lvt 0xe7 0x0_40d8 18 24 lposc[12:8] trim_osc (hi) 0xe8 0x0_40d9 19 25 lposc[7:0] trim_osc (lo) 0xe9 0x0_40da 1a 26 voc_s[7:0] comp_vos 0xaa (306) 0x0_40db 1b 27 voc_o[7:0] comp_voo 0xaa (306) 0x0_40dc 1c 28 voc_s[7:0] (chopper mode) comp_vos_chop 0xaa (306) 0x0_40dd 1d 29 voc_o[7:0] (chopper mode) comp_voo_chop 0xaa (306) 0x0_40de 1e 30 vsgc[9:8] comp_vsg (hi) 0xac (306) 0x0_40df 1f 31 vsgc[7:0] comp_vsg (lo) 0x0_40e0 20 32 vogc[9:8] comp_vog (hi) 0xac (306) 0x0_40e1 21 33 vogc[7:0] comp_vog (lo) 0x0_40e2 22 34 ito[7:0] comp_ito 0xd0 0x0_40e3 23 35 itg[7:0] comp_itg 0xd1 0x0_40e4 24 36 bg3 diag measurement from vsense channel after cal at room gain_cal_vsense_room (hi) n.a. 0x0_40e5 25 37 gain_cal_vsense_room (lo) n.a. 0x0_40e6 26 38 bg3 diag measurement from vopt channel after cal at room gain_cal_vopt_room (hi) n.a. 0x0_40e7 27 39 gain_cal_vopt_room (lo) n.a.
mm912_637 - trimming mm912_637, rev. 3.0 freescale semiconductor 397 0x0_40e8 28 40 bg3 diag measurement from i channel (gain4) at room gain_cal_ig4_room (hi) n.a. 0x0_40e9 29 41 gain_cal_ig4_room (med) n.a. 0x0_40ea 2a 42 gain_cal_ig4_room (lo) n.a. 0x0_40eb 2b 43 reserved 0x0_40ec 2c 44 comp_vsg_cold[7:0] vsense channel gain compensation - cold temp (307) n.a. 0x0_40ed 2d 45 comp_vsg_hot[7:0] vsense channel gain compensation - hot temp (307) n.a. 0x0_40ee 2e 46 comp_vog_cold[7:0] vopt channel gain compensation - cold temp (307) n.a. 0x0_40ef 2f 47 comp_vog_hot[7:0] vopt channel gain compensation - hot temp (307) n.a. 0x0_40f0 30 48 igc4_cold[7:0] current channel gain (4) compensation - cold temp (307) n.a. 0x0_40f1 31 49 igc4_hot[7:0] current channel gain (4) compensation - hot temp (307) n.a. 0x0_40f2 32 50 igc8_cold[7:0] current channel gain (8) compensation - cold temp (307) n.a. 0x0_40f3 33 51 igc8_hot[7:0] current channel gain (8) compensation - hot temp (307) n.a. 0x0_40f4 34 52 igc16_cold[7:0] current channel gain (16) compensation - cold temp (307) n.a. 0x0_40f5 35 53 igc16_hot[7:0] current channel gain (16) compensation - hot temp (307) n.a. 0x0_40f6 36 54 igc32_cold[7:0] current channel gain (32) compensation - cold temp (307) n.a. 0x0_40f7 37 55 igc32_hot[7:0] current channel gain (32) compensation - hot temp (307) n.a. 0x0_40f8 38 56 igc64_cold[7:0] current channel gain (64) compensation - cold temp (307) n.a. 0x0_40f9 39 57 igc64_hot[7:0] current channel gain (64) compensation - hot temp (307) n.a. 0x0_40fa 3a 58 igc128_cold[7:0] current channel gain (128) compensation - cold temp (307) n.a. 0x0_40fb 3b 59 igc128_hot[7:0] current channel gain (128) compensation - hot temp (307) n.a. 0x0_40fc 3c 60 igc256_cold[7:0] current channel gain (256) compensation - cold temp (307) n.a. 0x0_40fd 3d 61 igc256_hot[7:0] current channel gain (256) compensation - hot temp (307) n.a. 0x0_40fe 3e 62 igc512_cold[7:0] current channel gain (512) compensation - cold temp (307) n.a. 0x0_40ff 3f 63 igc512_hot[7:0] current channel gain (512) compensation - hot temp (307) n.a. notes 306.based on the selection of the voltage measurement so urce (vsense or vopt) and the activation of chopper mode. 307.7 bit character with bit 7 (msb) as sign (0 = ?+?; 1 = ?-?) with the difference to the corresponding room temperature value ? (e.g. 10000010 = ?-2?). table 564. analog die trimming information global address (ifron) offset byte description target register hexdec76543210 name offset
mm912_637 - trimming mm912_637, rev. 3.0 freescale semiconductor 398 6.2.2 analog die trimming overview 6.2.2.1 current channel gain compen sation trim (comp_ig4-comp_ig512) to achieve the specified accuracy of the cu rrent acquisition, the optimum trim value is calculated during final test and stored into the mcu flash memory. on device every power up, the corresponding trim value needs to be copied into the corresponding analog register via d2d interface. see section 5.7, ?channel acquisition" for additional details. 6.2.2.2 bandgap reference trimming (trim_bg0-trim_bg2) to achieve the specified accuracy of the in tegrated voltage regulators on the analog di e, the optimum trim value is calculated during final test and stored into the mcu flash memory. on dev ice every power up, the corresponding trim value needs to be copied into the desired analog register via d2d interface. 6.2.2.3 lin slope control trimming (trim_lin) to achieve the specified slope of the lin output signal, the op timum trim information is determined during final test and store d into the ifr register block of the mcu flash memory. on de vice every power up, the corresponding trim value needs to be copied into the desired analog register via d2d interface. 6.2.2.4 low voltage threshold trim (trim_lvt) to achieve the specified low voltage behavior, on device every pow er up, the corresponding trim value (lvr) needs to be copied into the corresponding analog trim register via d2d interface. 6.2.2.5 low power oscilla tor trimming (trim_osc) to achieve the specified accuracy of the analog low power reference frequency (f tol_a ), the optimum trim value is calculated during final test and stored into the ifr register block of th e mcu flash memory. on device every power up, the corresponding trim value needs to be copied into the desired analog register via d2d interface. 6.2.2.6 voltage channel compensation (comp_vox, comp_vsg, comp_vog) to achieve the specified accuracy of the voltage channels, gain and offset compensation are tri mmed during final test and store d into the ifr register block of the mcu flash memory. the info rmation is used during the calibration procedure described in section 5.7.5, ?calibration" .
mm912_637 - trimming mm912_637, rev. 3.0 freescale semiconductor 399 6.2.2.7 temperature sense module trimming (comp_ito, comp_itg) to achieve the specified accuracy of the internal temperature sense module, the optimum trim information is determined during final test at hot / cold temper ature and stored into the ifr r egister block of the mcu flash memory. on device every power up, the corresponding trim value needs to be copied in to the desired analog register via d2d interface. 6.2.2.8 band gap reference - diagno stic measurements (gain_cal_x_x) to achieve the specified accuracy of the voltage and current ch annels, reference measurements are performed during final test and stored for different temperatures into the ifr register bl ock of the mcu flash memory. the information is used during the calibration procedure described in section 5.7.5, ?calibration" . 6.2.2.9 hot / cold gain comp ensation data (0 x0_40ec...0x0_40ff) to achieve the specified accuracy of the voltage and current ch annels, reference measurements are performed during final test and stored for different temperatures into the ifr register bl ock of the mcu flash memory. the information is used during the calibration procedure described in section 5.7.5, ?calibration" . 6.3 memory map and registers 6.3.1 overview this section provides a detailed description of the memory map and registers for the analog die trimming excluding registers us ed for calibration located from offset 0xe0 to 0xef. refer to section 5.7.5, ?calibration" for details on current channel gain compensation trim (comp_ig4-comp_ig512) , voltage channel compensation (comp_vox, comp_vsg, comp_vog) , temperature sense module trim ming (comp_ito, comp_itg) , band gap reference - diagnostic measurements (gain_cal_x_x) and hot / cold gain compensation data (0x0_40ec...0x0_40ff) . 6.3.2 module memory map the memory map for the compensation module is given below in ta b l e 565 . table 565. module memory map offset (308) name 7 6 5 4 3 2 1 0 0xe0 trim_bg0 (hi) r 0 0 tcibg2[2:0] tcibg1[2:0] trim bandgap 0 w 0xe1 trim_bg0 (lo) r 0 0 ibg2[2:0] ibg1[2:0] trim bandgap 0 w 0xe2 trim_bg1 (hi) r ubg3 dbg3 tcbg2[2:0] tcbg1[2:0] trim bandgap 1 w 0xe3 trim_bg1 (lo) r 0 0 0 0 0 slpbg[2:0] trim bandgap 1 w 0xe4 trim_bg2 (hi) r v1p2bg2[3:0] v1p2bg1[3:0] trim bandgap 2 w 0xe5 trim_bg2 (lo) r v2p5bg2[3:0] v2p5bg1[3:0] trim bandgap 2 w 0xe6 trim_lin r 0 0 0 0 0 0 0 lin trim lin w
mm912_637 - trimming mm912_637, rev. 3.0 freescale semiconductor 400 6.3.2.1 trim bandgap 0 (trim_bg0 (hi)) 6.3.2.2 trim bandgap 0 (trim_bg0 (lo)) 0xe7 trim_lvt r 0 0 0 0 0 0 0 lvt trim low voltage threshold w 0xe8 trim_osc (hi) r trim lp oscillator w lposc[12:0] 0xe9 trim_osc (lo) r trim lp oscillator w 0xea- 0xef reserved r 0 0 0 0 0 0 0 0 w notes 308.offset related to 0x0200 for blocki ng access and 0x300 for non blocking access within the global address space. table 566. trim bandgap 0 (trim_bg0 (hi)) offset (309) 0xe0 access: user read/write 7 6 5 4 3 2 1 0 r 0 0 tcibg2[2:0] tcibg1[2:0] w reset 0 0 0 0 0 0 0 0 notes 309.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space. table 567. trim bandgap 0 (trim_bg0 (h i)) - register field descriptions field description 5-3 tcibg2[2:0] the optimal content of this register is determined during final test and stored in t he microcontroller ifr. for proper operatio n of the mm912_637, the content has to be copied to this location. see section 6.2.1, ?ifr - trimming content for analog die functionality" for location information. 2-0 tcibg1[2:0] table 568. trim bandgap 0 (trim_bg0 (lo)) offset (310) 0xe1 access: user read/write 7 6 5 4 3 2 1 0 r 0 0 ibg2[2:0] ibg1[2:0] w reset 0 0 0 0 0 0 0 0 notes 310.offset related to 0x0200 for blocking access and 0x300 fo r non blocking access within the global address space. table 565. module memory map offset (308) name 76543210
mm912_637 - trimming mm912_637, rev. 3.0 freescale semiconductor 401 6.3.2.3 trim bandgap 1 (trim_bg1 (hi)) 6.3.2.4 trim bandgap 1 (trim_bg1 (lo)) table 569. trim bandgap 0 (trim_bg0 (l o)) - register field descriptions field description 5-3 ibg2[2:0] the optimal content of this register is determined during final test and stored in the microcontroller ifr. for proper operatio n of the mm912_637, the content has to be copied to this location. see section 6.2.1, ?ifr - trimming content for analog die functionality" for location information. 2-0 ibg1[2:0] table 570. trim bandgap 1 (trim_bg1 (hi)) offset (311) 0xe2 access: user read/write 7 6 5 4 3 2 1 0 r ubg3 dbg3 tcbg2[2:0] tcbg1[2:0] w reset 0 0 0 0 0 0 0 0 notes 311.offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. table 571. trim bandgap 1 (trim_bg1 (h i)) - register field descriptions field description 7 ubg3 the optimal content of this register is determined during final test and stored in the microcontroller ifr. for proper operatio n of the mm912_637, the content has to be copied to this location. see section 6.2.1, ?ifr - trimming content for analog die functionality" for location information. 6 dbg3 5-3 tcbg2[2:0] 2-1 tcbg1[2:0] table 572. trim bandgap 1 (trim_bg1 (lo)) offset (312) 0xe3 access: user read/write 7 6 5 4 3 2 1 0 r 0 0 0 0 0 slpbg[2:0] w reset 0 0 0 0 0 0 0 0 notes 312.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within th e global address space. table 573. trim bandgap 1 (trim_bg1 (l o)) - register field descriptions field description 2-0 slpbg[2:0] the optimal content of this register is determined during final test and stored in the microcontroller ifr. for proper operatio n of the mm912_637, the content has to be copied to this location. see section 6.2.1, ?ifr - trimming content for analog die functionality" for location information.
mm912_637 - trimming mm912_637, rev. 3.0 freescale semiconductor 402 6.3.2.5 trim bandgap 2 (trim_bg2 (hi)) 6.3.2.6 trim bandgap 2 (trim_bg2 (lo)) table 574. trim bandgap 2 (trim_bg2 (hi)) offset (313) 0xe4 access: user read/write 7 6 5 4 3 2 1 0 r v1p2bg2[3:0] v1p2bg1[3:0] w reset 0 0 0 0 0 0 0 0 notes 313.offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. table 575. trim bandgap 2 (trim_bg2 (h i)) - register field descriptions field description 7-4 v1p2bg2[3:0 the optimal content of this register is determined during final test and stored in the microcontroller ifr. for proper operatio n of the mm912_637, the content has to be copied to this location. see section 6.2.1, ?ifr - trimming content for analog die functionality" for location information. 3-0 v1p2bg1[3:0 table 576. trim bandgap 2 (trim_bg2 (hi)) offset (314) 0xe5 access: user read/write 7 6 5 4 3 2 1 0 r v2p5bg2[3:0] v2p5bg1[3:0] w reset 0 0 0 0 0 0 0 0 notes 314.offset related to 0x0200 for blocki ng access and 0x300 for non blocking ac cess within the global address space. table 577. trim bandgap 2 (trim_bg2 (h i)) - register field descriptions field description 7-4 v2p5bg2[3:0 the optimal content of this register is determined during final test and stored in the microcontroller ifr. for proper operatio n of the mm912_637, the content has to be copied to this location. see section 6.2.1, ?ifr - trimming content for analog die functionality" for location information. 3-0 v2p5bg1[3:0
mm912_637 - trimming mm912_637, rev. 3.0 freescale semiconductor 403 6.3.2.7 trim lin (trim_lin) 6.3.2.8 trim low voltage threshold (trim_lvt) table 578. trim lin (trim_lin) offset (315) 0xe6 access: user read/write 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 lin w reset 0 0 0 0 0 0 0 0 notes 315.offset related to 0x0200 for blocki ng access and 0x300 for non blocking acce ss within the global address space. table 579. trim lin (trim_lin) - register field descriptions field description 0 lin the optimal content of this register is determined during final test and stored in t he microcontroller ifr. for proper operatio n of the mm912_637, the content has to be copied to this location. see section 6.2.1, ?ifr - trimming content for analog die functionality" for location information. table 580. trim low voltage threshold (trim_lvt) offset (316) 0xe7 access: user read/write 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 lvt w reset 0 0 0 0 0 0 0 0 notes 316.offset related to 0x0200 for bloc king access and 0x300 for non blocking access within th e global address space. table 581. trim low voltage threshold (trim_lvt) - register field descriptions field description 0 lvt the optimal content of this register is determined during final test and stored in t he microcontroller ifr. for proper operatio n of the mm912_637, the content has to be copied to this location. see section 6.2.1, ?ifr - trimming content for analog die functionality" for location information.
mm912_637 - trimming mm912_637, rev. 3.0 freescale semiconductor 404 6.3.2.9 trim lp oscillator (t rim_osc (hi), trim_osc (lo)) table 582. trim lp oscillator (trim_osc (hi), trim_osc (lo)) offset (317) 0xe8 access: user read/write 7 6 5 4 3 2 1 0 r lposc[12:8] w reset 0 0 0 0 0 0 0 0 r lposc[7:0] w reset 0 0 1 1 1 1 1 1 notes 317.offset related to 0x0200 for bloc king access and 0x300 for non blocking acce ss within the global address space. table 583. trim lp oscillator (trim_osc (hi), trim_osc (lo)) - register field descriptions field description 12-0 lposc[12:0] the optimal content of this register is determined during final test and stored in t he microcontroller ifr. for proper operatio n of the mm912_637, the content has to be copied to this location. see section 6.2.1, ?ifr - trimming content for analog die functionality" for location information.
packaging mm912_637, rev. 3.0 freescale semiconductor 405 7 packaging 7.1 package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. ep suffix 48 pin qfn qfn48ld-ep revision d
packaging mm912_637, rev. 3.0 freescale semiconductor 406 ep suffix 48 pin qfn qfn48ld-ep revision d
packaging mm912_637, rev. 3.0 freescale semiconductor 407 ep suffix 48 pin qfn qfn48ld-ep revision d
packaging mm912_637, rev. 3.0 freescale semiconductor 408 ep suffix 48 pin qfn qfn48ld-ep revision d
packaging mm912_637, rev. 3.0 freescale semiconductor 409 ep suffix 48 pin qfn qfn48ld-ep revision d
packaging mm912_637, rev. 3.0 freescale semiconductor 410 ep suffix 48 pin qfn qfn48ld-ep revision d
packaging mm912_637, rev. 3.0 freescale semiconductor 411 ep suffix 48 pin qfn qfn48ld-ep revision d
revision history mm912_637, rev. 3.0 freescale semiconductor 412 8 revision history revision date description of changes 1.0 4/2011 ? initial release 2.0 8/2011 ? minor changes throughout the document 3.0 1/2012 ? minor description changes and logo to align this data sh eet to the xtrinsic product platform. no content was altered.
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