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nand flash and mobile lpdram 168-ball package-on-package (pop) mcp combination memory (ti omap ? ) mt29cxgxxmaxxxxx features ? micron ? nand flash and lpdram components ? rohs-compliant, green package ? separate nand flash and lpdram interfaces ? space-saving multichip package/package-on-package combination ? low-voltage operation (1.70C1.95v) ? industrial temperature range: C40c to +85c nand flash-specific features organization ? page size C x8: 2112 bytes (2048 + 64 bytes) C x16: 1056 words (1024 + 32 words) ? block size: 64 pages (128k + 4k bytes) mobile lpdram-specific features ? no external voltage reference required ? no minimum clock rate requirement ? 1.8v lvcmos-compatible inputs ? programmable burst lengths ? partial-array self refresh (pasr) ? deep power-down (dpd) mode ? selectable output drive strength ? status register read (srr) supported 1 figure 1: pop block diagram nand flash device nand flash power nand flash interface lpdram power lpdram interface lpdram device options 2 marking ? mobile lpdram C 200 mhz cl3 3 -5 C 166 mhz cl3 -6 C 133 mhz cl3 -75 notes: 1. contact factory for remapped srr output. 2. for part numbering and physical part mark- ings, see figure 2 (page 2) and table 1 (page 3). 3. cl = cas (read) latency. preliminary ? 168-ball nand flash and lpdram pop (ti omap) mcp features pdf: 09005aef83070ff3 168ball_nand_lpdram_j4xx_omap.pdf - rev. i 6/09 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2007 micron technology, inc. all rights reserved. ?products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet microns production data sheet specifications.
part numbering information micron nand flash and lpdram devices are available in different configurations and densities. figure 2: 168-ball part number chart mt 29c 2g 24m a k l a jg -6 it es micron technology product family 29c = nand + lpdram mcp nand density 1g = 1gb 2g = 2gb 4g = 4gb lpdram density 12m = 512mb 24m = 1024mb 48m = 2048mb operating voltage range a = 1.8v (1.70C1.95v) production status blank = production es = engineering sample ms = mechanical sample operating temperature range it = industrial (C40 to +85c) lpdram self refresh current blank = standard lpdram access time -5 = 200 mhz cl3 -6 = 166 mhz cl3 -75 = 133 mhz cl3 package codes jg = 168-ball pop (ti omap) (12 x 12 x 0.9mm) ji = 168-ball pop (ti omap) (12 x 12 x 1.1mm) kq = 168-ball pop (ti omap) (12 x 12 x 0.75mm) nand flash configuration width density generation c x8 1gb first d x16 1gb first j x8 2gb second k x16 2gb second n x8 4gb first p x16 4gb first y x8 4gb second z x16 4gb second chip count ce#, cs# chip count a 1, 1 1 nand, 1 lpdram b 1, 1 2 nand, 1 lpdram c 1, 2 1 nand, 2 lpdram d 1, 2 2 nand, 2 lpdram lpdram configuration type width density generation j ddr x16 1gb first l ddr x32 1gb first n ddr x16 512mb second r ddr x32 512mb second am ddr x16 2gb first ap ddr x32 2gb first note: 1. not all possible combinations are available. contact factory for availability. preliminary 168-ball nand flash and lpdram pop (ti omap) mcp part numbering information pdf: 09005aef83070ff3 168ball_nand_lpdram_j4xx_omap.pdf - rev. i 6/09 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2007 micron technology, inc. all rights reserved.
table 1: production part numbers part number nand product lpddr product physical part marking mt29c2g24maklajg-6 it mt29f2g16abdhc-et mt46h32m32lfjg-6 it jw192 mt29c2g24maklajg-75 it mt29f2g16abdhc-et mt46h32m32lfjg-6 it jw193 mt29c2g48maklcji-6 it mt29f2g16abdhc-et mt46h32m32lfjg-6 it jw256 mt29c2g48maklcji-75 it mt29f2g16abdhc-et mt46h32m32lfjg-6 it jw255 mt29c4g48maplcjg-6 it mt29f4g16abcwc-et mt46h32m32lfjg-6 it jw426 mt29c4g48maplcji-6 it mt29f4g16abcwc-et mt46h32m32lfjg-6 it jw295 mt29c4g48maplcji-75 it mt29f4g16abcwc-et mt46h32m32lfjg-6 it jw294 device marking due to the size of the package, the micron-standard part number is not printed on the top of the device. instead, an abbreviated device mark consisting of a 5-digit alphanu- meric code is used. the abbreviated device marks are cross-referenced to the micron part numbers at the fbga part marking decoder site: www.micron.com/decoder . to view the location of the abbreviated mark on the device, refer to customer service note csn-11, product mark/label, at www.micron.com/csn . preliminary 168-ball nand flash and lpdram pop (ti omap) mcp part numbering information pdf: 09005aef83070ff3 168ball_nand_lpdram_j4xx_omap.pdf - rev. i 6/09 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2007 micron technology, inc. all rights reserved.
mcp general description micron package-on-package (pop) mcp products combine nand flash and mobile lpdram devices in a single mcp. these products target mobile applications with low- power, high-performance, and minimal package-footprint design requirements. the nand flash and mobile lpdram devices are also members of the micron discrete mem- ory products portfolio. the nand flash and mobile lpdram devices are packaged with separate interfaces (no shared address, control, data, or power balls). this bus architecture supports an op- timized interface to processors with separate nand flash and mobile lpdram buses. the nand flash and mobile lpdram devices have separate core power connections and share a common ground (that is, vss is tied together on the two devices). the bus architecture of this device also supports separate nand flash and mobile lpdram functionality without concern for device interaction. operational characteris- tics for the nand flash and mobile lpdram devices are found in the standard micron data sheets for each of the discrete devices. for device specifications and complete micron nand flash features documentation, refer to the component data sheet at www.micron.com/nand , or contact your local mi- cron sales office. for device specifications and complete mobile lpdram features documentation, refer to the component data sheet at www.micron.com/products/mobiledram , or contact your local micron sales office. preliminary 168-ball nand flash and lpdram pop (ti omap) mcp mcp general description pdf: 09005aef83070ff3 168ball_nand_lpdram_j4xx_omap.pdf - rev. i 6/09 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2007 micron technology, inc. all rights reserved.
ball assignments and descriptions figure 3: 168-ball vfbga (nand x8; lpddr x16) ball assignments 1 dnu dnu nc nc vddq nc nc vddq nc vdd vcc i/o1 i/o3 vcc i/o5 i/o7 vcc we# ale ce1# vcc dnu dnu 1 2 dnu dnu nc nc vssq nc nc vssq nc vss vss i/o0 i/o2 vss i/o4 i/o6 vss re# nc ce0# vss dnu dnu 2 4 vddq vssq rfu rfu 4 3 dq14 dq15 rfu rfu 3 5 dq12 dq13 vss vcc 5 6 udm udqs rfu rfu 6 7 vddq vssq rfu rfu 7 8 dq10 dq11 vss vcc 8 12 vdd vss r/b# cle 12 13 dq6 dq7 vss vcc 13 14 dq4 dq5 vss tq 14 15 vddq vssq nc nc 15 16 dq2 dq3 nc nc 16 17 ldm ldqs nc nc 17 18 vddq vssq nc nc 18 19 dq0 dq1 nc nc 19 20 nc nc vss nc 20 21 nc nc ba0 ba1 21 22 dnu dnu vssq nc nc vssq nc vss cke0 vss cas# cs0# a0 a2 a4 a6 a8 a10 a12 a14 vss dnu dnu 22 23 dnu dnu vddq nc nc vddq nc vdd cke1 we# ras# cs1# a1 a3 a5 a7 a9 a11 a13 vdd vdd dnu dnu 23 a b c d e f g h j k l m n p r t u v w y aa ab ac a b c d e f g h j k l m n p r t u v w y aa ab ac top view C ball down 9 dq8 dq9 lock nc 9 10 vddq vssq wp# nc 10 11 ck ck# nc nc 11 nand lpddr supply ground note: 1. contact factory for availability of x16 lpddr configuration. preliminary 168-ball nand flash and lpdram pop (ti omap) mcp ball assignments and descriptions pdf: 09005aef83070ff3 168ball_nand_lpdram_j4xx_omap.pdf - rev. i 6/09 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2007 micron technology, inc. all rights reserved.
figure 4: 168-ball vfbga (nand x16; lpddr x32) ball assignments 1 dnu dnu dm0 dq7 vddq dq5 dq3 vddq dq1 vdd vcc i/o1 i/o3 vcc i/o5 i/o7 vcc we# ale ce1# vcc dnu dnu 1 2 dnu dnu dqs0 dq6 vssq dq4 dq2 vssq dq0 vss vss i/o0 i/o2 vss i/o4 i/o6 vss re# nc ce0# vss dnu dnu 2 4 vddq vssq i/o10 i/o11 4 3 dq17 dq16 i/o8 i/o9 3 5 dq19 dq18 vss vcc 5 6 dm2 dqs2 i/o12 i/o13 6 7 vddq vssq i/o14 i/o15 7 8 dq21 dq20 vss vcc 8 12 vdd vss r/b# cle 12 13 dq9 dq8 vss vcc 13 14 dq11 dq10 vss tq 14 15 vddq vssq nc nc 15 16 dq13 dq12 nc nc 16 17 dm1 dqs1 nc nc 17 18 vddq vssq nc nc 18 19 dq15 dq14 nc nc 19 20 dm3 dqs3 vss nc 20 21 dq25 dq24 ba0 ba1 21 22 dnu dnu vssq dq26 dq28 vssq dq30 vss cke0 vss cas# cs0# a0 a2 a4 a6 a8 a10 a12 a14 vss dnu dnu 22 23 dnu dnu vddq dq27 dq29 vddq dq31 vdd cke1 we# ras# cs1# a1 a3 a5 a7 a9 a11 a13 vdd vdd dnu dnu 23 a b c d e f g h j k l m n p r t u v w y aa ab ac a b c d e f g h j k l m n p r t u v w y aa ab ac top view C ball down nand lpddr supply ground 9 dq23 dq22 lock nc 9 10 vddq vssq wp# nc 10 11 ck ck# nc nc 11 preliminary 168-ball nand flash and lpdram pop (ti omap) mcp ball assignments and descriptions pdf: 09005aef83070ff3 168ball_nand_lpdram_j4xx_omap.pdf - rev. i 6/09 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2007 micron technology, inc. all rights reserved.
table 2: x8, x16 nand ball descriptions symbol type description ale input address latch enable: when ale is high, addresses can be transferred to the on-chip address register. ce0#, ce1# input chip enable: gates transfers between the host system and the nand device. ce1# is used when a second ce# is required and is rfu in all other configurations. cle input command latch enable: when cle is high, commands can be transferred to the on-chip command register. lock input when lock is high during power-up, the block lock func- tion is enabled. to disable block lock, connect lock to vss during power-up, or leave it unconnected (internal pull-down). re# input read enable: gates information from the nand device to the host system. we# input write enable: gates information from the host system to the nand device. wp# input write protect: driving wp# low blocks erase and program operations. i/o[7:0] (x8) i/o[15:0] (x16) input/ output data inputs/outputs: the bidirectional i/os transfer address, data, and instruction information. data is output only during read operations; at other times the i/os are inputs. i/o[15:8] are rfu 1 for nand x8 devices. r/b# output ready/busy: open-drain, active-low output that indicates when an internal operation is in progress. vcc supply vcc: nand power supply. note: 1. balls marked rfu may or may not be connected internally. these balls should not be used. contact factory for details. preliminary 168-ball nand flash and lpdram pop (ti omap) mcp ball assignments and descriptions pdf: 09005aef83070ff3 168ball_nand_lpdram_j4xx_omap.pdf - rev. i 6/09 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2007 micron technology, inc. all rights reserved.
table 3: x16, x32 lpddr ball descriptions symbol type description a[14:0] (x16) a[14:0] (x32) input address inputs: specifies the row or column address. also used to load the mode registers. the maximum lpddr ad- dress is determined by density and configuration. consult the lpddr product data sheet for the maximum address for a giv- en density and configuration. unused address balls become rfu. 1 ba0, ba1 input bank address inputs: specifies one of the 4 banks. cas# input column select: specifies which command to execute. ck, ck# input ck is the system clock. ck and ck# are differential clock inputs. all address and control signals are sampled and referenced on the crossing of the rising edge of ck with the falling edge of ck#. cke0, cke1 input clock enable. cke0 is used for a single lpddr product. cke1 is used for dual lpddr products and is considered rfu for single lpddr mcps. cs0#, cs1# input chip select: cs0# is used for a single lpddr product. cs1# is used for dual lpddr products and is considered rfu for single lpddr mcps. udm, ldm (x16) dm[3:0] (x32) input data mask: determines which bytes are written during write operations. for x16 lpddr, unused dm balls become rfu. ras# input row select: specifies the command to execute. we# input write enable: specifies the command to execute. dq[15:0] (x16) dq[31:0] (x32) input/ output data bus: data inputs/outputs. dq[31:16] are rfu for x16 lpddr devices. udqs, ldqs (x16) dqs[3:0] (x32) input/ output data strobe: coordinates read/write transfers of data; one dqs per dq byte. for x16 lpddr, unused dqs balls become rfu. tq output temperature sensor output: tq high when lpddr t j exceeds 85c. vdd supply vdd: lpddr power supply. vddq supply vddq: lpddr i/o power supply. vssq supply vssq: lpddr i/o ground. note: 1. balls marked rfu may or may not be connected internally. these balls should not be used. contact factory for details. preliminary 168-ball nand flash and lpdram pop (ti omap) mcp ball assignments and descriptions pdf: 09005aef83070ff3 168ball_nand_lpdram_j4xx_omap.pdf - rev. i 6/09 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2007 micron technology, inc. all rights reserved.
table 4: non-device-specific descriptions symbol type description vss supply vss: shared ground. symbol type description dnu C do not use: must be grounded or left floating. nc C no connect: not internally connected. rfu 1 C reserved for future use. note: 1. balls marked rfu may or may not be connected internally. these balls should not be used. contact factory for details. preliminary 168-ball nand flash and lpdram pop (ti omap) mcp ball assignments and descriptions pdf: 09005aef83070ff3 168ball_nand_lpdram_j4xx_omap.pdf - rev. i 6/09 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2007 micron technology, inc. all rights reserved.
electrical specifications table 5: absolute maximum ratings parameters/conditions symbol min max unit vcc, vdd, vddq supply voltage relative to vss vcc, vdd, vddq C1.0 2.4 v voltage on any pin relative to vss vin C0.5 2.4 or (supply voltage 1 + 0.3v), whichever is less v storage temperature range C C55 +150 c note: 1. supply voltage references vcc, vdd, or vddq. stresses greater than those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sec- tions of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect reliability. table 6: recommended operating conditions parameters symbol min typ max unit supply voltage vcc, vdd 1.70 1.80 1.95 v i/o supply voltage vddq 1.70 1.80 1.95 v operating temperature range C C40 C +85 c preliminary 168-ball nand flash and lpdram pop (ti omap) mcp electrical specifications pdf: 09005aef83070ff3 168ball_nand_lpdram_j4xx_omap.pdf - rev. i 6/09 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2007 micron technology, inc. all rights reserved.
device diagrams figure 5: 168-ball (single lpddr) functional block diagram ce0# cle ale re# we# wp# lock cs0# ck ck# cke0 ras# cas# we# address, ba0, ba1 vcc i/o r/b# vss vdd vddq dm dq dqs tq vss vssq nand flash lpddr preliminary 168-ball nand flash and lpdram pop (ti omap) mcp device diagrams pdf: 09005aef83070ff3 168ball_nand_lpdram_j4xx_omap.pdf - rev. i 6/09 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2007 micron technology, inc. all rights reserved.
figure 6: 168-ball (dual lpddr) functional block diagram ce0# cle ale re# we# wp# cs0, cs1# ck ck# cke0, cke1 ras# cas# we# address, ba0, ba1 vcc i/o r/b# vss vdd vddq dm dq dqs tq vss vssq nand flash lpddr (die 0 and 1) preliminary 168-ball nand flash and lpdram pop (ti omap) mcp device diagrams pdf: 09005aef83070ff3 168ball_nand_lpdram_j4xx_omap.pdf - rev. i 6/09 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2007 micron technology, inc. all rights reserved.
package dimensions figure 7: 168-ball vfbga (package code: jg) 0.6 0.1 0.08 a a 11 ctr ball a1 id ball a1 id 0.5 typ 12 0.1 11 ctr seating plane 12 0.1 168x ?0.33 0.5 typ solder ball material: sac105. dimensions apply to solder balls post- reflow on ?0.27 smd ball pads. 0.9 max 0.25 min a b c d e f g h j k l m n p r t u v w y aa ab ac 23 22 21 20 19 17 16 15 18 14 9 10 11 12 13 8 7 6 5 4 3 2 1 note: 1. all dimensions are in millimeters. preliminary 168-ball nand flash and lpdram pop (ti omap) mcp package dimensions pdf: 09005aef83070ff3 168ball_nand_lpdram_j4xx_omap.pdf - rev. i 6/09 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2007 micron technology, inc. all rights reserved.
figure 8: 168-ball vfbga (package code: ji) 0.75 0.1 0.08 a a 11 ctr ball a1 id ball a1 id 0.5 typ 12 0.1 11 ctr seating plane 12 0.1 168x ?0.33 0.5 typ solder ball material: sac105. dimensions apply to solder balls post- reflow on ?0.27 smd ball pads. 1.1 max 0.25 min a b c d e f g h j k l m n p r t u v w y aa ab ac 21 22 23 19 20 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 note: 1. all dimensions are in millimeters. preliminary 168-ball nand flash and lpdram pop (ti omap) mcp package dimensions pdf: 09005aef83070ff3 168ball_nand_lpdram_j4xx_omap.pdf - rev. i 6/09 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2007 micron technology, inc. all rights reserved.
figure 9: 168-ball wfbga (package code: kq) 0.43 0.05 0.08 a a 11 ctr ball a1 id ball a1 id 0.5 typ 12 0.1 11 ctr seating plane 12 0.1 0.5 typ 168x ?0.34 solder ball material: sac105. dimensions apply to solder balls post- reflow on ?0.28 smd ball pads. 0.75 max 0.23 min 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa ab ac note: 1. all dimensions are in millimeters. preliminary 168-ball nand flash and lpdram pop (ti omap) mcp package dimensions pdf: 09005aef83070ff3 168ball_nand_lpdram_j4xx_omap.pdf - rev. i 6/09 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2007 micron technology, inc. all rights reserved.
revision history rev. i, preliminary C 6/09 ? updated figure 2 (page 2) for nand flash configuration codes by adding "y" informa- tion: y (x8, 4gb, second) and z (x16, 4gb, second). ? changed ball y22 from nc to a14 in figure 4 (page 6). ? changed a[13:0] to a[14:0] in table 3 (page 8). rev. h, preliminary C 5/09 ? deleted "device size" bullets from nand-flash-specific features on the page 1. ? added 200 mhz cl3 (-5) to options/marking table on page 1. ? updated figure 2 (page 2) to list "-5 = 200 mhz cl3" under "lpdram access time." udated the package codes to show the preferred format. added "cs#" after "ce#" in the chip count. changed row b under chip count to "1, 1" and row d to "1, 2." add- ed "am" and "ap" under "lpdram configuration." added "kq" under "package codes." deleted "l = low-power option." ? modified figure 5 (page 11) to change "cs#" to "cso#," "cke" to "cke0," and "ce#" to "ce0#." ? modified figure 6 (page 12) to change "ce#" to "ce0#." ? added new figure 9 (page 15). rev. g, preliminary C 3/09 ? added mt29c4g48maplcjg-6 it to part number table. rev. f, preliminary C 11/08 ? updated template for external publication rev. e, preliminary C 09/08 ? mt29cxgxxmaxxxjg, mt29cxgxxmaxxxji: as the third-from-the-last character in the part number, replaced a with an x. ? figure 3, ball assignment: 168-ball vfbga (x8 nand flash and x16 lpdram): upda- ted figure by replacing ncs in lower-left corner with rfus. ? table 2, nand flash ball descriptions, in ce1#/ce0# row, reversed order of ball numbers to reflect correct highest-to-lowest order; changed nc to rfu1 in the i/ o row; added note 1. ? table 3, lpddr ball descriptions,: in ba1/ba0, cke1/cke0, and cs1#/cs0# rows, reversed order of ball numbers to reflect correct highest-to-lowest order; in nc row, removed ae-indicated ball assignments and created a new rfu row. ? figure 6, 168-ball dual lpddr functional block diagram: added figure adapted from 152-ball. ? figure 7, 168-ball vfbga (package code: jg): updated figure with current version from mdm. ? figure 8, 168-ball vfbga (package code: ji): updated figure with current version from mdm. preliminary 168-ball nand flash and lpdram pop (ti omap) mcp revision history pdf: 09005aef83070ff3 168ball_nand_lpdram_j4xx_omap.pdf - rev. i 6/09 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2007 micron technology, inc. all rights reserved.
rev. d, preliminary C 04/08 ? changed status to preliminary. ? figure 2: 168-ball part number chart on page 2: added ji part number and package code. ? figure 3: ball assignment: 168-ball vfbga (x8 nand flash and x16 lpdram); figure 4: 168-ball vfbga (nand x16; lpddr x32) ball assignments; table 2, nand flash ball descriptions,; table 3, lpddr ball descriptions,; and table 4, non-device- specific ball descriptions,: updated ball assignments. ? removed former capacitance tables. see component data sheets for capacitance. ? figure 8: 168-ball vfbga (package code: ji): added figure. rev. c, advance C 02/08 ? figure 2: 168-ball part number chart: updated self-refresh current definition. ? figure 7: 168-ball vfbga (package code: jg): updated package diagram with 0.15 tol- erance. rev. b C 12/07 ? lp-dram-specific features: added srr feature. ? separated original single ball-assignment table into separate tables: table 2, nand flash ball descriptions, table 3, lpddr ball descriptions, and table 4, non-de- vice-specific ball descriptions. ? figure 3, 137-ball tfbga (lpddr) ball assignments, on page 4: changed pin p1 from nc to rfu. ? removed mobile from lp-dram references. rev. a C 12/07 ? initial release. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains initial characterization limits that are subject to change upon full characterization of production devices. preliminary 168-ball nand flash and lpdram pop (ti omap) mcp revision history pdf: 09005aef83070ff3 168ball_nand_lpdram_j4xx_omap.pdf - rev. i 6/09 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2007 micron technology, inc. all rights reserved.

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