1 2 3 4 5 6 7 8 9 16 15 14 13 12 11 10 a 8 a 9 a 11 a 13 we ce 2 a 15 vcc nc a 16 a 14 a 12 a 7 a 6 a 5 a 4 32 31 30 29 28 27 26 25 24 17 18 19 20 21 22 23 ce 1 a 10 oe i/o 8 i/o 7 i/o 6 i/o 5 i/o 4 gnd i/o 3 i/o 2 i/o 1 a 0 a 1 a 2 a 3 1024 x 1024 row decoder sense amp input buffer column decoder control circuit i/o 7 i/o 0 oe we ce1 ce2 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 SD18U128 SD18U128l ultra low power 128k x 8 cmos sram features ? low-power consumption - active: 20ma at 70ns - stand-by: 5 m a (cmos input/output) 1 m a cmos input/output, l version ? single +1.8to 2.2v power supply ? equal access and cycle time ? 70/85/100/150 ns access time ? easy memory expansion with ce1 , ce2 and oe inputs ? 1.0v data retention mode ? ttl compatible, tri-state input/output ? automatic power-down when deselected functional description the SD18U128 is a low power cmos static ram orga- nized as 131,072 words by 8 bits. easy memory expansion is provided by an active low ce1 , an active high ce2, an active low oe , and tri-state i/o?s. this device has an automatic power-down mode feature when deselected. writing to the device is accomplished by taking chip enable 1 ( ce1 ) with write enable ( we ) low, and chip enable 2 (ce2) high. reading from the device is per- formed by taking chip enable 1 ( ce1 ) with output enable ( oe ) low while write enable ( we ) and chip enable 2 (ce2) is high. the i/o pins are placed in a high-impedance state when the device is deselected: the outputs are disabled during a write cycle. the SD18U128l comes with a 1v data retention feature and lower standby power. the SD18U128 is available in a 32-pin 8 x 20 mm tsop1 / stsop / 48-fpbga pack- ages. 32-pin tsop1 / stsop (see next page) revised 12/2/98 20410 town center lane, ste 270 s cupertino, ca 95014 s tel (408) 255-1262 s fax (408) 255-1359 logic block diagram 1024 x 1024 row decoder sense amp input buffer column decoder control circuit i/o8 i/o1 oe we ce1 ce2 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 9 http://www..net/ datasheet pdf - http://www..net/
SD18U128/SD18U128l 2 top view 48-csp ball-grid array package(shading indicates no ball) 1 2 3 4 5 6 a a 0 a 1 ce2 a 3 a 6 a 8 b i/o 4 a 2 we a 4 a 7 i/o 0 c i/o 5 nc nc a 5 nc i/o 1 d v ss nc nc nc nc v dd e v dd nc nc nc nc v ss f i/o 6 nc nc nc nc i/o 2 g i/o 7 oe ce 1 a 16 a 15 i/o 3 h a 9 a 10 a 11 a 12 a 13 a 14 soft device, inc. sd28u128b top view 6 5 4 3 2 1 a b c d e f g h http://www..net/ datasheet pdf - http://www..net/
SD18U128/SD18U128l absolute maximum ratings * * note: stresses greater than those listed above absolute maximum ratings may cause permanent damage to the device. this is a stress ra t- ing only and functional operation of the device at these or any conditions outside those indicated in the operational sections o f this specifica- tion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol minimum maximum unit voltage on any pin relative to gnd vt -0.5 4.6 v power dissipation p t - 1.0 w storage temperature (plastic) tstg -55 +150 0 c temperature under bias tbias -40 +85 0 c truth table * key: x = don?t care, l = low, h = high ce1 ce2 we oe data mode h x x x high-z standby x l x x high-z standby l h h l data out active, read l h h h high-z active, output disable l h l x data in active, write 3 recommended operating conditions (t a = 0 0 c to +70 0 c / -40 0 c to 85 0 c ** ) * v il min = -1.0v for pulse width less than t rc /2. ** for industrial temperature. parameter symbol min typ max unit v cc 1.8 2.0 2.2 v gnd 0.0 0.0 0.0 v v ih 1.6 - v cc + 0.2 v v il -0.5* - 0.4 v supply voltage input voltage http://www..net/ datasheet pdf - http://www..net/
ac test conditions input pulse level 0.4v to 1.6v input rise and fall time 5ns input and output timing reference level 50% of input level (v il + v ih )/2 output load condition 70ns/85 ns c l = 30pf + 1ttl load load 100ns/150 ns c l = 100pf + 1ttl load c l * figure a. * including scope and jig capacitance ttl SD18U128/SD18U128l dc operating characteristics (v cc = 1.8 to 2.2v, gnd = 0v, t a = 0 0 c to +70 0 c / -40 0 c to 85 0 c) input leakage current i i li i v cc = max, v in = gnd to v cc - 1 - 1 - 1 - 1 m a output leakage current i i lo i ce1 = v ih or ce2 = v il v cc = max, v out = gnd to v cc - 1 - 1 - 1 - 1 m a operating power supply current i cc ce1 = v il , ce2 = v ih v in = v ih or v il , i out = 0 ma - 3 - 3 - 3 - 3 ma average operating current i cc1 ce1 = v il , ce2 = v ih i out = 0ma, min cycle, 100% duty - 25 - 20 - 15 - 15 ma i cc2 ce1 = 0.2v, ce2 = v cc - 0.2v i out = 0ma, cycle time=1 m s, 100% duty - 3 - 3 - 3 - 3 ma standby power supply current (ttl level) i sb ce1 = v ih or ce2 = v il - 0.5 - 0.5 - 0.5 - 0.5 ma standby power supply current (cmos level) i sb1 ce1 > v cc - 0.2v or ce2 < 0.2v, f = 0 v in < 0.2v or v in > v cc - 0.2v l - - 5 1 - - 5 1 - - 5 1 - - 5 1 m a m a output low voltage v ol i ol = 2 ma - 0.4 - 0.4 - 0.4 - 0.4 v output high voltage v oh i oh = -1 ma 1.6 - 1.6 - 1.6 - 1.6 - v -70 -100 -150 unit parameter sym test conditions min max min max min max min max -85 4 capacitance (f = 1mhz, t a = 25 0 c) parameter* symbol test condition max unit input capacitance c in v in = 0v 7 pf i/o capacitance c i/o v in = v out = 0v 8 pf * this parameter is guaranteed by device characterization and is not production tested. http://www..net/ datasheet pdf - http://www..net/
SD18U128/SD18U128l parameter symbol unit note read cycle time t rc 70 - 85 - 100 - 150 - ns address access time t aa - 70 - 85 - 100 - 150 ns chip enable access time t ace - 70 - 85 - 100 - 150 ns output enable access time t oe - 40 - 40 - 50 - 70 ns output hold from address change t oh 10 - 10 - 10 - 10 - ns chip enable to output in low-z t clz 10 - 10 - 10 - 10 - ns 4,5 chip disable to output in high-z t chz - 30 - 35 - 40 - 50 ns 4,5 output enable to output in low-z t olz 5 - 5 - 5 - 5 - ns 4,5 output disable to output in high-z t ohz - 25 - 30 - 35 - 40 ns 4,5 power-up time t pu 0 - 0 - 0 - 0 - ns 5 power-down time t pd - 70 - 85 - 100 - 150 ns 5 read cycle (3,9) (v cc = 1.8 to 2.2v, gnd = 0v, t a = 0 0 c to +70 0 c / -40 0 c to +85 0 c) write cycle (3,11) (v cc = 1.8 to 2.2v, gnd = 0v, t a = 0 0 c to +70 0 c / -40 0 c to +85 0 c) parameter symbol unit note write cycle time t wc 70 - 85 - 100 - 150 - ns chip enable to write end t cw 60 - 70 - 80 - 120 - ns address setup to write end t aw 60 - 70 - 80 - 120 - ns address setup time t as 0 - 0 - 0 - 0 - ns write pulse width t wp 50 - 60 - 70 - 100 - ns write recovering time t wr 0 - 0 - 0 - 0 - ns data valid to write end t dw 30 - 35 - 40 - 60 - ns data hold time t dh 0 - 0 - 0 - 0 - ns write enable to output in high-z t wz - 30 - 35 - 40 - 50 ns 4,5 output active from write end t ow 5 - 5 - 5 - 5 - ns 4,5 min max min max min max min max -70 -85 -100 5 min max min max min max min max -70 -85 -100 -150 -150 http://www..net/ datasheet pdf - http://www..net/
timing waveform of read cycle 1 (3,6,7,9) (address controlled) t r c t aa t o h data valid address d out timing waveform of read cycle 2 (5,6,8,9) (ce1 controlled) 50% 50% i cc i sb t pd t chz t ohz t rc t oe t olz t ace t clz t pu ce1 oe d out supply current data valid timing waveform of read cycle 3 (3,6,8,9) (ce2 controlled) 50% 50% i cc i sb t pd t chz t ohz t rc t oe t olz t ace t clz t pu ce2 oe d out supply current data valid SD18U128/SD18U128l 6 http://www..net/ datasheet pdf - http://www..net/
SD18U128/SD18U128l timing waveform of write cycle 1 (10,11) (we controlled) data valid address d out timing waveform of write cycle 2 (10,11) (ce1 controlled) timing waveform of write cycle 3 (10,11) (ce2 controlled) d in we t dw t dh t ow t wz t as t wp t wr t wc t aw d out d in we address ce1 data valid t wz t dw t dh t wp t wc t cw t aw t wr t as d out d in we address ce2 data valid t wz t dw t dh t wp t wc t cw t aw t wr t as 7 http://www..net/ datasheet pdf - http://www..net/
SD18U128/SD18U128l data retention characteristics (l version only) (1) parameter symbol test condition min max unit v cc for data retention v dr ce 1 > v cc - 0.2v or 1.0 - v data retention current i ccdr ce 2 < + 0.2v - 1 m a chip deselect to data retention time t cdr v in > v cc - 0.2v or 0 - ns operation recovery time (2) t r v in < 0.2v t rc - ns data retention mode v dr > 1.0v vcc_typ v ih v ih v dr v cc ce t r t cdr vcc_typ data retention waveform (l version only) (t a = 0 0 c to +70 0 c / -40 0 c to +85 0 c) 8 notes 1. l-version includes this feature. 2. this parameter is samples and not 100% tested. 3. for test conditions, see ac test condition , figure a. 4. this parameter is tested with cl = 5 p f as shown in figure b. transition is measured + 500mv from steady-state voltage. 5. this parameter is guaranteed, but is not tested. 6. we is high for read cycle. 7. ce1 and oe are low and ce2 is high for read cycle. 8. address valid prior to or coincident with ce1 transition low or ce2 transition high. 9. all read cycle timings are referenced from the last valid address to the first transtion address. 10. ce1 or we must be high or ce2 must be low during address transition. 11. all write cycle timings are referenced from the last valid address to the first transition address. http://www..net/ datasheet pdf - http://www..net/
SD18U128/SD18U128l ordering information device type* speed package SD18U128k-70 70 ns 8 x 20 mm 32-pin plastic tsop1 SD18U128k-85 85 ns SD18U128k-100 100 ns SD18U128k-150 150 ns SD18U128lk-70 70 ns SD18U128lk-85 85 ns SD18U128lk-100 100 ns SD18U128lk-150 150 ns SD18U128sk-70 70 ns 8 x 13.4 mm 32-pin plastic stsop SD18U128sk-85 85 ns SD18U128sk-100 100 ns SD18U128sk-150 150 ns SD18U128lsk-70 70 ns SD18U128lsk-85 85 ns SD18U128lsk-100 100 ns SD18U128lsk-150 150 ns SD18U128fg-70 70 ns SD18U128fg-85 85 ns SD18U128fg-100 100 ns SD18U128fg-150 150 ns note: soft device reserves the right to make changes to its products and to this data sheet at any time, without notice, to impr ove design or performance. soft device makes no representation that circuits shown are free from patent infringments. circuitry and other examples shown ar e meant only to indicate the performance and characteristics of our products. soft device products are not authorized for use as critical components in life support systems without written permission of the appropriate officer of soft device. 9 * for induatrial temperature tested devices, an ?i? designator will be added to the end of the device number. http://www..net/ datasheet pdf - http://www..net/
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