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nt1gd64s8ha0fm / nt1gd64s8hb0fm 1gb : 128m x 64 pc2700 / pc2100 unbuffered ddr so-dimm rev 1.2 1 12/19/2003 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. 200 pin unbuffered ddr so-dimm based on ddr333/266 64mx8 sdram features ? 200-pin small outline dual in-line memory module (so-dimm) ? 128mx64 unbuffered ddr so-dimm based on 64mx8 ddr sdram. ? performance: pc2700 pc2100 speed sort 6k 75b dimm cas latency 2.5 2.5 unit f ck clock frequency 166 133 mhz t ck clock cycle 6 7.5 ns f dq dq burst frequency 333 266 mhz ? intended for 133 and 166 mhz applications ? inputs and outputs are sstl-2 compatible ? v dd = v ddq = 2.5v 0.2v ? sdrams have 4 internal banks for concurrent operation ? module has two physical banks ? differential clock inputs ? data is read or written on both clock edges ? dram dll aligns dq and dqs trans itions with clock transitions. ? address and control signals are fully synchronous to positive clock edge ? programmable operation: - dimm cas latency: 2, 2.5 - burst type: sequential or interleave - burst length: 2, 4, 8 - operation: burst read and write ? auto refresh (cbr) and self refresh modes ? automatic and controlled precharge commands ? 13/11/2 addressing (row/column/bank) ? 7.8 s max. average periodic refresh interval ? serial presence detect ? gold contacts ? sdrams in 60-ball fbga package description nt1gd64s8ha0fm and nt1gd64s8hb0fm are unbuffered 200-pin doubl e data rate (ddr) synchronous dram small outline dual in-line memory module (so-dimm), organized as two banks of 64x 64 high-speed memory array. the module uses sixteen 16mx8 ddr sdrams in 60-ball fbga packages. these dimms are manufactur ed using raw cards developed for br oad industry use as reference designs. the use of these comm on design files minimizes electrical variation bet ween suppliers. all nanya ddr sdram dimms prov ide a high-performance, flexible 8-byte interf ace in a 2.66? long space-saving footprint. the dimm is intended for use in applications operating up to 166 mhz clock speeds and achieves hi gh-speed data transfer rates o f up to 333 mhz. prior to any access operation, the device cas latency and burst type/ length/operation type must be programmed into the dimm by address inputs a0-a12 and i/o inputs ba0 and ba1 using the mode register set cycle. the dimm uses serial presence-det ect implemented via a serial eeprom using a st andard iic protocol. the first 128 bytes of seri al pd data are programmed and locked during module assembly. the rema ining 128 bytes are available for use by the customer. ordering information part number speed power organization leads nt1gd64s8ha0fm-6k nt1gd64s8hb0fm-6k ddr333 pc2700 2.5-3-3 166mhz (6ns @ cl = 2.5) 133mhz (7.5ns @ cl = 2) nt1gd64s8ha0fm-75b nt1gd64s8hb0fm-75b ddr266b pc2100 2.5-3-3 133mhz (7.5ns @ cl = 2.5) 100mhz (10ns @ cl = 2) 2.5v 128mx64 gold
nt1gd64s8ha0fm / nt1gd64s8hb0fm 1gb : 128m x 64 pc2700 / pc2100 unbuffered ddr so-dimm rev 1.2 2 12/19/2003 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. pin description ck0, ck1, ck2, ck0 , ck1 , ck2 differential clock inputs. dq0-dq63 data input/output cke0, cke1 clock enable dqs0-dqs7 bidirectional data strobes ras row address strobe dm0-dm7 input data mask cas column address strobe v dd power we write enable v ddq supply voltage for dqs s0 , s1 chip selects v ss ground a0-a9, a11, a12 address inputs nc no connect a10/ap address input/auto-precharge scl serial presence detect clock input ba0, ba1 sdram bank address inputs sda se rial presence detect data input/output v ref ref. voltage for sstl_2 inputs sa0-2 serial presence detect address inputs v ddid v dd identification flag. v ddspd serial eeprom positive power supply pinout pin front pin back pin front pin back pin front pin back pin front pin back 1 v ref 2 v ref 51 v ss 52 v ss 101 a9 102 a8 151 dq42 152 dq46 3 v ss 4 v ss 53 dq19 54 dq23 103 v ss 104 v ss 153 dq43 154 dq47 5 dq0 6 dq4 55 dq24 56 dq28 105 a7 106 a6 155 v dd 156 v dd 7 dq1 8 dq5 57 v dd 58 v dd 107 a5 108 a4 157 v dd 158 ck1 9 v dd 10 v dd 59 dq25 60 dq29 109 a3 110 a2 159 v ss 160 ck1 11 dqs0 12 dm0 61 dqs3 62 dm3 111 a1 112 a0 161 v ss 162 v ss 13 dq2 14 dq6 63 v ss 64 v ss 113 v dd 114 v dd 163 dq48 164 dq52 15 v ss 16 v ss 65 dq26 66 dq30 115 a10/ap 116 ba1 165 dq49 166 dq53 17 dq3 18 dq7 67 dq27 68 dq31 117 ba0 118 ras 167 v dd 168 v dd 19 dq8 20 dq12 69 v dd 70 v dd 119 we 120 cas 169 dqs6 170 dm6 21 v dd 22 v dd 71 nc 72 nc 121 s0 122 s1 171 dq50 172 dq54 23 dq9 24 dq13 73 nc 74 nc 123 du 124 du 173 v ss 174 v ss 25 dqs1 26 dm1 75 v ss 76 v ss 125 v ss 126 v ss 175 dq51 176 dq55 27 v ss 28 v ss 77 dqs8 78 nc 127 dq32 128 dq36 177 dq56 178 dq60 29 dq10 30 dq14 79 nc 80 nc 129 dq33 130 dq37 179 v dd 180 v dd 31 dq11 32 dq15 81 v dd 82 v dd 131 v dd 132 v dd 181 dq57 182 dq61 33 v dd 34 v dd 83 nc 84 nc 133 dqs4 134 dm4 183 dqs7 184 dm7 35 ck0 36 v dd 85 du 86 du 135 dq34 136 dq38 185 v ss 186 v ss 37 ck0 38 v ss 87 v ss 88 v ss 137 v ss 138 v ss 187 dq58 188 dq62 39 v ss 40 v ss 89 ck2 90 v ss 139 dq35 140 dq39 189 dq59 190 dq63 41 dq16 42 dq20 91 ck2 92 v dd 141 dq40 142 dq44 191 v dd 192 v dd 43 dq17 44 dq21 93 v dd 94 v dd 143 v dd 144 v dd 193 sda 194 sa0 45 v dd 46 v dd 95 cke1 96 cke0 145 dq41 146 dq45 195 scl 196 sa1 47 dqs2 48 dm2 97 du 98 du 147 dqs5 148 dm5 197 v ddspd 198 sa2 49 dq18 50 dq22 99 a12 100 a11 149 v ss 150 v ss 199 v ddid 200 du note: all pin assignments are consistent for all 8-byte unbuffered versions.
nt1gd64s8ha0fm / nt1gd64s8hb0fm 1gb : 128m x 64 pc2700 / pc2100 unbuffered ddr so-dimm rev 1.2 3 12/19/2003 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. input/output functional description symbol type polarity function ck0, ck1, ck2, ck0 , ck1 , ck2 (sstl) cross point the system clock inputs. all address and comm and lines are sampled on the cross point of the rising edge of ck and falling edge of ck. a delay locked loop (dll) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. cke0, cke1 (sstl) active high activates the ddr sdram ck signal when hi gh and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode or the self refresh mode. s0 , s1 (sstl) active low enables the associated ddr sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. physic al bank 0 is selected by s0; bank 1 is selected by s1. ras , cas , we (sstl) active low when sampled at the positive rising edge of the clock, ras , cas , we define the operation to be executed by the sdram. v ref supply reference voltage for sstl-2 inputs v ddq supply isolated power supply for the ddr sdram out put buffers to provide improved noise immunity ba0, ba1 (sstl) - selects which sdram bank is to be active. a0 - a9 a10/ap a11, a12 (sstl) - during a bank activate command cycle, a0-a 12 defines the row add ress (ra0-ra12) when sampled at the rising clock edge. during a read or write command cycle, a0-a9 defines the column address (ca0-ca9) when sampled at the rising clock edge. in addition to the column address, ap is used to invoke auto-precharge operation at the end of the burst read or write cycle. if ap is high, auto-precharge is selected and ba0/ba1 defines the bank to be precharged. if ap is low, auto-precharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0/ba1 to control which bank(s) to precharge. if ap is high all 4 banks will be precharged regardless of the state of ba0/ba1. if ap is low, then ba0/ba1 are used to define which bank to pre-charge. dq0 - dq63 (sstl) - data and check bit input/output pins operate in the same manner as on conventional drams. dqs0 - dqs7 (sstl) active high data strobes: output with read data, input with write data. edge aligned with read data, centered on write data. used to capture write data. dm0 - dm7 input active high the data write masks, associated with one data byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. dm8 is associated with check bits cb0-cb7, and is not used on x64 modules. v dd , v ss supply power and ground for the ddr sdram input buffers and core logic sa0 ? sa2 - address inputs. connected to either v dd or v ss on the system board to configure the serial presence detect eeprom address. sda - this bi-directional pin is us ed to transfer data into or out of the spd eeprom. a resistor must be connected from the sda bus line to v dd to act as a pull-up. scl - this signal is used to clock data into and out of the spd eeprom. a resistor may be connected from the scl bus time to v dd to act as a pull-up. v ddspd supply serial eeprom positive power supply.
nt1gd64s8ha0fm / nt1gd64s8hb0fm 1gb : 128m x 64 pc2700 / pc2100 unbuffered ddr so-dimm rev 1.2 4 12/19/2003 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram (2 banks, 64mx8 ddr sdrams) serial pd a0 a2 a1 scl wp sda sa0 sa2 sa1 s1 dm0 dq0 dq1 dq2 dq7 dq4 dq6 dq5 dq3 dq8 dq9 dq10 dq15 dq12 dq14 dq13 dq11 dq16 dq17 dq18 dq23 dq20 dq22 dq21 dq19 dq24 dq25 dq26 dq31 dq28 dq30 dq29 dq27 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d3 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d2 dqs0 dm4 dqs4 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d0 dm1 dqs1 dqs dm2 dqs2 dm3 dqs3 dqs dq32 dq33 dq34 dq39 dq36 dq38 dq37 dq35 dq40 dq41 dq42 dq47 dq44 dq46 dq45 dq43 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d1 dqs dqs5 dm5 dq48 dq49 dq50 dq55 dq52 dq54 dq53 dq51 dq56 dq57 dq58 dq63 dq60 dq62 dq61 dq59 dqs6 dm6 dqs7 dm7 dqs s0 i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d8 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d9 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d10 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d11 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d7 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d6 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d4 dqs dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d5 dqs dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d12 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d13 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d14 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d15 dqs a0-a12 ras ba0-ba1 ba0-ba1 : sdrams d0-d15 a0-a12 : sdrams d0-d15 ras : sdrams d0-d15 cke0 we cas cas : sdrams d0-d15 cke : sdrams d0-d7 cke : sdrams d8-d15 we : sdrams d0-d15 cke1 v ddspd v ss v ref v ddid v dd /v ddq strap: see note 4 spd d0-d15 d0-d15 d0-d15 notes : 1. dq-to-i/o wring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships are maintained as shown. 3. dq/dqs/dm/dqs resistors are 22 ohms. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd is not equal to v ddq . clock wiring clock input sdrams ck0/ ck0 ck1/ ck1 ck2/ ck2 8 sdrams 8 sdrams nc * clock net wiring d0/d8 d1/d9 d2/d10 d3/d11 card edge ck0/ck1 ck0 / ck1 r=120 ohms d4/d12 d5/d13 d6/d14 d7/d15
nt1gd64s8ha0fm / nt1gd64s8hb0fm 1gb : 128m x 64 pc2700 / pc2100 unbuffered ddr so-dimm rev 1.2 5 12/19/2003 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. serial presence detect (part 1 of 2) byte description spd entry value spd data entry (hex) 0 number of serial pd bytes written during production 128 80 1 total number of bytes in serial pd device 256 08 2 fundamental memory type sdram ddr 07 3 number of row addresses on assembly 13 0d 4 number of column addresses on assembly 11 09 5 number of dimm bank 2 01 6 data width of assembly x64 40 7 data width of assembly (cont?) x64 00 8 voltage interface level of this assembly sstl 2.5v 04 ddr266b 7.5ns 75 9 ddr sdram device cycle time cl=2.5 ddr333 6.0ns 60 ddr266b 0.75ns 75 10 ddr sdram device access time from clock cl=2.5 ddr333 0.70ns 70 11 dimm configuration type non-parity 00 12 refresh rate/type sr/1x(7.8us) 82 13 primary ddr sdram width x8 08 14 error checking ddr sdram device width n/a 00 15 ddr sdram device attr: min clk delay, random col access 1 clock 01 16 ddr sdram device attributes: burst length supported 2,4,8 0e 17 ddr sdram device attributes: number of device banks 4 04 ddr266b 2/2.5 0c 18 ddr sdram device attributes: cas latencies supported ddr333 2/2.5 0c 19 ddr sdram device attributes: cs latency 0 01 20 ddr sdram device attributes: we latency 1 02 21 ddr sdram device attribut es: differential clock 20 22 ddr sdram device attributes: general 0.2v tolerance 00 ddr266b 7.5ns 75 23 minimum clock cycle cl=2.5 ddr333 10ns a0 ddr266b 0.70ns 70 24 maximum data access time from clock at cl=2 ddr333 0.75ns 75 ddr266b n/a 00 25 minimum clock cycle time at cl=1 ddr333 n/a 00 ddr266b n/a 00 26 maximum data access time from clock at cl=1 ddr333 n/a 00 ddr266b 18ns 48 27 minimum row precharge time (t rp ) ddr333 20ns 50 ddr266b 12ns 30 28 minimum row active to row active delay (t rrd ) ddr333 15ns 3c ddr266b 18ns 48 29 minimum ras to cas delay (t rcd ) ddr333 20ns 50 ddr266b 42ns 2a 30 minimum ras pulse width (t ras ) ddr333 45ns 2d 31 module bank density 512mb 80 ddr266b 0.75ns 75 32 address and command setup time before clock ddr333 0.90ns 90 ddr266b 0.75ns 75 33 address and command hold time after clock ddr333 0.90ns 90 ddr266b 0.45ns 45 34 data input setup time before clock ddr333 0.50ns 50
nt1gd64s8ha0fm / nt1gd64s8hb0fm 1gb : 128m x 64 pc2700 / pc2100 unbuffered ddr so-dimm rev 1.2 6 12/19/2003 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. serial presence detect (part 2 of 2) ddr266b 0.45ns 45 35 data input hold time after clock ddr333 0.50ns 50 36-40 reserved reserved 00 41 minimum active/auto-refresh time (t rc ) 60ns 3c 42 auto-refresh to active/auto-refresh command period (t rfc ) 72ns 48 43 max cycle time (t ck max ) 12ns 30 44 maximum dqs-dq skew time (t dqsq ) 0.4ns 28 45 maximum read data hold skew factor (t qhs ) 0.55ns 55 46-61 reserved reserved 00 62 spd revision initial 00 ddr266b 3c 63 checksum data ddr333 bd 64-71 manufacturer?s jedec id code nanya 7f7f7f0b00000000 72 module manufacturing location n/a 00 73-90 module part number n/a 00 91-92 module revision code n/a 00 93-94 module manufacturing data yy= binary coded decimal year c ode, 0-99(decimal), 00-63(hex) ww= binary coded decimal year code, 01-52(decimal), 01-34(hex) year/week code yy/ww 95-98 module serial number serial number 00 99-255 reserved reserved 00
nt1gd64s8ha0fm / nt1gd64s8hb0fm 1gb : 128m x 64 pc2700 / pc2100 unbuffered ddr so-dimm rev 1.2 7 12/19/2003 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. absolute maximum ratings symbol parameter rating units v in , v out voltage on i/o pins relative to v ss -0.5 to v ddq +0.5 v v in voltage on input relative to v ss -0.5 to +3.6 v v dd voltage on v dd supply relative to v ss -0.5 to +3.6 v v ddq voltage on v ddq supply relative to v ss -0.5 to +3.6 v t a operating temperature (ambient) 0 to +70 c t stg storage temperature (plastic) -55 to +150 c p d power dissipation 16 w i out short circuit output current 50 ma note : stresses greater than those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational s ections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions t a = 0 c ~ 70 c; v ddq = v dd = 2.5v 0.2v symbol parameter min max units notes v dd supply voltage 2.3 2.7 v 1 v ddq i/o supply voltage 2.3 2.7 v 1 v ss , v ssq supply voltage, i/o supply voltage 0 0 v v ref i/o reference voltage 0.49 x v ddq 0.51 x v ddq v 1, 2 v tt i/o termination voltage (system) v ref ? 0.04 v ref + 0.04 v 1, 3 v ih (dc) input high (logic1) voltage v ref + 0.15 v ddq + 0.3 v 1 v il (dc) input low (logic0) voltage -0.3 v ref - 0.15 v 1 v in (dc) input voltage level, ck and ck inputs -0.3 v ddq + 0.3 v 1 v id (dc) input differential voltage, ck and ck inputs 0.30 v ddq + 0.6 v 1, 4 i i input leakage current any input 0v v in v dd ; (all other pins not under test = 0v) -10 10 a 1 i oz output leakage current (dqs are disabled; 0v v out v ddq -10 10 a 1 i oh output high current (v out = v ddq -0.373v, min v ref , min v tt ) -16.8 - ma 1 i ol output low current (v out = 0.373, max v ref , max v tt ) 16.8 - ma 1 1. inputs are not recognized as valid until v ref stabilizes. 2. v ref is expected to be equal to 0.5 v ddq of the transmitting device, and to track variati ons in the dc level of the same. peak-to-peak noise on v ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the dimm. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 4. v id is the magnitude of the difference between the input level on ck and the input level on ck .
nt1gd64s8ha0fm / nt1gd64s8hb0fm 1gb : 128m x 64 pc2700 / pc2100 unbuffered ddr so-dimm rev 1.2 8 12/19/2003 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ac characteristics notes 1-5 apply to the following tables; electrical c haracteristics and dc operating conditions, ac operating conditions, operating, standby, and refresh current s, and electrical charac teristics and ac timing.) 1. all voltages referenced to v ss . 2. tests for ac timing, idd, and electrical, ac and dc characte ristics, may be conducted at nominal reference/supply voltage le vels, but the related specifications and devic e operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load. re fer to the ac output load circuit below. 4. ac timing and idd tests may use a v il to v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck, ck ), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between v il (ac) and v ih (ac) unless otherwise specified. 5. the ac and dc input level specificati ons are as defined in the sstl_2 standard (i.e . the receiver effectively switches as a result of the signal crossing the ac input level, and remains in that state as long as the signal does not ring back above (below) the dc inp ut low (high) level. ac output load circuits timing reference point v tt 50 ohms 30 pf output v out ac operating conditions t a = 0 c ~ 70 c; v ddq = v dd = 2.5v 0.2v symbol parameter/condition min max unit notes v ih (ac) input high (logic 1) voltage. v ref + 0.31 v 1, 2 v il (ac) input low (logic 0) voltage. v ref ? - 0.31 v 1, 2 v id (ac) input differential voltage, ck and ck inputs 0.62 v ddq + 0.6 v 1, 2, 3 v ix (ac) input differential pair cross point voltage, ck and ck inputs (0.5* v ddq ) - 0.2 (0.5* v ddq ) + 0.2 v 1, 2, 4 1. input slew rate = 1v/ ns. 2. inputs are not recognized as valid until v ref stabilizes. 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . 4. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track va riations in the dc level of the same.
nt1gd64s8ha0fm / nt1gd64s8hb0fm 1gb : 128m x 64 pc2700 / pc2100 unbuffered ddr so-dimm rev 1.2 9 12/19/2003 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. operating, standby, and refresh currents t a = 0 c ~ 70 c; v ddq = v dd = 2.5v 0.2v symbol parameter/condition pc2700 (6k) pc2100 (75b) unit notes idd0 operating current: one bank; active/precharge; t rc = t rc (min) ; t ck = t ck (min) ; dq, dm, and dqs inputs changing twice per clock cycl e; address and control inputs changing once per clock cycle 1466 1289 ma 1,2 idd1 operating current: one bank; active/read/precharge; burst = 2; t rc = t rc (min) ; cl=2.5; t ck = t ck (min) ; i out = 0ma; address and control inputs changing once per clock cycle 1625 1568 ma 1,2 idd2p precharge power-down standby current: all banks idle; power-down mode; cke v il (max) ; t ck = t ck (min) 165 165 ma 1,2 idd2n idle standby current: cs v ih (min) ; all banks idle; cke v ih (min) ; t ck = t ck (min) ; address and control inputs changing once per clock cycle 533 520 ma 1,2 idd3p active power-down standby current: one bank active; power-down mode; cke v il (max) ; t ck = t ck (min) 214 220 ma 1,2 idd3n active standby current: one bank; active/precharge; cs v ih (min) ; cke v ih (min) ; t rc = t ras (max) ; t ck = t ck (min) ; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 765 775 ma 1,2 idd4r operating current: one bank; burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; dq and dqs outputs changing twice per clock cycle; cl = 2.5; t ck = t ck (min) ; i out = 0ma 1840 1964 ma 1,2 idd4w operating current: one bank; burst = 2; writ es; continuous burst; address and control inputs changing once per clock cycle; dq and dqs inputs changing twice per clock cycle; cl=2.5; t ck = t ck (min) 1720 1584 ma 1,2 idd5 auto-refresh current: t rc = t rfc (min) 3429 2894 ma 1,2,3 idd6 self-refresh current: cke 0.2v 64 64 ma 1,2 idd7 operating current: four bank; four bank inte rleaving with bl = 4, address and control inputs randomly changing; 50% of dat a changing at every transfer; t rc = t rc (min) ; i out = 0ma. 3774 3918 ma 1,2 1. idd specifications are tested afte r the device is properly initialized. 2. input slew rate = 1v/ ns. 3. current at 7.8 s is time averaged value of idd5 at t rfc (min) and idd2p over 7.8 s.
nt1gd64s8ha0fm / nt1gd64s8hb0fm 1gb : 128m x 64 pc2700 / pc2100 unbuffered ddr so-dimm rev 1.2 10 12/19/2003 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ac timing specifications for d dr sdram devices used on module t a = 0 c ~ 70 c; v ddq = v dd = 2.5v 0.2v (part 1 of 2) 6k 75b unit notes symbol parameter min. max. min. max. t ac dq output access time from ck/ ck -0.7 +0.7 -0.75 +0.75 ns 1-4 t dqsck dqs output access time from ck/ ck -0.7 +0.7 -0.75 +0.75 ns 1-4 t ch ck high-level width 0.45 0.55 0.45 0.55 t ck 1-4 t cl ck low-level width 0.45 0.55 0.45 0.55 t ck 1-4 cl=2.5 6 12 7.5 12 ns 1-4 t ck clock cycle time cl=2 7.5 12 10 12 ns 1-4 t dh dq and dm input hold time 0.45 0.5 ns 1-4, 15, 16 t ds dq and dm input setup time 0.45 0.5 ns 1-4, 15, 16 t dipw dq and dm input pulse width (each input) 1.75 1.75 ns 1-4 t hz data-out high-impedance time from ck/ ck -0.7 +0.7 -0.75 +0.75 ns 1-4, 5 t lz data-out low-impedance time from ck/ ck -0.7 +0.7 -0.75 +0.75 ns 1-4, 5 t dqsq dqs-dq skew (dqs & associated dq signals) 0.45 0.5 ns 1-4 t hp minimum half clk period for any given cycle; defined by clk high (t ch ) or clk low (t cl ) time t ch or t cl t ch or t cl t ck 1-4 t qh data output hold time from dqs t hp - t qhs t hp - t qhs t ck 1-4 t qhs data hold skew factor 0.55 0.75 ns 1-4 t dqss write command to 1st dqs latching transition 0.75 1.25 0.75 1.25 t ck 1-4 t dqsl , t dqsh dqs input low (high) pulse width (write cycle) 0.35 0.35 t ck 1-4 t dss dqs falling edge to ck setup time (write cycle) 0.2 0.2 t ck 1-4 t dsh dqs falling edge hold time from ck (write cycle) 0.2 0.2 t ck 1-4 t mrd mode register set command cycle time 2 2 t ck 1-4 t wpres write preamble setup time 0 0 ns 1-4, 7 t wpst write postamble 0.40 0.60 0.40 0.60 t ck 1-4, 6 t wpre write preamble 0.25 0.25 t ck 1-4 t ih address and control input hold time (fast slew rate) 0.75 0.9 ns 2-4, 9, 11, 12 t is address and control input setup time (fast slew rate) 0.75 0.9 ns 2-4, 9, 11, 12 t ih address and control input hold time (slow slew rate) 0.8 1.0 ns 2-4, 10, 11, 12, 14
nt1gd64s8ha0fm / nt1gd64s8hb0fm 1gb : 128m x 64 pc2700 / pc2100 unbuffered ddr so-dimm rev 1.2 11 12/19/2003 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ac timing specifications for d dr sdram devices used on module t a = 0 c ~ 70 c; v ddq = v dd = 2.5v 0.2v (part 2 of 2) 6k 75b unit notes symbol parameter min. max. min. max. t is address and control input setup time (slow slew rate) 0.8 1.0 ns 2-4, 10-12, 14 t ipw input pulse width 2.2 2.2 ns 2-4, 12 t rp re read preamble 0.9 1.1 0.9 1.1 t ck 1-4 t rp st read postamble 0.40 0.60 0.40 0.60 t ck 1-4 t ras active to precharge command 42ns 120us 45ns 120us 1-4 t rc active to active/auto-refresh command period 60 65 ns 1-4 t rfc auto-refresh to active/auto-refresh command period 72 75 ns 1-4 t rcd active to read or write delay 18 20 ns 1-4 t rap active to read command with auto-precharge 18 20 ns 1-4 t rp precharge command period 18 20 ns 1-4 t rrd active bank a to active bank b command 12 15 ns 1-4 t wr write recovery time 15 15 ns 1-4 t dal auto-precharge write recovery + precharge time (t wr / t ck ) + (t rp / t ck ) (t wr / t ck ) + (t rp / t ck ) t ck 1-4, 13 t wtr internal write to read command delay 1 1 t ck 1-4 t pdex power down exit time 6 7.5 ns 1-4 t xsnr exit self-refresh to non-read command 75 75 ns 1-4 t xsrd exit self-refresh to read command 200 200 t ck 1-4 t refi average periodic refresh interv al 7.8 7.8 s 1-4, 8
nt1gd64s8ha0fm / nt1gd64s8hb0fm 1gb : 128m x 64 pc2700 / pc2100 unbuffered ddr so-dimm rev 1.2 12 12/19/2003 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ac timing specification notes 1. input slew rate = 1v/ns. 2. the ck/ ck input reference level (for timing reference to ck/ ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ ck is v ref . 3. inputs are not recognized as valid until v ref stabilizes. 4. the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 5. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 6. the maximum limit for this parameter is not a device limi t. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input sl ew rate specifications of the device. w hen no writes were previously in progres s on the bus, dqs will be transitioning from hi-z to logic low. if a previ ous write was in progress, dqs could be high, low, or transiti oning from high to low at this time, depending on t dqss . 8. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 9. for command/address input slew rate >= 1.0 v/ns. slew rate is measured between v oh (ac) and v ol (ac) . 10. for command/address input slew rate >= 0.5 v/ns and < 1.0 v/ns. slew rate is measured between v oh (ac) and v ol (ac) . 11. ck/ ck slew rates are >= 1.0 v/ns. 12. these parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 13. for each of the terms in parentheses, if not al ready an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. for example, for pc2100 at cl= 2.5, t dal = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5. 14. an input setup and hold time de rating table is used to increase t is and t ih in the case where the input slew rate is below 0.5 v/ns. input slew rate delta (t is ) delta (t ih ) unit note 0.5 v/ns 0 0 ps 1, 2 0.4 v/ns +50 0 ps 1, 2 0.3 v/ns +100 0 ps 1, 2 1. input slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. these derating parameters may be guaranteed by design or test er characterization and are not necessarily tested on each devi ce. 15. an input setup and hold time de rating table is used to increase t ds and t dh in the case where the i/o slew rate is below 0.5 v/ns. input slew rate delta (t ds ) delta (t dh ) unit note 0.5 v/ns 0 0 ps 1, 2 0.4 v/ns +75 +75 ps 1, 2 0.3 v/ns +150 +150 ps 1, 2 1. i/o slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. these derating parameters may be guaranteed by design or test er characterization and are not necessarily tested on each devi ce. 16. an i/o delta rise, fall derating table is used to increase t ds and t dh in the case where dq, dm, and dqs slew rates differ. delta rise and fall rate delta (t ds ) delta (t dh ) unit note 0.0 ns/v 0 0 ps 1-4 0.25 ns/v +50 +50 ps 1-4 0.5 ns/v +100 +100 ps 1-4 1. input slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. input slew rate is based on the larger of ac to ac delta rise, fall rate and dc to dc delta rise, fall rate. 3. the delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] for example: slew rate 1 = 0.5 v/ns; slew rate 2 = 0.4 v/ns. delta rise, fall = (1/0.5) - (1/0.4) [ns/v] = -0.5 ns/v using the table above, this would result in an increase in t ds and t dh of 100 ps. 4. these derating parameters may be guaranteed by design or test er characterization and are not necessarily tested on each devi ce.
nt1gd64s8ha0fm / nt1gd64s8hb0fm 1gb : 128m x 64 pc2700 / pc2100 unbuffered ddr so-dimm rev 1.2 13 12/19/2003 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. package dimensions non-ecc, bga devices 67.60 4.00+/-0.10 1.00+/- 0.1 front side 1.00+/- 0.10 detail a 2.55 0.60 detail b 0.45 0.25 max 199 13941 detail a detail b 4.00 20.00 31.75 6.00 2.15 11.40 4.20 1.80 47.40 3.80 max (2x) 1.80 2.45 back 63.60 note: all dimensions are typical with tolerances of +/- 0.15 unless otherwise stated. units: millimeters (inches)
nt1gd64s8ha0fm / nt1gd64s8hb0fm 1gb : 128m x 64 pc2700 / pc2100 unbuffered ddr so-dimm rev 1.2 14 12/19/2003 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. revision log rev date modification 0.1 05/2003 preliminary release 0.2 05/2003 updated functional block diagram 0.3 11/2003 updated format. 1.0 12/12/2003 release 1.1 dec 17,2003 update to tables 1.2 dec 19, 2003 idd from device level nanya technology corporation hwa ya technology park 669 fu hsing 3rd rd., kueishan, taoyuan, 333, taiwan, r.o.c. tel: +886-3-328-1688 please visit our home page for more information: www.nanya.com printed in taiwan ?2003

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