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? document id# 080686 date: aug 29, 2005 rev: e version: 1 distribution: public document le79555 subscriber line interface circuit ve580 series applications ? ideal for high-density, low-power linecard applications features ? control states: active, reverse polarity, tip open, ringing, standby, and open circuit ? low standby power ? ?40 to ?58 v battery operation ? on-hook transmission ? two-wire impedance set by single external impedance ? programmable constant-current feed ? low off-hook active overhead voltage ? programmable loop-detect threshold ? ground-start detector ? programmable ring-trip detect threshold ? no ?5 v supply required ? three on-chip relay drivers and relay snubbers, one ringing and two general purpose ? tip open state for ground-start lines ? on-chip switching regulato r for low powe r dissipation ? supports 30 ma for active, norma,l and reverse polarity operation description the le79555 device, part of legerity?s voiceedge? family ve580 series of devices, was designed for high-density pots applications requiring a power saving, small footprint slic device. the new slic device fulf ills today's requirements for pots linecard markets requiring a balance of high- performance cost-effective si licon components. the le79555 device delivers economical linecard solutions by offering power and space savings to linecard designers. the on-chip switching regulator allows for power dissipation to be minimized for the entire system. another benefit is that the device is offered in a reduced footprint package type, a 44-pin tqfp. this small footprint saves designers board space, thus increasing the density or number of lines on the board. legerity offers a range of compatible slac? devices providing a complete line circuit that can be optimized for varying requirements. the slic device is designed to operate with a range of slac devices from low cost, non- programmable to more advanced, highly programmable options viable for a range of applications. related literature ? 080125 slic switcher circuit application note ? 080725 le79555 switching regulator applications ? 080753 le58ql02/021/031 qlslac? data sheet ? 080754 le58ql061/063 qlslac? data sheet block diagram two wire interface signal transmission input decoder and control ring relay driver relay driver relay driver off-hook detector power feed controller ring-trip detector switching regulator chs qbat chclk vcc rsvd agnd a(tip) hpa hpb b(ring) da db l vbat bgnd ringout ryout1 ryout2 c1 vtx rd det c2 c3 d1 d2 rsn rdc cas vdc ground detector vreg ordering information 1. the green package meets rohs directive 2002/95/ec of the european council to minimize the environmental impact of electrical equipment. 2. for delivery using a tape and reel packing system, add a "t" suffix to the opn (ordering part number) when placing an order. standard packages device performance grade/package packing 2 le79555-1vc le79555-1qc 52 db pol. rev., 44-pin tqfp 52 db pol. rev., 32-pin qfn tray le79555-2vc le79555-2qc 63 db pol. rev., 44-pin tqfp 63 db pol. rev., 32-pin qfn tray le79555-3vc le79555-3qc 52 db no pol. rev., 44-pin tqfp 52 db no pol. rev., 32-pin qfn tray le79555-4vc le79555-4qc 63 db no pol. rev., 44-pin tqfp 63 db no pol. rev., 32-pin qfn tray green packages 1 device performance grade/package packing 2 le79555-1bvc le79555-1fqc 52 db pol. rev., 44-pin tqfp 52 db pol. rev., 32-pin qfn tray le79555-2bvc le79555-2fqc 63 db pol. rev., 44-pin tqfp 63 db pol. rev., 32-pin qfn tray le79555-3bvc LE79555-3FQC 52 db no pol. rev., 44-pin tqfp 52 db no pol. rev., 32-pin qfn tray le79555-4bvc le79555-4fqc 63 db no pol. rev., 44-pin tqfp 63 db no pol. rev., 32-pin qfn tray
2 le79555 ve580 series data sheet table of contents applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 related literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 block descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 two-wire interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 ground detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 signal transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 power feed controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 input decoder and control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 off-hook detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 ring-trip detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 ring relay driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 relay driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 transmission performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 longitudinal capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 idle channel noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 insertion loss and balance return signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 line characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 power supply rejection ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 rfi rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 receive summing node (rsn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 logic output det . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 ring-trip detector input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 loop detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 relay driver output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 dc feed characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 test circuit scenarios. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 line card parts list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 physical dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 44-pin tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 32-pin qfn (8x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 revision c1 to c2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 revision c2 to d1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 revision d1 to e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
le79555 ve580 series data sheet 3 product description the le79555 device is designed for short loop and long loop high- density pots applications requiring a power saving, small footprint slic. the le79555 device boasts increased power saving s over legerity's other pots solutions by using an internal switching regulator for each channel to enhance system power management. the switching regula tor eliminates the need for a second voltage supply, commonly required for slic devices in pots applications. such elimination passes on board space and cost savings to the designers. thus, the smaller footprint and added features of the le79555 devic e allows customers to amortiz e the cost of common hardware across more channels and increase the line density per board. additionally, the le79555 device gives line card designers a simple control interface that suppor ts six control states: active, ringing, standby, disconnect, re verse polarity, and tip open. the le79555 device is a low cost, high performance device providing ke y features required for pots markets worldwide, including: low power dissipation and ground key detection, as well as all of the features offered currently by legerity's transformer slic family, le7920/22. block descriptions two-wire interface the two-wire interface provides dc current and sends voice signals to a telephone apparatus connected to the line card with a two-wire line. the two-wire interface also receives the returning voice signals from the telephone. ground detector the ground detector block performs ground start and ground key dete ction, as well as automatical ly detects a ring-ground fault. therefore, when the longitudinal current is greater than the ground key detector threshol d, igk, in either active, standby, or tip open, the det will go low. note that when the device is in active or standby, det may be an indication of off-hook, ground fault, or both. signal transmission the rsn input current controls the receive current sent to the tw o-wire interface. the ac line voltage is sensed by differentia l amplifiers between the a and hpa leads, and between hpb and b leads. the outputs of these ampl ifiers are equal to the ac metallic components of the line voltages. the transmission circ uit also contains a longitudinal feedback circuit to shunt longitudinal signals to a dc bias voltage. the longitudinal feedback does not affect metallic signals. power feed controller the power feed controller has three sections: (1) the battery feed circuit, (2) the reverse polarity circuit, and (3) the bias circuit. the battery feed circuit regulates the amount of dc current and voltage supplied to the telephone over a wide range of loop resistance. the reverse polarity circuit provides the capability to reverse the loop current for pay telephone key pad disable and other applications. the bias circuit provides a reference voltage, which is offset from the sub scriber line voltage. the refere nce voltage controls the switched mode r egulator, which minimizes slic power cons umption by providing the minimum supply voltage needed by the line drivers for proper operation. switching regulator a switching regulator function is implemented on the chip with a few external components. the power feed contro ller generates a reference voltage which is the minimum voltage required to f eed the output line amplifiers. the efficiency of the switching regulator ( > 80%) minimizes both the on-chip power dissipation and the system power dissipation. this is particularly important for short loops operating at high currents wh ich otherwise cause high power dissipation. input decoder and control the input decoder and control blo ck provides a means for a microprocessor or slac ic to control such system functi ons as line activate, on-hook transmission, ringing, and reverse polarity. th e input decoder and control block has ttl-compatible inputs, which set the operating states of the slic. it also prov ides the supervision signal sent back to the controller. off-hook detector the most important loop monitoring function is off-hook detecti on. the two-wire interface produc es a current equal in magnitude to the loop current divided by a constant, and sends it out on the rd pin. an external resistor and capacitor (rd and cd) conne ct the rd pin to ground. the value of the voltage across resistor r d is proportional to the current leaving the rd pin times the value of r d . the det pin will show a logic low when this voltage rises above a threshold.
4 le79555 ve580 series data sheet ring-trip detector during the ringing state, the da pin is more positive than the db pin, and the det pin will show high to indicate the on hook. when an off hook condition occurs, the db pin beco mes more positive than the da pin, and the det pin will go low to indicate an off-hook. ring relay driver the ring relay driver is active only in the ringing state. relay driver a relay driver is activated by logic low at either input pin, d1 , or d2. d1 controls relay driver ryout1; d2 controls relay dri ver ryout2.
le79555 ve580 series data sheet 5 connection diagrams note: 1. pin 1 is marked for orientation. 2. n/c = no connect 3. rsvd = reserved 4. there is vbat potential on the exposed pad. do not connect to gnd pin. 11 10 9 8 7 6 5 4 3 2 1 23 24 25 26 27 28 29 30 31 32 33 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 da n/c rd n/c hpb n/c hpa n/c vtx n/c rsvd det c3 c2 n/c n/c cas vdc rdc agnd/ dgnd n/c rsn ryout1 ryout2 l vbat chs qbat chclk n/c d2 d1 c1 ringout vcc n/c vreg n/c bgnd n/c b(ring) a(tip) n/c db 44-pin tqfp 1 32-pin qfn exposed pad 21 20 19 18 17 22 23 24 2 3 4 5 6 7 8 10 912 11 14 13 16 15 32 31 30 29 28 27 26 25 c1 c3 angd/ dgnd vdc rdc c2 cas det chclk d2 d1 ryout2 l vbat chs qbat rsn rsvd vtx hpa hpb rd n/c da db b (ring) a (tip) bgnd vcc vreg ringout ryout1
6 le79555 ve580 series data sheet pin descriptions pin name type description agnd/ dgnd ground analog and digital ground. a(tip) output output of a(tip) power amplifier. bgnd ground battery (power) ground. b(ring) output output of b(ring) power amplifier. c3?c1 input slic control pins. c3 is msb and c1 is lsb. cas capacitor anti-saturation pin for capacitor to filter reference voltage when operating in anti-saturation region. chclk input (chopper clock) input to switching regulator. f = 200 to 600 khz. chs input (chopper stabilization) connection for external stabilization components. d2?d1 input relay driver control. d1 and d2 control the relay drivers ryout1 and ryout2. logic low on d1 activates the ryout1 relay driver. logic low on d2 activates the ryout2 relay driver. da input negative input to ring-trip comparator. db input positive input to ring-trip comparator. det output hook-switch detector. a logic low i ndicates that selected condition is detected. the detect condition is selected by the logic inputs (c3?c1). the out put is open-collector with a built-in 15 k ? pull-up resistor. hpa capacitor a (tip) side of high-pass filter capacitor. hpb capacitor b (ring) side of high-pass filter capacitor. l output (switching regulator power transis tor) connection point for filter inductor and anode of catch diode. this pin will have up to 60 v of pulse waveform on i t, and it must be isolated from sensitive circuits. care must be taken to keep the diode connections short because of the high currents and di/dt. n/c ? no connect. this pin is not internally connected. qbat battery (quiet battery) filtered battery supply for the signal-processing circuits. rd resistor detector threshold set and filter pin. rdc resistor connection point for the dc feed current programming network. the other end of the network connects to the receiver summing node (rsn). ringout output ring relay driver. open-collector dr iver with emitter inte rnally connected to bgnd. rsn input receive summing node. in the active, reverse polarity, and tip open states, the metallic current (both ac and dc) between a(tip) and b(ring) is equal to 500 times the current into this pin. the networks which program receive gain, two-wire imped ance, and feed resistance all connect to this node. ryout1 output relay/switch driver. open-collector dr iver with emitter internally connected to bgnd. ryout2 output relay/switch driver. open-collector dr iver with emitter internally connected to bgnd. vbat battery most negative battery. rsvd ? this is a reserved pin and must always be left open. vcc power supply +5 v power supply. vdc output output that is proportional to the line voltage: . kdc is the vdc scale factor. vreg input (regulated voltage) provides internal negative power supply and connection point for inductor, filter capacitor, and chopper stabilization. vtx output transmit audio. this output is a 0. 50 gain version of the a(tip) and b(ring) me tallic voltage. vtx also sources the two-wire input impedance programming network. exposed pad battery this must be connected to the most negative battery on the slic device pin side of d vbh shown on the test and application circuits. vdc kdc vab ? =
le79555 ve580 series data sheet 7 electrical characteristics absolute maximum ratings stresses greater than those listed under absolute maximum ratings can cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute ma ximum ratings for extended periods can effect device reliability. notes: thermal limiting circuitry on-chip will shut down t he circuit at a junction temperature of about 165 c. operation above 145 c junction temper- ature may degrade device reliability. the thermal performance of a thermally enhanced package is assure d through optimized printed circuit board layout. specified pe rformance re- quires that the exposed thermal pad be soldered to an equally siz ed exposed copper surface, which, in turn, conducts heat throu gh multiple vias to a large internal copper plane. package assembly the standard (non-green) package devices are assembled with in dustry-standard mold compounds, and the leads possess a tin/ lead (sn/pb) plating. these packages are compatible with conv entional snpb eutectic solder board assembly processes. the peak soldering temperature should not exceed 225c during printed circuit board assembly. the green package devices are assembled with enhanced environm ental compatible lead (pb), halogen, and antimony-free materials. the leads possess a matte-tin plating which is compat ible with conventional board assembly processes or newer lead- free board assembly processes. the peak soldering temperatur e should not exceed 245c during printed circuit board assembly. refer to ipc/jedec j-std-020b table 5-2 for the recommended solder reflow temperature profile. operating ranges legerity guarantees the performance of this device over commercial (0 to 70o c) and industrial (-40 to 85oc) temperature ranges by conducting electrical characterization over each range and by conducting a production test with single insertion coupled to periodic sampling. these characterization and test procedures comply with secti on 4.6.2 of bellcore gr-357-core component reliability assurance requirements for telecommunications equipment. storage temperature ?55 to +150oc v cc with respect to agnd ?0.4 to +7.0 v v bat with respect to agnd: continuous +0.4 to ?70 v 10 ms +0.4 to ?75 v bgnd with respect to agnd +3 to ?3 v a (tip) or b (ring) to bgnd: continuous v bat to +1 v 10 ms (f = 0.1 hz) ?70 to +5 v 1 s (f = 0.1 hz) ?80 to +8 v 250 ns (f = 0.1 hz) ?90 to +12 v current from a (tip) or b (ring) 150 ma ringout/ryout1,2 current 50 ma ringout/ryout1,2 voltage bgnd to +7 v ringout/ryout1,2 transient bgnd to +10 v da and db inputs: voltage on ring-trip inputs v bat to 0 v current into ring-trip inputs 10 ma c3?c1,d2?d1, chclk input voltage ?0.4 to v cc + 0.4 v maximum power dissipation, continuous, t a = 70c, no heat sink (see note) in 44-pin tqfp package in 32-pin qfn package 1.4 w 3.0 w thermal data: in 44-pin tqfp package in 32-pin qfn package ja 52 c/w typ 25 c/w typ esd immunity (human body model) jesd22 class 1c compliant ambient temperature ?40 to +85 c v cc 4.75 to 5.25 v v bat ?40 to ?58 v agnd 0 v bgnd with respect to agnd ?100 to +100 mv load resistance on vtx to ground 20 k ? min
8 le79555 ve580 series data sheet specifications refer to figure 9 , on page 16 for the le79555 test circuit specifications. transmission performance longitudinal capability ( see figure 6 . ) idle channel noise description test conditions (see note 1) min typ max unit note two-wire return loss 200 hz to 3.4 khz 26 db 1, 4 analog output (vtx) impedance 1 20 ? 4 analog (vtx) output offset voltage ?50 +50 mv overload level, 2-wire active state 2.5 vpk 2a overload level on hook, r lac = 600 ? 1.1 2b thd (total harmonic distortion) 0 dbm ?64 ?50 db 5 +7 dbm ?55 ?40 thd, on hook 0dbm, r lac = 600 ? ?36 5 description test conditions (see note 1) perf. grade min typ max unit note longitudinal to metallic l-t, l-4 200 hz to 1 khz normal polarity: db 0oc to +70oc -2,-4 63 -40oc to +85oc -2,-4 58 4 0oc to +70oc -1,-3 52 -40oc to +85oc -1,-3 50 4 reverse polarity: -40oc to +85oc -2 54 4 0oc to +70oc -1 52 -40oc to +85oc -1 50 4 longitudinal to metallic l-t, l-4 1 khz to 3.4 khz normal polarity: 0oc to +70oc -2,-4 58 -40oc to +85oc -2,-4 53 4 0oc to +70oc -1,-3 52 -40oc to +85oc -1,-3 50 4 reverse polarity: -40oc to +85oc -2 53 4 0oc to +70oc -1 52 -40oc to +85oc -1 50 4 longitudinal signal generation 4-l 200 hz to 3.4 khz 40 longitudinal current per pin (a or b) active state 17 27 marms 4, 8 longitudinal impedance at a or b 0 to 100 hz 25 ? /pin 4 description test conditions (see note 1) min typ max unit note c-message weighted noise r l = 600 ?, 0o to +70oc 7+10 dbrnc 4 r l = 600 ?, ?40o to +85oc +12 psophometric weighted noise r l = 600 ?, 0o to +70oc ?83 ?80 dbmp r l = 600 ? , ?40o to +85oc ?78
le79555 ve580 series data sheet 9 insertion loss and balance return signal ( see figure 4 and figure 5 .) line characteristics power supply rejection ratio description test conditions (see note 1) min typ max unit note gain accuracy, 4- to 2-wire 0 dbm, 1 khz 0o to +70 oc ?0.10 0 +0.10 db 3 0 dbm, 1 khz ? 40o to +85 oc ?0.15 +0.15 3, 4 gain accuracy 2- to 4-wire, 4- to 4-wire 0 dbm, 1 khz 0o to +70 oc ?6.12 ?6.02 ?5.92 3 0 dbm, 1 khz ? 40o to +85 oc ?6.17 ?5.87 3, 4 gain accuracy, 4- to 2-wire on hook ?0.35 +0.35 3,4 gain accuracy, 2- to 4-wire, 4- to 4-wire on hook ?6.37 ?6.02 ?5.67 gain accuracy over frequency 300 to 3.4 khz relative to 1 khz 0o to +70 oc ?0.10 +0.10 3 300 to 3.4 khz relative to 1 khz ? 40o to +85 oc ?0.15 +0.15 3, 4 gain tracking +3 dbm to ?55 dbm relative to 0 dbm 0o to +70 oc ?0.10 +0.10 3, 4 3, 4 +3 dbm to ?55 dbm relative to 0 dbm ? 40o to +85 oc ?0.15 +0.15 gain tracking on hook 0 dbm to ?37 dbm ?0.15 +0.15 3,4 +3 dbm to 0 dbm ?0.35 +0.35 description test conditions (see note 1) min typ max unit note i l , short loops, active state 22.5 24.5 26.5 ma i l , long loops, active state r l = 2010 ? 20 22.5 i l , standby state r l = 2010 ? t a = 25 oc 15 r l = 600 ? (current limit) 18 30 i l lim active, a and b to ground 75 120 k dc (v dc scaling) r l = 300 to 1500 ? 0.052 0.055 0.058 v ab , open circuit voltage active state 42.75 44 v i a , leakage, tip open state r l = 0 100 a i b , current, tip open state b to gnd 153056ma v a , active state ra to bat = 7 k ? , rb to gnd = 100 ? ?7.5 ?5 v 4 description test conditions (see note 1) min typ max unit note v cc , active state 50 hz to 3.4 khz (v ripple = 100 mv rms) 30 40 db 5 v bat , active state 50 hz to 3.4 khz off-hook constant current region (v ripple = 500 mv pp) 28 50 effective internal resistance cas pin to v bat 85 170 255 k ? 4 k dc v dc v ab ----------- =
10 le79555 ve580 series data sheet power dissipation supply currents rfi rejection receive summing node (rsn) logic inputs (c3-c1, d2-d1, and chclk) logic output det ring-trip detector input (da, db) description test conditions (see note 1) min typ max unit note on-hook, standby state r l = open 45 70 mw on-hook active state r l = open 130 190 off-hook, standby state 860 1200 off-hook active state 350 400 description test conditions (see note 1) min typ max unit note i cc , on-hook v cc supply current standby state 2.5 3.2 ma active/polarity reversed states 4.55 6.0 open circuit, r l = open 2.5 ringing, r l = open 6.0 i bat , on-hook v bat supply current + v reg supply current standby state 0.65 0.9 active/polarity reversed states 2.3 4.0 open circuit, r l = open 0.5 ringing, r l = open 1.5 description test conditions (see note 1) min typ max unit note vab, rms 100 khz to 30 mhz, (see figure 8 )1.0mvrms4 description test conditions (see note 1) min typ max unit note rsn dc voltage i rsn = 0 ma 0v 4 rsn impedance 200 hz to 3.4 khz 10 20 ? description test conditions (see note 1) min typ max unit note v ih , input high voltage 2.0 v v il , input low voltage 0.8 i ih , input high current ?75 40 a i il , input low current ?400 description test conditions (see note 1) min typ max unit note v ol , output low voltage i out = 0.3 ma 0.40 v v oh , output high voltage i out = ?0.1 ma 2.4 description test conditions (see note 1) min typ max unit note bias current ?500 ?50 na offset voltage source resistance = 2 m ? ?500+50mv6
le79555 ve580 series data sheet 11 loop detector relay driver output (ringout, ryout1, ryout2) figure 1. relay driver schematic 1. unless otherwise noted, r l = 600 ? . also, refer to the le79555 device test circuit in figure 9 , on page 16 . 2. a) overload level is defined as thd = 1%. b) overload level is defined as thd = 1.5%. 3. balance return signal is the signal generated at v tx by v rx . this specification assumes that the two-wire, ac-load impedance matches the programmed impedance. 4. not tested in production. this parameter is guarant eed by characterization or correlation to other tests. 5. this parameter is tested at 1 khz in production. perf ormance at other frequencies is guaranteed by characterization. 6. tested with 0 ? source impedance. 2 m ? is specified for system design only. 7. group delay can be greatly reduced by using a z t network such as that shown in figure 7 . the network reduces the group delay to less than 2 s and increases 2wrl. the effect of group delay on line card performance also may be co mpensated for by synthesizing co mplex impedance with the qlslac? device. 8. minimum current level guaranteed not to cause a false loop detect. description test conditions (see note 1) min typ max unit note off-hook threshold r d = 35.4 k ? 9.4 11.7 14.0 ma on-hook threshold r d = 35.4 k ? 8.8 10.4 12.0 hysteresis r d = 35.4 k ? 1.3 igk, ground-key detector threshold r l from bx to gnd active, standby, and tip open 5913 description test conditions (see note 1) min typ max unit note on voltage i ol = 40 ma +0.3 +0.7 v off leakage v oh = +5 v 100 a zener breakover i z = 100 a 67.2 v zener on voltage i z = 30 ma 8 ryout1, ryout2 ringout, bgnd
12 le79555 ve580 series data sheet note: ring ground detection in tip open is automat ic. if longitudinal current is greater than igk in active, standby, or tip open, th e det will go low. therefore, if in active or standby, det may be an indication of off hook, ground fault, or both. table 1. slic device decoding state c3c2c1 two-wire status det output 0 000reserved x 1 001reserved x 2 0 1 0 active reverse polarity (-1, 2 devices) loop detector 3 0 1 1 tip open ring ground (see note) 4 1 0 0 open circuit ring trip 5 1 0 1 ringing ring trip 6 1 1 0 active loop detector 7 1 1 1 standby loop detector table 2. user-programmable components z t is connected between the vtx and rsn pins. the fuse resistors are r f , and z 2win is the desired 2-wire ac input impedance. when computing z t , the internal current amplifier pole and any external stray capacitance between vtx and rsn must be taken into account. z rx is connected from vrx to rsn. z t is defined above, and g 42l is the desired receive gain. z l = load impedance, ad to bd. r dc1 , r dc2 , and c dc form the network connected to the r dc pin. r dc1 and r dc2 are approximately equal. i loop is the desired loop current in the constant-current region. (i threshold on to off hook ) (i threshold off to on hook ) r d and c d form the network connected from r d to agnd/dgnd and i t is the threshold current between on-hook and off-hook. c cas is the regulator filter capacitor and f c is the desired filter cut-off frequency. standby loop current (resistive region). z t 250 z 2win 2r f ? () = z rx z l g 42l ------------ - ? 500z t z t 250 z l 2r f + () + ---------------------------------------------------- = r dc1 r dc2 625 i loop --------------- = + c dc 1.5 ms r dc1 r dc2 + r dc1 r dc2 ? ----------------------------------- ? = i t off 414 r d --------- - , i t on 368 r d --------- - , c d 0.5 ms r d ------------------ - = = = c cas 1 170 k ? 2 f c ? ? ------------------------------------------ - = i standby v bat 3v ? 400 ? r l + -------------------------------- =
le79555 ve580 series data sheet 13 dc feed characteristics figure 2. load line (typical) regions: 1. constant current region: 2. battery tracking anti-sat: figure 3. feed programming 0 2 4 6 8 1012141618202224262830 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 v ab (v) loop current (ma) 2 1 v ab i l r l ' 625 r dc ----------- r l ' where r l ' r l 2r f + = , = = r dc r dc1 r dc2 + = v ab = |bat| ? v diode ? 7.2 v ? i l (r dc /210) r l a (tip) b (ring) rdc slic i l rsn r dc1 c dc r dc2
14 le79555 ve580 series data sheet test circuit scenarios figure 4. two-to-four-wire insertion loss figure 5. four-to-two-wire insertion loss and balance return signal figure 6. longitudinal balance slic a (tip) vtx agnd rsn v ab r t r rx i l2-4 = 20 log(v tx / v ab ) r l 2 r l 2 v l b (ring) slic a (tip) vtx agnd r sn v ab r t r rx i l4-2 = 20 log(v ab / v rx ) b (ring) brs = 20 log(v tx / v rx ) v rx r l slic a (tip) vtx agnd r sn v ab r t r rx l -t long. bal. = 20 log(v ab / v l ) b (ring) v r x r l 2 r l 2 v l s1 1 c r l << s2 s2 open, s1 closed s2 closed, s1open 4-l long. sig. gen. = 20 log(v l / v rx ) c l -4 long. bal. = 20 log(v tx / v l )
le79555 ve580 series data sheet 15 figure 7. two-wire return loss figure 8. rfi return loss = ?20 log (2v m / v s ) z d : the desired impedance; eg., the characteristic impedance of the line slic a (tip) vtx agnd rsn r rx = 150 k ? b (ring) c t1 = 180 p f r t1 r t2 v m z in = 600 ? z d = 600 ? v s r r 300 ? 300 ? 75 k ? 75 k ? 1.5 vrms 80% amplitude modulated 1 00 khz to 30 mhz hf gen 50 ? l 1 l 2 200 ? 200 ? c 1 c 2 50 ? 50 ? rf 1 rf 2 a (tip) b (ring) vtx c ax 33 nf c bx 33 nf slic device under test v ab
16 le79555 ve580 series data sheet figure 9. le79555 engineering test circuit da db da db a (tip) c ax 2.2 nf a (tip) c hp 220 nf b (ring) c bx 2.2 nf ringout ryout1 ryout2 n/c bat c qb 330 nf d vbh c ch1 15 nf r ch 1.3 k ? l 1 1mh c ch2 560 pf c fil 0.47 f d chclk1 hpa hpb b (ring) ringout ryout1 ryout2 bgnd rsvd qbat vbat chs vreg l vcc rd vtx +5 v r d r t vdc agnd cas chclk c cas batter y groun d analog groun d le79555 v tx v rx rsn rdc vdc d2 d1 c3 c2 c1 chclk r rx r dc1 r dc2 c dc d2 d1 c3 c2 c1 det det c v1 0.47 f - 52 v in400x mur120 low esr 256 khz 330 nf 220 nf 13.02 k ? 13.02 k ? 35.4 k ? 150 k ? 150 k ? v cc
le79555 ve580 series data sheet 17 application circuits note: 1. protection circuitry does not need to be battery tracking. 2. for chclk operation between 190 khz and 290 khz, l1 is recommended to be 2 mh. for chclk operation between 290 khz and 600 khz, l1 is recommended to be 1 mh. da db a(tip) c ax 2.2 nf a (tip) c hp 220 nf r f 50 ? rr rr b (ring) c bx 2.2 nf r f 50 ? - - - + ringout ryout1 ryout2 n/c c qb 0.33 f mur120 c ch1 15 nf r ch 1.3 k ? l 1 1mh c ch2 560 pf c fil 0.47 f d chclk1 mur120 u2 edf1dm 1 2 3 4 u3 p0640ea70 rs hpa hpb b(ring) ringout ryout1 ryout2 bgnd rsvd qbat vbat chs vreg l vcc rd vtx rsn rdc +5 va r d 35.7 k ? c d 15 nf r tx1 125 k ? c in vin #1 100 nf vout #1 c out 100 nf r dc1 r dc2 13 k ? 13 k ? vdc vdc agnd d2 d1 c3 c2 c1 det cas chclk c cas 330 nf chclk 124 k ? r rx battery ground analog ground u1 le79555 c dc 220 nf d vbh da db c7 #1 c6 #1 c5 #1 c4 #1 c3 #1 cd1 #1 r ing_source r sr 400 ? r sr3 1.0 m ? r sr1 909 k ? r sr2 1.0 m ? c sr1 330 nf bgnd r sr4 909 k ? c sr2 330 nf da rs db clock bat c v1 0.47 f
18 le79555 ve580 series data sheet u4 le58ql063 c7 #1 vin #2 c7 #2 chclk dxb drb tscb fs/fsc pclk/dcl mclk/e1 dclk/s0 cs/pg dio/s1 int rst +5vd vccd dgnd vcca vref agnd c ref +5v 0.1 f +5vd 10 k ? r pa r pb 10 k ? dxa/du dra/dd dxa/du dra/dd tsca tsca dxb drb tscb fs/fsc pclk/dcl mclk/e1 dclk/s0 cs/pg dio/s1 int rst vin #1 vout #1 cd1 #1 spare c3 #1 c4 #1 c5 #1 c6 #1 vin #1 vout #1 cd1 #1 cd2 #1 c3 #1 c4 #1 c5 #1 c6 #1 vin #2 c7 #1 vout #2 cd1 #2 spare c3 #2 c4 #2 c5 #2 c6 #2 vout #2 cd1 #2 cd2 #2 c3 #2 c4 #2 c5 #2 c6 #2 c7 #2 vin #3 vout #3 cd1 #3 spare c3 #3 c4 #3 c5 #3 c6 #3 c7 #3 vin #3 vout #3 cd1 #3 cd2 #3 c3 #3 c4 #3 c5 #3 c6 #3 c7 #3 vin #4 vout #4 cd1 #4 spare c3 #4 c4 #4 c5 #4 c6 #4 c7 #4 vin #4 vout #4 cd1 #4 cd2 #4 c3 #4 c4 #4 c5 #4 c6 #4 c7 #4 t o slic #1 (u1) to slic #2 to slic #3 to slic #4 chclk analog ground digital groun d
le79555 ve580 series data sheet 19 line card parts list the following list defines the parts and part values requir ed to meet target specification limits for one channel. item quantity type value tol. rating comments note c ch2 1 capacitor (cog) 560 pf 5% 50 v c ax , c bx 2 capacitor (x7r) 2200 pf 20% 100 v c ch1 1 capacitor (x7r) 15 nf 10% 50 v c hp 1 capacitor (x7r) 220 nf 20% 100 v c dc 1 capacitor (x7r) 220 nf 20% 16 v c cas 1 capacitor (x7r) 330 nf 20% 100 v c qb 1 capacitor (x7r) 330 nf 20% 100 v c v1 1 capacitor (x7r) 470 nf 20% 100 v c fil 1 capacitor (low esr) 470 nf 20% 100 v c d 1 capacitor (x7r) 15 nf 10% 16 v r f 1 resistor hybrid 50 1% r ch 1 axial/smt 1.3 k 1% 0.1 w rdc1, rdc2 2 smt 13.0 k 1% 0.1 w rd 1 smt 35.7 k 1% 0.1 w rt 1 smt 124 k 1% 0.1 w rrx 1 smt 124 k 1% 0.1 w d vbh , d chclk1 2 mur 120 (d0-41) diode 1 a, 100 v l1 1 coiltronics sd25-102 inductor 1.0 mh (20 > r > 5) 100 ma u3 1 sidactor p0640ea70 u2 1 diode bridge edf1dm u1 1 le79555 u4 1 le58ql063 c in , c out , c ref 3 capacitor (x7r) 100 nf 20% 16 v rpa, rpb 2 smt 10 k 1% 0.25 w r sr2 , r sr3 2 smt 1 m 1% 0.25 w r sr4 , r sr1 2 smt 909 k 1% 0.25 w c sr1 , c sr2 2 capacitor (x7r) 330 nf 20% 100 v r sr 1 resistor hybrid 400 1%
20 le79555 ve580 series data sheet physical dimensions 44-pin tqfp note: bsc is an ansi standard for basic centering. dimensions are meas ured in millimeters. dwg rev. as; 08/00 tqfp 044 tqfp 044
le79555 ve580 series data sheet 21 32-pin qfn (8x8) notes: 1. dimensioning and tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. is in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jep 95-1 and ssp-012. details of the terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. coplanarity applies to the exposed pad as well as the terminals. 6. reference document: jedec mo-220. 7. lead width deviates from the jedec mo-220 standard. 0.57 0.80 0.90 1.00 ref 0.18 0.23 0.28 8.00 bsc 5.70 5.80 5.90 8.00 bsc 5.70 5.80 5.90 0.80 bsc 0.43 0.53 0.63 32 0.00 0.02 0.05 0.20 ref 0.20 0.10 0.10 32 lead qfn symbol min nom max 32 lead qfn with chamfer
22 le79555 ve580 series data sheet revision history revision a to b ? updated document format. ? in the "features" section, the following changes were made: ? removed "(45 mw)" from low standby power (since it?s already in the specification). ? changed battery voltage range from ? 16 v to ? 58 v to ? 40 v to ? 58 v. ? removed "(6.5 v)" from low off-hook active overhead voltage. ? in "related literature", added the "introdu ction to the slic family" application note. ? added the 32-pin plcc information to the ordering information and absolute maximum ratings sections and added the connection diagram. ? updated the connection diagram. ? updated the pin description table to correct inconsistencies; added range for chclk. ? in the electrical characteristics table: ? updated the information in the line characteristics section on the long loops row and the vdc accuracy row. ? deleted the disconnect state information in the power dissipation and supply currents sections. ? in "specifications", the following changes were made: ? added a column for performance grade in the longitudinal capability and insertion loss and balance return signal tables. ? changed test circuit reference in the longitudinal capability table ? updated the insertion loss and balance return signal table. ? in the line characteristics table, i l standby state test conditions, changed the equation to r l = 2.5 k. ? in the line characteristics table, added spec for overhead voltage. ? made changes to test conditions for i l , long loops, active state; kdc (v dc accuracy); vab, open circuit voltage in the line characteristics table. ? added value for chclk in note 1. ? in the "dc feed characteristics" section, revised equat ions in notes and updated dc feed characteristics graphic. ? changed the equation for z rx in the user-programmables table ? updated engineering test circuit and application circuit graphics; added graphic for u4/am79q063 ? added linecard parts list page ? the physical dimension (pqt044) was added to the physical dimension section. revision b to c ? removed current gain featur e from the "features" section ? updated "related literature" section to include the qlslac data sheets ? in the "ordering information" table, added dashes before performance grades ? removed package graphic from "ordering information" section ? added opns for the qfn package in "ordering information"; added note regarding markings on qfn packages ? edited "block descriptions" section ? in "connection diagrams," added pinout diagram for 32-pin qfn package; added notes regarding exposed pad and rsvd pin ? in the "pin descriptions" table, the following edits were made: ? updated the pin description table to correct inconsistencies ? edited the description of the rsn pin ? added range for chclk ? made minor edits to rsvd description ? added a sentence to the description for vdc ? added a row to describe the exposed pad ? in "electrical characteristics", "absolute maximum ratings" table, the following was added: ? max power dissipation of 3.0 w for 32-pin qfn package ? thermal data for 32-pin qfn package ? added a note regarding maximum power dissipation values under the absolute maximum ratings table
le79555 ve580 series data sheet 23 ? in the "operating ranges" table, chan ged the ambient temperature range to ? 40o to 85o c ? in "specifications," the following changes were made: ? "transmission performance" table, overload level, edited test conditions; changed min to 1.1; changed units to vpk. ? "transmission performance" table, thd, on-hook, edited test conditions; changed units to db ? "longitudinal capability" table, longitudinal current per pin (a or b), added note 4 to note column ? "insertion loss and balance return signal" table, gain accu racy, 2-to-4 and 4-to-4 wire, changed max from -5.82 to - 5.87 ? "insertion loss and balance return signal" table, deleted the group delay row ? "line characteristics" table, changed k dc (v dc accuracy) to k dc (v dc scaling) ? "line characterisitcs" table, i l , long loops, active state, edited the test conditions ? "line characterisitcs" table, k dc (v dc scaling), edited the test conditions ? "power dissipation" table, changed the description "on-hook, ac tive, polarity reversal state" to "on-hook active state" ? "power dissipation" table, changed max value of off-hook active state from 380 mw to 400 mw ? "supply currents" table, added rl = open to open circuit and ringing test conditions; deleted references to note 4 ? "power dissipation" table, on-hook standby and on -hook active, added rl = open to test conditions ? changed "power supply rejection ratio" to "power supply rejection ratio at the two-wire interface" ? "power dissipation" table, on-hook, standby state, changed max from 60 to 70 ? "logic inputs" table, added chclk as an input ? "logic inputs" table, edited description of v ih , input high voltage ? "logic inputs" table, deleted row for v ih , c3, chclk ? "logic inputs" table, edited description of v il ? "logic output det " table, edited test conditions ? "loop detector" table, changed "on th reshold" to "off-hook threshold" ? "loop detector" table, changed "off threshold" to "on-hook threshold" ? extensively edited note 1; removed figure 2, "ac input impedance programming network" ? made minor formatting edits to slic device decoding table ? in "user-programmable components", the following changes were made: ? edited equations for i ton and i toff ? edited equation for z rx and c cas . ? in "dc feed characteristics", edited note 2 ? in "test circuit scenarios", the following changes were made: ? edited title of graphic "four-to-four-wire insertion loss and balance return signal" ? modified longitudinal balance graphic ? modified two-wire return loss graphic (changed ct1 from 120 pf to 180 pf) ? modified rfi graphic ? modified le79555 test circuit graphic ? modified application circuit graphic ? added note 2 to "application circuit" section ? updated linecard parts list to reflect the updated application circuit revision c1 to c2 ? formatting updates made revision c2 to d1 ? added green package opns to ordering information , on page 1 ? added package assembly , on page 7 revision d1 to e1 ? added "packing" column and note 2 to ordering information , on page 1 ? updated 32qfn drawing in physical dimensions , on page 20
24 le79555 ve580 series data sheet the contents of this document are provided in connection with l egerity, inc. products. legerity makes no representations or war ranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descri ptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellect ual property rights is granted by this pub lication. except as set forth in legerity's standard terms and conditions of sale, legerity assumes no liab ility whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitn ess for a particular purpose, or infringement of any intellect ual property right. legerity's products are not designed, intended, authorized or warra nted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any ot her application in which the failure of legerity's product could create a situation where personal injury, death, or severe property or environmental damage may occur. leger ity reserves the right to discontinue or make changes to its products at any time without notice. ? 2005 legerity, inc. all rights reserved. trademarks legerity, the legerity logo and combinations thereof, slac, qlslac, winslac, and voiceedge are trademarks of legerity, inc. other product names used in this publication are for identifica tion purposes only and may be trademarks of their respective com panies.
4509 freidrich lane austin, texas 78744-1812 telephone: (512) 228-5400 fax: (512) 228-5508 north america toll free: (800) 432-4009 to find the legerity sales office nearest you, visit our website at: http://www.legerity.com/sales or email: sales@legerity.com to download or order data sheets, application notes, or evaluation tools, go to: www.legerity.com/support for all other technical inquiries, please contact legerity tech support at: techsupport@legerity.com or call +1 512.228.5400. tm

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