wireless mcu copyright ? 2010 by silicon laboratories 1.15.10 cip-51 8051 controller core 64k byte isp flash program memory 256 byte sram sfr bus 4096 byte xram vdd xtal1 sysclk system clock configuration external oscillator circuit precision 24.5 mhz oscillator debug / programming hardware power on reset/pmu reset c2d c2ck/rst wake xtal2 low power 20 mhz oscillator smartclock oscillator xtal3 xtal4 gnd vreg crc engine rxp rxn tx xin xout analog peripherals comparators + - 10-bit 300ksps adc a m u x temp sensor external vref internal vref vdd 6-bit iref vref gnd iref0 cp0, cp0a + - cp1, cp1a xcvr (240-960 mhz) osc pa lna agc digital modem delta sigma modulator digital logic mixer pga adc port i/o config digital peripherals uart timers 0, 1, 2, 3 pca/ wdt smbus priority crossbar decoder transceiver control interface spi 0 22 analog & digital i/o SI1000-C ultra-low power 64 kb, 10-bit adc mcu with integrated 240?960 mhz transceiver supply voltage: 1.8 to 3.6 v - typical sleep mode current < 0.1 a; retains state and ram contents over full supply range; fast wakeup of < 2 s - two built-in brown-out detectors cover sleep and active modes 10-bit analog to digital converter - up to 300 ksps - up to 18 external inputs - external pin or internal vref (no external capacitor required) - built-in temperature sensor (3 c); no calibration required - external conversion start input option - autonomous burst mode with 16-bit automatic averaging ? accumulator dual comparators - programmable hysteresis and response time - configurable as interrupt or reset source - low current (< 0.5 a) memory - 64 kb bytes flash; in-system programmable in 1024-byte ? sectors; full read/write/erase functionality over the entire ? supply range - 4352 bytes internal data ram (256 + 4k) on-chip debug - on-chip debug circuitry facilitate s full speed, non-intrusive in- system debug (no emulator required) high-speed 8051 c core - pipe-lined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - 25 mips peak throughput with 25 mhz clock development kit: si1000dk transceiver features - frequency range = 240?960 mhz - sensitivity = ?121 dbm - fsk, gfsk, and ook modulation - max output power = +20 dbm - rf power consumption - 18.5 ma receive - 85 ma @ +20 dbm transmit - data rate = 0.123 to 256 kbps - auto-frequency calibration (afc) - antenna diversity and transmit/receive switch control - programmable packet handler - tx and rx 64 byte fifos - frequency hopping capability - on-chip crystal tuning digital peripherals - 22 port i/o - hardware enhanced uart, spi and i 2 c serial ports available concurrently - low power 32-bit smartclock - four general purpose 16-bit counter/timers; six channel ? programmable counter array (pca) clock sources - precision internal oscillators: 24.5 mhz with 2% accuracy sup - ports uart operation; spread-spectrum mode for reduced emi - low power 20 mhz internal oscillator - external oscillator: crys tal, rc, c, cmos clock - smartclock oscillator: 32.768 khz crystal or self-oscillate ordering part number - SI1000-C-gm, 42-pin qfn 5 x 7 mm 2
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