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lxt300z/lxt301z advanced t1/e1 short-haul transceivers datasheet the lxt300z and lxt301z are fully integrated transceivers for both north american 1.544 mbps (t1) and international 2.048 mbps (e1) applications. they are pin and functionally compatible with standard lxt300/301 devices, with some circuit enhancements. the lxt300z provides receive jitter attenuation starting at 3 hz, and is microprocessor controllable through a serial interface. the lxt301z is pin compatible, but does not provide jitter attenuation or a serial interface. an advanced transmit driver architecture provides constant low output impedance for both marks and spaces, for improved bit error rate performance over various cable network configurations. both transceivers offer a variety of diagnostic features including transmit and receive monitoring. clock inputs may be derived from an on-chip crystal oscillator or from digital inputs. they use an advanced double-poly, double-metal cmos process and require only a single 5-volt power supply. applications product features pcm/voice channel banks data channel bank/concentrator t1/e1 multiplexers digital access and cross-connect systems (dacs) computer to pbx interfaces (cpi & dmi) high-speed data transmission lines interfacing customer premises equipment to a csu digital loop carrier (dlc) terminals data recovery and clock recovery functions receive jitter attenuation starting at 3 hz exceeds at&t pub 62411, pub 43801, pub 43802, itu g.703, and itu g.823 (lxt300z only) line driver with constant low mark and space impedance (3 ? typical) minimum receive signal of 500 mv adaptive and selectable (e1/dsx-1) slicer levels for improved snr programmable transmit equalizer shapes pulses to meet dsx-1 pulse template from 0 to 655 feet or drive 120 ? twisted pair or 75 ? coax cable for e1 local and remote loopback functions digital transmit driver monitor digital receive monitor with loss of signal (los) output and first mark reset receiver jitter tolerance 0.4 ui from 40 khz to 100 khz microprocessor controllable (lxt300z only) compatible with most popular pcm framers available in 28-pin dip or plcc as of january 15, 2001, this document replaces the level one document order number: 249066-001 lxt300z/lxt301z ? advanced t1/e1 short-haul transceivers . january 2001
datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the lxt300z/lxt301z may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel?s website at http://www.intel.com. copyright ? intel corporation, 2001 *third-party brands and names are the property of their respective owners.
datasheet 3 advanced t1/e1 short-haul transceivers ? lxt300z/lxt301z contents 1.0 pin assignments and signal descriptions ...................................................... 6 2.0 functional description ............................................................................................. 9 2.1 power requirements............................................................................................. 9 2.1.1 reset operation (lxt300z and lxt301z) ..............................................9 2.2 receiver ..............................................................................................................10 2.2.1 receive (loss of signal) monitor ...........................................................11 2.2.2 jitter attenuation (lxt300z only)..........................................................11 2.3 transmitter ..........................................................................................................11 2.3.1 driver performance monitor ...................................................................11 2.3.2 line code ...............................................................................................12 2.4 operating modes.................................................................................................12 2.4.1 host mode operation (lxt300z only)...................................................12 2.4.2 hardware mode operation (lxt300z and lxt301z) ............................12 2.4.3 diagnostic mode operation....................................................................14 2.4.3.1 transmit all ones ......................................................................14 2.4.3.2 remote loopback .....................................................................14 2.4.3.3 local loopback .........................................................................14 3.0 application information .........................................................................................16 3.1 lxt300z host mode 1.544 mbps t1 interface ...................................................16 3.2 lxt300z hardware mode e1 interface application ............................................17 3.2.1 lxt301z 1.544 mbps t1 interface application ......................................19 3.2.2 lxt301z 2.048 mbps e1 interface application......................................20 4.0 test specifications ..................................................................................................21 5.0 mechanical specifications ....................................................................................29
lxt300z/lxt301z ? advanced t1/e1 short-haul transceivers 4 datasheet figures 1 lxt300z/lxt301z block diagram ....................................................................... 5 2 lxt300 pin assignments and package markings ................................................ 6 3 lxt301z block diagram ..................................................................................... 10 4 50% ami coding ................................................................................................. 13 5 lxt300z serial interface data structure ............................................................ 15 6 typical lxt300z 1.544 mbps t1 application (host mode)................................. 17 7 typical lxt300z 75 w e1 application (hardware mode)................................... 18 8 typical lxt301z 1.544 mbps t1 application ..................................................... 19 9 typical lxt301z 75 w e1 application................................................................ 20 10 lxt300z typical receive jitter tolerance ......................................................... 23 11 lxt300z typical receive jitter transfer performance ...................................... 24 12 lxt300z receive clock timing diagram ........................................................... 25 13 lxt301z receive clock timing diagram ........................................................... 26 14 lxt300z/301z transmit clock timing diagram................................................. 26 15 lxt300z serial data input timing diagram ....................................................... 27 16 lxt300z serial data output timing diagram .................................................... 28 17 package specifications ....................................................................................... 29 tables 1 pin descriptions .................................................................................................... 7 2 lxt300z serial data output bits (see figure 5 ) ................................................ 13 3 valid clke settings............................................................................................ 13 4 equalizer control inputs...................................................................................... 14 5 lxt300z crystal specifications (external) ......................................................... 18 6 absolute maximum ratings ................................................................................ 21 7 recommended operating conditions ................................................................. 21 8 electrical characteristics..................................................................................... 21 9 analog characteristics ........................................................................................ 22 10 lxt300z receiver timing characteristics (see figure 12 )................................ 24 11 lxt301z receive timing characteristics (see figure 13 ) ................................. 25 12 lxt300z/301z master clock and transmit timing characteristics (see figure 14) ................................................................................................... 26 13 lxt300z serial i/o timing characteristics (see figure 15 and figure 16 )........ 27
advanced t1/e1 short-haul transceivers ? lxt300z/lxt301z datasheet 5 figure 1. lxt300z/lxt301z block diagram control equalizer synchronizer hos t int sdi sdo cs sclk h/w ec1 ec2 ec3 rloop lloop taos tpos tneg tclk internal clock generator jitter attenuator elastic store timing recovery peak detector ttip tring rtip rring data latch receive monitor transmit driver control mtip mring mclk xtalin xtalout rclk rpos los rneg dpm constant impedance line driver mode data slicers
lxt300z/lxt301z ? advanced t1/e1 short-haul transceivers 6 datasheet 1.0 pin assignments and signal descriptions figure 2. lxt300 pin assignments and package markings package topside markings marking definition part # unique identifier for this product family. rev # identifies the particular silicon ? stepping ? ? refer to the specification update for additional stepping information. lot # identifies the batch. fpo # identifies the finish process order. mclk tclk tpos tneg mode rneg rpos rclk xtalin xtalout dpm los ttip tgnd 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 clke / taos sclk / lloop cs / rloop sdo / ec3 sdi / ec2 int / ec1 rgnd rv+ rring rtip mring mtip tring tv+ lxt300zne mclk tclk tpos tneg gnd rneg rpos rclk rt n/c dpm los ttip tgnd taos lloop rloop ec3 ec2 ec1 rgnd rv+ rring rtip mring mtip tring tv+ mode rneg rpos rclk xtalin xtalout dpm 25 24 23 22 21 20 19 5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 2 1 28 27 26 sdo / ec3 sdi / ec2 int / ec1 rgnd rv+ rring rtip tneg tpos tclk mclk clke / taos sclk / lloop cs / rloop los ttip tgnd tv+ tring mtip mring 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LXT301ZNE gnd rneg rpos rclk rt n/c dpm 25 24 23 22 21 20 19 5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 2 1 28 27 26 ec3 ec2 ec1 rgnd rv+ rring rtip tneg tpos tclk mclk taos lloop rloop los ttip tgnd tv+ tring mtip mring lxt301zpe xx xxxxxx xxxxxxxx lxt300zpe xx xxxxxx xxxxxxxx
advanced t1/e1 short-haul transceivers ? lxt300z/lxt301z datasheet 7 table 1. pin descriptions pin # sym i/o 1 description 1mclkdi master clock. a 1.544 or 2.048 mhz clock input used to generate internal clocks. upon loss of signal (los), rclk is derived from mclk. lxt300z only: if mclk is not applied, this pin must be grounded. 2tclkdi transmit clock. transmit clock input. tpos and tneg are sampled on the falling edge of tclk. if tclk is grounded, the output drivers enter a high-z state, except during remote loopback. 3tposdi transmit positive data. input for positive pulse to be transmitted on the twisted-pair line or coax. 4tnegdi transmit negative data. input for negative pulse to be transmitted on the twisted-pair line. 5 mode di mode select (lxt300z) . setting mode high puts the lxt300z in the host mode. in the host mode, the serial interface is used to control the lxt300z and determine its status. setting mode low puts the lxt300z in the hardware (h/w) mode. in the hardware mode, the serial interface is disabled and hard-wired pins are used to control configuration and report status. gnd s ground (lxt301z) . tie to ground. 6 rneg do receive negative data; receive positive data. received data outputs. a signal on rneg corresponds to receipt of a negative pulse on rtip and rring. a signal on rpos corresponds to receipt of a positive pulse on rtip and rring. rneg and rpos outputs are non-return-to-zero (nrz). both outputs are stable and valid on the rising edge of rclk. lxt300z only: in the host mode, clke determines the clock edge at which these outputs are stable and valid. in the hardware mode both outputs are stable and valid on the rising edge of rclk. 7rposdo 8rclkdo recovered clock. this is the clock recovered from the signal received at rtip and rring. 9 rt ai receive termination (lxt301z) . connect to rv+ through a 1 k ? resistor. xtalin ai crystal input; crystal output (lxt300z) . an external crystal operating at four times the bit rate (6.176 mhz for dsx-1, 8.192 mhz for e1 applications with an 18.7 pf load) is required to enable the jitter attenuation function of the lxt300z. these pins may also be used to disable the jitter attenuator by connecting the xtalin pin to the positive supply through a resistor, and floating the xtalout pin. 10 xtalout ao 10 n/c ? no connection (lxt301z) . 11 dpm do driver performance monitor. dpm goes high when the transmit monitor loop (mtip and mring) does not detect a signal for 63 2 clock periods. dpm remains high until a signal is detected. 12 los do loss of signal. los goes high when 175 consecutive spaces have been detected from receive. los returns low when a mark is detected from the receiver. 13 ttip ao transmit tip; transmit ring. differential driver outputs. these outputs are designed to drive a 25 ? load. the transmitter will drive 100 ? shielded twisted-pair cable through a 1:2 step-up transformer without additional components. to drive 75 ? coaxial cable, two 2.2 ? resistors are required in series with the transformer. 16 tring ao 14 tgnd s transmit ground. ground return for the transmit driver power supply tv+. 15 tv+ s transmit driver power supply. +5 vdc power supply input for the transmit drivers. tv+ must not vary from rv+ by more than 0.3 v. 17 mtip ai monitor tip; monitor ring. these pins are used to monitor the tip and ring transmit outputs. the transceiver can be connected to monitor its own output or the output of another lxt300z or lxt301z on the board. 18 mring ai 1. di = digital input; do = digital output; ai = analog input; ao = analog output; s = supply.
lxt300z/lxt301z ? advanced t1/e1 short-haul transceivers 8 datasheet 19 rtip ai receive tip; receive ring. the ami signal received from the line is applied at these pins. a center-tapped, center-grounded, 2:1 step-up transformer is required on these pins. data and clock from the signal applied at these pins are recovered and output on the rpos/rneg and rclk pins. 20 rring ai 21 rv+ s receive power supply. +5 vdc power supply for all circuits except the transmit drivers. (transmit drivers are supplied by tv+.) 22 rgnd s receive ground. ground return for power supply rv+. 23 int do interrupt (lxt300z - host mode) . this output goes low to flag the host processor when los or dpm go active. int is an open-drain output and should be tied to power supply rv+ through a resistor. int is reset by clearing the respective register bit (los and/or dpm). ec1 di equalizer control 1 (lxt301z and lxt300z - h/w mode) . the signal applied at this pin is used in conjunction with ec2 and ec3 inputs to determine shape and amplitude of ami output transmit pulses. 24 sdi di serial data in (lxt300z - host mode) . the serial data input stream is applied to this pin. sdi is sampled on the rising edge of sclk. ec2 di equalizer control 2 (lxt301z and lxt300z - h/w mode) . the signal applied at this pin is used in conjunction with ec1 and ec3 inputs to determine shape and amplitude of ami output transmit pulses. 25 sdo do serial data out (lxt300z - host mode) . the serial data from the on-chip register is output on this pin. if clke is high, sdo is valid on the rising edge of sclk. if clke is low sdo is valid on the falling edge of sclk. this pin goes to a high-impedance state when the serial port is being written to and when cs is high. ec3 di equalizer control 3 (lxt301z and lxt300z - h/w mode) . the signal applied at this pin is used in conjunction with ec1 and ec2 inputs to determine shape and amplitude of ami output transmit pulses. 26 cs di chip select (lxt300z - host mode) . this input is used to access the serial interface. for each read or write operation, cs must transition from high to low, and remain low. rloop di remote loopback (lxt301z and lxt300z - h/w mode) . setting rloop high enables the remote loopback mode. setting both rloop and lloop high causes a reset. 27 sclk di serial clock (lxt300z - host mode) . this clock is used to write data to or read data from the serial interface registers. lloop di local loopback (lxt301z and lxt300z - h/w mode) . this input controls loopback functions. setting lloop high enables the local loopback mode. 28 clke di clock edge (lxt300z - host mode) . setting clke high causes rpos and rneg to be valid on the falling edge of rclk, and sdo to be valid on the rising edge of sclk. when clke is low, rpos and rneg are valid on the rising edge of rclk, and sdo is valid on the falling edge of sclk. taos di transmit all ones (lxt301z and lxt300z - h/w mode) . when high, a continuous stream of marks is transmitted at the tclk frequency. activating taos causes tpos and tneg inputs to be ignored. taos is inhibited during remote loopback. table 1. pin descriptions (continued) pin # sym i/o 1 description 1. di = digital input; do = digital output; ai = analog input; ao = analog output; s = supply.
advanced t1/e1 short-haul transceivers ? lxt300z/lxt301z datasheet 9 2.0 functional description the lxt300z and lxt301z are fully integrated pcm transceivers for both 1.544 mbps (dsx-1) and 2.048 mbps (e1) applications. both transceivers allow full-duplex transmission of digital data over existing twisted-pair or coax installations. the first page of this data sheet shows a simplified block diagram of the lxt300z and figure 3 shows the lxt301z. the lxt301z is similar to the lxt300z, but does not incorporate the jitter attenuator and associated elastic store, nor the serial interface port. the lxt300z and lxt301z transceivers each interface with two twisted-pair or coax lines (one pair or coax for transmit, one pair or coax for receive) through standard pulse transformers and appropriate resistors. 2.1 power requirements the lxt300z and lxt301z are low-power cmos devices. each operates from a single +5 v power supply which can be connected externally to both the transmitter and receiver. however, the two inputs must be within 0.3v of each other, and decoupled to their respective grounds separately. refer to ?application information? on page 16 for typical decoupling circuitry. isolation between the transmit and receive circuits is provided internally. 2.1.1 reset operation (lxt300z and lxt301z) upon power up, the transceiver is held static until the power supply reaches approximately 3 v. upon crossing this threshold, the device begins a 32 ms reset cycle to calibrate the transmit and receive delay lines and lock the phase lock loop (pll) to the receive line. a reference clock is required to calibrate the delay lines. the transmitter reference is provided by tclk. mclk provides the receiver reference for the lxt301z. the crystal oscillator provides the receiver reference in the lxt300z. if the lxt300z crystal oscillator is grounded, mclk is used as the receiver reference clock. the transceiver can also be reset from the host mode or hardware mode. in host mode, reset is commanded by simultaneously writing rloop and lloop to the register. in hardware mode, reset is commanded by holding rloop and lloop high simultaneously for 200 ns. reset is initiated on the falling edge of the reset request. in either mode, the reset clears and sets all registers to 0 and then calibration begins.
lxt300z/lxt301z ? advanced t1/e1 short-haul transceivers 10 datasheet 2.2 receiver the lxt300z and lxt301z receivers are identical except for the jitter attenuator and elastic store. the following discussion applies to both transceivers except where noted. the signal is received from one twisted-pair line on each side of a center-grounded transformer. positive pulses are received at rtip and negative pulses are received at rring. recovered data is output at rpos and rneg, and the recovered clock is output at rclk. refer to the ? test specifications ? section of this data sheet for receiver timing. the signal received at rpos and rneg is processed through the peak detector and data slicers. the peak detector samples the inputs and determines the maximum value of the received signal. a percentage of the peak value is provided to the data slicers as a threshold level to ensure optimum signal-to-noise ratio. for dsx-1 applications (determined by equalizer control inputs ec1~ec3 000) the threshold is set to 70% of the peak value. this threshold is maintained above 65% for up to 15 successive zeros over the range of specified operating conditions. for e1 applications (ec inputs = 000) the threshold is set to 50%. the receiver is capable of accurately recovering signals with up to -13.6 db of attenuation (from 2.4 v), corresponding to a received signal level of approximately 500 mv. maximum line length is 1500 feet of abam cable (approximately 6 db). regardless of received signal level, the peak detectors are held above a minimum level of 300 mv to provide immunity from impulsive noise. note that during a loss of signal (los) condition, rpos and rneg are squelched if the received input signal drops below 300 mv. after processing through the data slicers, the received signal is routed to the data and clock recovery sections, and to the receive monitor. in the lxt300z only, recovered clock signals are supplied to the jitter attenuator and the data latch. the recovered data is passed to the elastic store where it is buffered and synchronized with the dejittered recovered clock (rclk). the data and clock recovery circuits have an input jitter tolerance significantly better than required by pub 62411. figure 3. lxt301z block diagram control equalizer synchronizer tpos tneg tclk internal clock generator timing recovery peak detector ttip tring rtip rring data latch receive monitor transmit driver monitor mtip mring mclk rpos los rneg dpm constant impedance line driver data slicers ec1, ec2, ec3 rclk
advanced t1/e1 short-haul transceivers ? lxt300z/lxt301z datasheet 11 2.2.1 receive (loss of signal) monitor the receive monitor generates a loss of signal (los) output upon receipt of 175 consecutive zeros (spaces). the receiver monitor loads a digital counter at the rclk frequency. the count is incremented each time a zero is received, and reset to zero each time a one (mark) is received. upon receipt of 175 consecutive zeros the los pin goes high, and the rclk output is replaced with mclk. los is reset when the first mark is received. ( in the lxt300z only, if mclk is not supplied, the rclk output will be replaced with the centered crystal clock .) 2.2.2 jitter attenuation (lxt300z only) in the lxt300z, recovered clock signals are supplied to the jitter attenuator and the data latch. the recovered data is passed to the elastic store where it is buffered and synchronized with the dejittered recovered clock (rclk). jitter attenuation of the lxt300z clock and data outputs (see figure 5 ) is provided by a jitter attenuation loop (jal) and an elastic store (es). an external crystal oscillating at 4 times the bit rate provides clock stabilization. refer to page 18 for crystal specifications. the es is a 32 x 2-bit register. recovered data is clocked into the es with the recovered clock signal, and clocked out of the es with the dejittered clock from the jal. when the bit count in the es is within two bits of overflowing or underflowing, the es adjusts the output clock by 1/8 of a bit period. the es produces an average delay of 16 bits in the receive path. 2.3 transmitter the transmitter circuits in the lxt300z and lxt301z are identical. the following discussion applies to both devices. data received for transmission onto the line is clocked serially into the device at tpos and tneg. input synchronization is supplied by the transmit clock (tclk). the transmitted pulse shape is determined by equalizer control signals ec1 through ec3 as shown in table 4 . refer to the ? test specifications ? section of this data sheet for master and transmit clock timing characteristics. shaped pulses are applied to the ami line driver for transmission onto the line at ttip and tring. equalizer control signals are hard-wired in the lxt301z. lxt300z only: equalizer control signals may be hardwired in the hardware mode, or input as part of the serial data stream (sdi) in the host mode. pulses can be shaped for either 1.544 or 2.048 mbps applications. dsx-1 applications with 1.544 mbps pulses can be programmed to match line lengths from 0 to 655 feet of abam cable. the lxt300z and lxt301z also match fcc specifications for csu applications. pulses at 2.048 mbps can drive coaxial or shielded twisted-pair lines using appropriate resistors in line with the output transformer. 2.3.1 driver performance monitor the transceiver incorporates an advanced driver performance monitor (dpm) in parallel with the ttip and tring at the output transformer. the dpm circuitry uses four comparators and a 150 ns pulse discriminator to filter glitches. the dpm output level goes high upon detection of 63 consecutive zeros, and is cleared when a one is detected on the transmit line, or when a reset command is received. the dpm output also goes high to indicate a ground on ttip or tring. a ground fault induced dpm flag is automatically cleared when the ground condition is corrected (chip reset is not required).
lxt300z/lxt301z ? advanced t1/e1 short-haul transceivers 12 datasheet 2.3.2 line code the lxt300z and lxt301z transmit data as a 50% ami line code as shown in figure 4 . power consumption is reduced by activating the ami line driver only to transmit a mark. the output driver is disabled during transmission of a space. 2.4 operating modes the lxt300z and lxt301z transceivers can be controlled through hard-wired pins (hardware mode). both transceivers can also be commanded to operate in one of several diagnostic modes. lxt300z only: the lxt300z can be controlled by a microprocessor through a serial interface (host mode). the mode of operation is set by the mode pin logic level. 2.4.1 host mode operation (lxt300z only) to allow a host microprocessor to access and control the lxt300z through the serial interface, mode is set to 1. the serial interface (sdi/sdo) uses a 16-bit word consisting of an 8-bit command/address byte and an 8-bit data byte. figure 5 shows the serial interface data structure and relative timing. the host mode provides a latched interrupt output (int ) which is triggered by a change in the loss of signal (los) and/or driver performance monitor (dpm) bits. the interrupt is cleared when the interrupt condition no longer exists, and the host processor enables the respective bit in the serial input data byte. host mode also allows control of the serial data and receive data output timing. the clock edge (clke) signal determines when these outputs are valid, relative to the serial clock (sclk) or rclk as listed in table 3 . the lxt300z serial port is addressed by setting bit a4 in the address/command byte, corresponding to address 16. the lxt300z contains only a single output data register so no complex chip addressing scheme is required. the register is accessed by causing the chip select (cs ) input to transition from high to low. bit 1 of the serial address/command byte provides read/write control when the chip is accessed. a logic 1 indicates a read operation, and a logic 0 indicates a write operation. table 4 lists serial data output bit combinations for each status. serial data i/o timing characteristics are shown in the test specifications section. 2.4.2 hardware mode operation (lxt300z and lxt301z) in hardware mode the transceiver is accessed and controlled through individual pins. with the exception of the int and clke functions, hardware mode provides all the functions provided in the host mode. in the hardware mode rpos and rneg outputs are valid on the rising edge of rclk. the lxt301z operates in hardware mode at all times. lxt300z only: to operate in hardware mode, mode must be set low. equalizer control signals (ec1 through ec3) are input on the interrupt, serial data in and serial data out pins respectively. diagnostic control for remote loopback (rloop), local loopback (lloop), and transmit all ones (taos) modes is provided through the individual pins used to control serial interface timing in the host mode.
advanced t1/e1 short-haul transceivers ? lxt300z/lxt301z datasheet 13 figure 4. 50% ami coding table 2. lxt300z serial data output bits (see figure 5 ) bit d5 bit d6 bit d7 status 0 0 0 reset has occurred, or no program input. 001taos is active. 0 1 0 local loopback is active. 0 1 1 taos and local loopback are active. 1 0 0 remote loopback is active. 1 0 1 dpm has changed state since last clear dpm occurred. 1 1 0 los has changed state since last clear los occurred. 111 los and dpm have both changed state since last clear dpm and clear los occurred. table 3. valid clke settings clke output clock valid edge low rpos rneg sdo rclk rclk sclk rising rising falling high rpos rneg sdo rclk rclk sclk falling falling rising ttip bit cell 1 1 0 tring
lxt300z/lxt301z ? advanced t1/e1 short-haul transceivers 14 datasheet 2.4.3 diagnostic mode operation 2.4.3.1 transmit all ones in transmit all ones (taos) mode, the tpos and tneg inputs to the transceiver are ignored. the transceiver transmits a continuous stream of ones. taos can be commanded simultaneously with local loopback, but is inhibited during remote loopback. 2.4.3.2 remote loopback in remote loopback (rloop) mode, the transmit data and clock inputs (tpos, tneg and tclk) are ignored. the rpos and rneg outputs are looped back through the transmit circuits and output on ttip and tring at the rclk frequency. receiver circuits are unaffected by the rloop command and continue to output the rpos, rneg and rclk signals received from the twisted-pair line. 2.4.3.3 local loopback in local loopback (lloop) mode, the receiver circuits are inhibited. the transmit data and clock inputs (tpos, tneg and tclk) are looped back onto the receive data and clock outputs (rpos, rneg and rclk) through the receive jitter attenuator. the transmitter circuits are unaffected by the lloop command. the tpos and tneg inputs (or a stream of ones if the taos command is active) will be transmitted normally. lxt300z only: when used in this mode with a crystal, the transceiver can be used as a stand-alone jitter attenuator. table 4. equalizer control inputs ec3 ec2 ec1 line length 1 cable loss 2 application bit rate 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 0 ~ 133 ft abam 133 ~ 266 ft abam 266 ~ 399 ft abam 399 ~ 533 ft abam 533 ~ 655 ft abam 0.6 db 1.2 db 1.8 db 2.4 db 3.0 db dsx-1 1.544 mbps 0 0 0 itu recommendation g.703 e1 2.048 mbps 0 1 0 fcc part 68, option a csu 1.544 mbps 1. line length from transceiver to dsx-1 cross-connect point. 2. maximum cable loss at 772 khz.
advanced t1/e1 short-haul transceivers ? lxt300z/lxt301z datasheet 15 figure 5. lxt300z serial interface data structure cs sclk sdi/ sdo input data byte r/w a0 a1 a2 a3 a4 a5 d0 d1 d2 d3 d4 d5 d6 d7 a6 address / command byte data input / output byte los dfm ec1 ec2 ec3 remote local taos r/w 00 0001 x a0 a6 clear interrupts set loopbacks or reset d0 (lsb) d7(msb) x=don ? t care r/w - = 1: read r/w - = 0: write a4 note: output data byte is the same as the input data byte except for bits d<5:7> shown in ta b l e 2 . address / command byte
lxt300z/lxt301z ? advanced t1/e1 short-haul transceivers 16 datasheet 3.0 application information 3.1 lxt300z host mode 1.544 mbps t1 interface figure 6 shows a typical 1.544 mbps t1 application. the lxt300z is configured in the host mode with a typical t1/esf framer providing the digital interface with the host controller. both devices are controlled through the serial interface. the lxp600a clock adapter (clad) provides the 2.048 mhz system backplane clock, locked to the recovered 1.544 mhz clock signal. the power supply inputs are tied to a common bus with appropriate decoupling capacitors installed (68 f on the transmit side, 1.0 f and 0.1 f on the receive side).
advanced t1/e1 short-haul transceivers ? lxt300z/lxt301z datasheet 17 3.2 lxt300z hardware mode e1 interface application figure 7 shows a typical 2.048 mbps e1 application. the lxt300z is configured in hardware mode with a typical e1/crc4 framer. resistors are installed in line with the transmit transformer for loading a 75 ? coaxial cable. the in-line resistors are not required for transmission on 120 ? shielded twisted-pair lines. as in the t1 application shown in figure 6 , this configuration is illustrated with a crystal in place to enable the lxt300z jitter attenuation loop, and a single figure 6. typical lxt300z 1.544 mbps t1 application (host mode) to host controller t1 esf framer 1.544 mhz clock v+ lxp600a/602 clad clki fsi clko 2.048 mhz 6.176 mhz 22 k ? 0 v 1 f t1 line receive 1 : 1 :1 1 : 2 1.544 mhz t1 line transmit 0.47 f f 68 non- polarized clke sclk cs sdo sdi int rgnd rv+ rring rtip mring mtip tring tv+ lxt300z transceiver +v 200 ? +v 200 ? tmsync cs sdo int sclk sdi tfsync tclk tpos tneg sps rneg rpos rclk mclk tclk tpos tneg mode rneg rpos rclk xtalin xtalout dpm los ttip tgnd 0.1 f note 1 note 2 note 1 the lxt300z is compatible with a wide variety of digital framing and signaling devices. note 2 when lxt300z is connected to the cross-connect frame through a low level monitor jack, receive transformer should be 1 : 2 : 2 to boost the input signal. 1.544 mhz
lxt300z/lxt301z ? advanced t1/e1 short-haul transceivers 18 datasheet power supply bus. the hard-wired control lines for taos, lloop and rloop are individually controllable, and the lloop and rloop lines are also tied to a single control for the reset function figure 7. typical lxt300z 75 ? e1 application (hardware mode) table 5. lxt300z crystal specifications (external) parameter t1 e1 frequency 6.176 mhz 8.192 mhz frequency stability 20 ppm @ 25 c 25 ppm from -40 c to 85 c (ref 25 c reading) 20 ppm @ 25 c 25 ppm from -40 c to +85 c (ref 25 c reading) pullability cl = 11 pf to 18.7 pf, + ? f = 175 to 195 ppm cl = 18.7 pf to 34 pf, - ? f = 175 to 195 ppm cl = 11 pf to 18.7 pf, + ? f = 95 to 115 ppm cl = 18.7 pf to 34 pf, - ? f = 95 to 115 ppm effective series resistance 40 ? maximum 30 ? maximum crystal cut at at resonance parallel parallel maximum drive level 2.0 mw 2.0 mw mode of operation fundamental fundamental crystal holder hc49 (r3w), c o = 7 pf maximum c m = 17 ff typical hc49 (r3w), c o = 7 pf maximum c m = 17 ff typical v+ 0 v 2.048 mbps receive 1:1:1 150 ? lxt300z transceiver 220 k ? e1/crc4 framer 100 k ? 10 k ? + 1 f 0.1 f tclk tpos tneg rneg rpos rclk mclk tclk tpos tneg mode rneg rpos rclk xtalout dpm los ttip tgnd taos lloop rloop ec1 rgnd rv+ rring rtip mring mtip tring tv+ + 68 f 150 ? xtalin 2.048 mhz clock v+ 10 k ? 2.2 ? 2.2 ? 1:2 2.048 mbps transmit 0.47 f note 2 note 1 non-polarized ec2 ec3 note 1 2.2 ? resistors required only for 75 ? coaxial cable. not required for transmission onto 120 ? cable. note 2 the lxt300z is compatible with a wide variety of framing and signaling devices, including the ds2181a, mt8979, and r8070. 8.192 mhz
advanced t1/e1 short-haul transceivers ? lxt300z/lxt301z datasheet 19 3.2.1 lxt301z 1.544 mbps t1 interface application figure 8 shows a typical 1.544 mbps t1 application of the lxt301z. the lxt301z is shown with a typical t1/esf framer. the lxp600a clock adapter (clad) provides the 2.048 mhz system backplane clock, locked to the recovered 1.544 mhz clock signal. the power supply inputs are tied to a common bus with appropriate decoupling capacitors installed (68 f on the transmit side, 1.0 f and 0.1 f on the receive side). figure 8. typical lxt301z 1.544 mbps t1 application v+ 0 v t1 line receive 1:1:1 200 ? lxt301z transceiver 220 k ? t1/esf framer 100 k ? 10 k ? 1 f 0.1 f tclk tpos tneg rneg rpos rclk mclk tclk tpos tneg gnd rneg rpos rclk n/c dpm los ttip tgnd taos lloop rloop ec1 rgnd rv+ rring rtip mring mtip tring tv+ + 68 f 200 ? 1 k ? rt 1.544 mhz clock v+ 10 k ? 1:2 1.544 mbps transmit 0.47 f note 1 non-polarized ec2 ec3 lx600a / 602 clad clki fsi clko 2.048 mhz 1.544 mhz note 1 the lxt300z is compatible with a wide variety of framing and signaling devices. e1.5i v+
lxt300z/lxt301z ? advanced t1/e1 short-haul transceivers 20 datasheet 3.2.2 lxt301z 2.048 mbps e1 interface application figure 9 shows a typical 2.048 mbps e1 application of the lxt301z. the lxt301z is shown with a typical e1/crc4 framer. resistors are installed in line with the transmit transformer for loading a 75 ? coaxial cable. the in-line resistors are not required for transmission on 120 ? shielded twisted-pair lines. as in the t1 application shown in figure 8 , this configuration is illustrated with a single power supply bus. the hard-wired control lines for taos, lloop and rloop are individually controllable, and the lloop and rloop lines are also tied to a single control for the reset function. figure 9. typical lxt301z 75 ? e1 application v+ 0 v 2.048 mbps receive 1:1:1 150 ? lxt301z transceiver 220 k ? e1/crc4 framer 100 k ? 10 k ? + 1 f 0.1 f tclk tpos tneg rneg rpos rclk mclk tclk tpos tneg gnd rneg rpos rclk n/c dpm los ttip tgnd taos lloop rloop ec1 rgnd rv+ rring rtip mring mtip tring tv+ + 68 f 150 ? rt 2.048 mhz clock v+ 10 k ? 2.2 ? 2.2 ? 1:2 2.048 mbps transmit 0.47 f note 1 non-polarized ec2 ec3 note 1 the lxt301z is compatible with a wide variety of framing and signaling devices. v+ 300zf08.vsd
advanced t1/e1 short-haul transceivers ? lxt300z/lxt301z datasheet 21 4.0 test specifications note: table 6 through table 13 and figure 10 through figure 16 represent the performance specifications of the lxt300z/301z and are guaranteed by test except, where noted, by design. the minimum and maximum values listed in table 8 through table 13 are guaranteed over the recommended operating conditions specified in table 7 . table 6. absolute maximum ratings parameter sym min max units dc supply (referenced to gnd) rv+, tv+ -0.3 6.0 v input voltage, any pin 1 v in rgnd - 0.3 rv+ + 0.3 v input current, any pin 2 iin -10 10 ma storage temperature t stg -65 150 c caution: exceeding these values may cause permanent damage. caution: functional operation under these conditions is not implied. caution: exposure to maximum rating conditions for extended periods may affect device reliability. 1. excluding rtip and rring which must stay between -6v and (rv+ + 0.3) v. 2. transient currents of up to 100 ma will not cause scr latch up. ttip, tring, tv+ and tgnd can withstand a continuous current of 100 ma. table 7. recommended operating conditions parameter sym min typ max units dc supply 1 rv+, tv+ 4.75 5.0 5.25 v ambient operating temperature t a -40 25 85 c 1. tv+ must not exceed rv+ by more than 0.3 v. table 8. electrical characteristics parameter sym min typ max units test conditions high level input voltage 1,2 (pins 1-5, 10, 23-28) v ih 2.0 ?? v low level input voltage 1,2 (pins 1-5, 10, 23-28) vil ?? 0.8 v high level output voltage 1,2 (pins 6-8, 11, 12, 23, 25) v oh 2.4 ?? vi out = -400 a low level output voltage 1,2 (pins 6-8, 11, 12, 23, 25) v ol ?? 0.4 v i out = 1.6 ma input leakage current (pins 1-5, and 23-28) i ll -10 ? +10 a input leakage current (pins 9, 17, and 18) i ll -50 ? +50 a three-state leakage current 1 (pin 25) i3 l -10 ? +10 a total power dissipation 3 p d ?? 700 mw 100% ones density & maximum line length @ 5.25 v 1. functionality of pins 23 through 28 depends on mode. see host and hardware mode functional descriptions. 2. output drivers will output cmos logic levels into cmos loads. 3. power dissipation while driving a 25 ? load over operating temperature range. includes device and load. digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pf capacitive load.
lxt300z/lxt301z ? advanced t1/e1 short-haul transceivers 22 datasheet table 9. analog characteristics parameter min typ 1 max units test conditions ami output pulse amplitudes dsx-1 2.4 3.0 3.6 v measured at the dsx e1 (120 ?) 2.7 3.0 3.3 v measured at line side e1 (75 ?) 2.14 2.37 2.6 v @ 772 khz transmit amplitude variation with supply 1 2.5 % recommended output load at ttip and tring ? 25 ? ? rtip to rring driver output impedance 2 ? 310 ? @ 10 khz jitter added by the transmitter 3 10 hz - 8 khz 2 ?? 0.02 ui 8 khz - 40 khz ?? 0.025 ui 10 hz - 40 khz ?? 0.025 ui broad band ?? 0.05 ui output power levels 2 ds1 2 khz bw @ 772 khz 12.6 ? 17.9 dbm @ 1544 khz 5 -29.0 ?? db positive to negative pulse imbalance ?? 0.5 db sensitivity below dsx 6 (0 db = 2.4 v) 13.6 ?? db 500 ?? mv receiver input impedance ? 40 ? k ? loss of signal threshold ? 0.3 ? v data decision threshold dsx-1 63 70 77 % peak e1 43 50 57 % peak allowable consecutive zeros before los 160 175 190 ? input jitter tolerance 10 hz ? 1200 ? ui 775 hz 14 ?? ui 10 khz - 100 khz 0.4 ?? ui jitter attenuation curve corner frequency 4 ? 3 ? hz jitter attenuation ? 50 ? db jitter attenuation tolerance before fifo overflow 2 28 ?? ui 1. typical values are measured at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. not production tested but guaranteed by design and other correlation methods. 3. input signal to tclk is jitter-free. 4. circuit attenuates jitter at 20 db/decade above the corner frequency. 5. referenced to power in 2 khz band. 6. with a maximum of 6 db of cable attenuation.
advanced t1/e1 short-haul transceivers ? lxt300z/lxt301z datasheet 23 figure 10. lxt300z typical receive jitter tolerance 300 jitter 400 1.2 ui pub 62411 dec 1990 lxt300z performance 10000 ui 1200 ui 1000 ui 138 ui 100 ui 28 ui 10 ui 1 ui 0.4 ui 0.1 ui 1 hz 10 hz 100 hz 1 khz 10 khz 100 khz 30 khz frequency 1.5 ui 0.2 ui 20 g. 8 2 3 mar 1993
lxt300z/lxt301z ? advanced t1/e1 short-haul transceivers 24 datasheet figure 11. lxt300z typical receive jitter transfer performance table 10. lxt300z receiver timing characteristics (see figure 12 ) parameter sym min typ 1 max units test conditions receive clock duty cycle rclkd 40 - 60 % receive clock pulse width 2 dsx-1 t pw ? 324 ? ns e1 t pw ? 244 ? ns rpos/rneg to rclk rising setup time dsx-1 t sur ? 274 ? ns e1 t sur ? 194 ? ns rclk rising to rpos/rneg hold time dsx-1 t hr ? 274 ? ns e1 t hr ? 194 ? ns 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. 20 db 1 hz typical lxt300z performance 0 db -10 db -20 db -30 db -40 db -60 db 10 hz 100 hz 1 khz 10 khz 100 khz 1450 hz 20 hz 0.5 db / 3 hz 0.5 db / 40 hz at&t 62411 template slope equivalent to 20 db per decade itu g.735 template slope equivalent to 20 db per decade at&t 62411 template slope equivalent to 40 db per decade frequency gain 19.5 db / 100 hz 19.5 db / 400 hz
advanced t1/e1 short-haul transceivers ? lxt300z/lxt301z datasheet 25 figure 12. lxt300z receive clock timing diagram table 11. lxt301z receive timing characteristics (see figure 13 ) parameter sym min typ 1 max units test conditions receive clock duty cycle 2 dsx-1 rclkd 40 50 60 % e1 rclkd 40 50 60 % receive clock pulse width 2 dsx-1 t pw 594 648 702 ns e1 t pw 447 488 529 ns receive clock pulse width high dsx-1 t pwh ? 324 ? ns e1 t pwh ? 244 ? ns receive clock pulse width low dsx-1 t pwl 270 324 378 ns e1 t pwl 203 244 285 ns rpos/rneg to rclk rising setup time dsx-1 t sur 50 270 ? ns e1 t sur 50 203 ? ns rclk rising to rpos/rneg hold time dsx-1 t hr 50 270 ? ns e1 t hr 50 203 ? ns 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. 2. rclk duty cycle widths will vary depending on extent of received pulse jitter displacement. max and min rclk duty cycles are for worst case jitter conditions (0.4 ui clock displacement for 1.544 mhz, 0.2 ui clock displacement for 2.048 mhz). t pwh t pwl t pw t hr t sur rclk rpos rneg rpos rneg t sur t hr host mode clke = 1 host mode clke = 0, & h/w mode
lxt300z/lxt301z ? advanced t1/e1 short-haul transceivers 26 datasheet figure 13. lxt301z receive clock timing diagram table 12. lxt300z/301z master clock and transmit timing characteristics (see figure 14) parameter sym min typ 1 max units master clock frequency dsx-1 mclk ? 1.544 ? mhz e1 mclk ? 2.048 ? mhz master clock tolerance mclkt ? 100 ? ppm master clock duty cycle mclkd 40 ? 60 % crystal frequency (lxt300z only) dsx-1 fc ? 6.176 ? mhz e1 fc ? 8.192 ? mhz transmit clock frequency dsx-1 tclk ? 1.544 ? mhz e1 tclk ? 2.048 ? mhz transmit clock tolerance tclkt ? 50 ? ppm transmit clock duty cycle tclkd 10 ? 90 % tpos/tneg to tclk setup time t sut 25 ?? ns tclk to tpos/tneg hold time t ht 25 ?? ns 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. 2. not production tested but guaranteed by design and other correlation methods. figure 14. lxt300z/301z transmit clock timing diagram t pwl t pwh t pw t hr t sur rclk rpos rneg t ht t sut tclk tpos tneg
advanced t1/e1 short-haul transceivers ? lxt300z/lxt301z datasheet 27 table 13. lxt300z serial i/o timing characteristics (see figure 15 and figure 16 ) parameter sym min typ 1 max units test conditions rise/fall time - any digital output t rf ?? 100 ns load 1.6 ma, 50 pf sdi to sclk setup time t dc 50 ?? ns sclk to sdi hold time t cdh 50 ?? ns sclk low time t cl 240 ?? ns sclk high time t ch 240 ?? ns sclk rise and fall time t r , t f ?? 50 ns cs to sclk setup time t cc 50 ?? ns sclk to cs hold time t cch 50 ?? ns cs inactive time t cwh 250 ?? ns sclk to sdo valid t cdv ?? 200 ns sclk falling edge or cs rising edge to sdo high z t cdz ? 100 ? ns 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. figure 15. lxt300z serial data input timing diagram cs t cwh t cch t cl t ch t cc sclk sdi t dc lsb t cdh lsb t cdh msb control byte data byte
lxt300z/lxt301z ? advanced t1/e1 short-haul transceivers 28 datasheet figure 16. lxt300z serial data output timing diagram sclk t cdz cs high z high z t cdv t cdv sdo sdo clke=1 clke=0 t cdz
advanced t1/e1 short-haul transceivers ? lxt300z/lxt301z datasheet 29 5.0 mechanical specifications figure 17. package specifications 1 b 2 e 1 a a 2 b l e d ea eb e d 1 d c b c l d f a 2 a 1 a 28-pin plastic dual in-line package extended temperature range (-40 c to 85 c) part number lxt300zne part number LXT301ZNE 28-pin plastic leaded chip carrier extended temperature range (-40 c to 85 c) part number lxt300zpe part number lxt301zpe dim inches millimeters min max min max a ? 0.250 ? 6.350 a 2 0.125 0.195 3.175 4.953 b 0.014 0.022 0.356 0.559 b 2 0.030 0.070 0.762 1.778 d 1.380 1.565 35.052 39.751 e 0.600 0.625 15.240 15.875 e 1 0.485 0.580 12.319 14.732 e 0.100 bsc 1 (nominal) 2.540 bsc 1 (nominal) ea 0.600 bsc 1 (nominal) 15.240 bsc 1 (nominal) eb ? 0.700 ? 17.780 l 0.115 0.200 2.921 5.080 1. bsc ? basic spacing between centers. dim inches millimeters minmaxminmax a 0.165 0.180 4.191 4.572 a1 0.090 0.120 2.286 3.048 a2 0.062 0.083 1.575 2.108 b .050 bsc 1 (nominal) 1.27 bsc 1 (nominal) c 0.026 0.032 0.660 0.813 d 0.485 0.495 12.319 12.573 d1 0.450 0.456 11.430 11.582 f 0.013 0.021 0.330 0.533 1. bsc ? basic spacing between centers.

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