| clock crystal oscillators surface mount type k50h-3c series cmos/ 3.3v/ 7.0 5.0mm this product is not recommended for new designs. features ? miniature ceramic package ? highly reliable with seam welding ? cmos output ? supply voltage v dd =3.3v ? internal bypass capacitor ? low jitter ? 25ppm available table 1 how to order dimensions specifications (unit : mm) recommended land pattern (unit : mm) k50h-3c 0 - s e 125.000 q type(7 5 smd, 3.3v) w frequency stability code(see table1) e duty ratio(s: 45% to 55% std) r enable/disable function(std) t oscillation frequency(ex.: 125.000mhz) packaging(tape & reel 1,000pcs/reel) w q e r t stability t opr note code (ppm) ( c) 0 50 ? 10 to + 70 standard specifications s 30 (standard) u 25 f 100 ? 40 to + 85 g 50 (extend) with only certain frequencies with only certain frequencies note: k50h series has bypass capacitor of 0.01 f between v dd and gnd. 1.8 5.08 4.2 2.0 plating: ni + au tolerance: 0.2 pin connections q control w case gnd e output r v dd enable/disable function pin1 pin3(output) open active "h" level active "l" level high z(no-oscillation) 7.0 5.0 1.6 0.7 1.4 q w r e 2.6 5.08 1.1 0.6 overall conditions: initial tolerance, operating temperature range, rated power supply voltage change, load change, aging(1year @25 c), shock and vibration note: please contact us for inquires about extended operating temperature range, available frequencies and other conditions. all electrical characteristics are defined at the maximum load and operating temperature range. item symbol conditions min. max. units 20% v dd to 80% v dd 10% v dd to 90% v dd 20% v dd to 80% v dd 10% v dd to 90% v dd output frequency range frequency stability storage temperature range operating temperature range max. supply voltage supply voltage current consumption (maximum loaded) duty ratio(symmetry) duty ratio(symmetry) rise/fall time ( 10% v dd to 90% v dd maximum loaded ) output voltage-"l" output voltage-"h" output load input voltage range input voltage-"l" input voltage-"h" output disable time output enable time start-up time deterministic jitter pk-pk 1sigma jitter f out 50 170 mhz ? 25 + 25 f sby ? 30 + 30 ppm ? 50 + 50 t stg ? 55 + 125 t opr standard ? 10 + 70 c extend(option) ? 40 + 85 ----- ? 0.5 7.0 v dd stability: 50ppm, 100ppm (ext temp) 2.97 3.63 volt stability: 25ppm, 30ppm, 50ppm (ext temp) 3.14 3.46 50 f out 85mhz ----- 30 i dd 85 |
