3/97 block diagram precision 5v reference 4-bit digital-to-analog (dac) converter 0.5% dac/reference combined error programmable undervoltage and overvoltage fault windows overvoltage comparator with complementary scr driver and open collector outputs undervoltage lockout the uc3910 is a complete precision reference and voltage monitor cir- cuit for intel pentium? pro and other high-end microprocessor power supplies. it is designed for use in conjunction with the uc3886 pwm. the uc3910 together with the uc3886 converts 5vdc to an adjustable out- put ranging from 2.0vdc to 3.5vdc in 100mv steps with 1% dc system accuracy. the uc3910 utilizes thin film resistors to ensure high accuracy and sta- bility of its precision circuits. the chip includes a precision 5v voltage ref- erence which is capable of sourcing 10ma to external circuitry. the output voltage of the dac is derived from this reference, and the accu- racy of the dac/reference combination is 0.5%. programmable window comparators monitor the supply voltage to indicate that it is within ac- ceptable limits. the window is programmed as a percentage centered around the dac output. an overvoltage protection comparator is set at a percentage 2 times larger than the programmed lower overvoltage level and drives an external scr as well as provides an open collector output. undervoltage lockout protection assures the correct logic states at the outputs during power-up and power-down. 4-bit dac and voltage monitor features description uc1910 uc2910 uc3910 udg-95097-3
uc1910 uc2910 uc3910 parameter test conditions min typ max units undervoltage lockout v in uvlo turn-on threshold 7 8 9 v uvlo threshold hysteresis 50 200 500 mv supply current i in startup vcc = 5v 2 3.5 ma i in vcc = 12v 10 12 ma dac/reference dacout voltage accuracy line, load, 0c < t a < 70c (note 1) - 0.9 0.9 % line, load, C55c < t a < 125c C1.5 1.5 % d0-d3 voltage high d x pin floating 4.6 4.85 v d0-d3 input bias current d x pin tied to gnd C140 - 105 m a vref output voltage i vref = 0ma, 0c < t a < 70c 4.97 5 5.03 v vref total variation line, load, 0c < t a < 70c (note 1) 4.96 5 5.04 v line, load, C55c < t a < 125c 4.925 5 5.075 v vref sourcing current vref = 0v 10 ma dac buffer input offset voltage i dacbuf = C1ma, 0c < t a < 70c - 25 25 mv output sourcing current C12 C1 ma monitor circuitry (note 2) vsense uv threshold voltage code 0, ratio = 0.45 (note 3) 3.174 3.237 3.3 v code 0, ratio = 0.9 2.87 2.975 3.08 v code 15, ratio = 0.45 1.816 1.85 1.884 v code 15, ratio = 0.9 1.635 1.7 1.765 v vsense ov threshold voltage code 0, ratio = 0.45 3.7 3.763 3.826 v code 0, ratio = 0.9 3.92 4.025 4.13 v code 15, ratio = 0.45 2.116 2.15 2.184 v code 15, ratio = 0.9 1.635 2.3 2.365 v electrical characteristics unless otherwise specified, vcc = 12v, vsense = 3.5v, v ovth/uvth = 1.26v, v d0 = v d1 = v d2 = v d3 = 0v, 0c < t a < 70c for the uc3910, C25c < t a < 80c for the uc2910, C55c < t a < 125c for the uc1910 t a = t j . connection diagram dil-16, soic-16 (top view) j, n, or d packages 2
uc1910 uc2910 uc3910 parameter test conditions min typ max units monitor circuitry (note 2) (cont.) vsense ovp threshold voltage code 0, ratio = 0.45 3.937 4.025 4.113 v code 0, ratio = 0.9 4.41 4.55 4.69 v code 15, ratio = 0.45 2.235 2.3 2.365 v code 15, ratio = 0.9 2.505 2.6 2.695 v ov, uv comparator hysteresis code 0, ratio = 0.9 70 88 120 mv code 15, ratio = 0.45 15 25 40 mv ovp comparator hysteresis code 0, ratio = 0.9 160 218 300 mv code 15, ratio = 0.45 40 62 85 mv input common mode range ov, uv, ovp comparators 0 5 v propagation delay ov, uv comparators 5 m s ovp comparator 5 m s pwrgood, ovp, ovpb outputs pwrgood voltage low i pwrgood = 10ma 0.4 v ovp sourcing current v ovp = 1.4v 65 ma ovpb voltage low i ovpb = 1ma 0.4 v electrical characteristics (cont.) unless otherwise specified, vcc = 12v, vsense = 3.5v, v ovth/uvth = 1.26v, v d0 = v d1 = v d2 = v d3 = 0v, 0c < t a < 70c for the uc3910, C25c < t a < 80c for the uc2910, C55c < t a < 125c for the uc1910 t a = t j . d0-d3 (dac digital input control codes): these are the dac digital input control codes, with d0 repre- senting the least significant bit (lsb) and d3, the most significant bit (msb) (see table 1). a bit is set low by being connected to gnd; a bit is set high by floating it, or connecting it to a 3v to 5v voltage source. each con- trol pin is pulled up to approximately 4.8v by an internal 40 m a current source. dacbuf (buffered dacout voltage): this pin pro- vides a buffered version of the dacout voltage to al- low external programming of the ov/uv thresholds (see ovth/uvth below). dacout (digital-to-analog converter output volt- age): this pin is the output of the 4-bit digital to analog (dac) converter. setting all input control codes low pro- duces 3.5v at dacout; setting all codes high pro- duces 2.0v at dacout. the lsb step size (i.e. resolution) is 100mv (see table 1). the dacout source impedance is typically 3k w and must therefore drive a high impedance input. bypass dacout at the driven input with a 0.01 m f, low esr, low esl capacitor for best circuit noise immunity. gnd (signal ground): all voltages are measured with respect to gnd. the two gnd pins are connected to- gether internally but should also be connected exter- nally using a short pc board trace. bypass capacitors on the vcc and vref pins should be connected di- rectly to the ground plane near one of the signal ground pin descriptions note 1: "line, load" implies that the parameter is tested at all combinations of the conditions: 10.8v < vcc < 13.2v, C2ma < i vref < 0ma. note 2: these are the actual voltages on vsense which will cause the ovpb and pwrgood outputs to switch, assuming the dacout voltage is perfect. these limits apply for 0c < t a < 70c. note 3: "code 0" means pins d0 - d4 are all low; "code 15" means they are all floating or high (see table 1). "ratio" is the div ider ratio of the resistor string between dacbuf and ovth/uvth (see figure 1). decimal code d3 d2 d1 d0 dacout voltage 1511112.0 1411102.1 1311012.2 1211002.3 1110112.4 1010102.5 910012.6 810002.7 701112.8 601102.9 501013.0 401003.1 300113.2 200103.3 100013.4 000003.5 table 1. programming the dacout voltage 3
pins. ovp (overvoltage comparator output): this output pin drives an external scr circuit with up to 65ma when the voltage on vsense rises above its nominal value by a percentage set by the voltage on the ovth/uvth pin (see below). the ovp comparator hys- teresis is a function of both the dacbuf voltage and the ov/uv percentage programmed. ovpb (overvoltage comparator complementary output): this output is a complement to the ovp out- put (see above) and provides an open collector capable of sinking 1ma when the voltage on vsense rises above its nominal value by a percentage set by the volt- age on the ovth/uvth pin (see below). ovth/uvth (undervoltage and lower overvoltage threshold input): this pin is used to program the win- dow thresholds for the ov and uv comparators. the ov-uv window is centered around the dacbuf voltage and can be programmed from 5% to 15% about dacbuf. connect a resistor divider between dacbuf and gnd to set the percentage. the threshold for the ovp comparator is internally set to a percentage 2 times larger than the programmed ov percentage; therefore, its range extends from 10% to 30% above dacbuf. pwrgood (undervoltage/lower overvoltage out- put): this pin is an open collector output which is driven low to reset the microprocessor when vsense rises above or falls below its nominal value by a per- centage programmed by ovth/uvth. the ov and uv comparators hysteresis is a function of the dacbuf voltage and the ov/uv programmed percentage. vcc (positive supply voltage): this pin supplies power to the chip. connect vcc to a stable voltage source of at least 9v and capable of sourcing at least 15ma. the ovp and pwrgood outputs are held low, the ovpb output is in a high impedance state, and the vsense pin is pulled low until vcc exceeds the upper undervoltage lockout threshold. this pin should be by- passed directly to the gnd pin with a 0.1 m f low esr, low esl capacitor. vref (voltage reference output): this pin provides an accurate 5v reference, capable of delivering up to 10ma to external circuitry, and is internally short circuit current limited. for best reference stability, bypass vref directly to the gnd pin with a 0.1 m f, low esr, low esl capacitor. vsense (output voltage sensing input): this pin is the input to the ovp and pwrgood comparators and is connected to the system output voltage through a lowpass filter. when choosing the resistor value for this filter, make sure that no more than 500 m a will flow pin descriptions (cont.) uc1910 uc2910 uc3910 application information the overvoltage (ov), undervoltage (uv) and overvol- tage protection voltage (ovp) threshold detection volt- ages are programmed as a percentage about the nominal dac output voltage, dacout. figure 1 illus- trates how to program the uc3910 by setting a voltage divider, r div , at the ovth/uvth pin. the voltage di- vider ratio is defined as r div = rs1 rs1 + rs2 the uc3910 allows a ratio r div at the ovth/uvth pin from 0.3 to 0.9, which corresponds to overvoltage and undervoltage percentage thresholds from 5% to 15% and an ovp percentage threshold from 10% to 30%. these thresholds are shown in figure 2. the ov, uv and ovp percentage thresholds are given by %v ov = r div 16.7 %v uv = C(r div 16.7) %v ovp = %v ov 2.0 = r div 33.4 an r-c filter is added to the vsense pin to filter noise and ripple at the comparator inputs. an r-c filter fre- quency of f switch /10 is recommended. choose the figure 1. setting the ov/uv/ovp threshold percentages udg-96020 4
unitrode corporation 7 continental blvd. merrimack, nh 03054 tel. (603) 424-2410 fax (603) 424-3460 value of r f such that it limits the current into vsense to 0.5ma. r f c f = 1 2 p ? ? f switch 10 ? ? r f 3 v out 0.5ma the overvoltage protection output, ovp, can be used to directly drive a crowbarring scr, as shown in figure 3. a typical application is shown in figure 4 using the uc3910 together with the uc3886 average current mode pwm controller ic for a power supply to drive in- tels pentium?pro processor. -15 -10 -5 0 5 10 15 20 25 30 0.3 0.4 0.5 0.6 0.7 0.8 0.9 ratio r div thresholds (%) uv ov ovp figure 2. ov, uv and ovp percentage thresholds as a function of the divider ratio r div uc1910 uc2910 uc3910 figure 3. driving and scr using the uc3910 ovp signal figure 4. uc3910 configured with the uc3886 for a pentium? pro dc/dc converter application information (cont.) udg-96021 udg-96019 5
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