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rev. 1.0 4/12 copyright ? 2012 by silicon laboratories si5315 si5315 s ynchronous e thernet /t elecom j itter a ttenuating c lock m ultiplier features applications description the si5315 is a jitter-attenuating clock multiplier for gb and 10g synchronous ethernet, sonet/sdh, and pdh (t1/e1) applications. the si5315 supports synce eec options 1 and 2 when paired with a timing card that implements the required wander filter. the si5315 accepts dual clock inputs ranging from 8 khz to 644.53 mhz and generates two equal frequency-multiplied clock outputs ranging from 8 khz to 644.53 mhz. the input clock frequency and clock multiplication ratio are selectable from a table of popular synce and t1/e1 rates. the si5315 is based on silicon laboratories' thir d-generation dspll ? technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components. the dspll loop bandwidth is user programmable, providing jitter performance optimization at the application level. functional block diagram ? provides jitter attenuation and frequency translation between sonet/pdh and ethernet ? supports itu-t g.8262 synchronous ethernet equipment slave clock (eec option 1 and 2) requirements with optional stratum 3 compliant timing card clock source ? two clock inputs/two clock outputs ? input frequency range: 8 khz?644 mhz ? output frequency range: 8 khz?644 mhz ? ultra low jitter: 0.23 ps rms (1.875?20 mhz) 0.47 ps rms (12 khz?20 mhz) ? simple pin control interface ? selectable loop bandwidth for jitter attenuation: 60 to 8.4 khz ? automatic/manual hitless switching and holdover during loss of inputs clock ? programmable output clock signal format: lvpecl, lvds, cml or cmos ? 40 mhz crystal or xo reference ? single supply: 1.8, 2.5, or 3.3 v ? on-chip voltage regulator with high psrr ? loss of lock and loss of signal alarms ? small size: 6 x 6 mm, 36-qfn ? wide temperature range: ?40 to +85 oc ? synchronous ethernet line cards ? sonet oc-3/12/48 line cards ? pon olt/onu ? carrier ethernet switches routers ? msan / dslam ? t1/e1/ds3/e3 line cards dspll ? clock in 1 clock in 2 clock out 1 clock out 2 clock 2 disable/pll bypass output signal format[1:0] xtal/clock vdd (1.8, 2.5, or 3.3 v) gnd status/control loss of lock loss of signal 2 frequency select[3:0] frequency table select manual/auto clock selection clock switch/clock active indicator loss of signal 1 loop bandwidth select[1:0] xtal/clock si5315 ordering information: see page 48. pin assignments 1 2 3 29 30 31 32 33 34 35 36 20 21 22 23 24 25 26 27 10 11 12 13 14 15 16 17 4 5 6 7 8 frqtbl autosel rst los2 los1 gnd vdd xa vdd xtal/clock ckin2+ ckin2? dbl2_by gnd ckin1+ ckin1? cs_ca bwsel0 bwsel1 frqsel1 frqsel2 frqsel3 ckout1? sfout1 gnd vdd sfout0 ckout2? ckout2+ nc gnd pad frqsel0 gnd 9 18 19 28 xb lol gnd ckout1+
si5315 2 rev. 1.0
si5315 rev. 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1. three-level (3l) input pins (no external resistors) . . . . . . . . . . . . . . . . . . . . . . . .11 1.2. three-level (3l) input pins (with external resistors) . . . . . . . . . . . . . . . . . . . . . . . 12 2. typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3. system level overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.2. pll performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5. frequency plan tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1. frequency multiplication plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5.2. pll self-calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3. input clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4. alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.5. holdover mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.6. pll bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6. high-speed i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1. input clock buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2. output clock drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 7. crystal/reference cl ock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 7.1. crystal/reference clock se lection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 8. power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 9. typical phase noise plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2 9.1. 10g lan synce example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10. pin descriptions: si5315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3 11. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12. package outline: 36-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 13. pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 14. top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 14.1. si5315 top marking (qfn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14.2. top marking explana tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
si5315 4 rev. 1.0 1. electrical specifications table 1. recommended operating conditions (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit temperature range t a ?40 25 85 oc supply voltage v dd 3.3 v nominal 2.97 3.3 3.63 v 2.5 v nominal 2.25 2.5 2.75 v 1.8 v nominal 1.71 1.8 1.89 v note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise noted. table 2. dc characteristics (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max units supply current (supply current is independent of v dd ) i dd lvpecl format 644.53125 mhz out all ckouts enabled 1 ?251279 ma lvpecl format 644.53125 mhz out only 1 ckout enabled 1 ?217243 ma cmos format 25.00 mhz out all ckouts enabled 2 ?204234 ma cmos format 25.00 mhz out only ckout1 enabled 2 ?194220 ma ckinn input pins input common mode voltage (input threshold voltage) v icm 1.8 v 5% 0.9 ? 1.4 v 2.5 v 10% 1.0 ? 1.7 v 3.3 v 10% 1.1 ? 1.95 v input resistance ckn rin single-ended 20 40 60 k ? input voltage level limits ckn vin 0?v dd v notes: 1. refers to si5315a speed grade. 2. refers to si5315b speed grade. 3. this is the amount of leakage that the 3l inputs can tole rate from an external driver. see figure 3 on page 11.
si5315 rev. 1.0 5 single-ended input voltage swing v ise f ckin < 212.5 mhz see figure 2. 0.2 ? ? v pp f ckin > 212.5 mhz see figure 2. 0.25 ? ? v pp differential input voltage swing v id f ckin < 212.5 mhz see figure 2. 0.2 ? ? v pp f ckin > 212.5 mhz see figure 2. 0.25 ? ? v pp ckoutn output clocks common mode v ocm lvpecl 100 ? load line-to-line v dd ? 1.42 ?v dd ? 1.25 v differential ou tput swing v od lvpecl 100 ? load line-to-line 1.1 ? 1.9 v pp single ended output swing v se lvpecl 100 ? load line-to-line 0.5 ? 0.93 v pp differential output voltage cko vd cml 100 ? load line-to-line 350 425 500 mv pp common mode output voltage cko vcm cml 100 ? load line-to-line ?v dd ? 0.36 ?v differential output voltage cko vd lvds 100 ? load line-to-line 500 700 900 mv pp low swing lvds 100 ? load line-to-line 350 425 500 mv pp common mode output voltage cko vcm lvds 100 ? load line-to-line 1.125 1.2 1.275 v differential outp ut resistance cko rd cml, lvpecl, lvds, disable ?200? ? output voltage low cko vollh cmos ? ? 0.4 v output voltage high cko vohlh v dd = 1.71 v cmos 0.8 x v dd ?? v table 2. dc characteristics (continued) (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max units notes: 1. refers to si5315a speed grade. 2. refers to si5315b speed grade. 3. this is the amount of leakage that the 3l inputs can tole rate from an external driver. see figure 3 on page 11.
si5315 6 rev. 1.0 output drive current cko io cmos driving into cko vol for out- put low or cko voh for out- put high. ckout+ and ckout? shorted externally. v dd = 1.71 v 7.5 ? ? ma v dd = 2.97 v 32 ? ? ma 2-level lvcmos input pins input voltage low v il v dd =1.71v ? ? 0.5 v v dd =2.25v ? ? 0.7 v v dd =2.97v ? ? 0.8 v input voltage high v ih v dd =1.89v 1.4 ? ? v v dd =2.25v 1.8 ? ? v v dd =3.63v 2.5 ? ? v input low current i il ??50 a input high current i ih ??50 a weak internal input pull-up resistor r pup ?75? k ? weak internal input pull-down resistor r pdn ?75? k ? 3-level input pins input voltage low v ill ?? 0.15 x v dd v input voltage mid v imm 0.45 x v dd ? 0.55 x v dd v input voltage high v ihh 0.85 x v dd ?? v input low current i ill see note 3. ?20 ? ? a input mid current i imm see note 3. ?2 ? 2 a input high current i ihh see note 3. ? ? 20 a table 2. dc characteristics (continued) (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max units notes: 1. refers to si5315a speed grade. 2. refers to si5315b speed grade. 3. this is the amount of leakage that the 3l inputs can tole rate from an external driver. see figure 3 on page 11.
si5315 rev. 1.0 7 lvcmos output pins output voltage low v ol i o =2ma v dd =1.62v ??0.4 v i o =2ma v dd =2.97v ??0.4 v output voltage high v oh i o =?2ma v dd =1.62v v dd ?0.4 ? ? v i o =?2ma v dd =2.97v v dd ?0.4 ? ? v disabled leakage current i oz rst = 0 ?100 ? 100 a single-ended reference clock input pin xa (xb with cap to gnd) input resistance xa rin xtal/clock = m ? 12 ? k ? input voltage level limits xa vin 0?1.2 v input voltage swing xa vpp 0.5 ? 1.2 v pp differential reference cl ock input pins (xa/xb) input resistance xa/xb rin xtal/clock = m ? 12 ? k ? differential input voltage level limits xa/xb vin 0?1.2 v input voltage swing xa vpp /xb vpp 0.5 ? 2.4 v pp table 2. dc characteristics (continued) (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max units notes: 1. refers to si5315a speed grade. 2. refers to si5315b speed grade. 3. this is the amount of leakage that the 3l inputs can tole rate from an external driver. see figure 3 on page 11.
si5315 8 rev. 1.0 table 3. ac characteristics (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max units input frequency ckn f 0.008 ? 644.53 mhz ckinn input pins input duty cycle (minimum pulse width) ckn dc whichever is smaller 1 40 ? 60 % 2??ns input capacitance ckn cin ?? 3pf input rise/fall time ckn trf 20?80% see figure 2 ?? 11ns ckoutn output pins output frequency (output not configured for cmos or disable) ck of note 2 0.008 ? 644.53 mhz note 3 0.008 ? 125 mhz maximum output frequency in cmos format cko fmc ? ? 161.13 mhz output rise/fall (20?80%) at 644.5313 mhz cko trf output not configured for cmos or disabled, see figure 2 ? 230 350 ps single ended output rise/fall (20?80%) cko trf cmos output v dd = 1.62 cload = 5 pf ?? 8ns cmos output v dd = 2.97 cload = 5 pf ?? 2ns output duty cycle differential uncertainty cko dc 100 ? load line to line measured at 50% point (not for cmos) ??40ps lvcmos pins input capacitance c in ?? 3pf notes: 1. assumes n3 does not equal 1. if n3 = 1, ckn dc = 50 s. 2. refers to si5315a speed grade. 3. refers to si5315b speed grade.
si5315 rev. 1.0 9 lvcmos output pins rise/fall times t rf cload = 20 pf see figure 2 ?25 ?ns losn trigger window los trig from last ckinn ? to internal detection of losn ??750s time to clear lol after los cleared t clrlol ?? los to ? lol assume fold=fnew, stable xa-xb reference ?10 ?ms pll performance output clock skew t skew ?? of ckoutn to ?? ckoutn ? ? 100 ps phase change due to temperature variation t temp maximum phase change from ?40 to +85 c ? 300 500 ps lock time t lockhw ?? rst with valid ckin to ?? lol; bw = 100 hz ? 1200 ? ms closed loop jitter peaking j pk ?0.050.1db jitter tolerance j tol see 4.2.3. "jitter toler- ance" on page 18. ns pk- pk minimum reset pulse width t rstmin 1??s output clock initial phase step t p_step during clock switch ckin > 19.44 mhz ? 100 200 ps holdover frequency historical averaging time t histavg ?6.7 ?sec holdover frequency historical delay time t histdel ?26.2 ? ms spurious noise sp spur max spur @ n x f3 (n > 1, n x f3 < 100 mhz) ??75 ?dbc table 3. ac characteristics (continued) (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max units notes: 1. assumes n3 does not equal 1. if n3 = 1, ckn dc = 50 s. 2. refers to si5315a speed grade. 3. refers to si5315b speed grade.
si5315 10 rev. 1.0 figure 1. ckin voltage characteristics figure 2. rise/fall time characteristics table 4. jitter generation (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition 1,2,3,4 min typ max gr-253 spec unit measuremen t filter (mhz) dspll bw 1 jitter gen oc-192 j gen 0.02?80 167 hz 5 ? 0.483 0.628 n/a ps rms 4?80 167 hz 5 ? 0.302 0.392 n/a ps rms 0.05?80 167 hz 5 ? 0.467 0.607 1.0 ps rms (0.01 ui rms ps rms jitter gen oc-48 j gen 0.012?20 167 hz 5 ? 0.470 0.611 4.02 ps rms (0.01 ui rms ) ps rms 111 hz 6 ? 0.565 0.734 4.02 ps rms (0.01 ui rms ) ps rms ieee 802.3 gbe rms jitter j gen 1.875?20 83 hz 6 ? 0.232 0.301 ps rms notes: 1. bwsel [1:0] loop bandwidth settings provided in table 9 on page 20. 2. 40 mhz fundamental mode crystal used as xa/xb input. 3. v dd = 2.5 v 4. t a = 85 c 5. si5315a test condition: f in = 19.44 mhz, f out = 156.25 mhz, lvpecl clock input: 1.19 vppd with 0.5 ns rise/fall time (20?80%), lvpecl clock output. 6. si5315b test condition: f in =19.44 mhz, f out = 125 mhz, lvpecl clock input: 1.19 vppd with 0.5 ns rise/fall time (20- 80%), lvpecl clock output. v ise , v ose v id ,v od differential i/os v icm , v ocm single-ended peak-to-peak voltage differential peak-to-peak voltage signal + signal ? (signal +) ? (signal ?) v t signal + signal ? v id = (signal+) ? (signal?) v icm , v ocm t f t r 80% 20% dout, clout
si5315 rev. 1.0 11 1.1. three-level (3 l) input pins (no external resistors) figure 3. three-level input pins table 5. three-level input pins (no external resistors) parameter symbol min max input voltage low vill ? 0.15 x v dd input voltage mid vimm 0.45 x v dd 0.55 x v dd input voltage high vihh 0.85 x v dd ? input low current iill ?6 a ? input mid current iimm ?2 a 2 a input high current iihh ? 6 a note: the above currents are the amount of l eakage that the 3l inputs can tolerate from an external driver. external driver si5315 i imm 75 k ? v dd 75 k ?
si5315 12 rev. 1.0 1.2. three-level (3 l) input pins (with external resistors) figure 4. three level input pins ? any resistor pack may be used. ?? the panasonic exb-d10c183j is an example. ?? pcb layout is not critical. ? resistor packs are only needed if the leakage current of the external driver exceeds the listed currents. ? if a pin is tied to ground or v dd , no resistors are needed. ? if a pin is left open (no connect), no resistors are needed. table 6. three-level input pins (with external resistors) parameter symbol min max input low current iill ?30 a ? input mid current iimm ?11 a ?11 a input high current iihh ? ?30 a note: the above currents are the amount of l eakage that the 3l inputs can tolerate from an external driver. external driver si5315 i imm 18 k : v dd 18 k : 75 k : v dd 75 k : one of eight resistors from a panasonic exb-d10c183j (or similar) resistor pack
si5315 rev. 1.0 13 table 7. thermal characteristics (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit thermal resistance junction to ambient ? ja still air ? 32 ? oc/w thermal resistance junction to case ? jc still air ? 14 ? oc/w table 8. absolute maximum limits parameter symbol value unit dc supply voltage v dd ?0.5 to 3.8 v lvcmos input voltage v dig ?0.3 to (v dd + 0.3) v ckinn voltage level limits ckn vin 0 to v dd v xa/xb voltage level limits xa vin 0 to 1.2 v operating junction temperature t jct ?55 to 150 c storage temperature range t stg ?55 to 150 c esd hbm tolerance (100 pf, 1.5 k ? ); all pins except ckin+/ckin? 2k v esd mm tolerance; all pins except ckin+/ckin? 150 v esd hbm tolerance (100 pf, 1.5 k ? ); ckin+/ckin? 750 v esd mm tolerance; ckin+/ckin? 100 v latch-up tolerance jesd78 compliant note: permanent device damage may occur if the absolute maximu m ratings are exceeded. functional operation should be restricted to the conditions as specified in the operation se ctions of this data sheet. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
si5315 14 rev. 1.0 2. typical application circuit figure 5. si5315 typical application circuit si5315 los1 los2 lol ckout1+ ckout1? ckin1 loss of signal indicator ckin2 loss of signal indicator pll loss of lock indicator ckout2+ ckout2? 2. denotes tri-level input pins with states designated as l (ground), m (v dd /2), and h (v dd ). ckin1+ ckin1? backplane or line recovered clock inputs ckin2+ ckin2? notes: 3. assumes manual input clock selection. xa xb 40 mhz crystal option 1: 1. assumes differential lvpecl termination (3.3 v) on clock inputs. vdd gnd ferrite bead system power supply c 3 c 2 c 1 c 4 0.1 f 0.1 f 0.1 f 1 f 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v clock outputs to ethernet phys 100 ? 0.1 f 0.1 f + ? 100 ? 0.1 f 0.1 f + ? xa xb ext. refclk+ option 2: 0.1 f ext. refclk? 0.1 f bwsel[1:0] 2 bandwidth select v dd 15 k ? 15 k ? sfout[1:0] 2 signal format select v dd 15 k ? 15 k ? dbl2_by 2 clock output 2 disable/ bypass mode control v dd 15 k ? 15 k ? frqsel[3:0] 2 frequency select v dd 15 k ? 15 k ? frqtbl 2 frequency table select v dd 15 k ? 15 k ? cs 3 input clock select v dd 15 k ? 15 k ? autosel 2 manual/automatic clock selection (l) v dd 15 k ? 15 k ? xtal/clock 2 crystal/ref clk v dd 15 k ? 15 k ? rst reset gnd pad
si5315 rev. 1.0 15 3. system level overview the si5315 provides clock translation, jitter attenuation, and clock distribution for hi gh-performance synchronous ethernet* line card timing applications. *note: the si5315 supports synce eec options 1 and 2 when paired with a timing card that implements the required wander filtering and stratum 3 compliant reference clock. for deta iled information, refer to ?an420: synce and ieee 1588: sync distribution for a unified network?. the si5315 provides clock translation, jitter attenuation, and clock distribution for hi gh-performance synchronous ethernet line card timing applications . the device accepts two clock inputs ranging from 8 khz to 644.53 mhz and generates two equal frequency, low jitter clock outputs rang ing from 8 khz to 644.53 mhz. for ease of use, the si5315 is pin controlled to enable simp le device configuration of frequency plans, pll loop bandwidth, and input clock selection. the dspll locks to one of two input reference clocks and provides over 200 frequency translations to synchronize output clocks for ethernet, sonet/sdh, and pdh line cards. the si5315 implements internal state machines to control hitless switching between input clocks and holdover. status alarms, loss of signal (los) and loss of lock (lol) are provided on output pins to indicate a change in device status. this device is designed for systems with line cards that are synchronized to a redundant, centralized telecom or ethernet backplane. the si5315 synchron izes to backplane clocks and gener ates a multiplied, jitter attenuated ethernet/sonet/sdh clock or pdh clock. a typical sy stem application is shown in figure 6. the si5315 translates a 19.44 mhz clock from the telecom backplane to an ethernet or sonet/ sdh clock frequency to the phy and filters the jitter to ensure compliance with related itu-t and telcordia standards. figure 6. typical si5315 application telecom or ethernet backplane wander filtering hitless switching holdover network sync pll 8 khz 19.44 mhz 25 mhz network synchronization a b bits a l i n e r e c o v e r e d t i m i n g bits b 10g lan / wan synce line card line recovered clocks 155.52 mhz 156.25 mhz 161.1328125 mhz 10gbe phy si5315 tx timing path rx timing path 8 khz 19.44 mhz 25 mhz jitter filtering hitless switching frequency translation 10gbe phy a b redundant timing cards multi-port sonet / sdh / pdh line card line recovered clocks 77.76 / 155.52 mhz 1.544 / 2.048 mhz oc-3 / 12 si5315 tx timing path rx timing path 8 khz 19.44 mhz 25 mhz jitter filtering hitless switching frequency translation a b t1 / e1
si5315 16 rev. 1.0 4. functional description figure 7. detailed block diagram 4.1. overview the si5315 is a jitter-attenuating precision clock mult iplier for synchronous ethe rnet, sonet/sdh, and pdh (t1/e1) applications. the si5315 accepts dual clock input s ranging from 8 khz to 644.53 mhz and generates two frequency-multiplied clock outputs ranging from 8 khz to 644.53 mhz. the two input clocks are at the same frequency and the two output clocks are at the same freq uency. the input clock frequen cy and clock multiplication ratio are selectable from a look up table of popular synce and t1/e1 rates. the si5315 is based on silicon laboratories' 3rd- generation dspll ? technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components. the si5315 pll loop bandwidth is selectable via the bwsel[1:0] pins and supports a range from 60 to 8.4 khz. the si5315 supports hitless switching between the two input clocks in compliance with itu-t g.8262 and telcordia gr-253-core and gr-1244-core. this feature greatly mi nimizes the propagation of phase transients to the clock outputs during an input clock transition (<200 ps typ) . manual and automatic revertive and non-revertive input clock switching options are available vi a the autosel input pin. the si5315 mo nitors both input clocks for loss-of- signal and provides a los alarm when it detects missing pu lses on either input clock. the device monitors the lock status of the pll. the lock detect algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. the si5315 provides a holdov er capability that allows the device to continue generation of a stable output cloc k when the selected inpu t reference is lost. the si5315 has two differential clock outputs. the signal format of the clock output s is programmable to support lvpecl, lvds, cml, or cmos loads . the second clock output can be powered down to minimize power consumption. for system-level debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal dspll. the device operates from a single 1. 8, 2.5, or 3.3 v supply. dspll ? los1 lol cs/ca bwsel[1:0] dbl2_by sfout[1:0] ckout2+ ckout2? ckin1+ ckin1? ckout1+ ckout1? ckin2+ ckin2? autosel frqtbl vdd (1.8, 2.5, or 3.3 v) gnd los2 2 2 frqsel[3:0] rst 0 1 xtal/clock xa xb f osc 2 2 0 1 0 1 f 3 frequency control bandwidth control signal detect control crystal or reference clock pll bypass
si5315 rev. 1.0 17 4.2. pll performance the si5315 provides extremely low jit ter generation, a well-controlled jitter transfer function, and high jitter tolerance due to the high level of integration. 4.2.1. jitter generation jitter generation is defined as the amount of jitter produced at the output of the device with a jitter free input clock. generated jitter arises from sources within the vco and ot her pll components. jitter g eneration is a function of the pll bandwidth setting. higher loop bandwidth settings may result in lower jitter gen eration, but may result in less attenuation of jitter that might be present on the input clock signal. 4.2.2. jitter transfer jitter transfer is defined as the ratio of output signal jit ter to input signal jitter for a specified jitter frequency. the jitter transfer characteristic determines the amount of in put clock jitter that passes to the outputs. the dspll technology used in the si5315 provides tightly controlle d jitter transfer curves because the pll gain parameters are determined largely by digital circuits which do not vary over supply voltage, process, and temperature. in a system application, a well-controlled tran sfer curve minimizes the output clock jitter variation from board to board and provides more consistent system level jitter performance. the jitter transfer characteristic is a function of the loop bandwidth setting. lower bandwidth setti ngs result in more jitter attenuation of the incoming clock, but may result in higher jitter generation. fi gure 8 shows the jitter transfer curve mask. figure 8. pll jitter transfer mask/template jitter transfer 0 db bw f jitter peaking ?20 db/dec. jitter out jitter in
si5315 18 rev. 1.0 4.2.3. jitter tolerance jitter tolerance is defined as the maximum peak-to-peak sinusoidal jitter that can be present on the incoming clock before the dspll loses lock. the tolerance is a function of the jitter frequency, bec ause tolerance improves for lower input jitter frequency. the jitter tolerance of the dspll is a function of the loop bandwidth setti ng. figure 9 shows the general shape of the jitter tolerance curve versus input jitter frequency. for jitter frequencies above the loop bandwidth, the tolerance is a constant value a j0 . beginning at the pll bandwidth, the tolerance increases at a rate of 20 db/decade for lower input jitter frequencies. figure 9. jitter tolerance mask/template the equation for the high frequency jitter tolerance can be expressed as a function of the pll loop bandwidth (i.e., bw): for example, the jitter tolerance when f in = 19.44 mhz, f out = 161.13 mhz and the loop bandwidth (bw) is 113 hz: 4.2.4. jitter attenuation performance the internal vco uses the reference clock on the xa/xb pins as its referenc e for jitter attenuation. the xa/xb pins support either a crystal input or an input buffer single-ended or differential clock input, such that an external oscillator can become the reference sour ce. in either case, the device accept s a wide margin in absolute frequency of the reference input. (see 5.5. "holdover mode" on pa ge 32.) in holdover, the si 5315's output clock stability matches the reference supplied on the xa/xb pins. the exter nal crystal or reference clock must be selected based on the stability requirements of the application if hold over is a key requirement. however, care must be exer cised in certain areas for optimum performa nce. for examples of connections to the xa/xb pins, refer to 7. "crystal/reference clock input" on page 38. input jitter amplitude a j0 ?20 db/dec. f jitter in excessive input jitter range bw/100 bw/10 bw a j0 5000 bw ------------ - ns pk-pk = a j0 5000 113 ------------ - 44.24 ns pk-pk ==
si5315 rev. 1.0 19 5. frequency plan tables for ease of use, the si5315 is pin controlled to enable si mple device configuration of the frequency plan and pll loop bandwidth via a predefined look up table. the d spll has been optimized for each frequency multiplication and pll loop bandwidth provided in table 9 on page 20. many of the control inputs are three levels: high, low, and medium. high and low are standard voltage levels determined by the supply voltage: v dd and ground. if the input pin is left floa ting, it is driven to nominally half of v dd . effectively, this creates three logi c levels for these controls. see 1.2. "three-level (3l) input pins (with external resistors)" on page 12 and 8. "power suppl y filtering" on page 41 for additional information. 5.1. frequency multiplication plan the input to output clock multiplication is set by the 3-le vel frqsel[3:0] pins. the device provides a wide range of commonly used synce, sonet/sdh, an d pdh frequency translations. the ck in1 and ckin2 inputs must be the same frequency as specified in table 9. both ckou t1 and ckout2 outputs are at the same frequency. 5.1.1. pll loop bandwidth plan the si5315's loop bandwidth ranges from 60 hz to 8.4 k hz. for each frequency multiplication, its corresponding loop bandwidth is provided in a simple look up table. (see table 9 on page 20.) the loop bandwidth (bw) is digitally programmable using the 3-leve l bwsel [1:0] and frqtbl input pins.
si5315 20 rev. 1.0 table 9. look up tables for clock multiplication and loop bandwidth settings plan # f in (mhz) f out (mhz) frqtbl frqsel [3:0] loop bandwidth selection (hz), bwsel[1:0] lm lh ml mm mh hl hh 1 0.008 0.008 l llll 257 60 ? ? ? ? ? 2 0.008 1.544 l lllm 257 60 ? ? ? ? ? 3 0.008 2.048 l lllh 257 60 ? ? ? ? ? 4 0.008 8.192 l llml 257 60 ? ? ? ? ? 5 0.008 19.44 l llmm 257 60 ? ? ? ? ? 6 0.008 25 l llmh 257 60 ? ? ? ? ? 7 0.008 32.768 l llhl 257 60 ? ? ? ? ? 8 0.008 34.368 m llll 257 60 ? ? ? ? ? 9 0.008 38.88 m lllm 257 60 ? ? ? ? ? 10 0.008 44.736 m lllh 257 60 ? ? ? ? ? 11 0.008 51.84 m llml 257 60 ? ? ? ? ? 120.00865.536mllmm 257?????? 13 0.008 77.76 m llmh 257 60 ? ? ? ? ? 14 0.008 125 m llhl 257 60 ? ? ? ? ? 15 0.008 155.52 h llll 257 60 ? ? ? ? ? 16 0.008 156.25 h lllm 257 60 ? ? ? ? ? 17 0.008 311.04 h lllh 257 60 ? ? ? ? ? 18 0.008 312.5 h llml 257 60 ? ? ? ? ? 19 0.008 622.08 h llmm 257 60 ? ? ? ? ? 20 1.544 0.008 l llhm 257 60 ? ? ? ? ? 21 1.544 1.544 l llhh ? ? 6047 1451 359 179 89 22 1.544 2.048 l lmll 257 60 ? ? ? ? ? 23 1.544 8.192 l lmlm 257 60 ? ? ? ? ? 24 1.544 19.44 l lmlh 257 60 ? ? ? ? ? notes: 1. f in and f out frequency values may be rounded off. for exact mult iplication ratios, please contact silicon labs. 2. si5315a supports all frequency plans. 3. si5315b supports output frequency plans up to 125 mhz.
si5315 rev. 1.0 21 25 1.544 25 l lmml 257 60 ? ? ? ? ? 26 1.544 32.768 l lmmm 257 60 ? ? ? ? ? 27 1.544 34.368 m llhm 257 60 ? ? ? ? ? 28 1.544 38.88 m llhh 257 60 ? ? ? ? ? 29 1.544 44.736 m lmll 257 60 ? ? ? ? ? 30 1.544 51.84 m lmlm 257 60 ? ? ? ? ? 311.54465.536mlmlh 257?????? 32 1.544 77.76 m lmml 257 60 ? ? ? ? ? 33 1.544 125 m lmmm 257 60 ? ? ? ? ? 34 1.544 155.52 h llmh 257 60 ? ? ? ? ? 35 1.544 156.25 h llhl 257 60 ? ? ? ? ? 36 1.544 311.04 h llhm 257 60 ? ? ? ? ? 37 1.544 312.5 h llhh 257 60 ? ? ? ? ? 38 1.544 622.08 h lmll 257 60 ? ? ? ? ? 39 2.048 0.008 l lmmh 2089 485 240 59 ? ? ? 40 2.048 1.544 l lmhl 1037 242 119 ? ? ? ? 41 2.048 2.048 l lmhm ? ? 3949 959 238 118 59 42 2.048 8.192 l lmhh ? ? 3949 959 238 118 59 43 2.048 19.44 l lhll ? ? 3946 958 238 118 59 44 2.048 25 l lhlm 2087 485 240 ? ? ? ? 45 2.048 32.768 l lhlh ? ? 3947 959 238 118 59 46 2.048 34.368 m lmmh ? 8163 3935 958 238 118 ? 47 2.048 38.88 m lmhl ? ? 3946 958 238 118 59 48 2.048 44.736 m lmhm ? 3983 1944 477 118 59 ? 49 2.048 51.84 m lmhh ? ? 3946 958 238 118 59 table 9. look up tables for clock multiplication and loop bandwidth settings (continued) plan # f in (mhz) f out (mhz) frqtbl frqsel [3:0] loop bandwidth selection (hz), bwsel[1:0] lm lh ml mm mh hl hh notes: 1. f in and f out frequency values may be rounded off. for exact mult iplication ratios, please contact silicon labs. 2. si5315a supports all frequency plans. 3. si5315b supports output frequency plans up to 125 mhz.
si5315 22 rev. 1.0 50 2.048 65.536 m lhll ? 8185 3940 958 238 118 ? 51 2.048 77.76 m lhlm ? ? 3946 958 238 118 59 52 2.048 125 m lhlh 1037 242 119 ? ? ? ? 53 2.048 155.52 h lmlm ? ? 3946 958 238 118 59 54 2.048 156.25 h lmlh 1037 242 119 ? ? ? ? 55 2.048 311.04 h lmml ? ? 3946 958 238 118 59 56 2.048 312.5 h lmmm 1037 242 119 ? ? ? ? 57 2.048 622.08 h lmmh ? ? 3946 958 238 118 59 58 8.192 0.008 l lhml 2089 485 240 59 ? ? ? 59 8.192 1.544 l lhmm 1037 242 119 ? ? ? ? 60 8.192 2.048 l lhmh ? ? 6434 1541 381 190 95 61 8.192 8.192 l lhhl ? ? 6434 1541 381 190 95 62 8.192 19.44 l lhhm ? ? 3946 958 238 118 59 63 8.192 25 l lhhh 2087 485 240 ? ? ? ? 64 8.192 32.768 l mlll ? ? 6431 1541 381 190 95 65 8.192 34.368 m lhml ? 8163 3935 958 238 118 ? 66 8.192 38.88 m lhmm ? ? 3946 958 238 118 59 67 8.192 44.736 m lhmh ? 3983 1944 477 118 59 ? 68 8.192 51.84 m lhhl ? ? 3946 958 238 118 59 69 8.192 65.536 m lhhm ? ? 6411 1539 381 190 95 70 8.192 77.76 m lhhh ? ? 3946 958 238 118 59 71 8.192 125 m mlll 1037 242 119 ? ? ? ? 72 19.44 0.008 l mllm 1759 409 202 ? ? ? ? 73 19.44 1.544 l mllh ? 2779 1362 335 83 ? ? 74 19.44 2.048 l mlml ? 3348 1638 402 100 ? ? table 9. look up tables for clock multiplication and loop bandwidth settings (continued) plan # f in (mhz) f out (mhz) frqtbl frqsel [3:0] loop bandwidth selection (hz), bwsel[1:0] lm lh ml mm mh hl hh notes: 1. f in and f out frequency values may be rounded off. for exact mult iplication ratios, please contact silicon labs. 2. si5315a supports all frequency plans. 3. si5315b supports output frequency plans up to 125 mhz.
si5315 rev. 1.0 23 75 19.44 8.192 l mlmm ? 3348 1638 402 100 ? ? 76 19.44 19.44 l mlmh ? ? 7706 1832 452 225 112 77 19.44 25 l mlhl ? 2778 1362 335 83 ? ? 78 19.44 32.768 l mlhm ? ? 5022 1215 301 150 75 79 19.44 34.368 m mllm ? 5662 2749 672 167 83 ? 80 19.44 38.88 m mllh ? ? 7703 1832 452 225 112 81 19.44 44.736 m mlml ? 5653 2747 672 167 83 ? 82 19.44 51.84 m mlmm ? ? 7696 1832 452 225 112 83 19.44 65.536 m mlmh 2618 607 300 74 ? ? ? 84 19.44 77.76 m mlhl ? ? 7696 1832 452 225 112 85 19.44 125 m mlhm 3960 913 450 111 ? ? ? 86 19.44 155.52 h lmhl ? ? 7696 1832 452 225 112 87 19.44 156.25 h lmhm 6003 1373 677 167 ? ? ? 88 19.44 161.1328 h lmhh 484 113 ? ? ? ? ? 89 19.44 311.04 h lhll ? ? 7696 1832 452 225 112 90 19.44 312.5 h lhlm 6003 1373 677 167 ? ? ? 91 19.44 622.08 h lhlh ? ? 7696 1832 452 225 112 9219.44644.5313hlhml 103?????? 93 25 0.008 l mlhh ? ? 7045 1681 415 207 103 94 25 1.544 l mmll 6741 1529 753 186 ? ? ? 95 25 2.048 l mmlm 1299 303 150 ? ? ? ? 96 25 8.192 l mmlh 6737 1529 753 186 ? ? ? 97 25 19.44 l mmml ? ? 6551 1568 387 193 96 98 25 25 l mmmm ? ? 7615 1812 447 223 111 99 25 32.768 l mmmh 6737 1529 753 186 ? ? ? table 9. look up tables for clock multiplication and loop bandwidth settings (continued) plan # f in (mhz) f out (mhz) frqtbl frqsel [3:0] loop bandwidth selection (hz), bwsel[1:0] lm lh ml mm mh hl hh notes: 1. f in and f out frequency values may be rounded off. for exact mult iplication ratios, please contact silicon labs. 2. si5315a supports all frequency plans. 3. si5315b supports output frequency plans up to 125 mhz.
si5315 24 rev. 1.0 100 25 34.368 m mlhh 6722 1528 753 186 ? ? ? 101 25 38.88 m mmll 6729 1529 753 186 ? ? ? 102 25 44.736 m mmlm 1298 303 150 ? ? ? ? 103 25 50 h hmlh ? ? 7880 1880 470 230 120 104 25 51.84 m mmlh ? 7988 3846 936 232 116 ? 105 25 65.536 m mmml 1298 303 150 ? ? ? ? 106 25 77.76 m mmmm 6706 1528 753 186 ? ? ? 107 25 125 m mmmh ? ? 7606 1811 447 223 111 108 25 155.52 h lhmm 1298 303 150 ? ? ? ? 109 25 156.25 h lhmh ? ? 7606 1811 447 223 111 110 25 161.1328 h lhhl ? ? 6106 1468 363 181 90 111 25 311.04 h lhhm 1298 303 150 ? ? ? ? 112 25 312.5 h lhhh ? ? 7606 1811 447 223 111 113 25 622.08 h mlll 1298 303 150 ? ? ? ? 114 25 644.5313 h mllm ? ? 6106 1468 363 181 90 115 32.768 0.008 l mmhl 2089 485 240 59 ? ? ? 116 32.768 1.544 l mmhm 1037 242 119 ? ? ? ? 117 32.768 2.048 l mmhh ? ? 7187 1714 423 211 105 118 32.768 8.192 l mhll ? ? 7632 1816 448 223 111 119 32.768 19.44 l mhlm ? ? 3946 958 238 118 59 120 32.768 25 l mhlh 2087 485 240 ? ? ? ? 121 32.768 32.768 l mhml ? ? 7632 1816 448 223 111 122 32.768 34.368 m mmhl ? 8163 3935 958 238 118 ? 123 32.768 38.88 m mmhm ? ? ? 958 238 118 59 124 32.768 44.736 m mmhh ? 3983 1944 477 118 59 ? table 9. look up tables for clock multiplication and loop bandwidth settings (continued) plan # f in (mhz) f out (mhz) frqtbl frqsel [3:0] loop bandwidth selection (hz), bwsel[1:0] lm lh ml mm mh hl hh notes: 1. f in and f out frequency values may be rounded off. for exact mult iplication ratios, please contact silicon labs. 2. si5315a supports all frequency plans. 3. si5315b supports output frequency plans up to 125 mhz.
si5315 rev. 1.0 25 125 32.768 51.84 m mhll ? ? 3946 958 238 118 59 126 32.768 65.536 m mhlm ? ? 7604 1815 448 223 111 127 32.768 77.76 m mhlh ? ? 3946 958 238 118 59 128 32.768 125 m mhml 1037 242 119 ? ? ? ? 129 50 25 l hhhh ? ? 7880 1880 470 230 120 130 50 50 m hmlh ? ? 7770 1850 466 230 110 131 77.76 0.008 l mhmm 2089 485 240 59 ? ? ? 132 77.76 1.544 l mhmh ? 2779 1362 335 83 ? ? 133 77.76 2.048 l mhhl ? ? 6804 1626 402 200 100 134 77.76 19.44 l mhhm ? ? 7905 1879 464 231 115 135 77.76 25 l mhhh ? 2778 1362 335 83 ? ? 136 77.76 34.368 m mhmm ? ? 6798 1626 402 200 100 137 77.76 38.88 m mhmh ? ? 7905 1879 464 231 115 138 77.76 44.736 m mhhl ? ? 6756 1623 402 200 100 139 77.76 51.84 m mhhm ? ? 7905 1879 464 231 115 140 77.76 65.536 m mhhh ? 2461 1208 298 74 ? ? 141 77.76 77.76 m hlll ? ? 7905 1879 464 231 115 142 77.76 125 m hllm 5336 1220 602 148 ? ? ? 143 77.76 155.52 h mllh ? ? 7905 1879 464 231 115 144 77.76 156.25 h mlml 6003 1373 677 167 ? ? ? 145 77.76 161.1328 h mlmm 484 113 ? ? ? ? ? 146 77.76 311.04 h mlmh ? ? 7905 1879 464 231 115 147 77.76 312.5 h mlhl 6003 1373 677 167 ? ? ? 148 77.76 622.08 h mlhm ? ? 7905 1879 464 231 115 149 77.76 644.5313 h mlhh 484 113 ? ? ? ? ? table 9. look up tables for clock multiplication and loop bandwidth settings (continued) plan # f in (mhz) f out (mhz) frqtbl frqsel [3:0] loop bandwidth selection (hz), bwsel[1:0] lm lh ml mm mh hl hh notes: 1. f in and f out frequency values may be rounded off. for exact mult iplication ratios, please contact silicon labs. 2. si5315a supports all frequency plans. 3. si5315b supports output frequency plans up to 125 mhz.
si5315 26 rev. 1.0 150 125 0.008 l hlll ? ? 7045 1681 415 207 103 151 125 1.544 l hllm 6741 1529 753 186 ? ? ? 152 125 2.048 l hllh 1299 303 150 ? ? ? ? 153 125 19.44 l hlml ? ? 6551 1568 387 193 96 154 125 25 l hlmm ? ? 7862 1870 462 230 115 155 125 34.368 m hllh 6722 1528 753 186 ? ? ? 156 125 38.88 m hlml 6729 1529 753 186 ? ? ? 157 125 44.736 m hlmm 1298 303 150 ? ? ? ? 158 125 51.84 m hlmh ? 7988 3846 936 232 116 ? 159 125 65.536 m hlhl 1298 303 150 ? ? ? ? 160 125 77.76 m hlhm 6706 1528 753 186 ? ? ? 161 125 125 m hlhh ? ? 7862 1870 462 230 115 162 125 155.52 h mmll 1298 303 150 ? ? ? ? 163 125 156.25 h mmlm ? ? 7862 1870 462 230 115 164 125 161.1328 h mmlh ? ? 7718 1839 454 226 113 165 125 311.04 h mmml 1298 303 150 ? ? ? ? 166 125 312.5 h mmmm ? ? 7862 1870 462 230 115 167 125 622.08 h mmmh 1298 303 150 ? ? ? ? 168 125 644.5313 h mmhl ? ? 7718 1839 454 226 113 169 155.52 0.008 l hlmh 2089 485 240 59 ? ? ? 170 155.52 1.544 l hlhl ? 2779 1362 335 83 ? ? 171 155.52 2.048 l hlhm ? ? 7606 1809 447 223 111 172 155.52 19.44 l hlhh ? ? 7905 1879 464 231 115 173 155.52 25 l hmll ? 2778 1362 335 83 ? ? 174 155.52 77.76 h mmhm ? ? 7905 1879 464 231 115 table 9. look up tables for clock multiplication and loop bandwidth settings (continued) plan # f in (mhz) f out (mhz) frqtbl frqsel [3:0] loop bandwidth selection (hz), bwsel[1:0] lm lh ml mm mh hl hh notes: 1. f in and f out frequency values may be rounded off. for exact mult iplication ratios, please contact silicon labs. 2. si5315a supports all frequency plans. 3. si5315b supports output frequency plans up to 125 mhz.
si5315 rev. 1.0 27 175 155.52 125 h mmhh 5336 1220 602 148 ? ? ? 176 155.52 155.52 h mhll ? ? 7905 1879 464 231 115 177 155.52 156.25 h mhlm 6003 1373 677 167 ? ? ? 178 155.52 161.1328 h mhlh 484 113 ? ? ? ? ? 179 155.52 311.04 h mhml ? ? 7905 1879 464 231 115 180 155.52 312.5 h mhmm 6003 1373 677 167 ? ? ? 181 155.52 622.08 h mhmh ? ? 7905 1879 464 231 115 182 155.52 644.5313 h mhhl 828 193 95 ? ? ? ? 183 156.25 0.008 l hmlm ? ? 6123 1469 363 181 90 184 156.25 1.544 l hmlh 1627 379 187 ? ? ? ? 185 156.25 2.048 l hmml 322 75 ? ? ? ? ? 186 156.25 19.44 l hmmm ? ? 4852 1172 290 145 72 187 156.25 25 l hmmh ? ? 7835 1864 460 229 114 188 156.25 77.76 h mhhm 1625 379 187 ? ? ? ? 189 156.25 125 h mhhh ? ? 7835 1864 460 229 114 190 156.25 155.52 h hlll 322 75 ? ? ? ? ? 191 156.25 156.25 h hllm ? ? 7835 1864 460 229 114 192 156.25 161.1328 h hllh ? ? 7718 1839 454 226 113 193 156.25 311.04 h hlml 322 75 ? ? ? ? ? 194 156.25 312.5 h hlmm ? ? 7835 1864 460 229 114 195 156.25 622.08 h hlmh 322 75 ? ? ? ? ? 196 156.25 644.5313 h hlhl ? ? 7718 1839 454 226 113 197161.13280.008lhmhl 225?????? 198161.13281.544lhmhm 151?????? 199161.13282.048lhmhh 225?????? table 9. look up tables for clock multiplication and loop bandwidth settings (continued) plan # f in (mhz) f out (mhz) frqtbl frqsel [3:0] loop bandwidth selection (hz), bwsel[1:0] lm lh ml mm mh hl hh notes: 1. f in and f out frequency values may be rounded off. for exact mult iplication ratios, please contact silicon labs. 2. si5315a supports all frequency plans. 3. si5315b supports output frequency plans up to 125 mhz.
si5315 28 rev. 1.0 200 161.1328 19.44 l hhll 679 159 78 ? ? ? ? 201 161.1328 25 l hhlm 678 159 78 ? ? ? ? 202 161.1328 77.76 h hlhm 678 159 78 ? ? ? ? 203 161.1328 125 h hlhh ? ? 7179 1721 426 212 106 204 161.1328 156.25 h hmll ? ? 7019 1683 416 207 103 205 161.1328 161.1328 h hmlm 332 78 ? ? ? ? ? 206 161.1328 312.5 h hmml 3873 892 440 109 ? ? ? 207161.1328644.5313hhmmm 151?????? 208 644.5313 0.008 l hhlh 880 206 101 ? ? ? ? 209 644.5313 1.544 l hhml 413 96 ? ? ? ? ? 210 644.5313 2.048 l hhmm ? 3373 1650 405 101 ? ? 211 644.5313 19.44 l hhmh ? 3641 1779 437 108 ? ? 212 644.5313 25 l hhhl ? ? 7886 1875 463 231 115 213 644.5313 77.76 h hmmh 828 193 95 ? ? ? ? 214 644.5313 125 h hmhl ? ? 7732 1840 454 226 113 215 644.5313 155.52 h hmhm 828 193 95 ? ? ? ? 216 644.5313 156.25 h hmhh ? ? 7732 1840 454 226 113 217 644.5313 161.1328 h hhll ? ? 7895 1880 464 231 115 218 644.5313 311.04 h hhlm 828 193 95 ? ? ? ? 219644.5313312.5hhhlh 206?????? 220644.5313622.08hhhml 120?????? 221 644.5313 644.5313 h hhmm ? ? 7895 1880 464 231 115 table 9. look up tables for clock multiplication and loop bandwidth settings (continued) plan # f in (mhz) f out (mhz) frqtbl frqsel [3:0] loop bandwidth selection (hz), bwsel[1:0] lm lh ml mm mh hl hh notes: 1. f in and f out frequency values may be rounded off. for exact mult iplication ratios, please contact silicon labs. 2. si5315a supports all frequency plans. 3. si5315b supports output frequency plans up to 125 mhz.
si5315 rev. 1.0 29 5.2. pll self-calibration an internal self-calibrati on (ical) is performed before operation to optimize loop parameters and jitter performance. while the self-calibration is being performed, the dspll is being internally controlled by the self- calibration state machine. the lo l alarm will be active during ical. the self-calibration time t lockhw is given in table 3, ?ac characteristics?. any of the following events will trigger a self -calibration: ? power-on-reset (por) ? release of the external reset pin rst (transition of rst from 0 to 1) ? change in frqsel, frqtbl, bwsel, or xtal/clock pins ? internal dspll registers out-of-range, indicating the need to relock the dspll in any of the above cases, an internal self-calibration will be initiated if a va lid input clock exists (no input alarm) and is selected as the active clock at that time. the extern al crystal or reference clock must also be present for the self-calibration to begin. if valid clocks are not present, the self-calibration state machine will wait until they appear, at which time the calibration will start. an output clock will be active while wa iting for a valid input clock. the output clock frequency is based on the vco range determine by frqsel and frqtbl settings. this output clock will vary by 20%. if no output clock is desired prior to an ical, then the sfout pins should be kept at lm for 1.2 seconds until the output clock is stable. after a successful self-calibration has been performed with a valid input clock, no subsequent self calibrations are performed unless one of the above conditi ons are met. if the input clock is lost following self-ca libration, the device enters holdover mode. when the input clock returns, the device relocks to the input clock without performing a self- calibration. 5.2.1. input clock stability during internal self-calibration an exit from reset must occur when the selected ckinn cl ock is stable in frequency with a frequency value that is within the device operating range. the other ckins must also either be stable in frequency or squelched during a reset. 5.2.2. self-calibration caused by changes in input frequency if the selected ckinn varies by 500 ppm or more in freque ncy since the last calibration , the device may initiate a self-calibration. 5.2.3. device reset upon powerup, the device internally executes a power-on-r eset (por) which resets the internal device logic. the pin rst can also be used to initiate a re set. the device stays in this state until a valid ckinn is present, when it then performs a pll self-calibration (see 5.2. "pll self-calibration?). 5.2.4. recommended reset guidelines follow the recommended reset guidelines in table 10 when reset should be applied to a device. table 10. si5315 pins and reset pin # si5315 pin name must reset after changing 2f r q t b l y e s 11 xtal/clock yes 22 bwsel0 yes 23 bwsel1 yes 24 frqsel0 yes 25 frqsel1 yes 26 frqsel2 yes 27 frqsel3 yes
si5315 30 rev. 1.0 5.2.5. hitless switching with phase build-out silicon laboratories switching technology performs "phase build-out" to minimize the propagation of phase transients to the clock outputs during input clock switching. all switching between input clocks occurs within the input multiplexor and phase detector circuitry. the p hase detector circuitry cont inually monitors the phase difference between each input clo ck and the dspll output clock, f osc . the phase detector circuitry can lock to a clock signal at a specified phase offset relative to f osc so that the phase offset is maintained by the pll circuitry. at the time a clock switch occurs, the phase detector circuitry knows both the input-to-output phase relationship for the original input clock and for the new input clock. the pha se detector circuitry locks to the new input clock at the new clock's phase offset so that the phase of the output clock is not disturbed. the phase difference between the two input clocks is absorbed in the phas e detector's offset value, rather than being propagated to the clock output. the switching technology virtua lly eliminates the output clock phase tran sients traditionally associated with clock rearrangement (input clock switching). the maximum ti me interval error (mtie) and maximum slope for clock output phase transients during clock switching are given in (table 3, ?ac characteri stics?). these values fall significantly below the limits spec ified in the itu-t g.8262, telcor dia gr-1244-core, and gr-253-core requirements. 5.3. input clock control this section describes the clock select ion capabilities (manual input selection, automatic input selection, hitless switching, and revertive sw itching). when switching between two clocks, lol may temporarily go high if the two clocks differ in frequency by more than 100 ppm. 5.3.1. manual clock selection manual control of input clock sele ction is chosen via the cs_ca pin according to table 11 and table 12. 5.3.2. automatic clock selection the autosel input pin sets the input clock selection mode as shown in table 11. au tomatic switching is either revertive or non-revertive. setting autosel to m or h, c hanges the cs_ca pin to an out put pin that indicates the state of the automatic clock selection. table 11. automatic/manual clock selection autosel clock selection mode l manual m automatic non-revertive h automatic revertive table 12. manual input clock selection, autosel = l cs_ca si5315 autosel = l 0c k i n 1 1c k i n 2 table 13. clock active indicators, autosel = m or h cs_ca active clock 0c k i n 1 1c k i n 2
si5315 rev. 1.0 31 the prioritization of clock inputs for automatic switching is shown in table 1 4. this priority is hardwired in the devices. at power-on or reset, the va lid ckinn with the highest priority (1 being the highest priority) is automatically selected. if no valid ckinn is available, the device suppre sses the output clocks and waits for a valid ckinn signal. if the currently selected ckinn goes into an alarm state, the nex t valid ckinn in priority order is selected. if no valid ckinn is available, the device enters holdover. operation in revertive and non- revertive is different when a signal becomes valid: revertive (autosel = h): the device cons tantly monitors all ckinn. if a ckinn with a higher priority than the current active ckinn becomes valid , the active ckinn is changed to the ckinn with the highest priority. non-revertive (autosel = m): the active clock does not chan ge until there is an alarm on the active clock. the device will then select the highest priority ckinn that is valid. once in holdover, the device will switch to the fi rst ckinn that becomes valid. 5.4. alarms summary alarms are available to indicate the overall status of the input signals. alarm outputs stay high until all the alarm conditions for that alarm output are cleared. 5.4.1. loss-of-signal the device has loss-of-signal circuitr y that continuously monitors ckinn for missing pulses. the los circuitry generates an internal losn_int output signal that is processed with othe r alarms to generate los1 and los2. an los condition on ckin1 causes the internal los1_int alarm to become ac tive. similarly, an los condition on ckinn causes the losn_int alarm to become active. on ce a losn_int alarm is asserted on one of the input clocks, it remains asserted until that input clock is validated over a designated time period. the time to clear losn_int after a valid input clock appears is listed in table 3, ?ac characteristics?. if another error condition on the same input clock is detected during the validation time then the alarm remains asserted and the validation time starts over. 5.4.1.1. los algorithm the los circuitry divides down each input clock to produ ce an 8 khz to 2 mhz signal. the los circuitry over samples this divided down in put clock using a 40 mhz clock to search for extended periods of time without input clock transitions. if the los monitor detects twice the normal number of samples without a clock edge, a losn_int alarm is declared. table 3, ?ac characteristi cs? gives the minimum and maximum amount of time for the los monitor to trigger. 5.4.1.2. lock detect the pll lock detection algorithm indicates the lock st atus on the lol out put pin. the algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. if the time between two consecutive phase cycle slips is greater than the retrigger time, the pll is in lock. the lol output has a guaranteed minimum pulse width as shown in (table 3, ?ac characteristics?). the lo l pin is also held in the active state during an internal pll calibration. the retrigge r time is automatically set based on the pll closed loop bandwidth (see table 15). table 14. input clock priority for auto switching priority input clocks 1c k i n 1 2c k i n 2 3 holdover
si5315 32 rev. 1.0 5.5. holdover mode if an los condition exists on the select ed input clock, the device enters holdover. in this mode, the device provides a stable output frequency until the input clock returns and is validated. when the device enters holdover, the internal oscillator is initially held to its last frequency va lue. next, the internal oscillator slowly transitions to a historical average frequency value that was taken over a time window of 6,711 ms in size that ended 26 ms before the device entered holdover. this frequency value is taken from an internal memory location that keeps a record of previous dspll frequency values. by using a historic al average frequency, input clock phase and frequency transients that may occur immediately preceding loss of clock or any event causing holdover do not affect the holdover frequency. also, noise related to input clock jitter or in ternal pll jitter is minimized. if a highly stable reference, such as an oven-controlled crystal os cillator, is supplied at xa/xb, an extremely stable holdover can be achiev ed. if a crystal is supplied at the xa/xb port, the holdover stability will be limited by the stability of the crystal; table 3, ?ac characteristics? give s the specifications related to the holdover function. 5.5.1. recovery from holdover when the input clock signal returns, the device transitions from holdover to the selected input clock. the device performs hitless recovery from holdover. the clock transi tion from holdover to the returned input clock includes "phase buildout" to absorb the phase difference between the holdover clock phase and the input clock phase. see table 3, ?ac characteristic s? for specifications. 5.6. pll bypass mode the si5315 supports a pll bypass mode in which the sele cted input clock is fed directly to both enabled output buffers, bypassing the dspll. internally, the bypass path is implemented with high-speed differential signaling; however, this path is not a low jitter path and will see sign ificantly higher jitte r on ckout. in pll bypass mode, the input and output clocks will be at the sa me frequency. pll bypass mode is useful in a laboratory environment to measure system performance with and without the jitter attenuation provided by the dspll. the dsbl2_by pin is used to select the pll bypass mode according to table 16. bypass mode is not supported for cmos clock outputs (sfout = lh). table 15. lock detect retrigger time pll bandwidth setting (bw) retrigger time (ms) 60?120 hz 53 120?240 hz 26.5 240?480 hz 13.3 480?960 hz 6.6 960?1920 hz 3.3 1920?3840 hz 1.66 3840?7680 hz 0.833 table 16. dsbl2/bypass pin settings dsbl2/bypass function l ckout2 enabled m ckout2 disabled h pll bypass mode w/ ckout2 enabled
si5315 rev. 1.0 33 figure 10. bypass signal dspll ? dbl2_by crystal or reference clock sfout[1:0] ckout2+ ckout2? ckin1+ ckin1? ckout1+ ckout1? ckin2+ ckin2? vdd (1.8, 2.5, or 3.3 v) gnd 2 2 0 1 xtal/clock xa xb f osc 2 2 0 1 0 1 f 3 frequency control bandwidth control signal detect control los1 lol cs/ca bwsel[1:0] autosel frqtbl los2 frqsel[3:0] rst pll bypass
si5315 34 rev. 1.0 6. high-speed i/o 6.1. input clock buffers the si5315 provides differential inputs for the ckinn cloc k inputs. these inputs are internally biased to a common mode voltage [see table 2, ?dc characteristics?] and can be driven by either a single-ended or differential source. figure 11 through figure 14 show typi cal interface circuits for lvpecl, cm l, lvds, or cmos input clocks. note that the jitter generation improves for higher levels on ckinn (within the limits in table 3, ?ac characteristics?). ac coupling the input clocks is recommended because it removes any issue with common mode input voltages. however, either ac or dc coupling is acceptable. figures 11 and 12 show various examples of different input termination arrangements. unused inputs can be left unconnected. figure 11. differential lvpecl termination figure 12. single-ended lvpecl termination 40 k c c ckin _ ckin + v icm 300 130 130 3.3 v 82 82 si5315 lvpecl driver ? ? ? ? ? ? 40 k ? 40 k c c ckin _ ckin + v icm 300 130 3.3 v 82 si5315 driver ? ? ? ? 40 k ?
si5315 rev. 1.0 35 figure 13. cml/lvds termination (1.8, 2.5, 3.3 v) figure 14. cmos termination (1.8, 2.5, 3.3 v) 40 k c c ckin _ ckin + v icm 300 100 si5315 cml/ lvds driver ? ? ? 40 k ? v dd v dd v dd cmos driver r1 33 ohms 50 r2 see table r3 150 ohms c1 100 nf r4 150 ohms c2 100 nf v icm ckin+ ckin? r5 40 kohm r6 40 kohm v dd r2 notes 3.3 v 100 ohm locate r1 near cmos driver 2.5 v 49.9 ohm locate other components near si5317 1.8 v 14.7 ohm recalculate resistor values for other drive strengths additional notes: 1. attenuation circuit limits overshoot and undershoot. 2. not to be used with non-square wave input clocks. si5315
si5315 36 rev. 1.0 6.2. output clock drivers the si5315 has a flexible output driv er structure that can dr ive a variety of loads, including lvpecl, lvds, cml, and cmos formats. the signal format is selected for both ckout1 and ckout2 outputs using the sfout [1:0] pins. this modifies the output common mode and differenti al signal swing. see table 2, ?dc characteristics? for output driver specifications. the sfout [1:0] pins are three-level input pins, with the states designated as l (ground), m (v dd /2), and h (v dd ). table 17 shows the signal formats based on the supply voltage and the type of load being driven. figure 15. typical differential output circuit figure 16. typical cmos output circuit (tie ckoutn+ and ckoutn? together) for the cmos setting (sfout = lh), both output pins driv e single-ended in-phase signals. the ckout+/- can be externally shorted together for greater drive str ength specified in table 2, ?dc characteristics?. table 17. output signal format selection (sfout) sfout[1:0] signal format hl cml hm lvds lh cmos lm disabled mh lvpecl ml low-swing lvds all others reserved si5315 rcvr 100 z0 = 50 z0 = 50 ? ? ? ckoutn cmos logic ckoutn optionally tie ckoutn outputs together for greater strength si5315
si5315 rev. 1.0 37 figure 17. disable ckoutn structure the sfout [1:0] pins can also be used to disable both outputs. disabling the output puts the ckoutn+ and ckoutn? pins in a high-impedance state relative to v dd (common mode tri-state) while the two outputs remain connected to each other through a 200 ? on-chip resistance (differential impedance of 200 ? ). the maximum amount of internal circuitry is powered down, minimizi ng power consumption and noise generation. recovery from the disable mode requires additional time as specified in table 3, ?ac characteristics?. sfout[1:0] = lm (output disable) 100 100 + ? ? ckoutn output from dspll
si5315 38 rev. 1.0 7. crystal/reference clock input the device can use an external crystal or external clock as a reference. if an external clock is used, it must be ac coupled. with appropriate buffers, the same external reference clock can be applied to ckinn. although the reference clock input can be driven single ended (see fi gure 18), the best performance is with a crystal or low jitter, differential clock source. no external loadin g capacitors are required for normal crystal operation. figure 18. cmos external reference circuit figure 19. sinewave external reference clock input example figure 20. differential external reference clock input example 3.3 v cmos buffer, 8 ma output current 3.3 v 130 ? 150 ? 150 ? xa 10 k ? 0.1 ? f 0.6 v 0.1 ? f xb si5315 for 2.5 v operation, change 130 ? to 82 ? . external clock source 50 ? 0.01 ? f 1.2 v 0.6 v 10 pf si5315 10 k ? xa 0 dbm into 50 ? 0.01 ? f xb 0.1 f lvpecl, cml, etc. 0.01 ? f 1.2 v 0.6 v si5315 xa ? xb 10 k ? 100 0.01 ? f 10 k ?
si5315 rev. 1.0 39 7.1. crystal/reference clock selection the si5315 requires either a low-jitter ex ternal oscillator or a low-cost fundam ental mode crystal to be connected to its xa/xb pins. this serves both as a jitter reference for jitter attenuation and as a re ference oscillator for stability during holdover. the frequency the reference is not dire ctly related to either the input or the output clock frequencies. the range of the reference frequency is from 37 to 41 mhz. for recommendations on the selection of the reference frequency and a list of approved crystals, see the application note an591 which can be downloaded from www.silabs.com/timing/. in holdover, the dspll remains locked to this external reference. any changes in the frequency of this reference when the dspll is in holdover will be tr acked by the output of the device. note that crysta ls can have temperature sensitivities. table 18 shows how the xtal/clock pin is used to select between a crystal and an external oscillator. because the crystal is used as a jitter reference, rapid ch anges of the crystal temperature can temporarily disturb the output phase and frequency. for exam ple, it is recommended that the crystal not be placed close to a fan that is being turned off and on. if a situation such as this is unavoidable, the crystal should be thermally isolated with an insulating cover. 7.1.1. reference drift during holdover, long-term and temperature related drift of the reference input result in a one-to-one drift of the output frequency. that is, the stability of the any-frequency ou tput is identical to the dr ift of the reference frequency. this means that for the most demandin g applications where the drift of a crystal is not acceptable, an external temperature compensated or ovenized oscillator will be required. drift is not an issue unless the part is in holdover. also, the initial accuracy of the reference oscillator (or crystal) is not relevant. table 18. xa/xb reference sources xtal/clock type m 37?41 mhz external clock l 40 mhz crystal
si5315 40 rev. 1.0 7.1.2. reference jitter jitter on the reference input has a roughly one-to-one tr ansfer function to the output jitter over the bandwidth ranging from 100 hz up to 30 khz. if a crystal is used on the xa/xb pins, the reference will have low jitter if a suitable crystal is in use. if the xa/xb pins are connecte d to an external reference oscillator, the jitter of the external reference oscillator may contribut e significantly to the output jitter. a typical reference input-to-output jit ter transfer function is shown in figure 21. figure 21. typical xa/xb reference jitter transfer function -30 -25 -20 -15 -10 -5 0 5 1 10 100 1000 10000 100000 1000000 jitter frequency (hz) jitter transfer xa/xb reference to ckout 38.88 mhz xo, 38.88 mhz ckin, 38.88 mhz ckout jitter transfer (db)
si5315 rev. 1.0 41 8. power supply filtering this device incorporates an on-chip voltage regulator with excellent psrr to power the device from a supply voltage of 1.8, 2.5, or 3.3 v. the dev ice requires minimal supply decoupling and no stringent layout or ground plane islands. internal core circuitry is driv en from the output of this regulator while i/o circuitry uses the external supply voltage directly. table 3, ?ac characterist ics? gives the sensitivity of the on-ch ip oscillator to ch anges in the supply voltage. refer to the si5315 evaluation board for an example. the center ground pad under the device must be electrically and thermally connected to the ground plane. see figure 26, ?ground pad recommended layout,? on page 50. figure 22. typical power supply bypass network figure 23. fout = 155 mhz with 112 hz loop bandwidth, 100 mvp-p supply noise si5315 v dd gnd & gnd pad c 1 ? c 3 c 4 ferrite bead 0.1 uf 1.0 uf system power supply (1.8, 2.5, or 3.3 v) -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 1 10 100 1000 frequency of power supply noise (khz) power supply noise to output transfer function power supply noise rejection ratio (db)
si5315 42 rev. 1.0 9. typical phase noise plots the following is a typical phase noise plot. the clock input source was a rohde and schwarz model sml03 rf generator. the spectrum analyzer was either an agilent model e5052b, model e4400a or model js-500. the si5315 operates at 3.3 v with an ac coupled differential pecl output and an ac coupled differential sine wave input from the rf generator at 0 dbm. note that, as with any pll, the output jitter that is below the loop bw is caused by the jitter at the input clock, not the si5315. except as noted, loop bws of 60 to 240 hz were in use. 9.1. 10g lan synce example frequency plan fin=19.44 mhz fout=156.25 mhz bw=167 hz fin=19.44 mhz fout=125 mhz bw=111 hz fin=25 mhz fout=156.25 mhz bw=111 hz fin=25 mhz fout=125 mhz bw=111 hz jitter integration filter band rms jitter (fs) ieee802.3 (1.875 to 20 mhz) 232 240 251 240 sonet oc-192 (20 khz to 80 mhz) 483 575 525 550 sonet oc-192 (4 to 80 mhz) 302 303 300 294 sonet oc-192 (50 khz to 80 mhz) 467 564 510 537 sonet oc-48 (12 khz to 20 mhz) 470 565 517 541 sonet oc-3 (12 khz to 5 mhz) 422 524 471 503 broadband (800 hz to 80 mhz) 511 584 533 557 \ 180 \ 160 \ 140 \ 120 \ 100 \ 80 \ 60 \ 40 \ 20 0 100 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 si5315 ? typical ? phase ? noise ? fin=19.44 ? mhz; fout=125 ? mhz; bw=111 ? hz fin=19.44 ? mhz fout=156.25 ? mhz bw=167 ? hz fin=25 ? mhz fout=125 ? mhz bw=111 ? hz fin=25 ? mhz fout=156.25 ? mhz bw=111 ? hz
si5315 rev. 1.0 43 10. pin descriptions: si5315 pin assignments are preliminary and subject to change. table 19. si5315 pin descriptions pin # pin name i/o signal level description 1 rst ilvcmos external reset. active low input that performs external hardware reset of device. resets all internal lo gic to a known state. clock out- puts are tristated during reset. after rising edge of rst sig- nal, the si5315 will pe rform an internal se lf-calibration when a valid input signal is present. this pin has a weak pull-up. 2 frqtbl i 3-level frequency table select. selects frequency table. (table 9 on page 20.) this pin has a weak pull-up and weak pull-down and defaults to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 3los1olvcmos ckin1 loss of signal. active high loss-of-signal indi cator for ckin1. once trig- gered, the alarm will remain acti ve until ckin1 is validated. 0 = ckin1 present 1 = los on ckin1 4los2olvcmos ckin2 loss of signal. active high loss-of-signal indi cator for ckin2. once trig- gered, the alarm will remain acti ve until ckin2 is validated. 0 = ckin2 present 1 = los on ckin2 1 2 3 29 30 31 32 33 34 35 36 20 21 22 23 24 25 26 27 10 11 12 13 14 15 16 17 4 5 6 7 8 frqtbl autosel rst los2 los1 gnd vdd xa vdd xtal/clock ckin2+ ckin2? dbl2_by gnd ckin1+ ckin1? cs_ca bwsel0 bwsel1 frqsel1 frqsel2 frqsel3 ckout1? sfout1 gnd vdd sfout0 ckout2? ckout2+ nc gnd pad frqsel0 gnd 9 18 19 28 xb lol gnd ckout1+
si5315 44 rev. 1.0 5, 10, 32 v dd v dd supply supply. the device operates from a 1.8, 2.5, or 3.3 v supply. bypass capacitors should be asso ciated with the following v dd pins: 5 0.1 f 10 0.1 f 32 0.1 f a 1.0 f should also be placed as close to device as is prac- tical. 7 6 xb xa ianalog external crystal or reference clock. external crystal should be connected to these pins to use internal oscillator based reference. crystal or reference clock selection is set by the xtal/clock pin. 8, 15,19, 20,31 gnd gnd supply ground. must be connected to system ground. minimize the ground path impedance for optimal performance of this device. 9 autosel i 3-level manual/automatic clock selection. three level input that selects the method of input clock selec- tion to be used. l = manual m = automatic non-revertive h = automatic revertive this pin has a weak pull-up and weak pull-down and defaults to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 11 xtal/clock i 3-level external crystal or reference clock rate. three level input that selects the type and rate of external crystal or reference clock to be applied to the xa/xb port. this pin has both a weak pull-up and a weak pull-down and defaults to m. l = crystal m = clock (default) h = reserved some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 12 13 ckin2+ ckin2? i clock input 2. differential input clock. this in put can also be driven with a single-ended signal. input frequency selected from a table of values. the same frequency must be applied to ckin1 and ckin2. table 19. si5315 pin descriptions (continued) pin # pin name i/o signal level description
si5315 rev. 1.0 45 14 dbl2_by i 3-level output 2 disable/bypass mode control. controls enable of ckout2 di vider/output buffer path and pll bypass mode. l = ckout2 enabled m = ckout2 disabled h = bypass mode with ckout2 enabled. bypass mode is not supported with cmos clock outputs (sfout = lh). this pin has a weak pull-up and weak pull-down and defaults to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 16 17 ckin1+ ckin1? imulti clock input 1. differential input clock. this in put can also be driven with a single-ended signal. input frequency selected from a table of values. the same frequency must be applied to ckin1 and ckin2. 18 lol o lvcmos pll loss of lock indicator. this pin functions as the active high pll loss of lock indica- tor. 0 = pll locked 1 = pll unlocked 21 cs_ca i/o lvcmos input clock select/active clock indicator. input : if manual clock selection mode is chosen (autosel = l), this pin functions as the manual input clock selector. this inpu t is internally deglitched to prevent inadvertent clock switching during changes in the cs input state. 0 = select ckin1 1 = select ckin2 if configured as input, must be set high or low. output : if automatic clock selection mode is chosen (autosel = m or h), this pin indicates which of the two input clocks is currently the active clock. if alarms exist on both ckin1 and ckin2, indicating that the holdover state has been entered, ca will indicate the last active clock that was used before entering the hold state. 0 = ckin1 active input clock 1 = ckin2 active input clock 23 22 bwsel1 bwsel0 i3-level loop bandwidth select. three level inputs that select the dspll closed loop band- width. see table 9 on page 20 for available settings. these pins have both weak pull-ups and weak pull-downs and default to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. table 19. si5315 pin descriptions (continued) pin # pin name i/o signal level description
si5315 46 rev. 1.0 27 26 25 24 frqsel3 frqsel2 frqsel1 frqsel0 i3-level frequency select. three level inputs th at select the input clock and clock multi- plication ratio, depending on the frqtbl setting. these pins have both weak pull-ups and weak pull-downs and default to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 29 28 ckout1? ckout1+ omulti clock output 1. differential output clock with a frequency selected from a table of values. output signal format is selected by sfout pins. output is differential for lvpecl, lvds, and cml com- patible modes. for cmos format, both output pins drive identical single-ended clock outputs. 33 30 sfout0 sfout1 i3-level signal format select. three level inputs that select the output signal format (com- mon mode voltage and differential swing) for both ckout1 and ckout2. these pins have both weak pull-ups and weak pull-downs and default to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 34 35 ckout2? ckout2+ omulti clock output 2. differential output clock with a frequency selected from a table of values. output signal format is selected by sfout pins. output is differential for lvpecl, lvds, and cml com- patible modes. for cmos format, both output pins drive identical single-ended clock outputs. 36 nc ? ? no connect. leave floating. make no external connections to this pin for normal operation. gnd pad gnd gnd supply ground pad. the ground pad must provide a low thermal and electrical impedance to a ground plane. table 19. si5315 pin descriptions (continued) pin # pin name i/o signal level description sfout[1:0] signal format hh reserved hm lvds hl cml mh lvpecl mm reserved ml lvds?low swing lh cmos lm disable ll reserved
si5315 rev. 1.0 47 table 20. si5315 pull-up/pull-down pin # si5315 pull 1r s t u 2frqtblu, d 9 autosel u, d 11 xtal/ clock u, d 14 dbl2_by u, d 21 cs_ca u, d 22 bwsel0 u, d 23 bwsel1 u, d 24 frqsel0 u, d 25 frqsel1 u, d 26 frqsel2 u, d 27 frqsel3 u, d 30 sfout1 u, d 33 sfout0 u, d
si5315 48 rev. 1.0 11. ordering guide ordering part number output clock freq range pkg rohs6, pb-free temp range si5315a-c-gm 8 khz?644.53 mhz 36-lead 6x6 mm qfn yes ?40 to 85 c SI5315B-C-GM 8 khz?125 mhz 36-lead 6x6 mm qfn yes ?40 to 85 c si5315-evb 8 khz?644.53 mhz evaluation board note: add an ?r? at the end of the device to denote tape and reel options (i.e., si5315a-c-gmr).
si5315 rev. 1.0 49 12. package out line: 36-pin qfn figure 24 illustrates the package details for the si5315. table 21 lists the valu es for the dimensions shown in the illustration. figure 24. 36-pin quad flat no-lead (qfn) table 21. package dimensions symbol millimeters sy mbol millimeters min nom max min nom max a 0.80 0.85 0.90 l 0.50 0.60 0.70 a1 0.00 0.02 0.05 ? ??12o b 0.18 0.25 0.30 aaa ? ? 0.10 d 6.00 bsc bbb ? ? 0.10 d2 3.95 4.10 4.25 ccc ? ? 0.08 e 0.50 bsc ddd ? ? 0.10 e 6.00 bsc eee ? ? 0.05 e2 3.95 4.10 4.25 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jede c outline mo-220, variation vjjd. 4. recommended card reflow profile is per the je dec/ipc j-std-020 specif ication for small body components. ?
si5315 50 rev. 1.0 13. pcb land pattern figure 25 illustrates the pcb land pattern for the si5315. figure 26 illu strates the recomme nded ground pad layout. table 22 lists the land pattern dimensions. figure 25. pcb land pattern figure 26. ground pad recommended layout
si5315 rev. 1.0 51 table 22. pcb land pattern dimensions dimension min max e 0.50 bsc. e5 . 4 2 r e f . d5 . 4 2 r e f . e2 4.00 4.20 d2 4.00 4.20 ge 4.53 ? gd 4.53 ? x ? 0.28 y0 . 8 9 r e f . ze ? 6.31 zd ? 6.31 notes (general): 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimensions shown are at maximum ma terial condition (mmc ). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. notes (solder mask design): 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes (stenc il design): 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. notes (card assembly): 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-02 0 specification for small body components.
si5315 52 rev. 1.0 14. top marking 14.1. si5315 top marking (qfn) 14.2. top marking explanation mark method: laser font size: 0.80 mm right-justified line 1 marking: si5315q customer part number q = speed code: a, b see ordering guide for options. line 2 marking: c-gm c = product revision g = temperature range ?40 to 85 c (rohs6) m = qfn package line 3 marking: yywwrf yy = year ww = work week r = die revision f = internal code assigned by the assembly house. corresponds to the year and work week of the mold date. line 4 marking: pin 1 identifier circle = 0.75 mm diameter lower-left justified xxxx internal code ? ?
si5315 rev. 1.0 53 d ocument c hange l ist revision 0.1 to revision 0.2 ? expanded/added numerous operating sections to initial data sheet revision 0.2 to revision 0.25 ? updated features and application list ? updated section 1. "ele ctrical specifications? ? added voltage regulator block to figure 7 ? revised footnotes in table 9 ? removed plan #203 from table 9 ? removed figure 17. crystal oscillator with feedback resistor diagram from section 7. "crystal/reference clock input? ? added xa/xb jitter transfer plot to section 7. "crystal/reference clock input? ? added psrr transfer function plot to section 8. "power supply filtering? ? updated typical phase noise plot and rms jitter table in section 9. "typical phase noise plots? revision 0.25 to revision 0.26 ? corrected section 11. "ordering guide? output clock frequency range for SI5315B-C-GM to 8 khz?125 mhz. revision 0.26 to revision 1.0 ? updated table 2 on page 4. ? updated table 3 on page 8. ? updated table 7 on page 13. ? moved ?typical application circuit? to page 14. ? added reference to an591. ? bypass mode not supported with cmos outputs. ? changed g.8262 compliance language. ? added frequency plans 103, 129, and 130.
si5315 54 rev. 1.0 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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