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| toshiba original cmos 16-bit microcontroller tlcs-900/l1 series tmp91c630 semiconductor company
preface thank you very much for making us e of toshiba microcomputer lsis. before use this lsi, refer the section, ?points of note and restrictions?. especially, take care below cautions. tmp91c630 2005-11-15 91c630-1 cmos 16-bit microcontrollers TMP91C630F 1. outline and features tmp91c630 is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment. with 2 kbytes of boot rom included, it allows your programs to be erased and rewritten on board. tmp91c630 comes in a 100-pin flat pack age. listed below are the features. (1) high-speed 16-bit cpu (900/l1 cpu) ? instruction mnemonics are upward-compatible with tlcs-90/900 ? 16 mbytes of linear address space ? general-purpose registers and register banks ? 16-bit multiplication and division instructions; bit transfer and arithmetic instructions ? micro dma: four-channels (444 ns/2 bytes at 36 mhz) (2) minimum instruction execution time: 111 ns (at 36 mhz) (3) built-in ram: 6 kbytes built-in rom: none built-in boot rom: 2 kbytes tmp91c630 2005-11-15 91c630-2 (4) external memory expansion ? expandable up to 16 mbytes (shared program/data area) ? can simultaneously support 8-/16- bit width external data bus ? ? ? dynamic data bus sizing (5) 8-bit timers: 6 channels ? event counter :2 channels (6) 16-bit timer/event counter: 1 channel (7) serial bus interface: 2 channels (8) 10-bit ad converter: 8 channels (9) watchdog timer (10) chip select/wait controller: 4 blocks (11) interrupts: 35 interrupts ? 9 cpu interrupts: software interrupt instruction and illegal instruction ? 19 internal interrupts: 7 priority levels are selectable. ? 7 external interrupts: 7 priority levels are selectable. (level mode, rising edge mode and falling edge mode are selectable.) (12) input/output ports: 53 pins (13) standby function three halt modes: idle2 (programmable), idle1, stop (14) operating voltage ? vcc = 2.7 v to 3.6 v (fc max = 36 mhz) (15) package ? 100-pin qfp: p-lqfp100-1414-0.50f tmp91c630 2005-11-15 91c630-3 adtrg (an3/pa3) an0~an7 (pa0~pa7) vrefh vrefl avcc avss rd wr pz2 ( hwr ) pz3 txd0 (p80) rxd0 (p81) sclk0/ cts0 (p82) 0 sts (p83) txd1 (p84) rxd1 (p85) sck1/ 1 cts (p86) 1 sts (p87) ta0in/int1 (p70) ta1out (p71) ta3out/int2 (p72) ta4in/int3 (p73) ta5out (p74) int4 (p75) dvcc [4] dvss [4] boot a m0/am1 reset x1 x2 emu0 emu1 (p10~p17) d8~d15 (p20~p27) a16~a23 d0~d7 a 0~a7 a 8~a15 busrq (p53) busak (p54) wait (p55) cs0 (p60) cs1 (p61) cs2 (p62) 3 cs (p63) nmi int0 (p56) tb0in0 (p93) tb0in1 (p94) tb0out0 (p95) tb0out1 (p96) int5 (p90) 10-bit 8-channel ad converter port a 8-bit timer (tmra0) port z 8-bit timer (tmra1) 8-bit timer (tmra2) 8-bit timer (tmra3) serial i/o (channel 0) osc clock gear port 1 cs/wait controller (4-block) address bus interrupt controller 16-bit timer (tmrb0) data bus port 9 6-kb ram watchdog timer (wdt) xwa xbc xde xhl xix xiy xiz xsp w a b c d e h l ix iy iz sp 32 bits sr pc f cpu (tlcs-900l1) port 2 2-kb boot rom port 5 serial i/o (channel 1) port 8 8-bit timer (tmra4) 8-bit timer (tmra5) port 7 figure 1.1 tmp91c630 block diagram tmp91c630 2005-11-15 91c630-4 2. pin assignment and pin functions the pin assignment and pin functions of the TMP91C630F are showed in figure 2.1.1. 2.1 pin assignment diagram figure 2.1.1 shows the pin assignment of the TMP91C630F. pin pin name pin name pin no. no. 63 dvcc p27/a23 64 62 boot p26/a22 65 61 dvss p25/a21 66 60 p17/d15 p24/a20 67 59 p16/d14 p23/a19 68 58 p15/d13 p22/a18 69 57 p14/d12 p21/a17 70 56 p13/d11 p20/a16 71 55 p12/d10 a15 72 54 p11/d9 a14 73 53 p10/d8 a13 74 52 d7 a12 75 51 d6 a11 76 50 d5 a10 77 49 d4 a9 78 48 d3 a8 79 47 d2 a7 80 46 d1 a6 81 45 d0 a5 82 44 p96/tb0out1 a4 83 43 p95/tb0out0 a3 84 42 p94/tb0in1 a2 85 41 p93/tb0in0 a1 86 40 p90/int5 a0 87 39 p75/int4 rd 88 38 p74/ta5out wr 89 37 p73/ta4in/int3 dvcc 90 36 p72/ta3out/int2 pz2/ hwr 91 35 p71/ta1out dvss 92 34 p70/ta0in/int1 pa0/an0 93 33 reset pa1/an1 94 32 am1 pa2/an2 95 31 x1 pa3/an3/ adtrg 96 30 dvss pa4/an4 97 29 x2 pa5/an5 98 28 dvcc pa6/an6 99 27 am0 pa7/an7 100 26 p63/ cs3 vrefh 1 25 p62/ cs2 vrefl 2 24 p61/ cs1 avss 3 23 p60/ cs0 avcc 4 22 emu1 nmi 5 21 emu0 dvss 6 20 p87/ 1 sts p53/ busrq 7 19 p86/sclk1/ 1 cts dvcc 8 18 p85/rxd1 p54/ busak 9 17 p84/txd1 p55/ wait 10 16 p83/ 0 sts p56/int0 11 15 p82/sclk0/ 0 cts pz3 12 14 p81/rxd0 p80/txd0 13 figure 2.1.1 pin assignment diagram (100-pin lqfp) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 p-lqfp100-1414-0.50f TMP91C630F to p view tmp91c630 2005-11-15 91c630-5 2.2 pin names and functions the names of the input/output pins and their functions are described below. table 2.2.1 to table 2.2.3 show pin name and functions. table 2.2.1 pin names and functions (1/3) pin names number of pins i/o functions d0 to d7 8 i/o data (lower): bits 0 to 7 of data bus p10 to p17 d8 to d15 8 i/o i/o port 1: i/o port that allows i/o to be selected at the bit level (when used to the external 8-bit bus) data (upper): bits 8 to15 of data bus p20 to p27 a16 to a23 8 output output port 2: output port address: bits 16 to 23 of address bus a8 to a15 8 output address: bits 8 to 15 of address bus a0 to a7 8 output address: bits 0 to 7 of address bus rd 1 output read: strobe signal for reading external memory wr 1 output write: strobe signal for writing data to pins d0 to d7 p53 busrq 1 i/o input port 53: i/o port (with pull-up resistor) bus request: signal used to reques t bus release (high-impedance). p54 busak 1 i/o output port 54: i/o port (with pull-up resistor) bus acknowledge: signal used to acknowledge bus release (high-impedance). p55 wait 1 i/o input port 55: i/o port (with pull-up resistor) wait: pin used to request cpu bus wait. ((1 + n) waits mode) p56 int0 1 i/o input port 56: i/o port (with pull-up resistor) interrupt request pin0: interrupt reques t pin with programmable level/rising edge/falling edge p60 cs0 1 output output port 60: output port chip select 0: outputs 0 when address is within specified address area. p61 cs1 1 output output port 61: output port chip select 1: outputs 0 when address is within specified address area. p62 cs2 1 output output port 62: output port chip select 2: outputs 0 when address is within specified address area. p63 3 cs 1 output output port 63: output port chip select 3: outputs 0 when address is within specified address area. p70 ta0in int1 1 i/o input input port 70: i/o port 8-bit tmra0 input interrupt request pin 2: interrupt reques t pin with programmable level/rising edge/falling edge p71 ta1out 1 i/o output port 71: i/o port 8-bit tmra0 or 8-bit tmra1 output p72 ta3out int2 1 i/o output input port 72: i/o port 8-bit tmra2 or 8-bit tmra3 output interrupt request pin 2: interrupt reques t pin with programmable level/rising edge/falling edge tmp91c630 2005-11-15 91c630-6 table 2.2.2 pin names and functions (2/3) pin names number of pins i/o functions p73 ta4in int3 1 i/o input input port 73: i/o port 8-bit tmra4 input interrupt request pin 3: interrupt reques t pin with programmable level/rising edge/falling edge. p74 ta5out 1 i/o output port 74: i/o port 8-bit tmra4 or 8-bit tmra5 output p75 int4 1 i/o input port 75: i/o port interrupt request pin 4: interrupt request pin with programmable p80 txd0 1 i/o output port 80: i/o port (with pull-up resistor) serial send data 0: programmable open-drain output pin p81 rxd0 1 i/o input port 81: i/o port (with pull-up resistor) serial receive data 0 p82 sclk0 cts0 1 i/o input i/o port 82: i/o port (with pull-up resistor) serial clock i/o 0 serial data send enable 0 (clear to send) p83 0 sts 1 i/o port 83: i/o port (with pull-up resistor) serial data request signal 0 p84 txd1 1 i/o output port 84: i/o port (with pull-up resistor) serial send data 0: programmable open-drain output pin p85 rxd1 1 i/o input port 85: i/o port (with pull-up resistor) serial receive data 1 p86 sclk1 cts1 1 i/o input i/o port 86: i/o port (with pull-up resistor) serial clock i/o 1 serial data send enable 1 (clear to send) p87 1 sts 1 i/o port 87: i/o port (with pull-up resistor) serial data request signal 1 p90 int5 1 i/o input port 90: i/o port interrupt request pin 5: interrupt reques t pin with programmable level/rising edge/falling edge p93 tb0in0 1 i/o input port 93: i/o port timer b0 input 0 p94 tb0in1 1 i/o input port 94: i/o port timer b0 input 1 p95 tb0out0 1 i/o output port 95: i/o port timer b0 output 0 p96 tb0out1 1 i/o output port 96: i/o port timer b0 output 1 pa0 to pa7 an0 to an7 adtrg 8 input input input port a0 to a7: pins used to input port. analog input 0 to 7: pins used to input to ad converter. ad trigger: signal used to request ad start (pa3). pz2 hwr 1 i/o output port z2: i/o port (with pull-up resistor) high write: strobe signal for writing data to pins d8 to d15 pz3 1 i/o port z3: i/o port (with pull-up resistor) tmp91c630 2005-11-15 91c630-7 table 2.2.3 pin names and functions (3/3) pin names number of pins i/o functions boot 1 input this pin sets boot mode (with pull-up resistor) nmi 1 input non-maskable interrupt request pin: interrupt request pin with programmable falling edge level or with both edge levels programmable am0 to am1 2 input operation mode: am1 = 0 and am0 = 1: external 16-bit bus is fixed or external 8-/16-bit buses are mixed. am1 = 0 and am0 = 0: external 8-bit bus is fixed. reset 1 input reset: initializes TMP91C630F (with pull-up resistor) vrefh 1 input pin for reference voltage input to ad converter (h) vrefl 1 input pin for reference voltage input to ad converter (l) avcc 1 i/o power supply pin for ad converter avss 1 gnd supply pin for ad converter x1/x2 2 oscillator connection pins dvcc 4 power supply pins dvss 4 gnd pins (0 v) emu0 1 output open pin emu1 1 output open pin note 1: an external dma controller cannot access t he device?s built-in memory or built-in i/o devices using the busrq and busak signals. tmp91c630 2005-11-15 91c630-8 3. operation this section describes the bas ic components, functions and operation of the tmp91c630. notes and restrictions which apply to the various items described here are outlined in section 7. precautions and restrictions at the end of this databook. 3.1 cpu the tmp91c630 incorporates a high-perform ance 16-bit cpu (the 900/l1 cpu). for a description of this cpu?s operatio n, please refer to the section of this databook which describes the tlcs-900/l1 cpu. the following sub-sections describe functions peculiar to the cpu used in the tmp91c630; these functions are not covered in the section devoted to the tlcs-900/l1 cpu. 3.1.1 reset when resetting the tmp91c630 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. then set the reset input to low level at least for 10 system clocks (8.89 s at 36 mhz). thus, when turn on the switch, be set to th e power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. then hold the reset input to low level at least for 10 system clocks. clock gear is initialized 1/16 mode by reset operation. it means that the system clock mode f sys is set to fc/32 ( = fc/16 1/2). when the reset has been accepted, the cpu performs the following: ? sets the program counter (pc) as follows in accordance with the reset vector stored at address ffff00h to ffff02h: pc<0:7> data in location ffff00h pc<8:15> data in location ffff01h pc<16:23> data in location ffff02h ? sets the stack pointer (xsp) to 100h. ? sets bits tmp91c630 2005-11-15 91c630-9 figure 3.1.1 shows the timing of a reset for the tmp91c630. read write f fph a23 to a0 data-in d0 to d15 d0 to d15 sampling (after reset released, startting 2 waits read cycle) note: pull-up (internal) high-z sampling 0ffff00h data-in d ata-in cs0 , cs1 , cs3 (pz2 input mode) reset cs2 rd w r hw r figure 3.1.1 tmp91c630 reset timing example tmp91c630 2005-11-15 91c630-10 3.2 outline of operation modes there are multi-chip and multi-boot modes. which mode is selected depends on the device?s pin state after a reset. ? multi-chip mode: the device normally operations in this mode. after a reset, the device starts executing the external memory program. ? multi-boot mode: this mode is used to rewrite the external flash memory by serial transfer (uart). after a reset, internal boot program starts up, executing an on-board rewrite program. table 3.2.1 operation mode setup table mode setup input pin operation mode reset boot multi-chip mode h multi-boot mode l tmp91c630 2005-11-15 91c630-11 3.3 memory map figure 3.3.1 is a memory map of the tmp91c630. multi-chip mode multi-boot mode 000000h 000100h internal i/o (4 kbytes) 000000h 000100h internal i/o (4 kbytes) direct area (n) 001000h internal ram (6 kbytes) 001000h internal ram (6 kbytes) 002800h external memory 002800h 01f800h 16-mbyte area 01ffffh internal boot rom (2 kbytes) (r32) ( ? r32) external memory external memory (r32 + ) (r32 + d8/16) (r32 + r8/16) (nnn) fff800h fffeffh internal boot rom (2 kbytes) ffff00h ffffffh vector table (256 bytes) ffff00h ffffffh vector table (256 bytes) ( = internal area) figure 3.3.1 tmp91c630 memory map tmp91c630 2005-11-15 91c630-169 4. electrical characteristics 4.1 maximum ratings parameter symbol rating unit power supply voltage vcc ? 0.5 to 4.0 v input voltage vin ? 0.5 to vcc + 0.5 v output current (per pin) iol 2 ma output current (per pin) ioh ? 2 ma output current (total) iol 80 ma output current (total) ioh ? 80 ma power dissipation (ta = 85c) pd 600 mw soldering temperature (10 s) tsolder 260 c storage temperature tstg ? 65 to 150 c operating temperature topr ? 40 to 85 c note: the maximum ratings are rated values which must not be exceeded during operation, even for an instant. any one of the ratings must not be exce eded. if any maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. thus, when designing products which include this device, ensure that no maximum rating value will ever be exceeded. 4.2 dc characteristics (1/2) parameter symbol condition min typ. (note) max unit power supply voltage (avcc = dvcc) (avss = dvss = 0 v) vcc fc = 10 mhz to 36 mhz 2.7 3.6 v d0 to d7, p10 to p17 (d8 to d15) v il vcc = 2.7 v to 3.6 v 0.6 the other ports v il1 vcc = 2.7 v to 3.6 v 0.3 vcc reset , nmi , boot p56 (int0), p70 (int1) p72 (int2), p73 (int3) p75 (int4), p90 (int5) v il2 vcc = 2.7 v to 3.6 v ? 0.3 0.25 vcc am0, 1 v il3 vcc = 2.7 v to 3.6 v 0.3 input low voltage x1 v il4 vcc = 2.7 v to 3.6 v 0.2 vcc d0 to d7, p10 to p17 (d8 to d15) v ih vcc = 2.7 v to 3.6 v 2.0 the other ports v ih1 vcc = 2.7 v to 3.6 v 0.7 vcc reset , nmi , boot p56 (int0), p70 (int1) p72 (int2), p73 (int3) p75 (int4), p90 (int5) v ih2 vcc = 2.7 v to 3.6 v 0.75 vcc am0, 1 v ih3 vcc = 2.7 v to 3.6 v vcc ? 0.3 input high voltage x1 v ih4 vcc = 2.7 v to 3.6 v 0.8 vcc vcc + 0.3 v output low voltage v ol iol = 1.6 ma 0.45 output high voltage v oh ioh = ? 400 a 2.4 v note: typical measurement condition is ta = 25c, vcc = 3.0 v unless otherwise noted. tmp91c630 2005-11-15 91c630-170 dc characteristics (2/2) parameter symbol min typ. (note 1) max condition unit input leakage current ili 0.02 5 0.0 v in vcc output leakage current ilo 0.05 10 0.2 v in vcc ? 0.2 a power down voltage (at stop, ram back-up) vstop 2.0 3.6 v il2 = 0.2 vcc, v ih2 = 0.8 vcc v reset pull-up resistor rrst 80 400 vcc = 2.7 v to 3.6 v k boot pull-up resistor rbt 80 400 vcc = 2.7 v to 3.6 v k pin capacitance cio 10 fc = 1 mhz pf schmitt width reset , nmi , boot , int0 to 5 vth 0.4 1.0 vcc = 2.7 v to 3.6 v v programmable pull-up resistor rkh 80 400 vcc = 2.7 v to 3.6 v k normal (note 2): (note 3) 17 25 idle2 (note 3) 4 8 idle1 (note 3) 1.5 3.5 vcc = 2.7 v to 3.6 v fc = 36 mhz ma stop icc 0.1 10 vcc = 2.7 v to 3.6 v a note 1: typical measurement condition is ta = 25c, vcc = 3.0 v unless otherwise noted. note 2: icc measurement conditions (normal): all functions operate; output pins are open and input pins are fixed. note 3: power supply current from avcc pin is incl uded in power supply current (icc) of dvcc pin. tmp91c630 2005-11-15 91c630-171 4.3 ac characteristics (1) vcc = 2.7 to 3.6 v variable f fph = 36 mhz no. parameter symbol min max min max unit 1 f fph period ( = x ) t fph 27.6 100 27.6 ns 2 a0 to 23 valid rd / wr fall t ac x ? 26 1.6 ns 3 rd rise a0 to a23 hold t car 0.5x ? 13.8 0.0 ns 4 wr rise a0 to a23 hold t caw x ? 13 14.6 ns 5 a0 to a23 valid d0 to d15 input t ad 3.5x ? 40 56.6 ns 6 rd fall d0 to d15 input t rd 2.5x ? 34 35.0 ns 7 rd low width t rr 2.5x ? 25 44.0 ns 8 rd rise d0 to d15 hold t hr 0 0 ns 9 wr low width t ww 2.0x ? 25 30.2 ns 10 d0 to d15 valid wr rise t dw 1.5x ? 35 6.4 ns 11 wr rise d0 to d15 hold (1 + n) waits mode t wd x ? 25 2.6 ns 12 a0 to a23 valid wait input (1 + n) waits mode t aw 3.5x ? 60 36.6 ns 13 rd / wr fall wait hold t cw 2.5x + 0 69.0 ns 14 a0 to a23 valid port input t aph 3.5x ? 76 20.6 ns 15 a0 to a23 valid port hold t aph2 3.5x 96.6 ns 16 a0 to a23 valid port valid t apo 3.5x + 60 156.6 ns ac measuring conditions ? output level : high = 0.7 vcc, low = 0.3 vcc, c l = 50 pf ? input level : high = 0.9 vcc, low = 0.1vcc note: symbol x in the above table means the period of clock f fph , it?s half period of the system clock f sys for cpu core. the period of f fph depends on the clock gear setting. tmp91c630 2005-11-15 91c630-172 (2) read cycle note: since the cpu accesses the internal area to r ead data from a port, the control signals of external pins such as rd and cs are not enabled. therefore, the above waveform diagram should be regarded as depicting internal operation. please also note that the timing and ac characteristics of port input/output shown above are typical representation. for details, contact your local toshiba sales representative. d0 to d15 t hr f fph a0 to a23 port input (note) rd d0 to d15 t fph t aw t ap t ad t ac t rr t car t cw t aph2 csn wait t rd tmp91c630 2005-11-15 91c630-173 (3) write cycle note: since the cpu accesses the internal area to writ e data to a port, the control signals of external pins such as wr and cs are not enabled. therefore, the above waveform diagram should be regarded as depicting internal operation. please also not e that the timing and ac characteristics of port input/output shown above are typica l representation. for details, contact your local toshiba sales representative. d0 to d15 t wd t apo t ww t dw f fph a0 to a23 port output (note) d0 to d15 wait csn t caw wr , hwr tmp91c630 2005-11-15 91c630-174 4.4 ad conversion characteristics avcc = dvcc, avss = dvss parameter symbol min typ. max unit analog reference voltage ( + ) vrefh vcc ? 0.2 v vcc vcc analog reference voltage ( ? ) vrefl v ss v ss vss + 0.2 v analog input voltage range vain v refl v refh v analog current for analog reference voltage tmp91c630 2005-11-15 91c630-175 4.5 serial channel timi ng (i/o internal mode) note: symbol x in the below table means the period of clock f fph , it?s half period of the system clock f sys for cpu core. the period of f fph depends on the clock gear setting. (1) sclk input mode variable 36 mhz (note) parameter symbol min max min max unit sclk period t scy 16x 0.44 s output data sclk rising/falling edge * t oss t scy /2 ? 4x ? 85 25 ns sclk rising/falling edge * output data hold t ohs t scy /2 + 2x + 0 276 ns sclk rising/falling edge * input data hold t hsr 3x + 10 92 ns sclk rising/falling edge * valid data input t srd t scy ? 0 440 ns valid data input sclk rising/falling edge * t rds 0 0 ns * ) sclk rinsing/falling edge: the rising edge is used in sclk rising mode. the falling edge is used in sclk falling mode. note: at t scy = 16x (2) sclk output mode variable 36 mhz (note) parameter symbol min max min max unit sclk period (programable) t scy 16x 8192x 0.44 s output data sclk rising/falling edge * t oss t scy /2 ? 40 180 ns sclk rising/falling edge * output data hold t ohs t scy /2 ? 40 180 ns sclk rising/falling edge * input data hold t hsr 0 0 ns sclk rising/falling edge * valid data input t srd t scy ? 1x ? 90 324 ns valid data input sclk rising/falling edge * t rds 1x + 90 117 ns * ) sclk rinsing/falling edge: the rising edge is used in sclk rising mode. the falling edge is used in sclk falling mode. note: at t scy = 16x t rds t srd t hsr t scy output data txd sclk sclk 0 t oss t ohs 1 3 0 1 3 2 2 valid input data rxd valid valid valid tmp91c630 2005-11-15 91c630-176 4.6 event counter (ta0in, ta4in, tb0in0, tb0in1) variable 36 mhz parameter symbol min max min max unit clock perild t vck 8x + 100 320 ns clock low level width t vckl 4x + 40 150 ns clock high level width t vckh 4x + 40 150 ns note: symbol x in the above table means the period of clock f fph , it?s half period of the system clock f sys for cpu core. the period of f fph depends on the clock gear setting. 4.7 interrupts note: symbol x in the above table means the period of clock f fph , it?s half period of the system clock f sys for cpu core. the period of f fph depends on the clock gear setting. (1) nmi , int0 to int5 interrupts variable 36 mhz parameter symbol min max min max unit nmi , int0 to int5 low level width t intal 4x + 40 150 ns nmi , int0 to int5 high level width t intah 4x + 40 150 ns tmp91c630 2005-11-15 91c630-177 4.8 bus request/bus acknowledge variable f fph = 36 mhz parameter symbol min max min max unit output buffer to busak low t aba 0 80 0 80 ns busak high to output buffer on t baa 0 80 0 80 ns note 1: even if the busrq signal goes low, the bus will not be released while the wait signal is low. the bus will only be released when busrq goes low while wait is high. note 2: this line shows only that t he output buffer is in the off state. it does not indicate that the signal level is fixed. just after the bus is released, the signal level set before the bus was released is maintained dynamically by the external capa citance. therefore, to fix the signal level using an external resister during bus release, careful design is necessary, since fixing of the level is delayed. the internal programmable pull-up/pull-down resistor is switched between the active and non-active states by the internal signal. busak a0 to a23, rd , wr cs0 to cs3 , hwr d0 to d15 t cbal t aba t baa (note 2) (note 2) (note 1) busrq |
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