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1 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 high performance v53c104d 60 70 80 max. ras access time, (t rac ) 60 ns 70 ns 80 ns max. column address access time, (t caa ) 30 ns 35 ns 40 ns min. fast page mode cycle time, (t pc ) 40 ns 45 ns 50 ns min. read/write cycle time, (t rc ) 120 ns 130 ns 150 ns v53c104d high performance, low power 256k x 4 bit fast page mode cmos dynamic ram preliminary features n 256k x 4 organization n ras access time: 60,70,80 ns n low power dissipation for v53c104d-80 ? operating current C 75 ma max. ? ttl standby current C 2.0 ma max. n low cmos standby current ? v53c104d C 1.0 ma max. n read-modify-write, ras-only refresh, cas -before- ras refresh capability. n common i/o capability n refresh interval ? v53c104d C 512 cycles/8ms n fast page mode for a sustained data rate greater than 25 mhz n standard packages are 20 pin plastic dip and 26/20 pin soj description the v53c104d is a high speed 262,144 x 4 bit cmos dynamic random access memory. the v53c104d offers a combination of features: fast page mode for high data bandwidth, fast usable speed, cmos standby current. all inputs and outputs are ttl compatible. input and output capacitances are significantly lowered to allow increased system performance. fast page mode operation allows random access of up to 512 (x4) bits within a row with cycle times as short as 40 ns. because of static circuitry, the cas clock is not in the critical timing path. the flow-through column address latches allow address pipelining while relax- ing many critical system timing requirements for fast usable speed. these features make the v53c104d ideally suited for graphics, digital signal processing and high performance computing systems device usage chart operating package outline access time (ns) power temperature temperature range p k 60 70 80 std. mark 0 c to 70 c ????? ? blank
2 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 20 lead plastic dip pin configuration top view 26/20 lead soj package pin configuration top view v family device p k (plastic dip) (soj) blank (0 c to 70 c) blank (normal) 60 (60 ns) 70 (70 ns) 80 (80 ns) low (low power) pkg. speed (t rac ) temp. pwr. 53c104d description pkg. pin count plastic dip p 20 soj k 26/20 we ras nc i/o 1 i/o 2 a 0 a 1 a 2 a 3 v dd 1 2 3 4 5 9 10 11 12 13 26 25 24 23 22 18 17 16 15 14 v i/o i/o cas oe a a a a a ss 4 3 8 7 6 5 4 v53c104dk we ras nc i/o 1 i/o 2 a 0 a 1 a 2 a 3 v dd 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v i/o i/o cas oe a a a a a ss 4 3 8 7 6 5 4 v53c104dp absolute maximum ratings* ambient temperature under bias ............................. C10 c to +80 c storage temperature (plastic) .... C55 c to +125 c voltage relative to v ss ...................... C1.0 v to +7.0 v voltage on v dd relative to v ss ....... C1.0 v to +7.0 v data output current .................................... 50 ma power dissipation ......................................... 1.0 w *note: operation above absolute maximum ratings can adversely affect device reliability. * note: capacitance is sampled and not 100% tested capacitance* t a = 25 c, v dd = 5 v 10%, v ss = 0 v symbol parameter typ. max. unit c in1 address input 6 pf c in2 ras , cas , we , oe 7 pf c out data input/output 6 pf pin names a 0 Ca 8 address inputs ras row address strobe cas column address strobe we write enable oe output enable i/o 1 Ci/o 4 data input, output v dd +5v supply v ss 0v supply nc no connect
3 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 block diagram a 0 a 1 a 7 a 8 sense amplifiers refresh counter v dd v ss 9 i/o 1 address buffers and predecoders x 0 -x row decoders 512 memory array column decoders data i/o bus y 0 -y 8 512 x 4 i/o buffer i/o 2 i/o 3 i/o 4 oe clock generator we clock generator cas clock generator ras clock generator oe we cas ras 8 256k x 4
4 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 dc and operating characteristics (1-2) t a = 0 c to 70 c, v dd = 5 v 10%, v ss = 0 v, unless otherwise specified. v53c104d symbol parameter time min. max. unit test conditions notes i li input leakage current C10 10 m av ss v in v dd (any input pin) i lo output leakage current C10 10 m av ss v out v dd (for high-z state) ras , cas at v ih 60 90 70 80 ma t rc = t rc (min.) 1, 2 80 75 i dd2 v dd supply current, ras , cas at v ih ttl standby .5 ma other inputs 3 v ss 60 90 i dd3 70 80 ma t rc = t rc (min.) 2 80 75 60 80 i dd4 70 70 ma minimum cycle 1, 2 80 65 i dd5 standby, output enabled 3.0 ma ras =v ih , cas =v il 1 other inputs 3 v ss i dd6 v dd supply current ras 3 v dd C0.2 v, cmos standby 50 m a cas 3 v dd -0.2 v other input 3 v ss v il input low voltage C1.0 0.8 v 3 v il input high voltage 2.4 v dd +1 v 3 v ol output low voltage 0.4 v i ol = 4.2 ma v oh output high voltage 2.4 v i oh = -5 ma access i dd1 v dd supply current, operating v dd supply current, fast page mode operation v dd supply current, ras -only refresh
5 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 ac characteristics t a = 0 c to 70 c, v dd = 5 v 10%, v ss = 0v unless otherwise noted ac test conditions, input pulse levels 0 to 3v 60 70 80 # symbol symbol parameter unit notes min. max. min. max. min. max. 1t rl1rh1 t ras ras pulse width 60 16k 70 16k 80 16k ns 2t rl2rl2 t rc read or write cycle time 110 130 150 ns 3t rh2rl2 t rp ras precharge time 40 50 60 ns 4t rl1ch1 t csh cas hold time 60 70 80 ns 5t cl1ch1 t cas cas pulse width 15 100k 20 100k 20 100k ns 6t rl1cl1 t rcd ras to cas delay 20 40 20 50 20 60 ns 4 7t wh2cl2 t rcs read command setup time 0 0 0 ns 8t avrl2 t asr row address setup time 0 0 0 ns 9t rl1ax t rah row address hold time 10 10 12 ns 10 t avcl2 t asc column address setup time 0 0 0 ns 11 t cl1ax t cah column address hold time 12 15 15 ns 12 t cl1rh1(r) t rsh (r) ras hold time (read cycle) 20 20 20 ns 13 t ch2rl2 t crp cas to ras precharge time 10 10 10 ns 14 t ch2wx t rch read command hold time 0 0 0 ns 5 referenced to cas 15 t rh2wx t rrh read command hold time 0 0 0 ns 5 referenced to ras 16 t oel1rh2 t roh ras hold time 15 15 20 ns referenced to oe 17 t gl1qv t oac access time from oe 15 15 20 ns 18 t cl1qv t cac access time from cas 20 20 20 ns 6,7 19 t rl1qv t rac access time from ras 60 70 80 ns 6,8,9 20 t avqv t caa access time from column 30 35 40 ns 6,7, address 10 jedec
6 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 ac characteristics (cont'd.) 60 70 80 # symbol symbol parameter unit notes min. max. min. max. min. max. 21 t cl1qx t lz oe or cas to low-z output 0 0 0 ns 16 22 t ch2qz t hz oe or cas to high-z output 0 15 0 15 0 20 ns 16 23 t rl1ax t ar column address hold time 50 55 60 ns from ras 24 t rl1av t rad ras to column address 15 30 15 35 17 40 ns 11 delay time 25 t cl1rh1(w) t rsh (w) ras or cas hold time 20 20 20 ns in write cycle 26 t wl1ch1 t cwl write command to cas 15 20 20 ns lead time 27 t wl1cl2 t wcs write command setup time 0 0 0 ns 12,13 28 t cl1wh1 t wch write command hold time 12 15 15 ns 29 t wl1wh1 t wp write pulse width 10 15 15 ns 30 t rl1wh1 t wcr write command hold time 50 55 60 ns from ras 31 t wl1rh1 t rwl write command to ras 15 20 20 ns lead time 32 t dvwl2 t ds data in setup time 0 0 0 ns 14 33 t wl1dx t dh data in hold time 12 15 15 ns 14 34 t wl1gl2 t woh write to oe hold time 15 20 20 ns 14 35 t gh2dx t oed oe to data delay time 15 15 20 ns 14 36 t rl2rl2 t rwc read-modify-write 160 185 205 ns (rmw) cycle time 37 t rl1rh1 t rasp ras pulse width 60 100k 70 100k 80 100k ns (fast page mode) 38 t cl1wl2 t cwd cas to we delay 45 45 50 ns 12 jedec
7 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 ac characteristics (cont'd.) 60 70 80 # symbol symbol parameter unit notes min. max. min. max. min. max. 39 t rl1wl2 t rwd ras to we delay in 90 100 110 ns 12 read-modify-write cycle 40 t cl1ch1 t crw cas pulse width (rmw) 60 65 70 ns 41 t avwl2 t awd col. address to we delay 60 65 70 ns 12 42 t cl2cl2 t pc fast page mode 35 40 45 ns read or write cycle time 43 t ch2cl2 t cp cas precharge time 10 10 10 ns 44 t avrh1 t car column address to ras 30 35 40 ns setup time 45 t ch2qv t cap access time from 35 40 45 ns 7 column precharge 46 t rl1dx t dhr data in hold time 50 55 60 ns referenced to ras 47 t cl1rl2 t csr cas setup time 10 10 10 ns cas -before- ras refresh 48 t rh2cl2 t rpc ras to cas precharge time 5 5 5 ns 49 t rl1ch1 t chr cas hold time 15 15 25 ns cas -before- ras refresh 50 t cl2cl2 t pcm fast page mode read- 90 100 105 ns (rmw) modify-write cycle time t t t t transition time 3 50 3 50 3 50 ns 15 (rise and fall) t ref refresh interval 8 8 8 ms 17 (512 cycles) jedec
8 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 1. i dd is dependent on output loading when the device output is selected. specified i dd (max.) is measured with the output open. 2. i dd is dependent upon the number of address transitions. specified i dd (max.) is measured with a maximum of two transitions per address cycle in fast page mode. 3. specified v il (min.) is steady state operating. during transitions, v il (min.) may undershoot to C1.0 v for a period not to exceed 20 ns. all ac parameters are measured with v il (min.) 3 v ss and v ih (max.) v dd . 4. t rcd (max.) is specified for reference only. operation within t rcd (max.) limits insures that t rac (max.) and t caa (max.) can be met. if t rcd is greater than the specified t rcd (max.), the access time is controlled by t caa and t cac . 5. either t rrh or t rch must be satisified for a read cycle to occur. 6. measured with a load equivalent to two ttl inputs and 100 pf. 7. access time is determined by the longest of t caa , t cac and t cap . 8. assumes that t rad t rad (max.). if t rad is greater than t rad (max.), t rac will increase by the amount that t rad exceeds t rad (max.). 9. assumes that t rcd t rcd (max.). if t rcd is greater than t rcd (max.), t rac will increase by the amount that t rcd exceeds t rcd (max.). 10. assumes that t rad 3 t rad (max.). 11. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, the access time is controlled by t caa and t cac . 12. t wcs , t rwd , t awd and t cwd are not restrictive operating parameters. 13. t wcs (min.) must be satisfied in an early write cycle. 14. t ds and t dh are referenced to the latter occurrence of cas or we . 15. t t is measured between v ih (min.) and v il (max.). ac-measurements assume t t = 5 ns. 16. assumes a three-state test load (5 pf and a 380 ohm thevenin equivalent). 17. an initial 200 m s pause and 8 ras -containing cycles are required when exiting an extended period of bias without clocks. an extended period of time without clocks is defined as one that exceeds the specified refresh interval.
9 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 waveforms of read cycle ih v il v ras ih v il v cas ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t csh (4) t rsh (r)(12) t cas (5) t rcd (6) t crp (13) t cah (11) t asc (10) t rad (24) t rah (9) t asr (8) t rcs (7) t rch (14) t rrh (15) t car (44) t caa (20) t cac (18) t t hz (22) t lz (21) ih v il v we oh v ol v i/o 676 01 valid data-out address rac (19) column address row address t oac (17) t hz (22) ih v il v oe t roh (16) waveforms of early write cycle ih v il v ih v il v ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t csh (4) t rsh (w)(25) t cas (5) t rcd (6) t crp (13) t cah (11) t t rad (24) t rah (9) t asr (8) t t wcr (30) t rwl (31) t dh (33) t dhr (46) ih v il v ih v il v ih v il v 676 02 t t cwl (26) wch (28) t t ds (32) column address valid data-in high-z ras cas we oe i/o address t car (44) asc (10) wcs (27) wp (29) row address
10 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 waveforms of oe-controlled write cycle ih v il v ih v il v ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t rcd (6) t crp (13) t cah (11) t asc (10) t rah (9) t asr (8) row address column address t woh (34) t dh (33) t oed (35) ih v il v ih v il v ih v il v 676 03 valid data-in t ds (32) t rad (24) ras cas we oe i/o t csh (4) address t car (44) t t cas (5) rsh (w)(12) t wp (29) rwl (31) t cwl (26) t waveforms of fast page mode read cycle valid data out valid data out column address cac (18) t t hz (22) hz (22) hz (22) hz (22) row address column address ih v il v ih v il v rp (3) t ih v il v ih v il v oh v ol v t rah (9) t asr (8) t rcs (7) t rch (14) t csh (4) 676 05 ih v il v cp (43) t asc (10) rcd (6) t t rasp (37) t rsh (r)(12) t cas (5) t cah (11) t hz (22) t t ar (23) t cas (5) t cas (5) pc (42) t crp (13) t t column address t t car (44) t cah (11) t rcs (7) t rcs (7) t rch (14) t oac (17) t t t oac (17) t caa (20) t rrh (15) t hz (22) lz (21) t rac (19) t t cac (18) valid data out t crp (13) t t lz (21) t ras cas we oe i/o address t asc (10) t lz (21) cac (18) t caa (20) oac (17) cap (45) t cah (11)
11 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 waveforms of fast page mode write cycle row add ih v il v ih v il v ih v il v ih v il v t t asr (8) 676 06 ih v il v cp (43) t asc (10) rcd (6) t rsh (w)(25) column address t cah (11) t cas (5) t cas (5) t car (44) t rad (24) t cwl (26) valid d ata i n t crp (13) t wcs (27) wp (29) t cah (11) t asc (10) t cah (11) t dh (33) t ds (32) ih v il v column address rah (9) column address t crp (13) t t wch (28) t cwl (26) t wcs (27) wp (29) t wch (28) t t cwl (26) t wcs (27) wp (29) t wch (28) t valid d ata i n t dh (33) t ds (32) valid d ata i n t dh (33) t ds (32) t rp (3) t ar (23) ras cas we oe i/o address open open t rwl (31) t t csh (4) t t pc (42) t t cas (5) rasp (37)
12 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 waveforms of ras-only refresh cycle ih v il v ras ih v il v rp (3) t ih v il v cas t ras (1) t rc (2) t crp (13) t asr (8) t rah (9) 1579 08 we, oe = dont care note: address row address waveforms of fast page mode read-write cycle rasp (37) row add ih v il v ih v il v rp (3) t ih v il v i/oh v i/ol v t t asr (8) column address 676 07 ih v il v cp (43) t asc (10) rcd (6) t t t rsh (w)(25) column address t cah (11) t cas (5) t cas (5) t t t crp (13) t rcs (7) t cah (11) t asc (10) t t cwd (38) t lz (21) ih v il v column address t asc (10) rah (9) t wp (29) t cwl (26) t t cwl (26) t rwl (31) t awd (41) t caa (20) t t oac (17) t awd (41) t oac (17) in t cac (18) t oed (35) t ds (32) t dh (33) t lz (21) in out hz (22) t oed (35) ds (32) t dh (33) t t cap (43) t t cac (18) t caa (20) lz (21) in hz (22) t oed (35) ds (32) t dh (33) t t t cac (18) t caa (20) cap (43) t t wp (29) t t wp (29) t cwl (26) t car (44) t rad (24) ras cas we oe i/o address t awd (41) out rac (19) t oac (17) t rwd (39) cah (11) pcm (50) t t csh (4) t cas (5) t cwd (38) hz (22) cwd (38) out
13 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 waveforms of cas-before-ras refresh cycle i/o ih v il v ras oh v ol v ih v il v cas t ras (1) t rc (2) t cp (43) t hz (22) t csr (47) 675 07 rp (3) t t rpc (48) t chr (49) rp (3) t we, oe, = dont care note: a Ca 0 7 ih v il v oh v ol v rp (3) t ih v il v t asr (8) t crp (13) t rcd (6) t rsh (r)(12) t rcs (7) 676 10 t chr (49) t rad (24) t asc (10) t t cah (11) row add column address t rrh (15) t oac (17) t lz (21) t hz (22) t hz (22) ih v il v ih v il v ih v il v ras cas we oe i/o address valid data rah (9) t caa (20) t cac (18) t rac (19) t ras (1) rp (3) t t ras (1) t ar (23) t crp (13) t rc (2) t rc (2) waveforms of hidden refresh cycle (read)
14 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 waveforms of hidden refresh cycle (write) ih v il v ih v il v rp (3) t ih v il v t ras (1) t rc (2) t asr (8) t crp (13) rp (3) t t rcd (6) t rsh (12) t wcs (27) 676 11 t ras (1) t ar (23) t chr (49) t crp (13) t rad (24) t asc (10) t rah (9) t cah (11) row add column address t wch (28) t ds (32) ih v il v ih v il v ih v il v valid data-in t dhr (46) t rc (2) ras cas we oe i/o address t dh (33)
15 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 waveforms of cas-before-ras refresh counter test cycle ih v il v ih v il v rp (3) t ih v il v t csr (47) t rsh (w)(25) 1486 12 t ras (1) t chr (49) t rcs (7) t wcs (27) t lz (21) ih v il v ih v il v ih v il v t dh (33) t cp (43) t cas (5) t rch (14) t rrh (15) t roh (16) t oac (17) t hz (22) t hz (22) t rwl (31) t cwl (26) t ds (32) ih v il v ih v il v ih v il v read cycle write cycle t wch (28) i/o address we we i/o d out d in ras cas oe oe t asc (10) column address t cah (11)
16 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 functional description the v53c104d is a cmos dynamic ram opti- mized for high data bandwidth, low power applica- tions. it is functionally similar to a traditional dynamic ram. the v53c104d reads and writes data by multiplexing an 18-bit address into a 9-bit row and a 9-bit column address. the row address is latched by the row address strobe ( ras ). the column address flows through an internal address buffer and is latched by the column address strobe ( cas ). be- cause access time is primarily dependent on a valid column address rather than the precise time that the cas edge occurs, the delay time from ras to cas has little effect on the access time. memory cycle a memory cycle is initiated by bringing ras low. any memory cycle, once initiated, must not be ended or aborted before the minimum t ras time has expired. this ensures proper device operation and data integ- rity. a new cycle must not be initiated until the minimum precharge time t rp /t cp has elapsed. read cycle a read cycle is performed by holding the write enable ( we ) signal high during a ras / cas opera- tion. the column address must be held for a mini- mum specified by t ar . data out becomes valid only when t oac , t rac , t caa and t cac are all satisifed. as a result, the access time is dependent on the timing relationships between these parameters. for ex- ample, the access time is limited by t caa when t rac , t cac and t oac are all satisfied. write cycle a write cycle is performed by taking we and cas low during a ras operation. the column address is latched by cas . the write cycle can be we con- trolled or cas controlled depending on whether we or cas falls later. consequently, the input data must be valid at or before the falling edge of we or cas , whichever occurs last. in the cas -controlled write cycle, when the leading edge of we occurs prior to the cas low transition, the i/o data pins will be in the high-z state at the beginning of the write function. ending the write with ras or cas will maintain the output in the high-z state. in the we controlled write cycle, oe must be in the high state and t oed must be satisfied. refresh cycle to retain data, 512 refresh cycles are required in each 8 ms period. there are two ways to refresh the memory: 1. by clocking each of the 512 row addresses (a 0 through a 8 ) with ras at least once every 8 ms. any read, write, read-modify-write or ras -only cycle refreshes the addressed row. 2. using a cas -before- ras refresh cycle. if cas makes a transition from low to high to low after the previous cycle and before ras falls, cas -before- ras refresh is activated. the v53c104d uses the output of an internal 9-bit counter as the source of row addresses and ignore external address in- puts. cas -before- ras is a refresh-only mode and no data access or device selection is allowed. thus, the output remains in the high-z state during the cycle. a cas -before- ras counter test mode is provided to ensure reliable operation of the internal refresh counter. data retention mode the v53c104d offers a cmos standby mode that is entered by causing the ras clock to swing be- tween a valid v il and an extra high v ih within 0.2 v of v dd . while the ras clock is at the extra high level, the v53c104d power consumption is reduced to the low i dd6 level. overall i dd consumption when operating in this mode can be calculated as follows: (t rc ) x (i dd1 ) + (t rx Ct rc ) x (i dd6 ) i = t rx where: t rc = refresh cycle time t rx = refresh interval / 512
17 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 fast page mode operation fast page mode operation permits all 512 col- umns within a selected row of the device to be randomly accessed at a high data rate. maintaining ras low while performing successive cas cycles retains the row address internally and eliminates the need to reapply it for each cycle. the column address buffer acts as a transparent or flow-through latch while cas is high. thus, access begins from the occurrence of a valid column address rather than from the falling edge of cas , eliminating t asc and t t from the critical timing path. cas latches the address into the column address buffer and acts as an output enable. during fast page mode operation, read, write, read-modify-write or read-write-read cycles are possible at random addresses within a row. following the initial entry cycle into fast page mode, access is t caa or t cap controlled. if the column address is valid prior to the rising edge of cas , the access time is referenced to the cas rising edge and is specified by t cap . if the column address is valid after the rising cas edge, access is timed from the occurrence of a valid address and is specified by t caa . in both cases, the falling edge of cas latches the address and enables the output. fast page mode provides a sustained data rate of 25 mhz for applications that require high data rates such as bit-mapped graphics or high-speed signal processing. the following equation can be used to calculate the maximum data rate: 512 data rate = t rc + 511 x t pc data output operation the v53c104d input/output is controlled by oe , cas , we and ras . a ras low transition enables the transfer of data to and from the selected row address in the memory array. a ras high transition disables data transfer and latches the output data if the output is enabled. after a memory cycle is initiated with a ras low transition, a cas low transition or cas low level enables the internal i/o path. a cas high transition or a cas high level disables the i/o path and the output driver if it is enabled. a cas low transition while ras is high has no effect on the i/o data path or on the output drivers. the output drivers, when otherwise enabled, can be disabled by holding oe high. the oe signal has no effect on any data stored in the output latches. a we low level can also disable the output drivers when cas is low. during a write cycle, if we goes low at a time in relationship to cas that would normally cause the outputs to be active, it is necessary to use oe to disable the output drivers prior to the we low transition to allow data in setup time (t ds ) to be satisfied. power-on after application of the v dd supply, an initial pause of 200 m s is required followed by a minimum of 8 initialization cycles (any combination of cycles con- taining a ras clock). eight initialization cycles are required after extended periods of bias without clocks (greater than the refresh interval). during power-on, the v dd current requirement of the v53c104d is dependent on the input levels of ras and cas . if ras is low during power-on, the device will go into an active cycle and i dd will exhibit current transients. it is recommended that ras and cas track with v dd or be held at a valid v ih during power-on to avoid current surges. table 1. v53c104d data output operation for various cycle types cycle type i/o state read cycles data from addressed memory cell cas -controlled write high-z cycle (early write) we -controlled write oe controlled. high cycle (late write) oe = high-z i/os read-modify-write data from addressed cycles memory cell fast page mode data from addressed read memory cell fast page mode write high-z cycle (early write) fast page mode read- data from addressed modify-write cycle memory cell ras -only refresh high-z cas -before- ras data remains as in refresh cycle previous cycle cas -only cycles high-z
18 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 package outlines 20-pin 300 mil plastic dip dimension inches millimeters a 0.980 max. 24.892 max. b 0.320/0.370 8.128/9.398 c .100 typ. 2.54 typ. d 0.018/0.024 0.457/0.610 e 0.048/0.054 1.219/1.372 f 0.110/0.140 2.794/3.556 g 0.005/0.050 0.127/1.270 h .180 max. 4.572 max. j 0.300/0.330 7.62/8.382 k 0.280/0.300 7.112/7.620 l 0.008/0.013 0.20/0.33 a e d h g c f l j k b
19 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 h g a j b c k d e f 26/20-pin soj dimension inches millimeters a 0.672/0.684 17.069/17.374 b 0.125/0.135 3.175/3.429 c 0.082/0.093 2.083/2.362 d 0.332/0.342 8.433/8.687 e 0.296/0.304 7.518/7.722 f 0.255/0.275 6.477/6.985 g 0.018 typ. 0.457 typ. h 0.05 typ. 1.270 typ. j 0.026 min. 0.660 min. k 0.028 typ. 0.711 typ.
20 v53c104d mosel vitelic v53c104d rev. 1.0 january 1995 mosel vitelic 1/95 printed in u.s.a. mosel-vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. mosel-vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. the information in this document is subject to change without notice. mosel-vitelic makes no commitment to update or keep current the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. worldwide offices u.s. sales offices northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 southwestern suite 200 5150 e. pacific coast hwy. long beach, ca 90804 phone: 310-498-3314 fax: 310-597-2174 central & southeastern 604 fieldwood circle richardson, tx 75081 phone: 214-690-1402 fax: 214-690-0341 northeastern suite 306 71 spitbrook road nashua, nh 03062 phone: 603-891-2007 fax: 603-891-3597 ? copyright 1995, mosel-vitelic inc. 3910 n. first street, san jose, ca 95134-1501 ph: (408) 433-6000 fax: (408) 433-0952 tlx: 371-9461 japan tbc 2-27-10 higashi shibuya-ku, tokyo 150 japan phone: 81-03-5467-9091 fax: 81-03-5467-9099 room 302 annex-g higashi-nakaro nakaro-ku, tokyo 164 phone: 81-3-3365-2851 fax 81-3-3365-2836 taiwan 5f, no.. 102 min chuan e. road, sec.3 taipei phone: 886-2-545-1213 fax: 886-2-545-1214 1 r&d road i science based ind. park hsin chu, taiwan, r.o.c. phone: 886-35-770055 fax: 886-35-776520 hong kong 19 dai fu street taipo industrial estate taipo, nt, hong kong phone: 852-665-4883 fax: 852-664-7535 u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-00952

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