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november 2003 asm5p23ss08a rev 1.1 a lliance semiconducto r 2575 , au g ustine drive ? santa clara , ca ? ? ? www.alsc.com notice: the information in this docum ent is subject to change without notice. 3.3v zero delay buffer general features ? zero input - output propagation delay, adjustable by capacitive load on fbk input. ? emi reduced output with on-chip emi reduction capability. ? multiple configurations - refer ?asm5p23ss08a configurations table?. ? input frequency range : 10mhz to 133mhz ? multiple low-skew outputs. ? output-output skew less than 200 ps. ? device-device skew less than 700 ps. ? two banks of four outputs, three-stateable by two select inputs. ? less than 200 ps cycle-to-cycle jitter (-1, -1h, -4, -5h). ? available in 16-pin soic and tssop packages. ? 3.3v operation. ? advanced 0.35 cmos technology. ? industrial temperature available. functional description asm5p23ss08a is a versatile, spread spectrum output, 3.3v zero-delay buffer designed to distribute high-speed clocks with emi supression capability. it is available in a 16-pin package. the asm5p23ss08a family incorporates the latest advances in pll spread spectrum techniques to greatly reduce the peak emi by modulating the output frequency with a low frequency carrier . the asm5p23ss08a allows significant system cost savings by reducing the number of circuit board layers and shielding that are traditionally requir ed to pass emi regulations. because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has negligible impact on system performance while giving significant cost savings. alliance offers options with different spreading patterns with more spread and greater emi reduction. the part has an on-chip pll whick locks to an input clock presented on the ref pin. the pll feedback is required to be driven to fbk pin, and can be obtained from one of the outputs. the input-to- input propogation delay is guaranteed to be less than 350ps, and the output-to-output skew is guaranteed to be less than 250ps. the asm5p23ss08a has two ba nks of four outputs each, which can be controlled by the select inputs as shown in the select input decoding table. if all the output clocks are not required, bank b can be th ree-stated. the select input also allows the input clock to be directly applied to the outputs for chip and system testing purposes. multiple asm5p23ss08a devices can accept the same input clock and distribute it. in this case the skew between the outputs of the two devices is guaranteed to be less than 700ps. the asm5p23ss08a is available in five different configurations (refer ?asm 5p23ss08a configurations table). the asm5p23ss08a-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. the asm5p23ss08a-1h is the high-drive version of the -1 and the rise and fall times on this device are much faster. the asm5p23ss08a-2 allows the user to obtain 2x and 1x frequencies on each output bank. the exact configuration and output fr equencies depends on which output drives the feedback pin. the asm5p23ss08a-3 allows the user to obtain 4x and 2x frequencies on the outputs. the asm5p23ss08a-4 enables the user to obtain 2x clocks on all outputs. thus, t he part is extremely versatile, and can be used in a variety of applications. the asm5p23ss08a-5h is a high-drive version with ref/2 on both banks.
november 2003 asm5p23ss08a rev 1.1 3.3v zero delay buffer notice: the information in this docum ent is subject to change without notice. block diagram select input decoding for asm5p23ss08a s2 s1 clock a1 - a4 clock b1 - b4 output source pll shut-down 0 0 three-state th ree-state pll y 0 1 driven three-state pll n 1 0 driven 1 driven reference y 1 1 driven driven pll n asm5p23ss08a configurations device feedback from bank a frequency bank b frequency asm5p2308-1 bank a or bank b reference reference asm5p2308-1h bank a or bank b reference reference asm5p2308-2 bank a reference reference /2 asm5p2308-2 bank b 2 x reference reference asm5p2308-3 bank a 2 x reference reference or reference 2 asm5p2308-3 bank b 4 x reference 2 x reference asm5p2308-4 bank a or bank b 2 x reference 2 x reference asm5p2308-5h bank a or bank b reference /2 referemce /2 note: 1. outputs inverted on 2308-2 and 2308-3 in bypass mode, s2 = 1 and s1 =0. 2. output phase is indeterminant (0 or 180 from input clock). if phase integrity is required, use the asm5p2308-2. clka1 clka2 clka3 clka4 clkb1 clkb2 clkb3 clkb4 fbk ref s1 s2 select input peak reducing mux asm5p23ss08a decodin g pll / 2 /2 /2 extra divider (-3,-4) extra divider (-5h) extra divider (-2,-3)
november 2003 asm5p23ss08a rev 1.1 a lliance semiconducto r 2575 , au g ustine drive ? santa clara , ca ? ? ? www.alsc.com notice: the information in this document is subject to change without notice. spread spectrum frequency generation the clocks in digital systems are typically square waves with a 50% duty cycle and as frequencies increase the edge rates also get faster. analysis shows that a square wave is composed of fundamental frequency and harmonics. the fundamental frequency and harmonics generate the energy peaks that become the source of emi. regulatory agencies test electronic equipment by measuring the amount of peak energy radiated from the equipment. in fact, the peak level allowed decreases as the frequency increases. the standard methods of reducing emi are to use shielding, filt ering, multi-layer-pcbs etc. these methods are expensive. spread spectrum clocking reduces the peak energy by reducing the q factor of the clock. this is done by slowly modulating the clock frequency. the asm5p23sxx uses the center modulation spread spectrum technique in which the modulated output frequency varies above and below the reference frequency with a specified modulation rate. with center modulation, the average frequency is the same as the un-modulated frequency and there is no pe rformance degradation. zero delay and skew control all outputs should be uniformly loaded to achieve zero delay between input and output. to close the feedback loop of the asm5p23ss08a, the fbk pin can be driven from any of the eight available output pins. the output driving the fbk pin will be driving a total load of 7 pf plus any additional load that it drives. the relative loading of this output (with respect to the remaining outputs) can adjust the input out put delay. this is shown in the above graph. for applications requiring ze ro input-output delay, all outputs including the one providing feedback should be equally loaded. if input-out put delay adjustments are required, use the above gr aph to calculate loading differences between the feedback output and remaining outputs. for zero output-output skew, be sure to load outputs equally. -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 0 -500 -1000 -1500 500 1000 1500 output load difference: fbk load - clka/clkb load (pf) ref-input to clka/lkb delay (ps)
november 2003 asm5p23ss08a rev 1.1 3.3v zero delay buffer notice: the information in this document is subject to change without notice. pin configuration pin description for asm5p23ss08a pin # pin name description 1 ref 3 input reference frequency, 5v tolerant input 2 clka1 4 buffered clock output, bank a 3 clka2 4 buffered clock output, bank a 4 v dd 3.3v supply 5 gnd ground 6 clkb1 4 buffered clock output, bank b 7 clkb2 4 buffered clock output, bank b 8 s2 5 select input, bit 2 9 s1 5 select input, bit 1 10 clkb3 4 buffered clock output, bank b 11 clkb4 4 buffered clock output, bank b 12 gnd ground 13 v dd 3.3v supply 14 clka3 4 buffered clock output, bank a 15 clka4 4 buffered clock output, bank a 16 fbk pll feedback input notes: 3. weak pull-down. 4. weak pull-down on all outputs. 5. weak pull-up on these inputs. 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 ref clka1 clka2 clka3 clka 4 clkb1 clkb2 clkb 3 clkb4 v dd gnd s2 fbk s1 gnd v dd asm5p23ss08a
november 2003 asm5p23ss08a rev 1.1 3.3v zero delay buffer notice: the information in this document is subject to change without notice. absolute maximum ratings parameter min max unit supply voltage to ground potential -0.5 +7.0 v dc input voltage (except ref) -0.5 v dd + 0.5 v dc input voltage (ref) -0.5 7 v storage temperature -65 +150 c max. soldering temperature (10 sec) 260 c junction temperature 150 c static discharge voltage (per mil-std-883, method 3015) >2000 v note: these are stress ratings only and functional usage is not implied. exposure to absolute maximum ratings for prolonged periods can affect device reliability. operating conditions for asm5p23ss08a commercial temperature devices parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (amb ient temperature) 0 70 ?c c l load capacitance, below 100 mhz 30 pf c l load capacitance, from 100 mhz to 133 mhz 10 pf c in input capacitance 6 7 pf note: 6. applies to both ref clock and fbk.
november 2003 asm5p23ss08a rev 1.1 3.3v zero delay buffer notice: the information in this document is subject to change without notice. electrical characteristics for asm5p23ss08a commercial temperature devices parameter description test conditions min max unit v il input low voltage 0.8 v v ih input high voltage 2.0 v i il input low current v in = 0v 50.0 a i ih input high current v in = v dd 100.0 a v ol output low voltage 7 i ol = 8ma (-1, -2, -3, -4) i oh = 12ma (-1h, -5h) 0.4 v v oh output high voltage 7 i ol = -8ma (-1, -2, -3, -4) i oh = -12ma (-1h, -5h) 2.4 v tbd unloaded outputs 100mhz ref, select inputs at v dd or gnd tbd unloaded outputs, 66mhz ref (-1, -2, -3, -4) tbd i dd supply current unloaded outputs, 33mhz ref (-1, -2, -3, -4) tbd ma note: 7. parameter is guaranteed by design and charac terization. not 100% tested in production.
november 2003 asm5p23ss08a rev 1.1 3.3v zero delay buffer notice: the information in this document is subject to change without notice. switching characteristics for asm5p23ss08a commercial temperature devices parameter description test conditions min typ max unit t 1 output frequency 30-pf load, all devices 10 100 mhz t 1 output frequency 20-pf load, -1h, -5h devices 8 10 133.3 mhz t 1 output frequency 15-pf load, -1, -2, -3, -4 devices 10 133.3 mhz duty cycle 7 = (t 2 / t 1 ) * 100 (-1, -2, -3, -4, -1h, -5h) measured at 1.4v, f out = <66.66 mhz 30-pf load 40.0 50.0 60.0 % duty cycle 7 = (t 2 / t 1 ) * 100 (-1, -2, -3, -4, -1h, -5h) measured at 1.4v, f out = <50 mhz 15-pf load 45.0 50.0 55.0 % t 3 output rise time 7 (-1, -2, -3, -4) measured between 0.8v and 2.0v 30-pf load 2.20 ns t 3 output rise time 7 (-1, -2, -3, -4) measured between 0.8v and 2.0v 15-pf load 1.50 ns t 3 output rise time 7 (-1h, -5h) measured between 0.8v and 2.0v 30-pf load 1.50 ns t 4 output fall time 7 (-1, -2, -3, -4) measured between 2.0v and 0.8v 30-pf load 2.20 ns t 4 output fall time 7 (-1, -2, -3, -4) measured between 0.8v and 2.0v 15-pf load 1.50 ns t 4 output fall time 7 (-1h, -5h) measured between 2.0v and 0.8v 30-pf load 1.25 ns output-to-output skew on same bank (-1, -2, -3, -4) 7 all outputs equally loaded 200 output-to-output skew (-1h, -5h) all outputs equally loaded 200 output bank a ?to- output bank b skew (-1, -4, -5h) all outputs equally loaded 200 t 5 output bank a -to- output bank b skew (-2, -3) all outputs equally loaded 400 ps
november 2003 asm5p23ss08a rev 1.1 3.3v zero delay buffer notice: the information in this document is subject to change without notice. switching characteristics for asm5p23ss08a commercial temperature devices (contd) parameter description test conditions min typ max unit t 6 delay, ref rising edge to fbk rising edge 7 measured at v dd /2 0 250 ps t 7 device-to-device skew 7 measured at v dd /2 on the fbk pins of the device 0 700 ps measured at 66.67 mhz, loaded outputs, 15 pf load 200 measured at 66.67 mhz, loaded outputs, 30 pf load 200 t j cycle-to-cycle jitter 7 (-1, -1h, -4, - 5h) measured at 133.3 mhz, loaded outputs, 15 pf load 100 ps measured at 66.67 mhz, loaded outputs, 30pf load 400 t j cycle-to-cycle jitter 7 (-2, -3) measured at 66.67 mhz, loaded outputs, 15 pf load 400 ps t lock pll lock time 7 stable power supply, valid clock presented on ref & fbk pins 1.0 ms switching characteristics for asm5i23ss08 industrial temperature devices parameter description test conditions min typ max unit t 1 output frequency 30-pf load, all devices 10 100 mhz t 1 output frequency 20-pf load, -1h, -5h devices 8 10 133.3 mhz t 1 output frequency 15-pf load, -1, -2, -3, -4 devices 10 133.3 mhz duty cycle 7 = (t 2 / t 1 ) * 100 (-1, -2, -3, -4, -1h, -5h) measured at 1.4v, f out = <66.66 mhz 30-pf load 40.0 50. 0 60.0 % duty cycle 7 = (t 2 / t 1 ) * 100 (-1, -2, -3, -4, -1h, -5h) measured at 1.4v, f out = <50 mhz 15-pf load 45.0 50. 0 55.0 %
november 2003 asm5p23ss08a rev 1.1 3.3v zero delay buffer notice: the information in this document is subject to change without notice. switching characteristics for asm5i23ss08 industrial temperature devices (contd) parameter description test conditions min typ max unit t 3 output rise time 7 (-1, -2, -3, -4) measured between 0.8v and 2.0v 30-pf load 2.50 ns t 3 output rise time 7 (-1, -2, -3, -4) measured between 0.8v and 2.0v 15-pf load 1.50 ns t 3 output rise time 7 (-1h, -5h) measured between 0.8v and 2.0v 30-pf load 1.50 ns t 4 output fall time 7 (-1, -2, -3, -4) measured between 2.0v and 0.8v 30-pf load 2.50 ns t 4 output fall time 7 (-1, -2, -3, -4) measured between 0.8v and 2.0v 15-pf load 1.50 ns t 4 output fall time 7 (-1h, -5h) measured between 2.0v and 0.8v 30-pf load 1.25 ns output-to-output skew on same bank (-1, -2, -3, -4) 7 all outputs equally loaded 200 output-to-output skew (-1h, -5h) all outputs equally loaded 200 output bank a -to- output bank b skew (-1, -4, -5h) all outputs equally loaded 200 t 5 output bank a -to- output bank b skew (-2, -3) all outputs equally loaded 400 ps t 6 delay, ref rising edge to fbk rising edge 7 measured at v dd /2 0 250 ps t 7 device-to-device skew 7 measured at v dd /2 on the fbk pins of the device 0 700 ps measured at 66.67 mhz, loaded outputs, 15 pf load 200 measured at 66.67 mhz, loaded outputs, 30 pf load 200 t j cycle-to-cycle jitter 7 (-1, -1h, -4, -5h) measured at 133.3 mhz, loaded outputs, 15 pf load 100 ps measured at 66.67 mhz, loaded outputs, 30pf load 400 t j cycle-to-cycle jitter 7 (-2, -3) measured at 66.67 mhz, loaded outputs, 15 pf load 400 ps t lock pll lock time 7 stable power supply, valid clock presented on ref and fbk pins 1.0 ms
november 2003 asm5p23ss08a rev 1.1 3.3v zero delay buffer notice: the information in this document is subject to change without notice. switching waveforms duty cycle timing all outputs rise/fall time output - output skew input - output propagation delay device - device skew t 1 t 2 1.4 v 1.4 v 1.4 v output 2.0 v 0. 8 v t 3 t4 3.3 v 0 v 2.0 v 0. 8 v 1.4 v 1.4 v t 5 output output v dd /2 t 6 input output v dd /2 v dd /2 t 7 clkout, device 1 v dd /2 clkout, device 2
november 2003 asm5p23ss08a rev 1.1 3.3v zero delay buffer notice: the information in this document is subject to change without notice. test circuits 1k ? 10 pf v dd gnd outputs clk out c load 0. 1 f 1k ? 0.1 f 0.1 f 0. 1 f v dd v dd v dd gnd gnd gnd outputs test circuit #1 test circuit #2 for p ar ame ter t 8 (output slew rate) on -1h devices
november 2003 asm5p23ss08a rev 1.1 3.3v zero delay buffer notice: the information in this document is subject to change without notice. package information: 16-lead (150 mil) molded soic e h a a1 a2 d e b l c h seating plane 0.004 pin 1 id 1 8 9 16 dimensions (inches) dimensions (millimeters) symbol min max min max a 0.061 0.068 1.55 1.73 a1 0.004 0.0098 0.102 0.249 a2 0.055 0.061 1.40 1.55 b 0.013 0.019 0.33 0.49 c 0.0075 0.0098 0.191 0.249 d 0.386 0.393 9.80 9.98 e 0.150 0.157 3.81 3.99 e 0.050 bsc 1.27 bsc h 0.230 0.244 5.84 6.20 h 0.010 0.016 0.25 0.41 l 0.016 0.035 0.41 0.89 0 8 0 8
november 2003 asm5p23ss08a rev 1.1 3.3v zero delay buffer notice: the information in this document is subject to change without notice. package information: 16-lead thin shrunk small outline package (4.40-mm body) dimensions (inches) dimensions (millimeters) symbol min max min max a 0.043 1.10 a1 0.002 0.006 0.05 0.15 a2 0.003 0.37 0.85 0.95 b 0.007 0.012 0.19 0.30 c 0.004 0.008 0.09 0.20 d 0.193 2.008 4.90 5.10 e 0.169 0.177 4.30 4.50 e 0.026 bsc 0.65 bsc h 0.246 0.256 6.25 6.50 l 0.020 0.028 0.50 0.70 0 8 0 8
november 2003 asm5p23ss08a rev 1.1 3.3v zero delay buffer notice: the information in this document is subject to change without notice. ordering information ordering code package type operating range asm5p23ss08a-1-16-st 16-pin 150-mil soic-tube commercial asm5i23ss08a-1-16-st 16-pin 150-mil soic- tube industrial asm5p23ss08a-1-16-sr 16-pin 150-mil soic-tape & reel commercial asm5i23ss08a-1-16-sr 16-pin 150-mil soic-tape & reel industrial asm5p23ss08a-1-16-tt 16-pin 150-mil tssop - tube commercial asm5i23ss08a-1-16-tt 16-pin 150 -mil tssop - tube industrial asm5p23ss08a-1-16-tr 16-pin 150-mil tssop - tape & reel commercial asm5i23ss08a-1-16-tr 16-pin 150-mil tssop - tape & reel industrial asm5p23ss08a-1h-16-st 16-pin 150-mil soic-tube commercial asm5i23ss08a-1h-16-st 16-pin 150-mil soic- tube industrial asm5p23ss08a-1h-16-sr 16-pin 150-mil soic-tape & reel commercial asm5i23ss08a-1h-16-sr 16-pin 150-mil soic-tape & reel industrial asm5p23ss08a-1h-16-tt 16-pin 150-mil tssop - tube commercial asm5i23ss08a-1h-16-tt 16-pin 150 -mil tssop - tube industrial asm5p23ss08a-1h-16-tr 16-pin 150-mil tssop - tape & reel commercial asm5i23ss08a-1h-16-tr 16-pin 150-mil tssop - tape & reel industrial asm5p23ss08a-2-16-st 16-pin 150-mil soic-tube commercial asm5i23ss08a-2-16-st 16-pin 150-mil soic- tube industrial asm5p23ss08a-2-16-sr 16-pin 150-mil soic-tape & reel commercial asm5i23ss08a-2-16-sr 16-pin 150-mil soic-tape & reel industrial asm5p23ss08a-2-16-tt 16-pin 150-mil tssop - tube commercial asm5i23ss08a-2-16-tt 16-pin 150 -mil tssop - tube industrial asm5p23ss08a-2-16-tr 16-pin 150-mil tssop - tape & reel commercial asm5i23ss08a-2-16-tr 16-pin 150-mil tssop - tape & reel industrial
november 2003 asm5p23ss08a rev 1.1 3.3v zero delay buffer notice: the information in this document is subject to change without notice. ordering code package type operating range asm5p23ss08a-3-16-st 16-pin 150-mil soic-tube commercial asm5i23ss08a-3-16-st 16-pin 150-mil soic- tube industrial asm5p23ss08a-3-16-sr 16-pin 150-mil soic-tape & reel commercial asm5i23ss08a-3-16-sr 16-pin 150-mil soic-tape & reel industrial asm5p23ss08a-3-16-tt 16-pin 150-mil tssop - tube commercial asm5i23ss08a-3-16-tt 16-pin 150 -mil tssop - tube industrial asm5p23ss08a-3-16-tr 16-pin 150-mil tssop - tape & reel commercial asm5i23ss08a-3-16-tr 16-pin 150-mil tssop - tape & reel industrial asm5p23ss08a-4-16-st 16-pin 150-mil soic-tube commercial asm5i23ss08a-4-16-st 16-pin 150-mil soic- tube industrial asm5p23ss08a-4-16-sr 16-pin 150-mil soic-tape & reel commercial asm5i23ss08a-4-16-sr 16-pin 150-mil soic-tape & reel industrial asm5p23ss08a-4-16-tt 16-pin 150-mil tssop - tube commercial asm5i23ss08a-4-16-tt 16-pin 150 -mil tssop - tube industrial asm5p23ss08a-4-16-tr 16-pin 150-mil tssop - tape & reel commercial asm5i23ss08a-4-16-tr 16-pin 150-mil tssop - tape & reel industrial asm5p23ss08a-5h-16-st 16-pin 150-mil soic-tube commercial asm5i23ss08a-5h-16-st 16-pin 150-mil soic- tube industrial asm5p23ss08a-5h-16-sr 16-pin 150-mil soic-tape & reel commercial asm5i23ss08a-5h-16-sr 16-pin 150-mil soic-tape & reel industrial asm5p23ss08a-5h-16-tt 16-pin 150-mil tssop - tube commercial ASM5I23SS08A-5H-16-TT 16-pin 150 -mil tssop - tube industrial asm5p23ss08a-5h-16-tr 16-pin 150-mil tssop - tape & reel commercial asm5i23ss08a-5h-16-tr 16-pin 150-mil tssop - tape & reel industrial licensed under us patent #5,488,627, # 6,646,463 and #5,631,920.
november 2003 asm5p23ss08a rev 1.1 3.3v zero delay buffer notice: the information in this document is subject to change without notice. ? copyright 2003 alliance semiconductor corporation. all right s reserved. our three-point logo, our name and intelliwatt are tr ademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of thei r respective companies. alliance reserve s the right to make changes to this document and its products at any ti me without notice. alliance assumes no res ponsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. allianc e reserves the right to chang e or correct this data at any time, without notice. if the product described herein is under developm ent, significant changes to thes e specifications are possible. the information in this product data sheet is intended to be general descriptive information fo r potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arisi ng out of the application or u se of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warr anties related to fitness for a particular purpose, merchantability, or infringement of any intelle ctual property rights, except as express agreed to in allian ce's terms and conditions of sale (which are available from alliance). all sales of alliance produ cts are made exclusively according to alliance's terms and cond itions of sale. the purchase of products from alliance does not convey a lic ense under any patent rights, copyrights; mask works righ ts, trademarks, or any oth er intellectual property rights of alliance or third parties. alliance does not authorize its produc ts for use as critical componen ts in life-supporting systems w here a malfunction or failure may reasonably be expected to result in significant injury to t he user, and the inclusion of alliance products in such life-support ing systems implies that the manufacturer assumes all risk of such use and agrees to i ndemnify alliance against all clai ms arising from such use. alliance semiconductor corporation 2575, augustine drive, santa clara, ca 95054 tel# 408-855-4900 fax: 408-855-4999 www.alsc.com copyright ? alliance semiconductor all rights reserved preliminary information part number: asm5p23ss08a document version: v1.1 note: this product utilizes us patent # 6, 646,463 impedance emulator patent issued to dan hariton / alliance semiconductor, dat ed 11-11-2003

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