 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1 pd - 97605 ir3863mpbf 8/8/2012 rev3.2 1 applications ? notebook and desktop computers ? game consoles ? consumer electronics C stb, lcd, tv, printers ? general purpose pol dc - dc converters description the ir 3863 supirbuck tm is an easy - to - use, fully integrated and highly efficient dc/dc voltage regulator . the onboard constant on - time hysteretic controller and mosfets make ir 3863 a space - efficient solution that delivers up to 6 a of precisely controlled output voltage . programmable switching frequency, soft start, and thermally compensated over current protection allows for a very flexible solution suitable for many different applications and an ideal choice for battery powered applications . additional features include pre - bias startup, very precise 0 . 5 v reference, over/under voltage shut down, power good output, and enable input with voltage monitoring capability . 6a highly integrated wide - input voltage, synchronous buck regulator sup ir buck tm features ? input voltage range: 3v to 21v ? output voltage range: 0.5v to 12v ? continuous 6a load capability ? constant on - time control ? compensation loop not required ? excellent efficiency at very low output currents ? programmable switching frequency and soft start ? thermally compensated over current protection ? power good output ? precision voltage reference (0.5v, +/ - 1%) ? enable input with voltage monitoring capability ? pre - bias start up ? thermal shut down ? under/over voltage fault protection ? forced continuous conduction mode option ? very small, low profile 4mm x 5mm qfn package
2 ir3863mpbf 8/8/2012 rev3.2 absolute maximum ratings (voltages referenced to gnd unless otherwise specified) ? vin, ff . - 0.3v to 25v ? vcc, pgood, en ..... - 0.3v to 8.0v ? boot - 0.3v to 33v ? phase . - 0.3v to 25v (dc), - 5v(100ns) ? boot to phase . - 0.3v to 8v ? iset .. - 0.3v to 25v, 30ma ? pgnd to gnd . - 0.3v to +0.3v ? all other pins - 0.3v to 3.9v ? storage temperature range - 65 c to 150 c ? junction temperature range - 4 0 c to 150 c ? esd classification .. jedec class 1c ? moisture sensitivity level .. jedec level 2 @ 260 c (note 2) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. package information 4mm x 5mm power qfn ordering information pkg desig package description pin count parts per reel m ir3863mtrpbf 17 4000 m ir3863mtr1pbf 17 750 w c w c o pcb j o ja / 2 / 32 - ? ? ? ? 3 ir3863mpbf 8/8/2012 rev3.2 simplified block diagram 4 ir3863mpbf 8/8/2012 rev3.2 pin description name number i/o level description fccm 1 3.3v forced continuous conduction mode (ccm). ground this pin to enable diode emulation mode or discontinuous conduction mode (dcm). pull this pin to 3.3v to operate in ccm under all load conditions. iset 2 connecting resistor to phase pin sets over current trip point. pgood 3 5v power good open drain output C pull up with a resistor to 3.3v gnd 4,17 reference bias return and signal reference. fb 5 3.3v inverting input to pwm comparator, ovp / pgood sense. ss 6 3.3v soft start/shutdown. this pin provides user programmable soft - start function. connect an external capacitor from this pin to gnd to set the startup time of the output voltage. the converter can be shutdown by pulling this pin below 0.3v. nc 7 - - 3vcbp 8 3.3v for internal ldo. bypass with a 1.0f capacitor to agnd. a resistor in series with the bypass capacitor may be required in single - ground plane designs. refer to layout recommendations for details. nc 9 - - vcc 10 5v vcc input . gate drive supply. a minimum of 1.0f ceramic capacitor is required. pgnd 11 reference power return. phase 12 vin phase node (or switching node) of mosfet half bridge. vin 13 vin input voltage for the system. boot 14 vin +vcc bootstrapped gate drive supply C connect a capacitor to phase. ff 15 vin input voltage feed forward C sets on - time with a resistor to vin. en 16 5v enable pin to turn on and off the device. use two external resistors to set the turn on threshold (see electrical specifications ) for input voltage monitoring. 5 ir3863mpbf 8/8/2012 rev3.2 electrical specifications unless otherwise specified, these specification apply over vin = 12v, 4.5v 8 ir3863mpbf 8/8/2012 rev3.2 typical application circuit demoboard bill of materials figure 7. typical application circuit for vout = 1.05v, fs = 300khz t p7 t p10 en v cc t p23 v outs t p24 p gnds c26 op en c27 op en v in c7 op en c8 op en c24 op en c9 15 0uf c10 47 uf c11 op en c1 1u f r7 2.80k r8 2.55k c12 0.1uf p good ise t +3 .3 v v out v cc +3 .3v v in t p6 p gnds t p14 +3 .3v u1 ir3 863 3v cbp 8 fccm 1 ss 6 p good 3 ff 15 gnd1 4 fb 5 gnd 17 nc1 7 ise t 2 b oot 14 v in 13 v cc 10 nc2 9 p gnd 11 p ha se 12 en 16 c4 0.22u f v cc t p4 en s w1 e n / fccm 1 2 4 3 t p17 p gnd c20 0.1uf t p26 a gnd v sw c21 1u f t p11 p good r9 op en l1 2.2uh r6 op en t p1 v ins r4 10 k r3 20 0k c13 op en c2 22 uf c16 op en + c3 68 uf t p2 v in t p5 p gnd c14 op en c17 op en c18 op en t p16 v cc fb r5 10 k c15 op en r10 op en c6 op en t p18 v olt a ge s e ns e +v i ns 1 +v dd1 s 2 +v dd2 s 3 +v out1s 4 +v out2s 5 -vo ut2 s 10 -vd d2s 8 -vo ut1 s 9 -vi ns 6 -vd d1s 7 r1 10 k fccm ir3863 +3 .3v r11 20 c22 op en t p25 b c25 1u f v out t p27 a +3 .3v t p28 v id t p13 ss v sw r12 4.99 ss r2 10 k c19 op en q1 op en 2 1 3 p gnd v out r13 op en c23 op en qty ref designator value description manufacturer part number 3 c1, c21, c25 1.00uf capacitor, x7r, 1.00uf, 25v, 0.1, 0603 murata grm188r71e105ka12d 1 c10 47uf capacitor, 47uf, 6.3v, 805 tdk c2012x5r0j476m 2 c12, c20 0.100uf capacitor, x7r, 0.100uf, 25v, 0.1, 603 tdk c1608x7r1e104k 1 c2 22.0uf capacitor, x5r, 22.0uf, 16v, 20%, 1206 taiyo yuden emk316bj226ml-t 1 c3 68uf capacitor, electrolytic, 68uf, 25v, 0.2, smd panasonic eev-fk1e680p 1 c4 0.22uf capacitor, x5r, 0.22uf, 10v, 0.1, 0603 tdk C1608X5R1A224K 1 c9 150uf capacitor, tantalum polymer, 150uf, 6.3v, 20%, 7343 sanyo 6tpc150m 1 l1 2.2uh inductor, ferrite, 2.2uh, 8.0a, 11.2mohm, smt cyntec pcmb065t-2r2ms 4 r1, r2, r4, r5 10.0k resistor, thick film, 10.0k, 1/10w, 0.01, 0603 koa rk73h1j1002f 1 r11 20 resistor, thick film, 20, 1/10w, 0.01, 603 koa rk73h1jltd20r0f 1 r12 4.99 resistor, thick film, 4.99, 1/8w, 0.01, 603 koa rk73h1j4r99f 1 r3 200k resistor, thick film, 200k, 1/10w, 0.01, 603 koa rk73h1jltd2003f 1 r7 2.80k resistor, thick film, 2.80k, 1/10w, 0.01, 603 koa rk73h1jltd2801f 1 r8 2.55k resistor, thick film, 2.55k, 1/10w, 0.01, 0603 koa rk73h1jltd2551f 1 sw1 spst switch, dip, spst, 2 position, smt c&k components sd02h0sk 1 u1 ir3863 4mm x 5mm qfn irf ir3863mtrpbf 9 ir3863mpbf 8/8/2012 rev3.2 figure 8: startup figure 9: shutdown figure 10: dcm (i out = 0.1a) figure 11: ccm (i out = 5a) figure 12: over current protection (tested by shorting vout to pgnd) figure 13: over voltage protection (tested by shorting fb to vout) en pgood ss vout en pgood ss vout vout phase i l vout phase i l pgood ss iout pgood fb vout i l 5v/div 5v/div 1v/div 500mv/div 5ms/div 5v/div 5v/div 1v/div 500mv/div 1ms/div 20mv/div 10v/div 500ma/div 5 s/div 20mv/div 10v/div 2a/div 2 s/div 5v/div 1v/div 500mv/div 2a/div 50 s/div 5v/div 1v/div 1v/div 5a/div 500us/div vout typical operating data tested with demoboard shown in figure 7, vin = 12v, vcc = 5v, vout = 1.05v, fs = 300khz, t a = 25 o c, no airflow, unless otherwise specified 10 ir3863mpbf 8/8/2012 rev3.2 figure 14: load transient 0 - 2a figure 15: load transient 3 - 5a figure 18: thermal image at vin = 12v, i out = 6a (ir3863: 60 o c, inductor: 45 o c, pcb: 32 o c) vout phase i l vout phase i l 50mv/div 10v/div 2a/div 50 s/div 50mv/div 10v/div 2a/div 50 s/div figure 19: thermal image at vin = 16v, i out = 6a (ir3863: 61 o c, inductor: 46 o c, pcb: 33 o c) figure 16: dcm/fccm transition figure 17: fccm/dcm transition fccm fccm phase phase i l i l vout vout 5v/div 10v/div 500mv/div 10 s/div 5a/div 2v/div 10v/div 500mv/div 5 s/div 5a/div typical operating data tested with demoboard shown in figure 7, vin = 12v, vcc = 5v, vout = 1.05v, fs = 300khz, t a = 25 o c, no airflow, unless otherwise specified 11 ir3863mpbf 8/8/2012 rev3.2 pwm comparator the pwm comparator initiates a set signal (pwm pulse) when the fb pin falls below the reference (vref) or the soft start (ss) voltage . on - time generator the pwm on - time duration is programmed with an external resistor (r ff ) from the input supply (vin) to the ff pin . the simplified equation for r ff is shown in equation 1 . the ff pin is held to an internal reference after en goes high . a copy of the current in r ff charges a timing capacitor, which sets the on - time duration, as shown in equation 2 . control logic the control logic monitors input power sources, sequences the converter through the soft - start and protective modes, and initiates an internal run signal when all conditions are met . vcc and 3 vcbp pins are continuously monitored, and the ir 3863 will be disabled if the voltage of either pin drops below the falling thresholds . en_delay will become high when vcc and 3 vcbp are in the normal operating range and the en pin = high . soft start with en = high, an internal 10 a current source charges the external capacitor (c ss ) on the ss pin to set the output voltage slew rate during the soft start interval . the soft start time (t ss ) can be calculated from equation 3 . the feedback voltage tracks the ss pin until ss reaches the 0 . 5 v reference voltage (vref), then feedback is regulated to vref . c ss will continue to be charged, and when ss pin reaches v ss (see electrical specification ), ss_delay goes high . with en_delay = low, the capacitor voltage and ss pin is held to the fb pin voltage . a normal startup sequence is shown in figure 20 . circuit description figure 20. normal startup pgood the pgood pin is open drain and it needs to be externally pulled high . high state indicates that output is in regulation . the pgood logic monitors en_delay, ss_delay, and under/over voltage fault signals . pgood is released only when en_delay and ss_delay = high and output voltage is within the ov and uv thresholds . pre - bias startup ir 3863 is able to start up into pre - charged output, which prevents oscillation and disturbances of the output voltage . with constant on - time control, the output voltage is compared with the soft start voltage (ss) or vref, depending on which one is lower, and will not start switching unless the output voltage drops below the reference . this scheme prevents discharge of a pre - biased output voltage . shutdown the ir 3863 will shutdown if vcc is below its uvlo limit . the ir 3863 can be shutdown by pulling the en pin below its lower threshold . alternatively, the output can be shutdown by pulling the soft start pin below 0 . 3 v . (2) v 20 1 r t in ff on pf v ? ? ? (1) f 20 1 v r sw out ff ? ? ? pf v (3) a 10 5 . 0 ? v c t ss ss ? ? 12 ir3863mpbf 8/8/2012 rev3.2 under/over voltage monitor the ir 3863 monitors the voltage at the fb node through a 350 ns filter . if the fb voltage is below the under voltage threshold, uv# is set to low holding pgood to be low . if the fb voltage is above the over voltage threshold, ov# is set to low, the shutdown signal (sd) is set to high, mosfet gates are turned off, and pgood signal is pulled low . toggling vcc or en will allow the next start up . figure 21 and 22 show pgood status change when uv/ov is detected . the over voltage and under voltage thresholds can be found in the electrical specification section . over current monitor the over - current circuitry monitors the output current during each switching cycle . the voltage across the lower mosfet, vphase, is monitored for over current and zero crossing . the ocp circuit evaluates vphase for an over current condition typically 270 ns after the lower mosfet is gated on . this delay functions to filter out switching noise . the minimum lower gate interval allows time to sample vphase . the over current trip point is programmed with a resistor from the iset pin to phase pin, as shown in equation 4 . when over current is detected, the mosfet gates are tri - state and ss voltage is pulled to 0 v . this initiates a new soft start cycle . if there is a total of four oc events, the ir 3863 will disable switching . toggling vcc or en will allow the next start up . under voltage lock - out the ir 3863 has vcc and en under voltage lock - out (uvlo) protection . when either vcc or en is below their uvlo threshold, ir 3863 is disabled . ir 3863 will restart when both vcc and en are above their uvlo thresholds . figure 23. over current protection figure 21. under/over voltage monitor figure 22. over voltage protection * typical filter delay circuit description * typical filter delay (4) 19 i r r oc dson set a ? ? ? 13 ir3863mpbf 8/8/2012 rev3.2 circuit description selection of components for the converter is an iterative process which involves meeting the specifications and tradeoffs between performance and cost . the following sections will guide one through the process . inductor selection inductor selection involves meeting the steady state output ripple requirement, minimizing the switching loss of the upper mosfet, meeting transient response specifications and minimizing the output capacitance . the output voltage includes a dc voltage and a small ac ripple component due to the low pass filter which has incomplete attenuation of the switching harmonics . neglecting the inductance in series with the output capacitor, the magnitude of the ac voltage ripple is determined by the total inductor ripple current flowing through the total equivalent series resistance (esr) of the output capacitor bank . one can use equation 5 to find the required inductance . i is defined as shown in figure 24 . the main advantage of small inductance is increased inductor current slew rate during a load transient, which leads to a smaller output capacitance requirement as discussed in the output capacitor selection section . the draw back of using smaller inductances is increased switching power loss in the upper mosfet, which reduces the system efficiency and increases the thermal dissipation . component selection figure 24. typical input current waveform over temperature protection when the ir3863 exceeds its over temperature threshold, the mosfet gates are tri - state and pgood is pulled low. switching resumes once temperature drops below the over temperature hysteresis level. gate drive logic the gate drive logic features adaptive dead time, diode emulation, and a minimum lower gate interval . an adaptive dead time prevents the simultaneous conduction of the upper and lower mosfets . the lower gate voltage must be below approximately 1 v after pwm goes high before the upper mosfet can be gated on . also, the differential voltage between the upper gate and phase must be below approximately 1 v after pwm goes low before the lower mosfet can be gated on . the upper mosfet is gated on after the adaptive delay for pwm = high and the lower mosfet is gated on after the adaptive delay for pwm = low . when fccm = low, the lower mosfet is driven off when the zcross signal indicates that the inductor current is about to reverse direction . the zcross comparator monitors the phase voltage to determine when to turn off the lower mosfet . the lower mosfet stays off until the next pwm falling edge . when the lower peak of the inductor current is above zero, ir 3863 operates in continuous conduction mode . the continuous conduction mode can also be selected for all load current levels by pulling fccm to high . whenever the upper mosfet is turned off, it stays off for the min off time denoted in the electrical specifications . this minimum duration allows time to recharge the bootstrap capacitor and allows the over current monitor to sample the phase voltage . ? ? (5) l 2 v v t i out in on ? ? ? ? i n p u t c u r r e n t i i o u t t s 14 ir3863mpbf 8/8/2012 rev3.2 input capacitor selection the main function of the input capacitor bank is to provide the input ripple current and fast slew rate current during the load current step up . the input capacitor bank must have adequate ripple current carrying capability to handle the total rms current . figure 24 shows a typical input current . equation 6 shows the rms input current . the rms input current contains the dc load current and the inductor ripple current . as shown in equation 5 , the inductor ripple current is unrelated to the load current . the maximum rms input current occurs at the maximum output current . the maximum power dissipation in the input capacitor equals the square of the maximum rms input current times the input capacitors total esr . the voltage rating of the input capacitor needs to be greater than the maximum input voltage because of high frequency ringing at the phase node . the typical percentage is 25 % . component selection output capacitor selection selection of the output capacitor requires meeting voltage overshoot requirements during load removal, and meeting steady state output ripple voltage requirements . the output capacitor is the most expensive converter component and increases the overall system cost . the output capacitor decoupling in the converter typically includes the low frequency capacitor, such as specialty polymer aluminum, and mid frequency ceramic capacitors . the first purpose of output capacitors is to provide current when the load demand exceeds the inductor current, as shown in figure 25 . equation 7 shows the charge requirement for a certain load step . the advantage provided by the ir 3863 at a load step is the reduced delay compared to a fixed frequency control method . if the load increases right after the pwm signal goes low, the longest delay will be equal to the minimum lower gate on - time as shown in the electrical specification table . the ir 3863 also reduces the inductor current slew time, the time it takes for the inductor current to reach equality with the output current, by increasing the switching frequency up to 1 /( t on + min off time ) . this results in reduced recovery time . figure 25. charge requirement during load step ? ? (6) i i 3 1 1 fs t i dt t f ts 1 i 2 out on out ts 0 2 in_rms ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? t l o a d c u r r e n t i s t e p i n d u c t o r s l e w r a t e o u t p u t c h a r g e t ? ? (7b) v v i l 2 1 v 1 c (7a) t i 0.5 v c q out in 2 step drop out step ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 15 ir3863mpbf 8/8/2012 rev3.2 boot capacitor selection the boot capacitor starts the cycle fully charged to a voltage of vb( 0 ) . cg equals 0 . 6 nf in ir 3863 . choose a sufficiently small v such that vb( 0 ) - v exceeds the maximum gate threshold voltage to turn on the upper mosfet . choose a boot capacitor value larger than the calculated c boot in equation 9 . equation 9 is based on charge balance at ccm operation . usually the boot capacitor will be discharged to a much lower voltage when the circuit is operating in dcm mode at light load, due to much longer lower mosfet off time and the bias current drawn by the ic . boot capacitance needs to be increased if insufficient turn - on of the upper mosfet is observed at light load, typically larger than 0 . 1 f is needed . the voltage rating of this part needs to be larger than vb( 0 ) plus the desired derating voltage . its esr and esl needs to be low in order to allow it to deliver the large current and di/dts which drive mosfets most efficiently . in support of these requirements a ceramic capacitor should be chosen . vesr is usually much greater than vesl . the ir 3863 requires a total esr such that the ripple voltage at the fb pin is greater than 7 mv . the second purpose of the output capacitor is to minimize the overshoot of the output voltage when the load decreases as shown in figure 26 . by using the law of energy before and after the load removal, equation 8 shows the output capacitance requirement for a load step down . the output voltage drop, v drop , initially depends on the characteristic of the output capacitor . v drop is the sum of the equivalent series inductance (esl) of the output capacitor times the rate of change of the output current and the esr times the change of the output current . figure 26. typical output voltage response waveform component selection (8) v v i l c 2 out 2 os 2 step out ? ? ? i o u t i s t e p v o u t v l v e s r v o s v d r o p (9) 1 v (0) v c c b g boot ? ? ? ? ? ? ? ? ? 16 ir3863mpbf 8/8/2012 rev3.2 design example design criteria: input voltage, vin, = 7v to 16v output voltage, vout = 1.5v switching frequency, fs = 300khz inductor ripple current, 2i = 1.5a maximum output current, iout = 6a over current trip, ioc = 9a overshoot allowance for 3a load step down, vos = vout + 50mv undershoot allowance for 3a load step up, vdrop = 50mv find r ff : pick a standard value 255 k, 1% resistor. find r set : choose an input capacitor : a panasonic 10 f (ecj 3 yb 1 e 106 m) accommodates 6 arms of ripple current at 300 khz . due to the chemistry of multilayer ceramic capacitors, the capacitance varies over temperature and operating voltage, both ac and dc . one 10 f capacitor is recommended . in a practical solution, one 1 f capacitor is required along with 10 f . the purpose of the 1 f capacitor is to suppress the switching noise and deliver high frequency current . choose an output capacitor : to meet the undershoot and overshoot specification, equation 7 b and 8 will be used to calculate the minimum output capacitance . as a result, 130 f will be needed for 3 a load removal . to meet the stability requirement, choose an output capacitors with esr larger than 16 m . combine those two requirements, one can choose a set of output capacitors from manufactures such as sp - cap (specialty polymer capacitor) from panasonic or poscap from sanyo . a 150 f ( 4 tpe 150 m) from sanyo with 25 m esr will meet both requirements . if an all ceramic output capacitor solution is desired, the external slope injection circuit composed of r 6 , c 13 , and c 14 is required as explained in the stability consideration section . in this design example, we can choose c 14 = 1 nf and c 13 = 100 nf . to calculate the value of r 6 with pcmb 065 t - 3 r 3 ms as our inductor : pick a standard value for r 6 = 1 . 65 k . pick a 9 . 53 k, 1 % standard resistor . find a resistive voltage divider for v out = 1 . 5 v : choose the soft start capacitor : once the soft start time has chosen, such as 1000 us to reach to the reference voltage, a 22 nf for c ss is used to meet 1000 s . choose an inductor to meet the design specification : r 2 = 1 . 40 k , r 1 = 2 . 80 k, both 1 % standard resistors . choose an inductor with low dcr and ac power loss to increase the overall system efficiency based on allowed physical size requirement . for instance, pcmb 065 t - 3 r 3 ms from cyntec is a 7 mm x 6 . 6 mm inductor with 19 . 9 m dcr . however, if space allows, pimb 104 t - 3 r 3 ms - 39 ( 11 mm x 10 mm) with 10 . 8 m dcr will provide higher efficiency . ripple current needs to be recalculated using the chosen inductor . a a a v v a 8 . 1 6 2 / 37 . 1 3 1 1 6 1 1.5 6 i 2 in_rms ? ? ? ? ? ? ? ? ? ? ? ? k 50 2 300k 20 1 1.5 r ff ? ? ? ? ? hz pf v v ? ? ? ? ? k 5 . 9 9 1 9 20.1m r set a a ? ? ? ? ? h hz a v v v v ? 3.0 300k 5 . 1 6 1 1.5 - 6 1 1.5 f i 2 v v v v l s in out in out ? ? ? ? ? ? ? ? ? ? ? ? a hz h v v v v i 37 . 1 300k 3 . 3 6 1 1.5 - 6 1 1.5 2 ? ? ? ? ? ? v 0.5 v r r r v out 1 2 2 fb ? ? ? ? ? ? ? ? ? ? ? k nf m h c dcr l r 66 . 1 100 9 . 19 3 . 3 13 6 ? 17 ir3863mpbf 8/8/2012 rev3.2 layout recommendations bypass capacitor : as vcc bypass capacitor, a 1 f high quality ceramic capacitor should be placed on the same side as the ir 3863 and connected to vcc and pgnd pins directly . a 1 f ceramic capacitor should be connected from 3 vcbp to agnd to avoid noise coupling into controller circuits . for single - ground designs, a resistor (r 12 ) in the range of 5 to 10 in series with the 1 f capacitor as shown in figure 7 is recommended . boot circuit : c boot should be placed near the boot and phase pins to reduce the impedance when the upper mosfet turns on . power stage : figure 27 shows the current paths and their directions for the on and off periods . the on time path has low average dc current and high ac current . therefore, it is recommended to place the input ceramic capacitor, upper, and lower mosfet in a tight loop as shown in figure 27 . the purpose of the tight loop from the input ceramic capacitor is to suppress the high frequency ( 10 mhz range) switching noise and reduce electromagnetic interference (emi) . if this path has high inductance, the circuit will cause voltage spikes and ringing, and increase the switching loss . the off time path has low ac and high average dc current . therefore, it should be laid out with a tight loop and wide trace at both ends of the inductor . lowering the loop resistance reduces the power loss . the typical resistance value of 1 - ounce copper thickness is 0 . 5 m per square inch . figure 27. current path of power stage stability considerations constant - on - time control is a fast , ripple based control scheme . unstable operation can occur if certain conditions are not met . the system instability is usually caused by : ? switching noise coupled to fb input : this causes the pwm comparator to trigger prematurely after the 400 ns minimum on - time for lower mosfet . it will result in double or multiple pulses every switching cycle instead of the expected single pulse . double pulsing can causes higher output voltage ripple, but in most application it will not affect operation . this can usually be prevented by careful layout of the ground plane and the fb sensing trace . ? steady state ripple on fb pin being too small : the pwm comparator in ir 3863 requires minimum 7 mvp - p ripple voltage to operate stably . not enough ripple will result in similar double pulsing issue described above . solving this may require using output capacitors with higher esr . ? esr loop instability : the stability criteria of constant on - time is : esr*cout>ton/ 2 . if esr is too small that this criteria is violated then sub - harmonic oscillation will occur . this is similar to the instability problem of peak - current - mode control with d> 0 . 5 . increasing esr is the most effective way to stabilize the system, but the tradeoff is the larger output voltage ripple . ? system with all ceramic output capacitors : for applications with all ceramic output capacitors, the esr is usually too small to meet the stability criteria . in these applications, external slope compensation is necessary to make the loop stable . the ramp injection circuit, composed of r 6 , c 13 , and c 14 , shown in figure 7 is required . the inductor current ripple sensed by r 6 and c 13 is ac coupled to the fb pin through c 14 . c 14 is usually chosen between 1 to 10 nf, and c 13 between 10 to 100 nf . r 6 should then be chosen such that l/dcr = c 13 *r 6 . q1 q2 18 ir3863mpbf 8/8/2012 rev3.2 pcb metal and components placement lead lands (the 13 ic pins) width should be equal to nominal part lead width . the minimum lead to lead spacing should be 0 . 2 mm to minimize shorting . lead land length should be equal to maximum part lead length + 0 . 3 mm outboard extension . the outboard extension ensures a large toe fillet that can be easily inspected . pad lands (the 4 big pads) length and width should be equal to maximum part pad length and width . however, the minimum metal to metal spacing should be no less than 0 . 17 mm for 2 oz . copper, or no less than 0 . 1 mm for 1 oz . copper, or no less than 0 . 23 mm for 3 oz . copper . 19 ir3863mpbf 8/8/2012 rev3.2 solder resist it is recommended that the lead lands are non solder mask defined (nsmd) . the solder resist should be pulled away from the metal lead lands by a minimum of 0 . 025 mm to ensure nsmd pads . the land pad should be solder mask defined (smd), with a minimum overlap of the solder resist onto the copper of 0 . 05 mm to accommodate solder resist misalignment . ensure that the solder resist in between the lead lands and the pad land is 0 . 15 mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land . 20 ir3863mpbf 8/8/2012 rev3.2 stencil design the stencil apertures for the lead lands should be approximately 80 % of the area of the lead lads . reducing the amount of solder deposited will minimize the occurrences of lead shorts . if too much solder is deposited on the center pad the part will float and the lead lands will open . the maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0 . 2 mm pull back in order to decrease the risk of shorting the center land to the lead lands when the part is pushed into the solder paste . 21 ir3863mpbf 8/8/2012 rev3.2 ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 - 7105 tac fax: (310) 252 - 7903 this product has been designed and qualified for the industrial market (note 2) visit us at www.irf.com for sales contact information data and specifications subject to change without notice. 03/12 |
Price & Availability of C1608X5R1A224K
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |