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pc-tel, inc. 1 1789w0docdat06a-0299 PCT303DW data sheet ! ! preliminary preliminary PCT303DW f e a t u r es complete daa includes: ? programmable line interface ? ac termination ? dc termination ? ringer impedance ? ringer threshold ? 86 db dynamic range tx/rx paths ? integrated ring detector ? up to 4000 v isolation ? support for caller id ? low-profile soic packages ? low power consumption (15mw operating @3.3v) ? 3.3 or 5 v analog/digital power supply ? direct interface to dsps ? integrated analog front end (afe) ? 2?4-wire hybrid ? daisy-chaining for up to eight devices PCT303DW a pp l i c a t i o n s ? modems ? phone line interface systems PCT303DW f un c t i o n a l d es c r i p t i o n the PCT303DW is an integrated direct access arrangement (daa) that provides a programmable line interface to meet international telephone line requirements. available in two 16-pin small outline packages, it eliminates the need for an analog front end (afe), an isolation transformer, relays, opto-isolators, and 2- to 4-wire hybrid. the PCT303DW dramatically reduces the number of discrete components and cost required to achieve compliance with international regulatory requirements. the PCT303DW interfaces directly to standard modem dsps. PCT303DW f un c t i o n a l b l o ck d i a g r a m PCT303DW chip set digital interface control interface isolation interface hybrid ring detect off-hook mclk sclk fsync sdi sdo fc/ rgdt rgdt /fsd ofhk mode rx vreg vreg2 rext rext2 rng1 rng2 qb qe reset pct303 w pct303d isolation interface and dc termination qe2 filt filt2 ref dct
pc-tel, inc. 6 1789w0docdat06a-0299 pct1789w data sheet PCT303DW a p p l i c a t i o n c i r c u i t s ! ! preliminary preliminary PCT303DW a p p l i c a t i o n c i r c u i t s typical application (ctr21 international design) figure 2 PCT303DW typical applications circuit (crt21 international design) p c t 3 0 3 w p c t 3 0 3 d
pc-tel, inc. 7 1789w0docdat06a-0299 pct1789w data sheet PCT303DW a p p l i c a t i o n c i r c u i t s ! ! preliminary preliminary typical application component values table 1 PCT303DW typical application component values (ctr21 international design) symbol north american value international value c1 150pf, 2kv, x7r,20% 150pf, 3kv, x7r, 20% c2,c4 1000pf, 2kv, x7r, 20% 1000pf, 3kv, x7r, 20% c3,c10 0.1f, 16v, x7r, 20% same as north american c5 0.47f, 16v, x7r, 20% 0.1f, 50v, x7r, 20% c6 0.047f, 16v, x7r, 20% 0.1f, 16v, x7r, 20% c7,c8 2200pf, 250v, x7r, 20% 680pf, 250v, x7r, 20% c9 15nf, 250v, x7r, 20% 22nf, 250v, x7r, 10% c11 5600pf, 16v, x7r, 20% not installed c12 not installed 0.22f, 16v, x7r, 20% c13,c16 not installed 0.1f, 16v, x7r, 20% c14 not installed 560nf,16v, x7r, 20% c15 a not installed 0.47f, 250v, 20% c18,c19 not installed 3900pf,16v, x7r, 20% c20 not installed 47pf, 250v, x7r, 20% r1 51 w , 1/2w 5% not installed r2 15 w , 1/4w 5% 402 w , 1/10 w, 1% r3 b 10 w , 1/10w, 5% same as north american r4 604 w , 1/4w, 1% not installed r5 36k w , 1/10w 5% same as north american r6 36k w , 1/10w 5% 121k w , 1/10w, 5% r7,r8,r15,r16,r17,r19 not installed 4.87k w , 1/4w, 1% r9,r10 10k w , 1/4w 5% 30k w , 1/4w, 5% r11 not installed 10k w , 1/10w, 1% r12 not installed 140 w , 1/10w, 1% r13 not installed 442 w , 1/10w, 1% r14 a not installed 18.7k w , 1/4w, 1% r18 0 w 2.2k w , 1/10w, 5% z1 zener diode, 18v not installed z2,z3 a not installed zener diode, 3v q1,q3 motorola mmbta42lt1 same as north american q2 motorola mmbta92lt1 same as north american q4 not installed motorola pzt2222at1, 1/2w d1?d4 1n4004 same as north american fb1,fb2 ferrite bead same as north american rv1 sidactor 275v, 100a same as north american a. c14, r15, z2, and z3 required only for south africa support. b. r3 not required when charge pump is enabled.
pc-tel, inc. 8 1789w0docdat06a-0299 pct1789w data sheet PCT303DW a p p l i c a t i o n c i r c u i t s ! ! preliminary preliminary analog output figure 3 illustrates an optional application circuit to support the analog output capability of the PCT303DW for call progress monitoring purposes. figure 3 optional connection to aout for a call progress speaker ? + ? aout speaker +5v 3 2 c1 c2 c3 c4 c5 r1 r2 6 4 5 r3 + c6 u1 table 2 optional connection component values symbol value c1 2200pf, 16v, 20% c2, c3, c5 0.1f, 16v, 20% c4 100f, 16v, elec. 20% c6 820pf, 16v, 20% r1 10k w , 1/10w, 5% r2 10 w , 1/10w, 5% r3 47k w , 1/10w, 5% u1 lm386
pc-tel, inc. 14 1789w0docdat06a-0299 pct1789w data sheet PCT303DW p i n o u t s ! ! preliminary preliminary PCT303DW p i n o u t s pct303d pinout figure 5 pct303d 16-pin soic pct303w pinout figure 6 pct303w 16-pin soic 1 2 3 4 5 6 7 8 9 10 11 12 13 16 15 14 ofhk rgdt /fsd m0 va gnd c1a m1 aout mclk fsync sclk vd sdo sdi fc/ rgdt reset 1 2 3 4 5 6 7 8 9 10 11 12 13 16 15 14 filt2 filt rx rext rext2 ref vreg2 vreg qe2 dct ignd c1b rng1 rng2 qb qe
pc-tel, inc. 15 1789w0docdat06a-0299 pct1789w data sheet PCT303DW p i n d e s c r i p t i o n s ! ! preliminary preliminary PCT303DW p i n d e s c r i p t i o n s pct303d pin description table 5 pct303d pin description name number i/o description serial interface mclk 1 master clock input. high speed master clock input. generally supplied by the system crystal clock or modem/dsp. sclk 3 serial port bit clock output. controls the serial data on sdout and latches the data on sdin. sdi 6 serial port data in. serial communication and control data that is generated by the modem/dsp and presented as an input to the pct303d. sdo 5 serial port data out. serial communication data that is provided by the pct303d to the modem/dsp. fsync 2 frame sync output. data framing signal that is used to indicate the start and stop of a communication data frame. fc/ rgdt 7 secondary transfer request input/ring detect. as fc, this pin is an optional signal to instruct the pct303d that control data is being requested in a secondary frame. when daisy-chain is enabled, this pin becomes the ring detect output, rgdt , which pro- duces an active-low, half-wave rectified version of the ring signal. control interface rgdt / fsd 15 ring detect/delayed frame sync. as rgdt , this pin is an output signal that indicates the status of a ring signal, which produces an active-low, half-wave rectified version of the ring signal. when daisy-chain is enabled, this signal becomes a delayed frame sync, fsd, to drive a slave device. ofhk 16 off hook. input control signal that provides a termination across tip and ring for line seizing and pulse dialing, active-low. reset 8 reset input. an active-low input that is used to reset all control registers to a defined, initialized state. also used to bring the PCT303DW out of sleep mode. m0 14 mode select 0. one of two mode select pins that is used to select the operation of the serial port/dsp interface. m1 10 mode select 1. the second of two mode select pins that is used to select the operation of the serial port/dsp interface. miscellaneous signals aout 9 analog speaker output. provides an analog output signal for driving a call progress speaker. c1a 11 isolation capacitor 1a. connects to one side of the isolation capacitor c1. power signals vd 4 digital supply voltage. provides the digital supply voltage to the pct303d. nominally either 5v or 3.3v. va 13 analog supply voltage. provides the analog supply voltage for the pct303d. nomi- nally either 5v or 3.3v. the 3.3v supply is internally generated with an on-chip charge pump set through a control register. gnd 12 ground. connects to the system digital ground.
pc-tel, inc. 16 1789w0docdat06a-0299 pct1789w data sheet p i n c o m p a r i s o n o f pct301l a n d pct303w ! ! preliminary preliminary pct303w pin descriptions p i n c o m p a r i s o n o f pct301l a n d pct303w table 6 pct303w pin descriptions name number i/o description line interface filt 15 filter. sets the time constant for the dc termination circuit. filt2 16 filter 2. sets the time constant for the dc termination circuit. rx 14 receive input. serves as the receive side input from the telephone network. dct 2 dc termination. provides dc termination to the telephone network. rext 13 external resistor. sets the real ac termination impedance. rext2 12 external resistor 2. sets the complex ac termination impedance. rng1 5 ring 1. connects through a 680pf capacitor to the ?tip? lead of the telephone line. pro- vides the ring and caller id signals to the PCT303DW. rng2 6 ring 2. connects through a 680pf capacitor to the ?ring? lead of the telephone line. provides the ring and caller id signals to the PCT303DW. qb 7 transistor base. connects to the base of transistor q3. qe 8 transistor emitter. connects to the emitter of transistor q3. qe2 1 transistor emitter 2. connects to the emitter of transistor q4. ref 11 reference. connects to an external resistor to provide a high-accuracy reference cur- rent. isolation c1b 4 isolation capacitor 1b. connects to one side of isolation capacitor c1. ignd 3 isolated ground. connects to ground on the line-side interface. also connects to capac- itor c2. miscellaneous signals vreg 9 voltage regulator. connects to an external capacitor to provide bypassing for an inter- nal power supply. vreg2 10 voltage regulator 2. connects to an external capacitor to provide bypassing for an internal power supply. table 7 pct301l/pct303w pin comparison pin number pin name pin number pin name pct301l pct303w pct301l pct303w 1 tsta qe2 9 vreg vreg 2 tstb dct 10 nc vreg2 3 ignd ignd 11 nc ref 4 c1b c1b 12 dct rext2 5 rng1 rng1 13 rext rext 6 rng2 rng2 14 rx rx 7 qb qb 15 nc filt 8 qe qe 16 tx filt2
pc-tel, inc. 17 1789w0docdat06a-0299 pct1789w data sheet PCT303DW f u n c t i o n a l d e s c r i p t i o n ! ! preliminary preliminary PCT303DW f u n c t i o n a l d e s c r i p t i o n the PCT303DW is an integrated direct access arrangement (daa) that provides a programmable line interface to meet international telephone-line requirements. the device implements silicon laboratories? proprietary isolink ? technology which offers the highest level of integration by replacing an analog front end (afe), an isolation transformer, relays, opto-isolators, and a 2?4-wire hybrid with two 16-pin small outline packages (soic). the chipset can be fully programmed to meet international requirements, and the device is compliant with fcc, net4, ctr21, jate, and country-specific ptt specifications. in addition, the PCT303DW has been designed to meet the most stringent world-wide requirements for out-of-band energy, billing-tone immunity, lightning surges, and safety requirements. the PCT303DW solution needs only a few low-cost discrete components to achieve global compliance. see figure2 on page 6 for a typical application circuit. isolation barrier the PCT303DW achieves an isolation barrier through a low-cost, high-voltage capacitor in conjunction with isolink signal processing techniques. these techniques eliminate any signal degradation due to capacitor mismatches, common mode interference, or noise coupling. as shown in figure 2, the c1, c2, and c4 capacitors isolate the pct303d (dsp side) from the pct303w (line side). all transmit, receive, control, and caller id data are communicated through this barrier. the isolation pass is disabled by default. to enable it, the pdl bit in register 6 must be cleared. no communication between the pct303d and pct303w can occur until this bit is cleared. the clock generator must be programmed to an acceptable sample rate prior to clearing the pdl bit. ac termination the PCT303DW supports international ac termination requirements with two selectable impedances, one real and one complex. mode 0 is a nominal 600-ohm termination that supports the fcc 68 requirement in addition to the requirement of many european countries. mode 1 is a complex impedance as dictated by countries such as the uk and germany, and also specified by ctr21. this complex impedance is set by circuitry internal to the PCT303DW as well as the external components connected to rext2. dc termination the PCT303DW has four programmable modes related to dc termination. two bits in register 16 (dct1, dct0) set the dc characteristics. while the modes are designed to support the extreme conditions in various countries, the user can determine if a line in a given country can support a mode with a higher transmit power level and switch to the appropriate mode. this decision will depend on the amount of loop current available on the line. mode 1 (0,1) is a low-voltage mode with no current limiting; it supports transmit signals up to ?2.71 dbm. the low voltage requirement is dictated by countries such as japan and australia. see figure 7. figure 7 mode 1 i/v characteristics (0,1) mode 2 (1,0) is the default dc termination mode, with no current limiting, providing a maximum transmit level of ?1 dbm at tip and ring. this mode meets fcc requirements in addition to the requirements of many european countries. figure 8 shows the i/v characteristics of mode 2. 10.5 10 9.5 9 8.5 8 7.5 7 6.5 .01 .02 .03 .04 .05 .06 .07 .08 .09 .1 loop current (a) mode 1 v o l t a g e a c r o s s d a a ( v ) 6 5.5 .11
pc-tel, inc. 18 1789w0docdat06a-0299 pct1789w data sheet PCT303DW f u n c t i o n a l d e s c r i p t i o n ! ! preliminary preliminary figure 8 mode 2 i/v characteristics (1,0) mode 3 (1,1) provides current limiting, while maintaining a transmit level of ?1 dbm at tip and ring. figure 9 shows the i/v characteristics of mode 3. in mode 3, the dc termination will current limit before reaching 60 ma. figure 9 mode 3 i/v characteristics (1,1) the PCT303DW can be fully programmed to meet international requirements, and the device is compliant with fcc, net4, ctr21, jate, and country-specific ptt specifications. figure 2 outlines a limited set of line interface configurations required to support ctr21 and other key countries by setting different ac and dc termination modes. see ? appendix: net4 country support ? on page65 for a more complete set of the line interface configurations required to support net4 countries. ring detection the ring signal is capacitively coupled from tip and ring to the rng1 and rng2 pins. the PCT303DW supports either full- or half-wave ring detection. with full-wave ring detection, the designer can detect a polarity reversal as well as the ring signal. the ring detector output can be monitored in one of three ways. the first method uses the rgdt pin. the second method uses the register bits rdtp, rdtn, and rdt of register 5. the final method uses the sdo output. the dsp must detect the frequency of the ring signal in order to distinguish a ring from pulse dialing by telephone equipment connected in parallel. if necessary, the dsp can estimate the amplitude of the ring signal based on the ring detect threshold and the duty cycle of the ring detector output. the PCT303DW can be programmed for both ringer impedance and ringer threshold as described in the ? appendix: net4 country support ? on page65. 12 11 10 9 8 7 6 mode 2 .01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11 loop current (a) v o l t a g e a c r o s s d a a ( v ) 45 40 35 30 25 20 15 10 5 .015 .02 .025 .03 .035 .04 .045 .05 .055 .06 loop current (a) mode 3 v o l t a g e a c r o s s d a a ( v ) table 8 line interface configurations (register 16) country ac termina- tion dc termination bit 5 bit 4 bit 3 1. fcc 0 1 0 2. australia 1 0 1 3. japan 0 0 1 4. new zealand 1 1 0 5. singapore a a. support for loop currents greater than or equal to 20 ma. 0 0 1 6. south africa 1 1 0 7. ctr21 b , c b. the PCT303DW can also be configured to meet the individual specifications for these countries. (see ? appendix: net4 country support ? on page65.) c. ctr21 includes austria, belgium, denmark, finland, france, germany, greece, hungary, iceland, ireland, italy, liechtenstein, luxembourg, netherlands, norway, portugal, spain, sweden, switzerland, and the uk. 1 1 1
pc-tel, inc. 19 1789w0docdat06a-0299 pct1789w data sheet PCT303DW f u n c t i o n a l d e s c r i p t i o n ! ! preliminary preliminary billing tone immunity in some countries, billing tones generated by the central office can cause modem connection difficulties. the PCT303DW enables the modem developer to provide feedback to the user for problems associated with billing tones on the line. billing tone detection is enabled by setting the bte bit of register 16. depending on line conditions, the billing tone can be large enough to cause major errors related to the modem data. if this situation occurs, the btd bit of register 17 is set. this bit remains set until the user sets it to zero or a reset of the device is executed. the billing tone may only be large enough to overdrive the receive input. in this case, the rov bit of register 17 is set, indicating an overdrive situation. this bit remains set until set to zero or a reset is executed. lightning test the PCT303DW meets the lightning test requirements of en6100-4-5 and fcc part 68. safety and isolation the PCT303DW meets the requirements of the european safety specification en60950 as well as the requirements of fcc part 68 and ul. off-hook the communication system generates an off-hook command by applying logic 0 to the ofhk pin or writing a logic 1 to bit 0 of control register 5. the ofhk pin must be enabled by setting bit 1 (ohe) of register 5. with ofhk at logic 0, the system is in an off-hook state. this state is used to seize the line for incoming/outgoing calls and can also be used for pulse dialing. with ofhk at logic 1, negligible dc current flows through the hookswitch. when a logic 0 is applied to the ofhk pin, the hookswitch transistor pair, q1 & q2, turn on. the net effect of the off-hook signal is the application of a termination impedance across tip and ring and the flow of dc loop current. the termination impedance has both an ac and dc component. when executing an off-hook sequence, the PCT303DW requires 4620/fs clock cycles to complete the off-hook and provide phone-line data on the serial link. this includes the 12/fs filter group delay. if necessary, for the shortest delay, a higher fs may be established prior to executing the off-hook, such as an fs of 10.286 khz. digital interface the PCT303DW has two serial interface modes that support most standard modem dsps. the m0 and m1 mode pins select the interface mode. the key difference between these two serial modes is the operation of the fsync signal. table 9 summarizes the serial mode definitions. table 9 serial modes mode m1 m0 description 0 0 0 fsync frames data 1 0 1 fsync pulse starts data frame 2 1 0 slave mode 3 1 1 reserved rng1/ rng2 rgdt sdo digitized line signal figure 10 ring detect timing 0.5?1.5 sec. data > 0.2 sec. first ring 0.2?3.0 seconds
pc-tel, inc. 20 1789w0docdat06a-0299 pct1789w data sheet PCT303DW f u n c t i o n a l d e s c r i p t i o n ! ! preliminary preliminary the digital interface consists of a single, synchronous serial link which communicates both telephony and control data. in serial mode 0 or 1, the pct303d operates as a master, where the master clock (mclk) is an input, the serial data clock (sclk) is an output, and the frame sync signal ( fsync ) is an output. the mclk frequency and the value of the sample rate control registers 7, 8, 9 and 10 determine the sample rate (fs). the serial port clock, sclk, runs at 256 bits per frame, where the frame rate is equivalent to the sample rate. refer to ? clock generation subsystem ? on page23 for more details on programming sample rates. the PCT303DW transfers 16-bit or 15-bit telephony data in the primary timeslot and 16-bit control data in the secondary timeslot. figure 11 and figure 12 show the relative timing of the serial frames. primary frames occur at the frame rate and are always present. to minimize overhead in the external dsp, secondary frames are present only when requested. two methods exist for transferring control information in the secondary frame. the default power-up mode uses the lsb of the 16-bit transmit (tx) data word as a flag to request a secondary transfer. in this mode, only 15-bit tx data is transferred, resulting in a loss of snr but allowing software control of the secondary frames. as an alternative method, the fc pin can serve as a hardware flag for requesting a secondary frame. the external dsp can turn on the 16-bit tx mode by setting the sb bit of register 1. in the 16-bit tx mode, the hardware fc pin must be used to request secondary transfers. figure 13 and figure 14 illustrate the secondary frame read cycle and write cycle, respectively. during a read cycle, the r/ w bit is high and the 5-bit address field contains the address of the register to be read. the contents of the 8-bit control register are placed on the sdo signal. during a write cycle, the r/ w bit is low and the 5-bit address field contains the address of the register to be written. the 8-bit data to be written immediately follows the address on sdi. only one register can be read or written during each secondary frame. see ? PCT303DW control registers ? on page41 for the register addresses and functions. in serial mode 2, the pct303d operates as a slave device, where the mclk is an input, the sclk is a no connect, and the fsync is an input. in addition, the rgdt /fsd pin operates as a delayed frame sync (fsd) and the fc/ rgdt pin operates as ring detect ( rgdt ). note that in this mode, fc operation is not supported. xmt data secondary fsync primary secondary primary communications frame 1 (cf1) (cf2) fc 0 secondary update xmt data rcv data d15-d1 d0=1 (software fc bit) 128 sclks 256 sclks 16 sclks sdi sdo rcv data update figure 11 software fc/ rgdt secondary request
pc-tel, inc. 21 1789w0docdat06a-0299 pct1789w data sheet PCT303DW f u n c t i o n a l d e s c r i p t i o n ! ! preliminary preliminary xmt data secondary update fsync communications frame 1 (cf1) (cf2) fc 0 rcv data secondary update xmt data rcv data d15-d0 128 sclks 256 sclks 16 sclks sdi sdo primary secondary primary figure 12 hardware fc/ rgdt secondary request figure 13 secondary communication data format - read cycle d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a a a a a d d d d d d d d fsync sdi sdo 1 0 0 r/w fsync (mode 0) (mode 1) d7 d0
pc-tel, inc. 22 1789w0docdat06a-0299 pct1789w data sheet PCT303DW f u n c t i o n a l d e s c r i p t i o n ! ! preliminary preliminary clock generation subsystem the PCT303DW contains an on-chip clock generator. using a single mclk input frequency, the PCT303DW can generate all the desired standard modem sample rates, as well as the common 11.025 khz rate for audio playback. the clock generator consists of two phase-locked loops (pll1 and pll2) that achieve the desired sample frequencies. figure 15 illustrates the clock generator. the architecture of the dual pll scheme allows for fast lock time on initial start-up, fast lock time when changing modem sample rates, high noise immunity, and the ability to change modem sample rates with a single register write. a large number of mclk frequencies between 1mhz and 60mhz are supported. in serial mode 2, the pct303d operates as a slave device. the clock generator is configured (by default) to set the sclk output equal to the mclk input. the net effect is the clock generator multiplies the mclk input by 20. programming the clock generator as noted in figure 15, the clock generator must output a clock equal to 1024*fs, where fs is the desired sample rate. the 1024*fs clock is determined through programming of the following registers: register 7?n1 divider, 8 bits. register 8?m1 divider, 8 bits. register 9?n2/m2 dividers, 4 bits/4 bits. register 10?cgm, 1 bit. when using the PCT303DW for modem applications, the clock generator can be programmed to allow for a single register write to change the modem sampling rate. these standard sample rates are shown in table 10. the programming method is described below. the main design consideration is the generation of a base frequency, defined as the following: n1 (register 7) and m1 (register 8) are 8-bit unsigned values. f mclk is the clock provided to the mclk pin. table 11 lists several standard crystal oscillator rates that could be supplied to mclk. this list simply represents a sample of mclk frequency choices. many more are possible. d15 d14 d13 d12 d11 d10 d9 d8 a a a a a fsync sdi sdo 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 d d d d d d d d r/w fsync (mode 1) (mode 0) figure 14 secondary communication data format - write cycle table 10 n2, m2 values (cgm = 0, 1) fs (hz) n2 m2 7200 2 2 8000 9 10 8229 7 8 8400 6 7 9000 4 5 9600 3 4 10286 7 10 f base f mclk m 1 n 1 ----------------------------------36.864 mhzcgm ,0 === f base f mclk m 1 16 n 125 ----------------------------------------------36.864 mhzcgm ,1 ===
pc-tel, inc. 23 1789w0docdat06a-0299 pct1789w data sheet PCT303DW f u n c t i o n a l d e s c r i p t i o n ! ! preliminary preliminary after the first pll has been setup, the second pll can be programmed easily. the values for n2 and m2 (register 9) are shown in table 10. n2 and m2 are 4-bit unsigned values. when programming the registers of the clock generator, the order of register writes is important. for pll1 updates, n1 (register 7) must always be written first, immediately followed by a write to m1 (register 8). for pll2, the cgm bit must set as desired prior to writing n2/m2 (register 9). changes to cgm only take effect when n2/m2 are written. note: the values shown in table 10 and table 11 satisfy the equations above. however, when programming the registers for n1, m1, n2, and m2, the value placed in these registers must be one less than the value calculated from the equations. for example, for cgm = 0 with a mclk of 48.0mhz, the values placed in the n1 and m1 registers would be 7ch and 5fh, respectively. if cgm = 1, a non-zero value must be programmed to register 9 in order for the 16/25 ratio to take effect. pll lock times the PCT303DW changes sample rates very quickly. however, lock time varies based on the programming of the clock generator. the major factor contributing to pll lock time is the cgm bit. when the cgm bit is used (set to one), pll2 locks slower than when cgm is zero. the following relationships describe the boundaries on pll locking time: pll1 lock time < 1 ms (cgm = 0,1) pll2 lock time <100 us (cgm = 0) pll2 lock time <1 ms (cgm = 1) for modem designs, it is recommended that pll1 be programmed during initialization. no further programming of pll1 is necessary. the cgm bit and pll2 can be programmed for the desired initial sample rate, typically 7200 hz. all further sample rate changes are made by simply writing to register 9 to update pll2. the final design consideration for the clock generator is the update rate of pll1. the following criteria must be satisfied in order for the plls to remain stable: where f up1 is shown in figure 15. setting generic sample rates the above clock generation description focuses on the common modem sample rates. an application may require a sample rate not listed in table 10, such as the common audio rate of 11.025 khz. the restrictions and equations above still apply; however, a more generic relationship between mclk and fs (the desired sample rate) is needed. the following equation describes this relationship: ? m1 vco1 p d ? 25 ? n2 p d 0 1 0 1 ? 16 mclk 8 bits 8 bits f up1 f pll1 f pll2 4 bits 1024fs pll1 f up2 cgm cgm ? n1 ? 5 ? m2 4 bits pll2 vco2 figure 15 clock generation subsystem f up1 f mclk n1 () =144 khz 3 ?m1??m2? ?n1??n2? ---------------------------------- ratio 51024 fs ?mclk? -------------------------------- =
pc-tel, inc. 24 1789w0docdat06a-0299 pct1789w data sheet PCT303DW f u n c t i o n a l d e s c r i p t i o n ! ! preliminary preliminary where fs is the sample frequency, ratio is 1 for cgm=0 and 25/16 for cgm = 1, and all other symbols are shown in figure 15. knowing the mclk frequency and desired sample rate the values for the m1, n1, m2, n2 registers can be determined. when determining these values, remember to consider the range for each register as well as the minimum update rate for the first pll. the values determined for m1, n1, m2, and n2 must be adjusted by minus one when determining the value written to the respective registers. this is due to internal logic, which adds one to the value stored in the register. this addition allows the user to write a zero value in any of the registers and the effective divide by is one. a special case occurs when both m1 and n1 and/or m2 and n2 are programmed with a zero value. when mx and nx are both zero, the corresponding pllx is bypassed. note that if m2 and n2 are set to zero, the ratio of 25/16 is eliminated and cannot be used in the above equation. in this condition the cgm bit has no effect. power management the PCT303DW supports four basic power management operation modes. the modes are normal operation, reset operation, sleep mode, and full power down mode. the power management modes are controlled by the pdn and pdl bits of register 6. on power up, or following a reset, the PCT303DW is in reset operation. in this mode, the pdl bit is set, while the pdn bit is cleared. the pct303d is fully operational, except for the isolink. no communication between the pct303d and pct303w can occur during reset operation. note, any bits associated with the pct303w are not valid in this mode. the most common mode of operation is the normal operation. in this mode, the pdl and pdn bits are cleared. the pct303d is fully operational and the isolink is communicating information between the pct303d and the pct303w. note that the clock generator must be programmed to a valid sample rate prior to entering this mode. the PCT303DW supports a low-power sleep mode. this mode supports the popular wake-up-on-ring feature of many modems. the clock generator registers 7, 8, and 9 must be programmed with valid non-zero values prior to enabling sleep mode. then, the pdn bit must be set and the pdl bit cleared. when the PCT303DW is in sleep mode, the mclk signal may be stopped or remain active, but it must be active before waking up the PCT303DW. the pct303d is non- functional except for the isolink and rgdt signal. to take the PCT303DW out of sleep mode, pulse the reset pin ( reset ) low. in summary, the power down/up sequence for sleep mode is as follows: 1. registers 7, 8, and 9 must have valid non-zero values. 2. set the pdn bit (register 6, bit 3) and clear the pdl bit (register 6, bit 4). 3. mclk may stay active or stop. 4. restore mclk before initiating the power-up sequence. 5. reset the PCT303DW using reset pin (after mclk is present). 6. program registers to desired settings. table 11 mclk examples mclk (mhz) n1 m1 cgm 1.8432 1 20 0 4.0000 5 72 1 4.0960 1 9 0 5.0688 11 80 0 6.0000 5 48 1 6.1440 1 6 0 8.1920 32 225 1 9.2160 1 4 0 10.0000 25 144 1 10.3680 9 32 0 11.0592 3 10 0 12.288 1 3 0 14.7456 2 5 0 16.0000 5 18 1 18.4320 1 2 0 24.5760 2 3 0 25.8048 7 10 0 33.8688 147 160 0 44.2368 96 125 1 46.0800 5 4 0 47.9232 13 10 0 48.0000 125 96 0 56.0000 35 36 1 60.0000 25 24 1
pc-tel, inc. 25 1789w0docdat06a-0299 pct1789w data sheet PCT303DW f u n c t i o n a l d e s c r i p t i o n ! ! preliminary preliminary the PCT303DW also supports an additional power- down mode. when both the pdn (register 6, bit 3) and pdl (register 6, bit 4) are set, the chip-set enters a complete power-down mode and draws negligible current. set the pdl bit either before setting the pdn bit or at the same time. in this mode, the rgdt pin does not function. normal operation may be restored using the same process for taking the chip-set out of sleep mode. analog output the PCT303DW supports an analog output (aout) for driving the call progress speaker found with most of today?s modems. aout is an analog signal that is comprised of a mix of the transmit and receive signals. the receive portion of this mixed signal has a 0 db gain, while the transmit signal has a gain of ?20 db. the transmit and receive signals of the aout signal have independent mute controls. the atm bit (register 6, bit 6) mutes the transmit portion, while the arm (register 6, bit 5) mutes the receive portion. figure3 on page 8 illustrates a recommended application circuit. note that in the configuration shown, the lm386 provides a gain of 26 db. additional gain adjustments may be made by varying the voltage divider created by r1 and r3 of figure 3. on-hook line monitor the PCT303DW allows the user to detect line activity when the device is in an on-hook state. when the system is on-hook, the line data can be passed to the dsp across the serial port while drawing a small amount of dc current from the line. this feature is similar to the passing of line information (such as caller id), while on- hook, following a ring signal detection. to activate this feature, set the onhm bit in register 5. the on-hook line monitor can also be used to detect whether a phone line is physically connected to the pct303w and associated circuitry. when the on-hook line monitor is activated (if no line is connected), the output of sdo will move towards a negative full scale value (?32768). the value is guaranteed to be at least 89% of negative full scale. if a line is present while in on-hook line monitor mode, sdo will have a near zero value. the designer must allow for the group delay of the receive filter before making a decision. the on-hook line monitor may be used in conjunction with the loop current sense bits to determine if a phone line is physically connected to the pct303w and associated circuitry. when on-hook line monitor is active (if a phone line is present), the lcs value will be a 1111b value. if a phone line is not present, the lcs value will be a zero value. the designer must allow for a 5/fs delay before making a decision. refer to ?loop current monitor? for more details on the lcs bits. loop current monitor when the system is in an off-hook state, the lcs bits of register 12 indicate the approximate amount of dc loop current that is flowing in the loop. the lcs is a 4-bit value ranging from zero to fifteen. each unit represents approximately 6 ma of loop current. an lcs value of zero means the loop current is less than required for normal operation and the system should be on-hook. an lcs value of 15 means the loop current is greater than 120 ma. to determine a rough approximation of the current (ma) flowing in the loop the following equation may be used: the lcs detector has a built-in hysteresis of 2 ma of current. this allows for a stable lcs value when the loop current is near a transition level. the lcs value is a rough approximation of the loop current, and the designer is advised to use this value in a relative means rather than an absolute value. this feature enables the modem to determine if an additional line has ?picked up? while the modem is transferring information. in the case of a second phone going off-hook, the loop current falls approximately 50% and is reflected in the value of the lcs bits. gain control the PCT303DW supports multiple gain and attenuation settings for the receive and transmit paths, respectively. when the arx bit is set, 6 db of gain is applied to the receive path. when the atx bit is set, ?3 db of gain is applied to the transmit path. register 15 can be used to provide additional gain control. for register 15 to have an effect on the receive and transmit paths, the atx and arx bits of register 13 must be zero. the receive path can support gains of 0, 3, 6, 9, and 12 db. the gain is selected by bits 2:0 (arx2:arx0). the receive path can also be muted by setting bit 3 (rxm). the transmit path can support attenuations of 0, 3, 6, 9, and 12 db. the attenuation is selected by bits 6:4 (atx2:atx0). the transmit path can also be muted by setting bit 7 (txm). loopcurrent 6 lcs 12 + ?
pc-tel, inc. 26 1789w0docdat06a-0299 pct1789w data sheet PCT303DW f u n c t i o n a l d e s c r i p t i o n ! ! preliminary preliminary filter selection the pct303d supports additional filter selections for the receive and transmit signals. the iir bit of register 16, when set, enables the iir filters defined in table29 on page59. this filter provides a much lower, however non-linear, group delay than the default fir filters. revision identification the PCT303DW provides the system designer the ability to determine the revision of the pct303d and/or the pct303w. register 11 identifies the revision of the pct303d with 4 bits named reva. register 13 identifies the revision of the pct303w with 4 bits named revb. table 12 shows the values for the various revisions. in-circuit testing the PCT303DW?s advanced design provides the modem manufacturer with increased ability to determine system functionality during production line tests, as well as support for end-user diagnostics. four loopback modes exist allowing increased coverage of system components. for three of the test modes, a line-side power source is needed. while a standard phone line can be used, the test circuit in figure20 on page 60 is adequate. in addition, an off-hook sequence must be performed to connect the power source to the line-side chip. for the start-up test mode, no line-side power is necessary and no off-hook sequence is required. the start-up test mode is enabled by default. when the pdl bit (register 6, bit 4) is set (the default case), the line side is in a power-down mode and the dsp side is in a digital loop-back mode. in this mode, data received on sdi is passed through the internal filters and transmitted on sdo. this path will introduce approximately 0.9 db of attenuation on the sdi signal received. the group delay of both transmit and receive filters will exist between sdi and sdo. clearing the pdl bit disables this mode and the sdo data is switched to the receive data from the line side. note, when pdl is cleared the fdt bit (register 12, bit 6) will become active, indicating the successful communication between the line side and dsp side. this can be used to verify that the isolink is operational. the remaining test modes require an off-hook sequence to operate. the following sequence defines the off-hook requirement: 1. power up or reset. 2. program clock generator to desired sample rate. 3. enable line side by clearing pdl bit. 4. issue off-hook 5. delay 4608/fs to allow calibration to occur. 6. set desired test mode. the isolink digital loopback mode allows the data pump to provide a digital input test pattern on sdi and receive that digital test pattern back on sdo. to enable this mode, set the dl bit of register 1. in this mode, the isolation barrier is actually being tested. the digital stream is delivered across the isolation capacitor, c1 of figure2 on page 6, to the line side device and returned across the same barrier. note in this mode, the 0.9db attenuation and filter group delays also exist. the analog loopback mode allows an external device to drive the rx pin of the line-side chip and receive the signal from the tx pin. this mode allows testing of external components connecting the rj-11 jack (tip and ring) to the line side of the PCT303DW. to enable this mode, set the al bit of register 2. the final testing mode, internal analog loopback, allows the system to test the basic operation of the transmit/ receive path of the line side and the external components r4 and c5 of figure2 on page 6. in this test mode, the data pump provides a digital test waveform on sdi. this data is passed across the isolation barrier, looped from the tx to rx pin, passed back across the isolation barrier, and presented to the data pump on sdo. to enable this mode, clear the hbe bit of register 2. when the hbe bit is cleared, this will cause a dc offset which affects the signal swing of the transmit signal. in this test mode, it is recommended that the transmit signal be 12 db lower than normal transmit levels. this lower level will eliminate clipping caused by the dc offset which results from disabling the hybrid. it is assumed in this test that the line ac impedance is nominally 600 w. note: all test modes are mutually exclusive. if more than one test mode is enabled concurrently, the results are unpredictable. table 12 revision values revision pct303d pct303w a 0100 0001
pc-tel, inc. 27 1789w0docdat06a-0299 pct1789w data sheet PCT303DW f u n c t i o n a l d e s c r i p t i o n ! ! preliminary preliminary exception handling the PCT303DW provides several mechanisms to determine if an error occurs during operation. through the secondary frames of the serial link, the controlling dsp can read several status bits. the bit of highest importance is the frame detect bit (fdt, register 12 bit 6). this bit indicates that the dsp side (pct303d) and line side (pct303w) devices are communicating. during normal operation, the fdt bit can be checked before reading any bits that indicate information about the line side. if fdt is not set, the following bits related to the line side are invalid?rdt, lcs, cbid, revb; the rgdt operation will also be non-functional. following power-up and reset, the fdt bit is not set because the pdl bit (register 6 bit 4) defaults to 1. in this state, the isolink is not operating and no information about the line side can be determined. the user must program the clock generator to a valid configuration for the system and clear the pdl bit to activate the isolink. while the dsp and line side are establishing communication, the dsp side does not generate fsync signals. therefore, if the controlling dsp serial interface is interrupt driven, based on the fsync signal, the controlling dsp does not require a special delay loop to wait for this event to complete. the fdt bit can also indicate if the line side executes an off-hook request successfully. if the line side is not connected to a phone line (that is, the user fails to connect a phone line to the modem), the fdt bit remains cleared. the controlling dsp must allow sufficient time for the line side to execute the off-hook request. the maximum time for fdt to be valid following an off-hook request is 10 ms. if the fdt is high, the lcs bits indicate the amount of loop current flowing. if the fdt fails to be set following an off-hook request, the pdl bit in register6 must be set high for at least 1ms to reset the line side. for more information, see ? loop current monitor ? on page25. another useful bit is the communication link error (cle) bit (register 12 bit 7). the cle bit indicates a time-out error for the isolink following a change to either pll1 or pll2. for more information, see ? clock generation subsystem ? on page22. when the cle bit is set, the dsp side chip has failed to receive verification from the line side that the clock change has been accepted in an expected period of time. this condition indicates a severe error in programming the clock generator or possibly a defective line-side chip.
pc-tel, inc. 41 1789w0docdat06a-0299 pct1789w data sheet PCT303DW c o n t r o l r e g i s t e r s ! ! preliminary preliminary PCT303DW c o n t r o l r e g i s t e r s any register not listed here is reserved and should not be written. control 1 (register 1, r/w) reset settings: 00h bit definitions: control 2 (register 2, r/w) reset settings: 03h bit definitions: control 3 (register 3, r) reset settings: 00h bit definitions: sr reserved dl sb 7 6 5 4 3 2 1 0 bits name description 7 sr software reset . 1 = sets all registers to their reset value. 0 = enables chip for normal operation. bit automatically clears after being set. 6:2 reserved reserved. read returns zero. 1 dl isolation digital loopback . 1 = enables digital loopback mode across isolation barrier. line side must be enabled prior to setting this mode. 0 sb serial digital interface mode . 1 = the serial port is operating in 16-bit mode and requires use of the secondary frame sync signal, fc, to initiate control data reads/writes. 0 = operation is in 15-bit mode and the lsb of the data field indicates whether a secondary frame is required. reserved al reserved hbe rxe 7 6 5 4 3 2 1 0 bits name description 7:4 reserved reserved. read returns zero. 3 al analog loopback . 1 = enables analog loopback mode. 2 reserved reserved. read returns zero. 1 hbe hybrid enable . 1 = connects transmit path in hybrid. 0 rxe receive enable . 1 = enables receive path. reserved 7 6 5 4 3 2 1 0 bits name description 7:0 reserved reserved. read returns zero.
pc-tel, inc. 42 1789w0docdat06a-0299 pct1789w data sheet PCT303DW c o n t r o l r e g i s t e r s ! ! preliminary preliminary control 4 (register 4, r) reset settings: 00h bit definitions: daa control 1 (register 5, r/w) reset settings: 00h bit definitions: reserved 7 6 5 4 3 2 1 0 bits name description 7:0 reserved reserved. read returns zero. reserved rdtn rdtp opol onhm rdt ohe oh 7 6 5 4 3 2 1 0 bits name description 7 reserved reserved. read returns zero. 6 rdtn ring detect signal negative. read-only. when set, a negative ring signal is occurring. 5 rdtp ring detect signal positive. read-only. when set, a positive ring signal is occurring. 4 opol off-hook polarity . 1 = off-hook pin is active-high. 0 = off-hook pin is active-low. 3 onhm on-hook line monitor . 1 = enables low-power monitoring mode allowing the dsp to receive line activity without going off-hook. 2 rdt ring detect . read-only. 1 = indicates a ring is occurring. 0 = reset either 4.5?9 seconds after last positive ring is detected or when the system executes an off-hook. 1 ohe off-hook pin enable . 1 = enables the operation of the off-hook pin. 0 = off-hook pin is ignored. 0 oh off-hook . 1 = causes the line-side chip to go off-hook. this bit operates indepen- dently of ohe and is a logic or with the off-hook pin when enabled.
pc-tel, inc. 43 1789w0docdat06a-0299 pct1789w data sheet PCT303DW c o n t r o l r e g i s t e r s ! ! preliminary preliminary daa control 2 (register 6, r/w) reset settings: 70h bit definitions: pll1 divide n1 (register 7, r/w) reset settings: 00h (serial mode 0, 1, 2) bit definitions: cpe atm1 arm1 pdl pdn reserved atm0 arm0 7 6 5 4 3 2 1 0 bits name description 7 cpe charge pump enable. 1 = charge pump on. 0 = charge pump off. 6,1 atm[1:0] aout transmit path level control . 5,0 arm[1:0] aout receive path level control . 4 pdl power down line-side chip . 1 = places the pct303w in lower power mode. 0 = normal operation. program the clock generator before clearing this bit. 3 pdn power down . 1 = powers down the PCT303DW. a reset pulse on reset is required to restore normal operation. 2 reserved reserved. read returns zero. divider n1 7 6 5 4 3 2 1 0 atm[1:0] description 00 ?20db transmit path attenuation for call progress aout pin only. 01 ?32db transmit path attenuation for call progress aout pin only. 10 mutes transmit path for call progress aout pin only. 11 ?26db transmit path attenuation for call progress aout pin only. arm[1:0] description 00 0db receive path attenuation for call progress aout pin only. 01 ?12db receive path attenuation for call progress aout pin only. 10 mutes receive path for call progress aout pin only. 11 ?6db receive path attenuation for call progress aout pin only. bits name description 7:0 divider n1 contains the (value ? 1) for determining the output frequency on pll1.
pc-tel, inc. 44 1789w0docdat06a-0299 pct1789w data sheet PCT303DW c o n t r o l r e g i s t e r s ! ! preliminary preliminary pll1 multiply m1 (register 8, r/w) reset settings: 00h (serial mode 0,1) reset settings: 13h (serial mode 2) bit definitions: pll2 divide/multiply n2/m2 (register 9, r/w) reset settings: 00h (serial mode 0, 1, 2) bit definitions: pll control (register 10, r/w) reset settings: 00h bit definitions: dsp-side chip revision (register 11, r) reset settings: n/a bit definitions: multiplier m1 7 6 5 4 3 2 1 0 bits name description 7:0 multiplier m1 contains the (value ? 1) for determining the output frequency on pll1. divider n2 multiplier m2 7 6 5 4 3 2 1 0 bits name description 7:4 divider n2 contains the (value ? 1) for determining the output frequency on pll2. 3:0 multiplier m2 contains the (value ? 1) for determining the output frequency on pll2. reserved cgm 7 6 5 4 3 2 1 0 bits name description 7:1 reserved reserved. read returns zero. 0 cgm clock generation mode . 1 = a 25/16 ratio is applied to the pll allowing for a more flexible choice of mclk frequencies while slowing down the pll lock time. 0 = no additional ratio is applied to the pll and faster lock times are possible. reserved reva 7 6 5 4 3 2 1 0 bits name description 7:4 reserved reserved. read returns zero. 3:0 reva chip revision . read-only. four-bit value indicating the revision of the pct303d (dsp-side) silicon.
pc-tel, inc. 45 1789w0docdat06a-0299 pct1789w data sheet PCT303DW c o n t r o l r e g i s t e r s ! ! preliminary preliminary line-side status (register 12, r/w) reset settings: n/a bit definitions: transmit and receive gain (register 13, r/w) reset settings: 00h bit definitions: cle fdt reserved lcs 7 6 5 4 3 2 1 0 bits name description 7 cle communications (isolink) error . 1 = indicates a communication problem between the pct303d and the pct303w. when it goes high, it remains high until a logic 0 is written to it. 6 fdt frame detect . read-only. 1 = indicates isolink frame lock has been established. 0 = indicates isolink has not established frame lock. 5:4 reserved reserved. read returns zero. 3:0 lcs loop current sense . read-only. four-bit value returning the loop current in 6ma increments. 0 = loop current < 6ma. 1111 = loop current > 120ma. see ? loop current monitor ? on page25. reserved cbid revb arx atx 7 6 5 4 3 2 1 0 bits name description 7 reserved reserved. read returns zero. 6 cbid chip b id . read-only. 1 = indicates the line-side has international support. 0 = indicates the line-side is domestic only. 5:2 revb chip revision . read-only. four-bit value indicating the revision of the pct303w (line-side) silicon. 1 arx receive gain . a 1 = a +6db gain is applied to the receive path. 0 = 0db gain is applied. 0 atx transmit gain . a 1 = a ?3db gain (attenuation) is applied to the transmit path. 0 = 0db gain is applied. a. see register 15 for additional transmit/receive gain and attenuation steps.
pc-tel, inc. 46 1789w0docdat06a-0299 pct1789w data sheet PCT303DW c o n t r o l r e g i s t e r s ! ! preliminary preliminary daisy-chain control (register 14, r/w) reset settings: 02h (serial mode 0,1) reset settings: 3fh (serial mode 2) bit definitions: nslv[2:0] ssel[1:0] fsd rpol dce 7 6 5 4 3 2 1 0 bits name description 7:5 nslv[2:0] number of slave devices . 4:3 ssel[1:0] slave device select . 2 fsd delayed frame sync control. 1 = sets the number of sclk periods between frame syncs to 16. 0 = sets the number of sclk periods between frame syncs to 32. this bit must be set when PCT303DW devices are used as slaves. for the master PCT303DW, only serial mode 1 is allowed in this case. 1 rpol ring detect polarity. 1 = the fc/ rgdt pin (operating as ring detect) is active-high. 0 = the fc/ rgdt pin (operating as ring detect) is active-low. 0 dce daisy-chain enable. 1 = enables the PCT303DW to operate with slave devices on the same serial bus. the fc/ rgdt signal (pin 7) becomes the ring detect output and the rgdt / fsd signal (pin 15) becomes the delayed frame sync signal. note that all other bits in this register are ignored if dce = 0. nslv[2:0] description 000 0 slave devices. simply redefines the fc/ rgdt and rgdt /fsd pins. 001 1 slave device. 010 2 slave devices. 011 3 slave devices. 100 4 slave devices. for four or more slave devices, the fsd bit must be set. 101 5 slave devices. 110 6 slave devices. 111 7 slave devices. ssel[1:0] description 00 16-bit sdo receive data. 01 reserved. 10 15-bit sdo receive data. lsb = 1 for the PCT303DW device. 11 15-bit sdo receive data. lsb = 0 for the PCT303DW device.
pc-tel, inc. 47 1789w0docdat06a-0299 pct1789w data sheet PCT303DW c o n t r o l r e g i s t e r s ! ! preliminary preliminary tx/rx gain control (register 15, r/w) reset settings: 00h bit definitions: txm atx[2:0] rxm arx[2:0] 7 6 5 4 3 2 1 0 bits name description 7 txm transmit mute. 1 = mutes the transmit signal. 6:4 atx[2:0] analog transmit attenuation . note: register 13 bit 0 (atx) must be 0 for these bits to work as expected. unpredictable results can occur if atx is 1 and these bits are non-zero. 3 rxm receive mute. 1 = mutes the receive signal. 2:0 arx[2:0] analog receive gain . note: register 13 bit 1 (arx) must be 0 for these bits to work as expected. unpredictable results can occur if arx is 1 and these bits are non-zero. atx[2:0] description 000 0db attenuation. 001 3db attenuation. 010 6db attenuation. 011 9db attenuation. 1xx 12db attenuation. atx[2:0] description 000 0db gain. 001 3db gain. 010 6db gain. 011 9db gain. 1xx 12db gain.
pc-tel, inc. 48 1789w0docdat06a-0299 pct1789w data sheet PCT303DW c o n t r o l r e g i s t e r s ! ! preliminary preliminary international control 1 (register 16, r/w) reset settings: 08h bit definitions: ons[1:0] act iire dct[1:0] rz rt 7 6 5 4 3 2 1 0 bits name description 7:6 ons[1:0] on-hook speed. 5 act ac termination select. 1 = selects the complex impedance. 0 = selects the real impedance. 4 iire iir filter enable. 1 = iir filter enabled for transmit and receive filters. (see figures 25?28 on page61.) 0 = fir filter enabled for transmit and receive filters. (see figures 21?24 on page60.) 3:2 dct[1:0] dc termination select. 1 rz ringer impedance select. when set, ringer impedance is decreased to satisfy some countries? ringer require- ments. 0 rt ringer threshold select. used to satisfy country requirements on ring detection. signals below the lower level will not generate a ring detection; signals above the upper level are guaranteed to generate a ring detection. 1 = 15 5 vrms 0 = 21.5 4.5 vrms ons[1:0] description 00 the PCT303DW will execute a slow controlled on-hook. 11 the PCT303DW will execute a fast on-hook. dct[1:0] mode description 00 0 low voltage mode. see ? appendix: net4 country support ? on page65. (transmit level = ?2dbm). 01 1 low voltage mode. provides different i/v characteristics than mode 0. (transmit level = ?5dbm). 10 2 standard voltage mode. (transmit level = ?1dbm). 11 3 current limiting mode. (transmit level = ?1dbm).
pc-tel, inc. 49 1789w0docdat06a-0299 pct1789w data sheet PCT303DW c o n t r o l r e g i s t e r s ! ! preliminary preliminary international control 2 (register 17, r/w) reset settings: 00h bit definitions: international control 3 (register 18, r/w) reset settings: 00h bit definitions: reserved bte rov btd 7 6 5 4 3 2 1 0 bits name description 7:3 reserved reserved. read returns zero. 2 bte billing tone detector enable. when set, the PCT303DW can detect a billing tone signal on the line and maintain off-hook through the billing tone. if a billing tone is detected, bit 0 (btd) is set to indi- cate the event. 1 rov receive overload. read-only. this bit is set when the receive input detects an excessive input level. this bit is cleared by writing a zero to this location. 0 btd billing tone detected. read-only. this bit is set if bit 2 (bte) is enabled and a billing tone is detected. this bit is cleared by writing a zero to this location. reserved rfwe sqlch 7 6 5 4 3 2 1 0 bits name description 7:2 reserved reserved. read returns zero. 1 rfwe ring detector full-wave rectifier enable. read-only. when set, the ring-detection circuitry provides full-wave rectification. this effects the data stream presented on sdo during ring detection. 0 sqlch ring detect network squelch. this bit must be set, then cleared, following a polarity reversal detection.
pc-tel, inc. 51 1789w0docdat06a-0299 pct1789w data sheet e l e c t r i c a l c h a r a c t e r i s t i c s ! ! preliminary preliminary PCT303DW electrical characteristics PCT303DW recommended operating conditions PCT303DW absolute maximum ratings permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 18 PCT303DW recommended operating conditions parameter a symbol test condition min b typ max a unit ambient temperature t a k-grade 0 25 70 c ambient temperature t a b-grade ?40 25 85 c pct303d supply voltage, analog v a 3.0 3.3/5.0 5.25 v pct303d supply voltage, digital c v d 3.0 3.3/5.0 5.25 v a. the PCT303DW specifications are guaranteed when the typical application circuit (including component tolerance) and any pct303d and pct303w are used. see figure 2 for typical application circuit. b. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25c unless otherwise stated. c. the digital supply, v d , can operate from either 3.3v or 5.0v. the pct303d supports interface to 3.3v logic when operating from 3.3v. the 3.3v operation applies to both the serial port and the digital signals rgdt /fsd, ofhk , reset , m0, and m1. table 19 PCT303DW absolute maximum ratings parameter symbol value unit dc supply voltage v d , v a ?0.5 to +6.0 v input current, pct303d digital input pins i in 10 ma digital input voltage v ind ?0.3 to (v d +0.3) v operating temperature range t a ?10 to +100 c storage temperature range t stg ?40 to +150 c
pc-tel, inc. 52 1789w0docdat06a-0299 pct1789w data sheet e l e c t r i c a l c h a r a c t e r i s t i c s ! ! preliminary preliminary PCT303DW loop characteristics given values are: v a = charge pump, v d = +3.3 v 5%; t a = 0 c to 70 c for k-grade, ?40 c to +85 c for b-grade; refer to figure20 on page 60. PCT303DW dc characteristics v d = 5v given values are: v a = +5 v 5%; v d = +5 v 5%; t a = 0 c to 70 c for k-grade, ?40 c to +85 c for b-grade. table 20 PCT303DW loop characteristics parameter symbol test condition min typ max unit dc termination voltage v dct i l = 20ma 7.7 v dc termination voltage v dct i l = 120ma 12 v dc ring current (with caller id) i rdc 500 a dc ring current (w/o caller id) i rdc 20 a ac termination impedance z act 600 w operating loop current i lp 20 100 ma ring voltage detect v rd 13 18 26 v rms ring frequency f r 15 68 hz on-hook leakage current i lk v bat = ?48v 1 a ringer equivalence num. (with caller id) ren 1.2 ringer equivalence num. (w/o caller id) ren 0.2 table 21 PCT303DW dc characteristics, v d = +5v parameter symbol test condition min typ max unit high-level input voltage v ih 3.5 v low-level input voltage v il 0.8 v high-level output voltage v oh i o = ?2ma 2.4 v low-level output voltage v ol i o = +2ma 0.4 v input leakage current i l 10 a power supply current, analog i a v a pin 1 6 ma power supply current, digital i d v d pin 13 17 ma total supply current, sleep mode 1.5 ma
pc-tel, inc. 53 1789w0docdat06a-0299 pct1789w data sheet e l e c t r i c a l c h a r a c t e r i s t i c s ! ! preliminary preliminary v d = 3.3v given values are: v a = charge pump; v d = +3.3 v 10%; t a = 0 c to 70 c for k-grade, ?40 c to +85 c for b-grade. table 22 PCT303DW dc characteristics, v d = +3.3v parameter symbol test condition min typ max unit high-level input voltage v ih 2.0 v low-level input voltage v il 0.8 v high-level output voltage v oh i o = ?2ma 2.4 v low-level output voltage v ol i o = +2ma 0.35 v input leakage current i l 10 a power supply current, analog i a v a pin 1 6 ma power supply current, digital i d v d pin 8 11 ma total supply current, sleep mode 1.5 ma
pc-tel, inc. 54 1789w0docdat06a-0299 pct1789w data sheet e l e c t r i c a l c h a r a c t e r i s t i c s ! ! preliminary preliminary PCT303DW ac characteristics given values are: v a = charge pump, v d = +3.3 v 5%; t a = 0 c to 70 c for k-grade, ?40 c to +85 c for b-grade. table 23 PCT303DW ac characteristics parameter symbol test condition min typ max unit freq response, transmit a , b a. these characteristics are determined by external components. see figure2 on page 6. b. sample rate = 8 khz f rt low ?3db corner 33 hz freq response, transmit a,b f rt 300hz ?0.2 0 db freq response, transmit b f rt 3400hz ?0.2 0 db transmit full scale level c (0db gain) c. parameter measured at tip and ring of figure2 on page 6. v tx 0.98 v peak freq response, receive a,b f rr low ?3db corner 33 hz freq response, receive a,b f rr 300hz ?0.01 0 db freq response, receive b f rr 3400hz ?0.2 0 db receive full scale level c , d (0db gain) d. full scale receive level produces ?0.9dbfs at sdo. v rx 0.98 v peak dynamic range e e. dr = 60db + 20 log (rms signal/rms noise). applies to both the transmit and receive paths. measurement bandwidth is 10hz to 3400hz. valid sample rate ranges between 7200hz and 11025hz. dr vin = 1khz, ?60db 84 db total harmonic distortion f f. thd = 20 log (rms distortion/rms signal). applies to both the transmit and receive paths. valid sample rate ranges between 7200hz and 11025hz. thd vin = 1khz, ?3db ?84 db gain drift a t vin = 1khz 0.002 db/c dynamic range (call progress aout) dr ao vin = 1khz 60 db thd (call progress aout) thd ao vin = 1khz 1.0 % aout full scale level 0.75v a v p-p aout output impedance 10 k w mute level (call progress aout) ?90 db dynamic range (caller id mode) dr cid vin = 1khz, ?60db 60 db caller id full scale level (0db gain) c v cid 0.8 v peak
pc-tel, inc. 55 1789w0docdat06a-0299 pct1789w data sheet s w i t c h i n g c h a r a c t e r i s t i c s ! ! preliminary preliminary s w i t c h i n g c h a r a c t e r i s t i c s general inputs given values are: v a = charge pump, v d = +3.3 v 5%; t a = 70 c for k-grade, 85 c for b-grade; c l = 20 pf. all timing is referenced to the 50% level of the waveform. input test levels are: v ih = v d ? 0.4v, v il = 0.4v. figure 16 general inputs timing diagram table 24 switching characteristics?general inputs parameter symbol min typ max unit cycle time, mclk t mc 16.67 ns mclk duty cycle t dty 40 50 60 % rise time, mclk t r 5 ns fall time, mclk t f 5 ns mclk before reset - t mr 10 cycles reset pulse width a a. the minimum reset pulse width is the greater of 250ns or 10 mclk cycle times. t rl 250 ns m0, m1 before reset - b b. m0 and m1 are typically connected to v d or gnd and should not be changed during normal operation. t mxr 20 ns mclk v ih v il reset t f t mc t mr t rl t r m0, m1 t mxr
pc-tel, inc. 56 1789w0docdat06a-0299 pct1789w data sheet s w i t c h i n g c h a r a c t e r i s t i c s ! ! preliminary preliminary serial interface (dce = 0) given values are: v a = charge pump, v d = +3.3 v 5%; t a = 70 c for k-grade, 85 c for b-grade; c l = 20 pf. all timing is referenced to the 50% level of the waveform. input test levels are: v ih = v d ? 0.4v, v il = 0.4v. figure 17 serial interface timing diagram (dce = 0) table 25 switching characteristics?serial interface (dce = 0) parameter symbol min typ max unit cycle time, sclk t c 354 1/256 fs ns sclk duty cycle t dty 50 % delay time, sclk - to fsync t d1 10 ns delay time, sclk - to sdo valid t d2 20 ns delay time, sclk - to fsync - t d3 10 ns setup time, sdi before sclk t su 25 ns hold time, sdi after sclk t h 20 ns setup time, fc - before sclk - t sfc 40 ns hold time, fc - after sclk - t hfc 40 ns sclk v oh v ol d15 d14 d1 d0 ... d2 16-bit d15 d14 d1 d0 ... d2 sdo 16-bit sdi t d2 t su t h fsync (mode 1) t d3 t c t hfc t sfc fc fsync (mode 0) t d1 t d3
pc-tel, inc. 57 1789w0docdat06a-0299 pct1789w data sheet s w i t c h i n g c h a r a c t e r i s t i c s ! ! preliminary preliminary serial interface (dce = 1, fsd = 0) given values are: v a = charge pump, v d = +3.3 v 5%; t a = 70 c for k-grade, 85 c for b-grade; c l = 20 pf. all timing is referenced to the 50% level of the waveform. input test levels are: v ih = v d ? 0.4v, v il = 0.4v. figure 18 serial interface timing diagram (dce = 1, fsd = 0) table 26 switching characteristics?serial interface (dce = 1, fsd = 0) parameter symbol min typ max unit sclk duty cycle t dty 50 % delay time, sclk - to fsync - t d1 10 ns delay time, sclk - to fsync t d2 10 ns delay time, sclk - to sdo valid t d3 20 ns delay time, sclk - to sdo hi-z t d4 20 ns setup time, sdo before sclk t su 25 ns hold time, sdo after sclk t h 20 ns setup time, sdi before sclk t su2 25 ns hold time, sdi after sclk t h2 20 ns sclk fsync (mode 1) fsync (mode 0) sdo sdi d15 d14 d1 d0 d15 d14 d13 d0 t su2 t h2 t su t h t d3 t d4 t d1 t d2 t d1
pc-tel, inc. 58 1789w0docdat06a-0299 pct1789w data sheet s w i t c h i n g c h a r a c t e r i s t i c s ! ! preliminary preliminary serial interface (dce = 1, fsd = 1) given values are: v a = charge pump, v d = +3.3 v 5%; t a = 70 c for k-grade, 85 c for b-grade; c l = 20 pf. all timing is referenced to the 50% level of the waveform. input test levels are: v ih = v d ? 0.4v, v il = 0.4v. figure 19 serial interface timing diagram (dce = 1, fsd = 1) table 27 switching characteristics?serial interface (dce = 1, fsd = 0) parameter symbol min typ max unit cycle time, sclk t c 354 1/256 fs ns sclk duty cycle t dty 50 % delay time, sclk - to fsync - t d1 10 ns delay time, sclk - to fsync t d2 10 ns delay time, sclk - to sdo valid t d3 0.25t c ?20 0.25t c +20 ns delay time, sclk - to sdo hi-z t d4 20 ns delay time, sdo before rgdt t d5 20 ns setup time, sdo before sclk t su 25 ns hold time, sdo after sclk t h 20 ns setup time, sdi before sclk t su2 25 ns hold time, sdi after sclk t h2 20 ns d15 d14 d1 d0 t su2 t h2 d15 d14 d13 d0 sclk fsync (mode 1) sdo (master) sdo (slave 1) fsd sdi d15 t d5 t d3 t d4 t su t h t d3 t d2 t d1 t c
pc-tel, inc. 59 1789w0docdat06a-0299 pct1789w data sheet d i g i t a l f i l t e r c h a r a c t e r i s t i c s ! ! preliminary preliminary d i g i t a l f i l t e r c h a r a c t e r i s t i c s digital fir filter characteristics given values are: v a = charge pump, v d = +3.3 v 5%; sample rate = 8 khz; t a = 70 c for k-grade, 85 c for b-grade. typical fir filter characteristics for fs = 8000hz are shown in figures 21, 22, 23, and 24. digital iir filter characteristics given values are: v a = charge pump, v d = +3.3 v 5%; sample rate = 8 khz; t a = 70 c for k-grade, 85 c for b-grade. typical iir filter characteristics for fs = 800 hz are shown in figures 25, 26, 27, and 28. figures 29 and 30 show group delay versus input frequency. table 28 digital fir filter characteristics?transmit and receive parameter symbol min typ max unit passband (0.1db) f (0.1db) 0 3.3 khz passband (3db) f (3db) 0 3.6 khz passband ripple peak-to-peak ?0.1 0.1 db stopband 4.4 khz stopband attenuation ?74 db group delay t gd 12/fs sec table 29 digital iir filter characteristics?transmit and receive parameter symbol min typ max unit passband (3db) f (3db) 0 3.6 khz passband ripple peak-to-peak ?0.2 0.2 db stopband 4.4 khz stopband attenuation ?40 db group delay t gd 1.6/fs sec pct303w tip ring 10 f 600 w note: the remainder of the circuit is identical to the one shown in the application diagram. i l
pc-tel, inc. 60 1789w0docdat06a-0299 pct1789w data sheet d i g i t a l f i l t e r c h a r a c t e r i s t i c s ! ! preliminary preliminary figure 20 test circuit for loop characteristics filter plot diagrams for figures 21, 22, 23, and 24, all filter plots apply to a sample rate of fs = 8 khz. the filters scale with the sample rate as follows: f (0.1 db) = 0.4125 fs f (? 3 db) = 0.45 fs where fs is the sample frequency. figure 21 fir receive filter response figure 22 fir receive filter passband ripple figure 23 fir transmit filter response figure 24 fir transmit filter passband ripple input frequency - khz a t t e n u a t i o n - d b input frequency - khz a t t e n u a t i o n - d b a t t e n u a t i o n - d b input frequency - khz input frequency - khz a t t e n u a t i o n - d b
pc-tel, inc. 61 1789w0docdat06a-0299 pct1789w data sheet d i g i t a l f i l t e r c h a r a c t e r i s t i c s ! ! preliminary preliminary figure 25 iir receive filter response figure 26 iir receive filter passband ripple figure 27 iir transmit filter response figure 28 iir transmit filter passband ripple input frequency - khz a t t e n u a t i o n - d b input frequency - khz a t t e n u a t i o n - d b input frequency - khz a t t e n u a t i o n - d b input frequency - khz a t t e n u a t i o n - d b
pc-tel, inc. 62 1789w0docdat06a-0299 pct1789w data sheet d i g i t a l f i l t e r c h a r a c t e r i s t i c s ! ! preliminary preliminary figure 29 iir receive group delay figure 30 iir transmit group delay input frequency - khz d e l a y - s input frequency - khz d e l a y - s
pc-tel, inc. 64 1789w0docdat06a-0299 pct1789w data sheet m e c h a n i c a l d i m e n s i o n s ! ! preliminary preliminary PCT303DW mechanical dimensions figure 32 16-pin soic package 16 9 1 8 e h b 0 0.010" gauge plane detail f l d e a 2 a a 1 seating plane c l1 see detail f table 31 soic mechanical dimensions (controlling dimension: millimeters) symbol millimeters inches min max min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 a2 1.30 1.50 0.051 0.059 b 0.330 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 9.80 10.01 0.386 0.394 e 3.80 4.00 0.150 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 l 0.40 1.27 0.016 0.050 l1 1.07 bsc 0.042 bsc g 0.10 0.004 q 0 8 0 8
pc-tel, inc. 65 1789w0docdat06a-0299 pct1789w data sheet a p p e n d i x : net4 c o u n t r y s u p p o r t ! ! preliminary preliminary a p p e n d i x : net4 c o u n t r y s u p p o r t introduction the international design for the PCT303DW can be implemented to support global requirements targeting compliance with ctr21 or compliance with net4. this appendix outlines the component changes and control registers required for net4 support. net4 support requires different dc termination (mode 0) and programmable ringer impedance and ringer threshold in order to meet country-specific requirements. some component changes (vs. ctr21 only support) are necessary and are outlined in the notes of table32 on page67. mode 0 mode 0 (0,0) is a low-voltage mode which supports a maximum transmit signal of ?5.22 dbm. this mode meets the very low voltage requirements for countries such as norway. see figure 33. figure 33 mode 0 i/v characteristics (0,0) ringer impedance the PCT303DW has a very high impedance ring detector that satisfies the requirements of most countries. in order to meet the maximum impedances of germany (20 k w ) and south africa (60 k w ), while not violating the minimum 20 k w requirement of austria, a selectable ringer impedance has been included. the default (mode0) is 24 k w and satisfies most countries. mode 1 selects a 16 k w impedance, primarily to support germany. the mode is selected by the rz bit of register16. ringer threshold the PCT303DW has a programmable ringer threshold. mode 1 sets a ring threshold of 21.5 5 vrms. the mode is selected by bit 0 (rt) of register16. most countries will be programmed as mode 1 except switzerland, austria, and belgium which require mode 0. many countries can operate in either mode, such as those complying to fcc regulations. 10 8 7 .01 .02 .03 .04 .05 .06 .07 .08 .09 .1 loop current (a) mode 0 v o l t a g e a c r o s s d a a ( v ) 6 5 .11 11 9
pc-tel, inc. 66 1789w0docdat06a-0299 pct1789w data sheet a p p e n d i x : net4 c o u n t r y s u p p o r t ! ! preliminary preliminary typical application (net4 specifications) figure 34 typical applications circuit (net4 specifications) p c t 3 0 3 w p c t 3 0 3 d
pc-tel, inc. 67 1789w0docdat06a-0299 pct1789w data sheet a p p e n d i x : net4 c o u n t r y s u p p o r t ! ! preliminary preliminary typical application component values table 32 component values (net4 specifications) symbol north american value international value c1 150pf, 2kv, x7r,20% 150pf, 3kv, x7r, 20% c2,c4 1000pf, 2kv, x7r, 20% 2200pf, 3kv, x7r, 20% c3,c10 0.1f, 16v, x7r, 20% same as north american c5 0.47f, 16v, x7r, 20% 0.1f, 50v, x7r, 20% c6 0.047f, 16v, x7r, 20% 0.1f, 16v, x7r, 20% c7 2200pf, 250v, x7r, 20% 680pf, 250v, x7r, 20% c8 a 2200pf, 250v, x7r, 20% 680pf, 250v, x7r, 10% c9 a 15nf, 250v, x7r, 20% 22nf, 250v, x7r, 10% c11 5600pf, 16v, x7r, 20% not installed c12 not installed 0.22f, 16v, x7r, 20% c13,c16 not installed 0.1f, 16v, x7r, 20% c14 not installed 560nf,16v, x7r, 20% c15 b not installed 0.47f, 250v, 20% c17 c not installed not installed c18,c19 a not installed 3900pf,16v, x7r, 10% c20 not installed 47pf, 250v, x7r, 20% r1 51 w , 1/2w 5% not installed r2 15 w , 1/4w 5% 402 w , 1/10w 1% r3 d 10 w , 1/10w, 5% same as north american r4 604 w , 1/4w, 1% not installed r5 36k w , 1/10w 5% same as north american r6 36k w , 1/10w 5% 121k w , 1/10w 5% r7,r8,r15,r16,r17,r19 not installed 4.87k w , 1/4w 1% r9,r10 10k w , 1/4w 5% 30k w , 1/4w 5% r11 not installed 10k w , 1/10w 1% r12 not installed 140 w , 1/10w 1% r13 not installed 442 w , 1/10w 1% r14 b not installed 18.7k w , 1/4w 1% r18 0 w 2.2k w , 1/10w 5% r20 c 0 w 0 w z1 zener diode, 18v not installed z2,z3 c not installed zener diode, 3v q1,q3 motorola mmbta42lt1 same as north american q2 motorola mmbta92lt1 same as north american q4 not installed motorola pzt2222at1, 1/2w
? 1998 pc-tel inc. all rights reserved. 68 1789w0docdat06a-0299 pct1789w data sheet a p p e n d i x : net4 c o u n t r y s u p p o r t no part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of pc-tel, inc. pc-tel, inc. makes no representations or warranties regarding the content of this document. all specifications are subject to change without prior notice. pc-tel, inc. assumes no responsibility for any errors contained herein. all other trademarks are owned by their respective holders and are used for identification purposes only. ! ! 70 rio robles drive san jose, ca 95134 fax: 1+(408) 383-0455 http://www.pctel.com tel: 1+(408) 383-0452 preliminary preliminary d1?d4 1n4004 same as north american fb1,fb2 ferrite bead same as north american rv1 sidactor 275v, 100a same as north american a. c8, c9, c18, and c19 require only 20% tolerance for ctr21 designs. b. c14, r15, z2, and z3 required only for south africa support. c. c17 and r20 required for austria net 4 support (not ctr21 designs). when omitted, c2 and c4 decrease to 1000 pf, 3kv, x7r, 20%. d. r3 not required when charge pump is enabled and v d = 3.3v. table 32 component values (net4 specifications) (continued) symbol north american value international value
pc-tel, inc. 69 1789w0docdat06a-0299 pct1789w data sheet a p p e n d i x : net4 c o u n t r y s u p p o r t ! ! preliminary preliminary net4 line interface configurations table 33 net4 country line interface configurations (register 16) country ac termination dc termination ringer impedance ringer threshold bit 5 bit 4 bit 3 bit 2 bit 0 1. fcc 0 1 0 0 0 2. australia 1 0 1 0 0 3. austria a 0 1 0 0 1 4. belgium a 0 1 0 0 1 5. denmark a 1 1 1 0 0 6. finland a 0 1 0 0 0 7. france a 0 1 1 0 0 8. germany a 1 1 0 1 0 9. greece a 1 1 1 0 0 10. hungary a 1 1 1 0 0 11. iceland a 1 1 1 0 0 12. ireland a 1 1 0 0 0 13. italy a 0 0 1 0 0 14. japan 0 0 1 0 0 15. liechtenstein a 1 1 1 0 0 16. luxembourg a 1 1 1 0 0 17. netherlands a 1 1 1 0 0 18. new zealand 1 1 0 0 0 19. norway a 1 0 0 0 0 20. portugal a 0 1 0 0 0 21. singapore b 0 0 1 0 0 22. south africa 1 1 0 0 0 23. spain a 0 1 0 0 0 24. sweden a 1 1 1 0 0 25. switzerland a 1 0 1 0 1 26. ctr21 1 1 1 0 0 27. uk a 1 1 0 0 1 a. these countries are now accepting ctr21. b. support for loop currents greater than or equal to 20 ma.

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