protection products 1 www.semtech.com preliminary protection products sfc05-5 chipclamp ? ? ? ? ? flip chip tvs diode array description features device dimensions schematic & pin configuration revision 11/21/03 the sfc05-5 is a five line flip chip tvs diode array. they are state-of-the-art devices that utilize solid-state silicon-avalanche technology for superior clamping performance and dc electrical characteristics. the sfc series tvs diodes are designed to protect sensi- tive semiconductor components from damage or latch- up due to electrostatic discharge (esd) and other voltage induced transient events. the sfc05-5 is a 6-bump, 0.5mm pitch flip chip array with a 3x2 bump grid. it measures 1.5 x 1.0 x 0.65mm. this small outline makes the sfc05-5 especially well suited for portable applications. csp tvs devices are compatible with current pick and place equipment and assembly methods. each device will protect up to five data or i/o lines. the csp design results in lower inductance, virtually eliminating voltage overshoot due to leads and inter- connecting bond wires. they may be used to meet the esd immunity requirements of iec 61000-4-2, level 4 (15kv air, 8kv contact discharge). applications mechanical characteristics ? cell phone handsets and accessories ? personal digital assistants (pda?s) ? notebook and hand held computers ? portable instrumentation ? pagers ? smart cards ? mp3 players ? gps ? 200 watts peak pulse power (tp = 8/20s) ? transient protection for data lines to iec 61000-4-2 (esd) 15kv (air), 8kv (contact) iec 61000-4-4 (eft) 40a (5/50ns) iec 61000-4-5 (lightning) 20a (8/20s) ? small chip scale package requires less board space ? low profile (< 0.65mm) ? no need for underfill material ? protects five i/o or data lines ? low clamping voltage ? working voltage: 5v ? solid-state silicon-avalanche technology ? jedec mo-211, variation bb, 0.50 mm pitch chip scale package (csp) ? marking : marking code ? packaging : tape and reel sfc05-5 maximum dimensions (mm) 3 x 2 grid csp tvs (bottom view)
2 ? 2003 semtech corp. www.semtech.com preliminary protection products sfc05-5 absolute maximum rating electrical characteristics (t=25 o c) s e n i l v 5 r o f 5 - 5 0 c f s r e t e m a r a pl o b m y ss n o i t i d n o cm u m i n i ml a c i p y tm u m i x a ms t i n u e g a t l o v f f o - d n a t s e s r e v e rv m w r 5v e g a t l o v n w o d k a e r b e s r e v e rv r b i t a m 1 =6 v t n e r r u c e g a k a e l e s r e v e ri r v m w r c 5 2 = t , v 5 =0 1a e g a t l o v g n i p m a l cv c i p p s 0 2 / 8 = p t , a 5 = d n u o r g o t o / i y n a 5 . 9v e g a t l o v g n i p m a l cv c i p p s 0 2 / 8 = p t , a 0 2 = d n u o r g o t o / i y n a 1 1v e c n a t i c a p a c n o i t c n u jc j v r z h m 1 = f , v 0 =0 5 3f p g n i t a rl o b m y se u l a vs t i n u 0 2 / 8 = p t ( r e w o p e s l u p k a e p ) sp k p 0 0 2s t t a w 0 2 / 8 = p t ( t n e r r u c e s l u p k a e p ) si p p 0 2a ) r i a ( 2 - 4 - 0 0 0 1 6 c e i r e p d s e ) t c a t n o c ( 2 - 4 - 0 0 0 1 6 c e i r e p d s e v d s e 5 2 > 5 1 > v k e r u t a r e p m e t g n i r e d l o st l ) s d n o c e s 0 1 ( 0 6 2 o c e r u t a r e p m e t g n i t a r e p ot j 5 2 1 + o t 5 5 - o c e r u t a r e p m e t e g a r o t st g t s 0 5 1 + o t 5 5 - o c
3 ? 2003 semtech corp. www.semtech.com preliminary protection products sfc05-5 typical characteristics non-repetitive peak pulse power vs. pulse time power derating curve 0 10 20 30 40 50 60 70 80 90 100 110 0 25 50 75 100 125 150 ambient temperature - t a ( o c) % of rated power or i pp clamping voltage vs. peak pulse current 0 10 20 30 40 50 60 70 80 90 100 110 0 5 10 15 20 25 30 time (s) percent of i pp e -t td = i pp /2 waveform parameters: tr = 8s td = 20s pulse waveform esd clamping (8kv contact discharge) 0.01 0.1 1 10 0.1 1 10 100 1000 pulse duration - tp (s) peak pulse power - p pk (kw) 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 0 5 10 15 20 25 peak pulse current - i pp (a) clamping voltage - v c (v) waveform parameters: tr = 8s td = 20s
4 ? 2003 semtech corp. www.semtech.com preliminary protection products sfc05-5 device connection options the sfc05-5 has solder bumps located in a 3 x 2 matrix layout on the active side of the device. the bumps are designated by the numbers 1 - 3 along the horizontal axis and letters a - b along the vertical axis. the lines to be protected are connected at bumps a1, b1, a2, a3, and b3. bump b2 is connected to ground. all path lengths should be kept as short as possible to minimize the effects of parasitic inductance in the board traces. wafer level csp tvs csp tvs devices are wafer level chip scale packages. they eliminate external plastic packages and leads and thus result in a significant board space savings. manu- facturing costs are minimized since they do not require an intermediate level interconnect or interposer layer for reliable operation. they are compatible with cur- rent pick and place equipment further reducing manu- facturing costs. certain precautions and design considerations have to be observed however for maximum solder joint reliability. these include solder pad definition, board finish, and assembly parameters. printed circuit board mounting non-solder mask defined (nsmd) land patterns are recommended for mounting the sfc05-5. solder mask defined (smd) pads produce stress points near the solder mask on the pcb side that can result in solder joint cracking when exposed to extreme fatigue conditions. the recommended pad size is 0.225 0.010 mm with a solder mask opening of 0.350 0.025 mm. grid courtyard the recommended grid placement courtyard is 1.3 x 1.8 mm. the grid courtyard is intended to encompass the land pattern and the component body that is centered in the land pattern. when placing parts on a pcb, the highest recommended density is when one courtyard touches another. applications information device schematic and pin configuration layout example nsmd package footprint to protected ic to protected ic to connector ground
5 ? 2003 semtech corp. www.semtech.com preliminary protection products sfc05-5 printed circuit board finish a uniform board finish is critical for good assembly yield. two finishes that provide uniform surface coat- ings are immersion nickel gold and organic surface protectant (osp). a non-uniform finish such as hot air solder leveling (hasl) can lead to mounting problems and should be avoided. stencil design a properly designed stencil is key to achieving ad- equate solder volume without compromising assembly yields. a 0.100mm thick, laser cut, electro-polished stencil with 0.275mm square apertures and rounded corners is recommended. reflow profile the flip chip tvs can be assembled using standard smt reflow processes. as with any component, ther- mal profiles at specific board locations can vary and must be determined by the manufacturer. the flip chip tvs peak reflow temperature is 230 10 c. time above eutectic temperature (183 c) should be 50 10 seconds. during reflow, the component self-aligns itself on the pad. circuit board layout recommendations for suppres- sion of esd good circuit board layout is critical for the suppression of esd induced transients. the following guidelines are recommended: z place the tvs near the input terminals or connec- tors to restrict transient coupling. z minimize the path length between the tvs and the protected line. z minimize all conductive loops including power and ground loops. z the esd transient return path to ground should be kept as short as possible. z never run critical signals near board edges. z use ground planes whenever possible. stencil design reflow profile applications information (continued)
6 ? 2003 semtech corp. www.semtech.com preliminary protection products sfc05-5 land pattern outline drawing
7 ? 2003 semtech corp. www.semtech.com preliminary protection products sfc05-5 contact information semtech corporation protection products division 200 flynn road, camarillo, ca 93012 phone: (805)498-2111 fax (805)498-3804 marking codes r e b m u n t r a p g n i k r a m e d o c 5 - 5 0 c f su 5 5 f 3 x 2 grid flip chip tvs (top view) t r a p r e b m u n n o i t p o h c t i p r e p y t q l e e r e z i s l e e r f t . 5 - 5 0 c f sm m 40 0 0 , 3h c n i 7 c t . 5 - 5 0 c f sm m 20 0 0 , 3h c n i 7 m t . 5 - - 5 0 c f sm m 20 0 0 , 6h c n i 7 ordering information tape and reel specification tape specifications device orientation 2mm pitch option (all pockets popluated) device orientation 4mm pitch option (every other pocket populated) pin a1 pin a1 pin a1 pin a1 pin a1 pin a1 f55u
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