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tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 1 post office box 655303 ? dallas, texas 75265 wide range of supply voltages over specified temperature range: t a = 40 c to 85 c...2 v to 8 v fully characterized at 3 v and 5 v single-supply operation common-mode input voltage range extends below the negative rail and up to v dd 1 v at t a = 25 c output voltage range includes negative rail high input impedanc e...10 12 w typical esd-protection circuitry designed-in latch-up immunity description the tlv232x operational amplifiers are in a family of devices that has been specifically designed for use in low-voltage single-supply applications. this amplifier is especially well suited to ultra-low-power systems that require devices to consume the absolute minimum of supply currents. each amplifier is fully functional down to a minimum supply voltage of 2 v, is fully characterized, tested, and specified at both 3-v and 5-v power supplies. the common-mode input voltage range includes the negative rail and extends to within 1 v of the positive rail. these amplifiers are specifically targeted for use in very low-power, portable, battery-driven applications with the maximum supply current per operational amplifier specified at only 27 m a over its full temperature range of 40 c to 85 c. available options v max at packaged devices chip form t a v io max at 25 c small outline 2 (d) plastic dip (n) plastic dip (p) tssop 3 (pw) chip form (y) 40 cto85 5 c 9 mv tlv2322id e tlv2322ip tlv2322ipwle tlv2322y 40 c t o 85 c 10 mv tlv2324id tlv2324in e tlv2324ipwle tlv2324y 2 the d package is available taped and reeled. add r suffix to the device type (e.g., tlv2322idr). 3 the pw package is only available left-end taped and reeled (e.g., tlv2322ipwle). chip forms are tested at 25 c only. copyright ? 1997, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. lincmos is a trademark of texas instruments incorporated. 1 2 3 4 8 7 6 5 1out 1in 1in + v dd /gnd v dd 2out 2in 2in + 1 2 3 4 8 7 6 5 1out 1in 1in + v dd / gnd v dd + 2out 2in 2in + 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1out 1in 1in + v dd+ 2in + 2in 2out 4out 4in 4in + v dd / gnd 3in + 3in 3out 1 14 8 7 4out 4in 4in + v dd / gnd 3in + 3in 3out 1out 1in 1in + v dd+ 2in + 2in 2out tlv2322 d or p package (top view) tlv2322 pw package (top view) tlv2324 d or n package (top view) tlv2324 pw package (top view)
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 2 post office box 655303 ? dallas, texas 75265 description (continued) low-voltage and low-power operation has been made possible by using the texas instruments silicon-gate lincmos technology. the lincmos process also features extremely high input impedance and ultra-low bias currents making these amplifiers ideal for interfacing to high-impedance sources such as sensor circuits or filter applications. to facilitate the design of small portable equipment, the tlv232x is made available in a wide range of package options, including the small-outline and thin-shrink small-outline packages (tssop). the tssop package has significantly reduced dimensions compared to a standard surface-mount package. its maximum height of only 1.1 mm makes it particularly attractive when space is critical. the device inputs and outputs are designed to withstand 100-ma currents without sustaining latch-up. the tlv232x incorporates internal esd-protection circuits that prevent functional failures at voltages up to 2000 v as tested under mil-std 883c, method 3015.2; however, care should be exercised in handling these devices as exposure to esd can result in the degradation of the device parametric performance. tlv2322y chip information this chip, when properly assembled, displays characteristics similar to the tlv2322i. thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. chips may be mounted with conductive epoxy or a gold-silicon preform. bonding pad assignments chip thickness: 15 mils typical bonding pads: 4 4 mils minimum t j max = 150 c tolerances are 10%. all dimensions are in mils. + 1out 1in + 1in v dd v dd /gnd (8) (3) (2) (4) + 2out 2in + 2in (5) (6) 59 72 (5) (4) (3) (2) (6) (7) (8) (1)
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 3 post office box 655303 ? dallas, texas 75265 tlv2324y chip information this chip, when properly assembled, display characteristics similar to the tlv2324. thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. chips may be mounted with conductive epoxy or a gold-silicon preform. bonding pad assignments + 1out 1in + 1in v dd (4) (6) (3) (2) (5) (1) 2in + 2in 2out (11) v dd /gnd + 3out 3in + 3in (13) (10) (9) (12) (8) + (14) 4out 4in + 4in + (7) chip thickness: 15 mils typical bonding pads: 4 4 mils minimum t j max = 150 c tolerances are 10%. all dimensions are in mils. pin (12) is internally connected to backside of chip. 68 108 (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14)
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 4 post office box 655303 ? dallas, texas 75265 equivalent schematic (each amplifier) in + p1 p2 p3 p4 p5 p6 in r1 r2 r3 r4 r5 r6 r7 n1 n2 n3 n4 n5 n6 n7 d1 d2 c1 out v dd gnd actual device component count 2 component tlv2342 tlv2344 transistors 54 108 resistors 14 28 diodes 4 8 capacitors 2 4 2 includes both amplifiers and all esd, bias, and trim circuitry.
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 5 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted) 2 supply voltage, v dd (see note 1) 8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . differential input voltage, v id (see note 2) v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (any input) 0.3 v to v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input current, i i 5 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output current, i o 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . duration of short-circuit current at (or below) t a = 25 c (see note 3) unlimited . . . . . . . . . . . . . . . . . . . . . . . . . continuous total dissipation see dissipation rating table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum rated conditions for extended periods may affect device reliability. notes: 1. all voltage values, except differential voltages, are with respect to network ground. 2. differential voltages are at the noninverting input with respect to the inverting input. 3. the output may be shorted to either supply. temperature and /or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded (see application section). dissipation rating table package t a 25 c derating factor t a = 85 c package power rating above t a = 25 c power rating d8 725 mw 5.8 mw/ c 377 mw d14 950 mw 7.6 mw/ c 494 mw n 1575 mw 12.6 mw/ c 819 mw p 1000 mw 8.0 mw/ c 520 mw pw8 525 mw 4.2 mw/ c 273 mw pw14 700 mw 5.6 mw/ c 364 mw recommended operating conditions min max unit supply voltage, v dd 2 8 v common mode in p ut voltage v ic v dd = 3 v 0.2 1.8 v c ommon-mo d e i npu t vo lt age, v ic v dd = 5 v 0.2 3.8 v operating free-air temperature, t a 40 85 c
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 6 post office box 655303 ? dallas, texas 75265 tlv2322 electrical characteristics at specified free-air temperature 2 tlv2322 parameter test conditions t a 2 v dd = 3 v v dd = 5 v unit a min typ max min typ max v io in p ut offset voltage v o = 1 v, v ic = 1 v, 25 c 1.1 9 1.1 9 mv v io i npu t o ff se t vo lt age ic , r s = 50 w, r l = 1 m w full range 11 11 m v a vio average temperature coefficient of input offset voltage 25 c to 85 c 1 1.1 m v/ c i io in p ut offset current (see note 4) v o = 1 v, 25 c 0.1 0.1 p a i io i npu t o ff se t curren t ( see n o t e 4) o , v ic = 1 v 85 c 22 1000 24 1000 p a i ib in p ut bias current (see note 4) v o = 1 v, 25 c 0.6 0.6 p a i ib i npu t bi as curren t ( see n o t e 4) o , v ic = 1 v 85 c 175 2000 200 2000 p a 25 c 0.2 to 0.3 to 0.2 to 0.3 to v v icr common-mode input voltage 25 c t o 2 t o 2.3 t o 4 t o 4.2 v v icr g range (see note 5) full range 0.2 to 0.2 to v f u ll range t o 1.8 t o 3.8 v v oh high level out p ut voltage v ic = 1 v, v id = 100 mv 25 c 1.75 1.9 3.2 3.8 v v oh hi g h - l eve l ou t pu t vo lt age v id = 100 m v , i oh = 1 ma full range 1.7 3 v v ol low level out p ut voltage v ic = 1 v, v id = 100 mv 25 c 115 150 95 150 mv v ol l ow- l eve l ou t pu t vo lt age v id = 100 m v , i ol = 1 ma full range 190 190 m v a vd large-signal differential voltage v ic = 1 v, r l =1m w 25 c 50 400 50 520 v/mv a vd gg g amplification r l = 1 m w , see note 6 full range 50 50 v/ m v cmrr common mode rejection ratio v o = 1 v, v ic =v icr min 25 c 65 88 65 94 db cmrr c ommon-mo d e re j ec ti on ra ti o v ic = v icr m i n, r s = 50 w full range 60 60 db k svr supply-voltage rejection ratio v ic = 1 v, v o =1v 25 c 70 86 70 86 db k svr ygj ( d v dd / d v io ) v o = 1 v , r s = 50 w full range 65 65 db i dd su pp ly current v o = 1 v, v ic = 1 v, 25 c 12 34 20 34 m a i dd s upp l y curren t o , ic , no load full range 54 54 m a 2 full range is 40 c to 85 c. notes: 4. the typical values of input bias current and input offset current below 5 pa are determined mathematically. 5. this range also applies to each input individually. 6. at v dd = 5 v, v o(pp) = 0.25 v to 2 v; at v dd = 3 v, v o = 0.5 v to 1.5
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 7 post office box 655303 ? dallas, texas 75265 tlv2322 operating characteristics at specified free-air temperature, v dd = 3 v parameter test conditions t a tlv2322 unit parameter test conditions t a min typ max unit sr slew rate at unity gain v ic = 1 v, r l =1m w v i(pp) = 1 v, c l = 20 p f 25 c 0.02 v/ m s sr sl ew ra t e a t un it y ga i n r l = 1 m w , sfi 35 c l = 20 f , 85 c 002 v/ m s see figure 35 85 c 0 . 02 v n equivalent input noise voltage f = 1 khz, see figure 36 r s = 20 w , 25 c 68 nv/ hz b om maximum out p ut swing bandwidth v o = v oh , c l = 20 pf, 25 c 2.5 khz b om m ax i mum ou t pu t -sw i ng b an d w idth ooh , r l = 1 m w , l , see figure 35 85 c 2 kh z b 1 unity gain bandwidth v i = 10 mv, c l = 20 pf, 25 c 27 khz b 1 u n it y-ga i n b an d w idth i , r l = 1 m w , l , see figure 37 85 c 21 kh z v i = 10 mv, f= b 1 , 40 c 39 f m phase margin v i 10 mv , c l = 20 pf, f b 1 , r l = 1 m w , 25 c 34 see figure 37 85 c 28 tlv2322 operating characteristics at specified free-air temperature, v dd = 5 v parameter test conditions t a tlv2322 unit parameter test conditions t a min typ max unit v ic = 1v v i(pp) =1v 25 c 0.03 sr slew rate at unity gain v ic = 1 v , r l = 1 m w , v i(pp) = 1 v 85 c 0.03 v/ m s sr sl ew ra t e a t un it y ga i n l , c l = 20 pf, sfi 35 v i(pp) =25v 25 c 0.03 v/ m s see figure 35 v i(pp) = 2 . 5 v 85 c 0.02 v n equivalent input noise voltage f = 1 khz, see figure 36 r s = 20 w , 25 c 68 nv/ hz b om maximum out p ut swing bandwidth v o = v oh , c l = 20 pf, 25 c 5 khz b om m ax i mum ou t pu t -sw i ng b an d w idth ooh , r l = 1 m w , l , see figure 35 85 c 4 kh z b 1 unity gain bandwidth v i = 10 mv, c l = 20 pf, 25 c 85 khz b 1 u n it y-ga i n b an d w idth i , r l = 1 m w , l , see figure 37 85 c 55 kh z v i = 10 mv, f = b 1 , 40 c 38 f m phase margin v i 10 mv , c l = 20 pf, f b 1 , r l = 1 m w , 25 c 34 see figure 37 85 c 28
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 8 post office box 655303 ? dallas, texas 75265 tlv2324i electrical characteristics at specified free-air temperature 2 tlv2324i parameter test conditions t a 2 v dd = 3 v v dd = 5 v unit a min typ max min typ max v o = 1 v, 25 c 11 10 11 10 v io in p ut offset voltage v o 1 v , v ic = 1 v, 25 c 1 . 1 10 1 . 1 10 mv v io i npu t o ff se t vo lt age ic , r s = 50 w, full range 12 12 m v s r l = 1 m w , f u ll range 12 12 a vio average temperature coefficient 25 c to 1 11 m v/ c a vio g of input offset voltage 85 c 1 1 . 1 m v/ c i io in p ut offset current (see note 4) v o = 1 v, 25 c 0.1 0.1 p a i io i npu t o ff se t curren t ( see n o t e 4) o , v ic = 1 v 85 c 22 1000 24 1000 p a i ib in p ut bias current (see note 4) v o = 1 v, 25 c 0.6 0.6 p a i ib i npu t bi as curren t ( see n o t e 4) o , v ic = 1 v 85 c 175 2000 200 2000 p a 0.2 0.3 0.2 0.3 25 c to to to to v v icr common-mode input 2 2.3 4 4.2 v icr voltage range (see note 5) 0.2 0.2 full range to to v g 1.8 3.8 v ic =1v 25 c 175 19 32 38 v high level output voltage v ic = 1 v , v 100 mv 25 c 1 . 75 1 . 9 3 . 2 3 . 8 v v oh high-level output voltage v id = 100 mv, i oh = 1 ma full range 1.7 3 v v ic =1v 25 c 115 150 95 150 v low level output voltage v ic = 1 v , v 100 mv 25 c 115 150 95 150 mv v ol low-level output voltage v id = 100 mv, i ol = 1 ma full range 190 190 mv v ic =1v 25 c 50 400 50 520 a large-signal differential v ic = 1 v , r1m w 25 c 50 400 50 520 v/mv a vd gg voltage amplification r l = 1 m w , see note 6 full range 50 50 v/mv v o =1v 25 c 65 88 65 94 cmrr common mode rejection ratio v o = 1 v , v c v c min 25 c 65 88 65 94 db cmrr common-mode rejection ratio v ic = v icr min, r s = 50 w full range 60 60 db s l lt j ti ti v1vv1v 25 c 70 86 70 86 k svr supply-voltage rejection ratio v ic = 1 v, v o = 1 v, 25 c 70 86 70 86 db k svr ygj ( d v dd / d v io ) ic o r s = 50 w full range 65 65 db v1vv 1v 25 c 24 68 39 68 i dd su pp ly current v o = 1 v, v ic = 1 v, 25 c 24 68 39 68 m a i dd su ly current oic no load full range 108 108 m a 2 full range is 40 c to 85 c. notes: 4. the typical values of input bias current and input offset current below 5 pa are determined mathematically. 5. this range also applies to each input individually. 6. at v dd = 5 v, v o(pp) = 0.25 v to 2 v; at v dd = 3 v, v o = 0.5 v to 1.5 v.
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 9 post office box 655303 ? dallas, texas 75265 tlv2324i operating characteristics at specified free-air temperature, v dd = 3 v parameter test conditions t a tlv2324i unit parameter test conditions t a min typ max unit v ic = 1v v i(pp) = 1v 25 c 002 sr slew rate at unity gain v ic = 1 v , r l =1m w v i(pp) = 1 v , c l =20 p f 25 c 0 . 02 v/ m s sr sl ew ra t e a t un it y ga i n r l = 1 m w , sfi 35 c l = 20 p f , 85 c 002 v/ m s see figure 35 85 c 0 . 02 v equivalent in p ut noise voltage f = 1 khz, r s = 20 w , 25 c 68 nv /hz v n e qu i va l en t i npu t no i se vo lt age , see figure 36 s , 25 c 68 nv ?? ? ? ???? ?? ? ????? ???????? ? ? ? ? ? ? ? ? c 2.5 khz b om m ax i mum ou t pu t -sw i ng b an d w idth ooh , r l = 1 m w , l , see figure 35 85 c 2 kh z b 1 unity gain bandwidth v i = 10 mv, c l = 20 pf, 25 c 27 khz b 1 u n it y-ga i n b an d w idth i , r l = 1 m w , l , see figure 37 85 c 21 kh z v i = 10 mv, f = b 1 , 40 c 39 f m phase margin v i 10 mv , c l = 20 pf, f b 1 , r l = 1 m w , 25 c 34 see figure 37 85 c 28 tlv2324i operating characteristics at specified free-air temperature, v dd = 5 v parameter test conditions t a tlv2324i unit parameter test conditions t a min typ max unit v ic = 1v v i(pp) =1v 25 c 0.03 sr slew rate at unity gain v ic = 1 v , r l = 1 m w , v i(pp) = 1 v 85 c 0.03 v/ m s sr sl ew ra t e a t un it y ga i n l , c l = 20 pf, sfi 35 v i(pp) =25v 25 c 0.03 v/ m s see figure 35 v i(pp) = 2 . 5 v 85 c 0.02 v equivalent in p ut noise voltage f = 1 khz, r s = 20 w , 25 c 68 nv/ hz v n e qu i va l en t i npu t no i se vo lt age , see figure 36 s , 25 c 68 nv/ ?? ? ? ???? ?? ? ????? ???????? ? ? ? ? ? ? ? ? c 5 khz b om m ax i mum ou t pu t -sw i ng b an d w idth ooh , r l = 1 m w , l , see figure 35 85 c 4 kh z b 1 unity gain bandwidth v i = 10 mv, c l = 20 pf, 25 c 85 khz b 1 u n it y-ga i n b an d w idth i , r l = 1 m w , l , see figure 37 85 c 55 kh z v i = 10 mv, f = b 1 , 40 c 38 f m phase margin v i 10 mv , c l = 20 pf, f b 1 , r l = 1 m w , 25 c 34 see figure 37 85 c 28
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 10 post office box 655303 ? dallas, texas 75265 tlv2322y electrical characteristics, t a = 25 c tlv2322y parameter test conditions v dd = 3 v v dd = 5 v unit min typ max min typ max v io input offset voltage v o = 1 v, r s = 50 w , v ic = 1 v, r l = 1 m w 1.1 1.1 mv i io input offset current (see note 4) v o = 1 v, v ic = 1 v 0.1 0.1 pa i ib input bias current (see note 4) v o = 1 v, v ic = 1 v 0.6 0.6 pa v icr common-mode input voltage range (see note 5) 0.3 to 2.3 0.3 to 4.2 v v oh high-level output voltage v ic = 1 v, i oh = 1 ma v id = 100 mv, 1.9 3.8 v v ol low-level output voltage v ic = 1 v, i ol = 1 ma v id = 100 mv, 115 95 mv a vd large-signal differential voltage amplification v ic = 1 v, see note 6 r l = 1 m w, 400 520 v/mv cmrr common-mode rejection ratio v o = 1 v, r s = 50 w v ic = v icr min, 88 94 db k svr supply-voltage rejection ratio ( d v dd / d v id ) v o = 1 v, r s = 50 w v ic = 1 v, 86 86 db i dd supply current v o = 1 v, no load v ic = 1 v, 12 20 m a notes: 4. the typical values of input bias current offset current below 5 pa are determined mathematically. 5. this range also applies to each input individually. 6. at v dd = 5 v, v o = 0.25 v to 2 v; at v dd = 3 v, v o = 0.5 v to 1.5 v.
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 11 post office box 655303 ? dallas, texas 75265 tlv2322y electrical characteristics,t a = 25 c tlv2324y parameter test conditions v dd = 3 v v dd = 5 v unit min typ max min typ max v io input offset voltage v o = 1 v, r s = 50 w , v ic = 1 v, r l = 1 m w 1.1 1.1 mv i io input offset current (see note 4) v o = 1 v, v ic = 1 v 0.1 0.1 pa i ib input bias current (see note 4) v o = 1 v, v ic = 1 v 0.6 0.6 pa v icr common-mode input voltage range (see note 5) 0.3 to 2.3 0.3 to 4.2 v v oh high-level output voltage v ic = 1 v, i oh = 1 ma v id = 100 mv, 1.9 3.8 v v ol low-level output voltage v ic = 1 v, i ol = 1 ma v id = 100 mv, 115 95 mv a vd large-signal differential voltage amplification v ic = 1 v, see note 6 r l = 1 m w , 400 520 v/mv cmrr common-mode rejection ratio v o = 1 v, r s = 50 w v ic = v icr min, 88 94 db k svr supply-voltage rejection ratio ( d v dd / d v id ) v o = 1 v, r s = 50 w v ic = 1 v, 86 86 db i dd supply current v o = 1 v, no load v ic = 1 v, 24 39 m a notes: 4. the typical values of input bias current offset current below 5 pa are determined mathematically. 5. this range also applies to each input individually. 6. at v dd = 5 v, v o = 0.25 v to 2 v; at v dd = 3 v, v o = 0.5 v to 1.5 v.
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 12 post office box 655303 ? dallas, texas 75265 typical characteristics table of graphs figure v io input offset voltage distribution 1 4 a vio input offset voltage temperature coefficient distribution 5 8 i ib input bias current vs free-air temperature 9 i io input offset current vs free-air temperature 9 v ic common-mode input voltage vs supply voltage 10 v oh high-level output voltage vs high-level output current vs supply voltage vs free-air temperature 11 12 13 v ol low-level output voltage vs common-mode input voltage vs free-air temperature vs differential input voltage vs low-level output current 14 15, 16 17 18 a vd large-signal differential voltage amplification vs supply voltage vs free-air temperature vs frequency 19 20 21, 22 i dd supply current vs supply voltage vs free-air temperature 23 24, 25 sr slew rate vs supply voltage vs free-air temperature 26 27 v o(pp) maximum peak-to-peak output voltage vs frequency 28 b 1 unity-gain bandwidth vs supply voltage vs free-air temperature 29 30 f m phase margin vs supply voltage vs free-air temperature vs load capacitance 31 32 33 phase shift vs frequency 21, 22 v n equivalent input noise voltage vs frequency 34
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 13 post office box 655303 ? dallas, texas 75265 typical characteristics figure 1 50 40 20 10 0 30 1 0 1 percentage of units % 2345 distribution of tlv2322 input offset voltage v io input offset voltage mv v dd = 3 v t a = 25 c p package 5 4 3 2 figure 2 50 40 20 10 0 30 1 0 1 70 60 2345 percentage of units % v io input offset voltage mv distribution of tlv2322 input offset voltage v dd = 5 v t a = 25 c p package 5 4 3 2 figure 3 50 40 20 10 0 30 5 4 3 2 1 0 1 percentage of units % 2345 distribution of tlv2324 input offset voltage v io input offset voltage mv v dd = 3 v t a = 25 c n package figure 4 50 40 20 10 0 30 5 4 3 2 1 0 1 70 60 2345 percentage of units % v io input offset voltage mv distribution of tlv2324 input offset voltage v dd = 5 v t a = 25 c n package
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 14 post office box 655303 ? dallas, texas 75265 typical characteristics figure 5 10 0 2 percentage of units % 46810 a vio temperature coefficient m v/ c 50 40 20 10 0 30 distribution of tlv2322 input offset voltage temperature coefficient v dd = 3 v t a = 25 c to 85 c p package 8 6 4 2 figure 6 a vio temperature coefficient m v/ c percentage of units % 10 0246810 50 40 20 10 0 30 70 60 distribution of tlv2322 input offset voltage temperature coefficient v dd = 5 v t a = 25 c to 85 c p package outliers: (1) 19.2 mv/ c (1) 12.1 mv/ c 8 6 4 2 figure 7 10 8 6 4 2 0 2 percentage of units % 46810 a vio temperature coefficient m v/ c 50 40 20 10 0 30 v dd = 3 v t a = 25 c to 85 c n package distribution of tlv2324 input offset voltage temperature coefficient figure 8 a vio temperature coefficient m v/ c percentage of units % 1086420246810 50 40 20 10 0 30 70 60 distribution of tlv2324 input offset voltage temperature coefficient v dd = 5 v t a = 25 c to 85 c n package outliers: (1) 19.2 mv/ c (1) 12.1 mv/ c
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 15 post office box 655303 ? dallas, texas 75265 typical characteristics figure 9 input bias current and input offset current vs free-air temperature t a free-air temperature c iib and iio input bias and offset currents pa i ib i io 10 4 10 3 10 2 10 1 1 0.1 25 45 65 85 105 125 v dd = 3 v v ic = 1 v see note a i ib i io note a: the typical values of input bias current and input offset current below 5 pa were determined mathematically. figure 10 4 2 0 8 6 02 46 8 v dd supply voltage v vic common-mode input voltage v ic v t a = 25 c positive limit common-mode input voltage vs supply voltage figure 11 v0h high-level output voltage v v oh 3 2 1 0 0 4 5 i oh high-level output current ma high-level output voltage vs high-level output current v ic = 1 v v id = 100 mv t a = 25 c v dd = 3 v v dd = 5 v 2 4 6 8 figure 12 4 2 0 8 6 02 46 8 high-level output voltage vs supply voltage v dd supply voltage v v ic = 1 v v id = 100 mv r l = 1 m w t a = 25 c v0h high-level output voltage v v oh
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 16 post office box 655303 ? dallas, texas 75265 typical characteristics figure 13 1.8 1.2 0.6 0 2.4 3 high-level output voltage vs free-air temperature 75 50 25 0 25 50 75 100 125 t a free-air temperature c v dd = 3 v v ic = 1 v v id = 100 mv i oh = 500 m a i oh = 1 ma i oh = 2 ma i oh = 3 ma i oh = 4 ma v0h high-level output voltage v v oh figure 14 500 400 350 300 0 0.5 1 1.5 2 2.5 600 650 700 3 3.5 4 550 450 low-level output voltage vs common-mode input voltage v ic common-mode input voltage v v dd = 5 v i ol = 5 ma t a = 25 c v id = 100 mv v id = 1 v vol low-level output voltage mv v ol figure 15 75 50 25 0 25 50 75 100 125 125 110 80 65 50 185 95 155 140 170 200 low-level output voltage vs free-air temperature t a free-air temperature c v dd = 3 v v ic = 1 v v id = 100 mv i ol = 1 ma vol low-level output voltage mv v ol 400 200 100 0 600 700 800 500 300 low-level output voltage vs free-air temperature 900 75 50 25 0 25 50 75 100 125 t a free-air temperature c v dd = 5 v v ic = 0.5 v v id = 1 v i ol = 5 ma vol low-level output voltage mv v ol figure 16
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 17 post office box 655303 ? dallas, texas 75265 typical characteristics figure 17 400 200 100 0 012345 600 700 800 6 7 8 500 300 low-level output voltage vs differential input voltage v id differential input voltage v v dd = 5 v v ic = |v id /2| i ol = 5 ma t a = 25 c vol low-level output voltage mv v ol figure 18 0.5 0.4 0.2 0.1 0 0.9 0.3 0123456 0.7 0.6 0.8 1 78 low-level output voltage vs low-level output current i ol low-level output current ma v ic = 1 v v id = 1 v t a = 25 c v dd = 3 v v dd = 5 v vol low-level output voltage mv v ol figure 19 1000 800 400 200 0 1800 600 02468 1400 1200 1600 large-signal differential voltage amplification vs supply voltage 2000 v dd supply voltage v r l = 1 m w t a = 25 c t a = 85 c t a = 40 c large-signal differential voltage a vd amplification v/mv figure 20 large-signal differential voltage amplification vs free-air temperature 1000 800 400 200 0 1800 600 1400 1200 1600 2000 75 50 25 0 25 50 75 100 125 t a free-air temperature c r l = 1 m w v dd = 5 v v dd = 3 v large-signal differential voltage a vd amplification v/mv
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 18 post office box 655303 ? dallas, texas 75265 typical characteristics large-signal differential voltage amplification and phase shift vs frequency 1 10 100 1 k 10 k 100 k f frequency hz 1 m large-signal differential vd a phase shift 60 30 0 30 60 90 120 150 180 10 7 10 6 10 5 10 4 10 3 10 2 10 1 0.1 v dd = 3 v r l = 1 m w c l = 20 pf t a = 25 c a vd phase shift 1 voltage amplification figure 21 0 large-signal differential voltage amplification and phase shift vs frequency 1 10 100 1 k 10 k 100 k 1 m f frequency hz phase shift 60 30 30 60 90 120 150 180 10 6 10 5 10 4 10 3 10 2 10 1 1 a vd phase shift 10 7 0.1 v dd = 5 v r l = 1 m w c l = 20 pf t a = 25 c large-signal differential vd a voltage amplification figure 22
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 19 post office box 655303 ? dallas, texas 75265 typical characteristics figure 23 20 10 5 0 30 15 02 46 8 25 supply current vs supply voltage 35 45 40 v dd supply voltage v idd supply current ma dd i a m t a = 40 c t a = 25 c v ic = 1 v v o = 1 v no load t a = 85 c figure 24 20 10 5 0 30 35 25 15 75 50 25 0 25 50 75 100 125 t a free-air temperature c v ic = 1 v v o = 1 v no load v dd = 5 v v dd = 3 v idd supply current ma dd i a m tlv2322 supply current vs free-air temperature figure 25 idd supply current ma dd i a m 75 50 25 0 25 50 75 100 125 0 20 40 60 80 100 t a free-air temperature c 120 v dd = 5 v v ic = 1 v v o = 1 v no load v dd = 3 v tlv2324 supply current vs free-air temperature figure 26 0.04 0.02 0.01 0 0.06 0.03 02 46 8 0.05 slew rate vs supply voltage 0.07 v dd supply voltage v v ic = 1 v v i(pp) = 1 v a v = 1 r l = 1 m w c l = 20 pf t a = 25 c sr slew rate v/us s m v/
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 20 post office box 655303 ? dallas, texas 75265 typical characteristics figure 27 0.04 0.02 0.01 0 0.06 0.07 0.05 0.03 slew rate vs free-air temperature 75 50 25 0 25 50 75 100 125 t a free-air temperature c v ic = 1 v v i(pp) = 1 v a v = 1 r l = 1 m w c l = 20 pf v dd = 5 v v dd = 3 v sr slew rate v/us s m v/ figure 28 3 2 1 0 maximum peak-to-peak output voltage v 4 f frequency khz 5 maximum peak-to-peak output voltage vs frequency v o(pp) 0.1 1 10 100 v dd = 5 v v dd = 3 v r l = 1 m w t a = 40 c t a = 85 c t a = 25 c figure 29 70 60 40 30 20 110 50 0123456 90 80 100 120 78 unity-gain bandwidth vs supply voltage v dd supply voltage v b1 unity-gain bandwidth mhz b 1 v i = 10 mv r l = 1 m w c l = 20 pf t a = 25 c figure 30 b1 unity-gain bandwidth khz 80 50 35 20 110 125 140 95 65 unity-gain bandwidth vs free-air temperature 75 50 25 0 25 50 75 100 125 t a free-air temperature c b 1 v i = 10 mv r l = 1 m w c l = 20 pf v dd = 5 v v dd = 3 v
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 21 post office box 655303 ? dallas, texas 75265 typical characteristics figure 31 02 46 8 om phase margin phase margin vs supply voltage v dd supply voltage v f m v i = 10 mv r l = 1 m w c l = 20 pf t a = 25 c 42 40 38 36 34 32 30 figure 32 phase margin vs free-air temperature 75 50 25 0 25 50 75 100 125 t a free-air temperature c v dd = 3 v v dd = 5 v 40 38 36 34 32 30 28 26 24 22 20 om phase margin f m v i = 10 mv r l = 1 m w c l = 20 pf figure 33 40 38 36 34 32 30 28 26 24 22 20 0 102030405060708090100 phase margin vs load capacitance c l load capacitance pf v i = 10 mv r l = 1 m w t a = 25 c v dd = 5 v v dd = 3 v om phase margin f m figure 34 0 f frequency hz equivalent input noise voltage vs frequency 100 75 25 125 175 200 50 150 1 10 100 1000 vn equivalent input noise voltage nv hz v n nv/ hz v dd = 3 v, 5 v r s = 20 w t a = 25 c
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 22 post office box 655303 ? dallas, texas 75265 parameter measurement information single-supply versus split-supply test circuits because the tlv232x is optimized for single-supply operation, circuit configurations used for the various tests often present some inconvenience since the input signal, in many cases, must be offset from ground. this inconvenience can be avoided by testing the device with split supplies and the output load tied to the negative rail. a comparison of single-supply versus split-supply test circuits is shown below. the use of either circuit gives the same result. + + v dd v i c l r l v o v dd + v dd v i v o c l r l (a) single supply (b) split supply figure 35. unity-gain amplifier + + 1/2 v dd v dd 20 w 20 w 2 k w 2 k w v dd + v dd v o v o 20 w 20 w (a) single supply (b) split supply figure 36. noise-test circuits + + 10 k w 1/2 v dd 100 w v o v dd v i v i 100 w (a) single supply (b) split supply 10 k w v dd + v dd c l c l v o figure 37. gain-of-100 inverting amplifier
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 23 post office box 655303 ? dallas, texas 75265 parameter measurement information input bias current because of the high input impedance of the tlv232x operational amplifier, attempts to measure the input bias current can result in erroneous readings. the bias current at normal ambient temperature is typically less than 1 pa, a value that is easily exceeded by leakages on the test socket. two suggestions are offered to avoid erroneous measurements: ? isolate the device from other potential leakage sources. use a grounded shield around and between the device inputs (see figure 38). leakages that would otherwise flow to the inputs are shunted away. ? compensate for the leakage of the test socket by actually performing an input bias current test (using a picoammeter) with no device in the test socket. the actual input bias current can then be calculated by subtracting the open-socket leakage readings from the readings obtained with a device in the test socket. many automatic testers as well as some bench-top operational amplifier testers use the servo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage drop across the series resistor is measured and the bias current is calculated). this method requires that a device be inserted into a test socket to obtain a correct reading; therefore, an open-socket reading is not feasible using this method. v = v ic 8 5 1 4 figure 38. isolation metal around device inputs (p package) low-level output voltage to obtain low-level supply-voltage operation, some compromise is necessary in the input stage. this compromise results in the device low-level output voltage being dependent on both the common-mode input voltage level as well as the differential input voltage level. when attempting to correlate low-level output readings with those quoted in the electrical specifications, these two conditions should be observed. if conditions other than these are to be used, please refer to the typical characteristics section of this data sheet. input offset voltage temperature coefficient erroneous readings often result from attempts to measure the temperature coefficient of input offset voltage. this parameter is actually a calculation using input offset voltage measurements obtained at two different temperatures. when one (or both) of the temperatures is below freezing, moisture can collect on both the device and the test socket. this moisture results in leakage and contact resistance that can cause erroneous input offset voltage readings. the isolation techniques previously mentioned have no effect on the leakage since the moisture also covers the isolation metal itself, thereby rendering it useless. these measurements should be performed at temperatures above freezing to minimize error. full-power response full-power response, the frequency above which the operational amplifier slew rate limits the output voltage swing, is often specified two ways: full-linear response and full-peak response. the full-linear response is
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 24 post office box 655303 ? dallas, texas 75265 parameter measurement information generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal input signal until the maximum frequency is found above which the output contains significant distortion. the full-peak response is defined as the maximum output frequency, without regard to distortion, above which full peak-to-peak output swing cannot be maintained. because there is no industry-wide accepted value for significant distortion, the full-peak response is specified in this data sheet and is measured using the circuit of figure 35. the initial setup involves the use of a sinusoidal input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is increased until clipping occurs). the sinusoidal wave is then replaced with a square wave of the same amplitude. the frequency is then increased until the maximum peak-to-peak output can no longer be maintained (figure 39). a square wave is used to allow a more accurate determination of the point at which the maximum peak-to-peak output is reached. (d) f > b om (d) f = b om (d) b om > f > 100 hz (a) f = 100 hz figure 39. full-power-response output signal test time inadequate test time is a frequent problem, especially when testing cmos devices in a high-volume, short-test-time environment. internal capacitances are inherently higher in cmos than in bipolar and bifet devices and require longer test times than their bipolar and bifet counterparts. the problem becomes more pronounced with reduced supply levels and lower temperatures. application information single-supply operation while the tlv232x performs well using dual- power supplies (also called balanced or split supplies), the design is optimized for single- supply operation. this includes an input common- mode voltage range that encompasses ground as well as an output voltage range that pulls down to ground. the supply voltage range extends down to 2 v, thus allowing operation with supply levels commonly available for ttl and hcmos. many single-supply applications require that a voltage be applied to one input to establish a reference level that is above ground. this virtual ground can be generated using two large resistors, but a preferred technique is to use a virtual-ground generator such as the tle2426 (see figure 40). the tle2426 supplies an accurate voltage equal to v dd /2, while consuming very little power and is suitable for supply voltages of greater than 4 v. v o v dd v i 2 r2 r1 v dd 2 + tle2426 v o v i r1 r2 v dd figure 40. inverting amplifier with voltage reference
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 25 post office box 655303 ? dallas, texas 75265 application information single-supply operation (continued) the tlv232x works well in conjunction with digital logic; however, when powering both linear devices and digital logic from the same power supply, the following precautions are recommended: ? power the linear devices from separate bypassed supply lines (see figure 41); otherwise, the linear device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital logic. ? use proper bypass techniques to reduce the probability of noise-induced errors. single capacitive decoupling is often adequate; however, rc decoupling may be necessary in high-frequency applications. + logic logic logic power supply + logic logic logic power supply (a) common-supply rails (b) separate-bypassed supply rails (preferred) figure 41. common versus separate supply rails input characteristics the tlv232x is specified with a minimum and a maximum input voltage that, if exceeded at either input, could cause the device to malfunction. exceeding this specified range is a common problem, especially in single-supply operation. the lower the range limit includes the negative rail, while the upper range limit is specified at v dd 1 v at t a = 25 c and at v dd 1.2 v at all other temperatures. the use of the polysilicon-gate process and the careful input circuit design gives the tlv232x very good input offset voltage drift characteristics relative to conventional metal-gate processes. offset voltage drift in cmos devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant implanted in the oxide. placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. the offset voltage drift with time has been calculated to be typically 0.1 m v/month, including the first month of operation. because of the extremely high input impedance and resulting low bias-current requirements, the tlv232x is well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets can easily exceed bias-current requirements and cause a degradation in device performance. it is good practice to include guard rings around inputs (similar to those of figure 38 in the parameter measurement information section). these guards should be driven from a low-impedance source at the same voltage level as the common-mode input (see figure 42). the inputs of any unused amplifiers should be tied to ground to avoid possible oscillation.
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 26 post office box 655303 ? dallas, texas 75265 application information input characteristics (continued) + + + (a) noninverting amplifier (b) inverting amplifier (c) unity-gain amplifier v i v i v i v o v o v o figure 42. guard-ring schemes noise performance the noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage differential amplifier. the low input bias-current requirements of the tlv232x result in a very low noise current, which is insignificant in most applications. this feature makes the device especially favorable over bipolar devices when using values of circuit impedance greater than 50 k w , since bipolar devices exhibit greater noise currents. feedback operational amplifier circuits nearly always employ feedback, and since feedback is the first prerequisite for oscillation, caution is appropriate. most oscillation problems result from driving capacitive loads and ignoring stray input capacitance. a small-value capacitor connected in parallel with the feedback resistor is an effective remedy (see figure 43). the value of this capacitor is optimized empirically. electrostatic-discharge protection the tlv232x incorporates an internal electrostatic-discharge (esd)-protection circuit that prevents functional failures at voltages up to 2000 v as tested under mil-prf-38535, method 3015.2. care should be exercised, however, when handling these devices as exposure to esd can result in the degradation of the device parametric performance. the protection circuit also causes the input bias currents to be temperature dependent and have the characteristics of a reverse-biased diode. latch-up because cmos devices are susceptible to latch-up due to their inherent parasitic thyristors, the tlv232x inputs and outputs are designed to withstand 100-ma surge currents without sustaining latch-up; however, techniques should be used to reduce the chance of latch-up whenever possible. internal-protection diodes should not by design be forward biased. applied input and output voltage should not exceed the supply voltage + figure 43. compensation for input capacitance
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 27 post office box 655303 ? dallas, texas 75265 application information by more than 300 mv. care should be exercised when using capacitive coupling on pulse generators. supply transients should be shunted by the use of decoupling capacitors (0.1 m f typical) located across the supply rails as close to the device as possible. the current path established if latch-up occurs is usually between the positive supply rail and ground and can be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply voltage. once latch-up occurs, the current flow is limited only by the impedance of the power supply and the forward resistance of the parasitic thyristor and usually results in the destruction of the device. the chance of latch-up occurring increases with increasing temperature and supply voltages. output characteristics the output stage of the tlv232x is designed to sink and source relatively high amounts of current (see typical characteristics). if the output is subjected to a short-circuit condition, this high-current capability can cause device damage under certain conditions. output current capability increases with supply voltage. although the tlv232x possesses excellent high-level output voltage and current capability, methods are available for boosting this capability, if needed. the simplest method involves the use of a pullup resistor (r p ) connected from the output to the positive supply rail (see figure 44). there are two disadvantages to the use of this circuit. first, the nmos pulldown transistor n4 (see equivalent schematic) must sink a comparatively large amount of current. in this circuit, n4 behaves like a linear resistor with an on resistance between approximately 60 w and 180 w depending on how hard the operational amplifier input is driven. with very low values of r p , a voltage offset from 0 v at the output occurs. secondly, pullup resistor r p acts as a drain load to n4 and the gain of the operational amplifier is reduced at output voltage levels where n5 is not supplying the output current. all operating characteristics of the tlv232x are measured using a 20-pf load. the device drives higher capacitive loads; however, as output load capacitance increases, the resulting response pole occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation (see figure 45 and figure 46). in many cases, adding some compensation in the form of a series resistor in the feedback loop alleviates the problem. + v o c l v i 2.5 v t a = 25 c f = 1 khz v i(pp) = 1 v 2.5 v + r p v dd v o i f i l i p i p = pullup current required by the operational amplifier (typically 500 m a) v o v dd r p i p i f i l r l v i r1 r2 figure 44. resistive pullup to increase v oh figure 45. test circuit for output characteristics
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 28 post office box 655303 ? dallas, texas 75265 application information output characteristics (continued) (a) c l = 20 pf, r l = no load (b) c l = 260 pf, r l = no load (c) c l = 310 pf, r l = no load figure 46. effect of capacitive loads
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 29 post office box 655303 ? dallas, texas 75265 mechanical information d (r-pdso-g**) plastic small-outline package 14 pin shown 4040047 / b 03/95 0.228 (5,80) 0.244 (6,20) 0.069 (1,75) max 0.010 (0,25) 0.004 (0,10) 1 14 0.014 (0,35) 0.020 (0,51) a 0.157 (4,00) 0.150 (3,81) 7 8 0.044 (1,12) 0.016 (0,40) seating plane 0.010 (0,25) pins ** 0.008 (0,20) nom a min a max dim gage plane 0.189 (4,80) (5,00) 0.197 8 (8,55) (8,75) 0.337 14 0.344 (9,80) 16 0.394 (10,00) 0.386 0.004 (0,10) m 0.010 (0,25) 0.050 (1,27) 0 8 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). d. four center pins are connected to die mount pad. e. falls within jedec ms-012
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 30 post office box 655303 ? dallas, texas 75265 mechanical information n (r-pdip-t**) plastic dual-in-line package 20 0.975 (24,77) 0.940 (23,88) 18 0.920 0.850 14 0.775 0.745 (19,69) (18,92) 16 0.775 (19,69) (18,92) 0.745 a min dim a max pins ** 0.310 (7,87) 0.290 (7,37) (23.37) (21.59) seating plane 0.010 (0,25) nom 14/18 pin only 4040049/c 08/95 9 8 0.070 (1,78) max a 0.035 (0,89) max 0.020 (0,51) min 16 1 0.015 (0,38) 0.021 (0,53) 0.200 (5,08) max 0.125 (3,18) min 0.240 (6,10) 0.260 (6,60) m 0.010 (0,25) 0.100 (2,54) 0 15 16 pin shown notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms-001 (20 pin package is shorter then ms-001.)
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 31 post office box 655303 ? dallas, texas 75265 mechanical information p (r-pdip-t8) plastic dual-in-line package 4040082 / b 03/95 0.310 (7,87) 0.290 (7,37) 0.010 (0,25) nom 0.400 (10,60) 0.355 (9,02) 5 8 4 1 0.020 (0,51) min 0.070 (1,78) max 0.240 (6,10) 0.260 (6,60) 0.200 (5,08) max 0.125 (3,18) min 0.015 (0,38) 0.021 (0,53) seating plane m 0.010 (0,25) 0.100 (2,54) 0 15 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms-001
tlv2322, tlv2322y, tlv2324, tlv2324y lincmos ? low-voltage low-power operational amplifiers slos187 february 1997 32 post office box 655303 ? dallas, texas 75265 mechanical information pw (r-pdso-g**) plastic small-outline package 4040064 / d 10/95 14 pin shown seating plane 0,10 min 1,20 max 1 a 7 14 0,19 4,50 4,30 8 6,10 6,70 0,32 0,75 0,50 0,25 gage plane 0,15 nom 0,65 m 0,13 0 8 0,10 pins ** a min a max dim 2,90 3,10 8 4,90 5,10 14 6,60 6,40 4,90 5,10 16 7,70 20 7,90 24 9,60 9,80 28 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
important notice texas instruments (ti) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. ti warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the risk of the customer. use of ti products in such applications requires the written approval of an appropriate ti officer. questions concerning potential risk applications should be directed to ti through a local sc sales office. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. nor does ti warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. copyright ? 1997, texas instruments incorporated

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