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dual 12-bit, high bandwidth, multiplying dac with 4-quadrant resistors and parallel interface ad5405 rev. b information furnished by analog devices is believed to be a ccurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chan ge without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2009 analog devices, inc. all rights reserved. features 10 mhz multiplying bandwidth on-chip 4-quadrant resistors allow flexible output ranges inl of 1 lsb 40-lead lfcsp package 2.5 v to 5.5 v supply operation 10 v reference input 21.3 msps update rate extended temperature range: ?40c to 125c 4-quadrant multiplication power-on reset 0.5 a typical current consumption guaranteed monotonic readback function applications portable battery-powered applications waveform generators analog processing instrumentation applications programmable amplifiers and attenuators digitally controlled calibration programmable filters and oscillators composite video ultrasound gain, offset, and voltage trimming general description the ad5405 1 is a cmos, 12-bit, dual-channel, current output digital-to-analog converter (dac). this device operates from a 2.5 v to 5.5 v power supply, making it suited to battery-powered and other applications. as a result of manufacture with a cmos submicron process, the device offers excellent 4-quadrant multiplication characteristics, with large signal multiplying bandwidths of up to 10 mhz. the applied external reference input voltage (v ref ) determines the full-scale output current. an integrated feedback resistor (r fb ) provides temperature tracking and full-scale voltage output when combined with an external i-to-v precision amplifier. this device also contains the 4-quadrant resistors necessary for bipolar operation and other configuration modes. this dac uses data readback, allowing the user to read the contents of the dac register via the db pins. on power-up, the internal register and latches are filled with 0s, and the dac outputs are at zero scale. the ad5405 has a 6 mm 6 mm, 40-lead lfcsp package. 1 u.s. patent number 5,689,257. functional block diagram v ref a ad5405 v ref b v dd db0 db11 data inputs dac a/b cs r/w gnd control logic input buffer latch i out 1b i out 1a 12-bit r-2r dac a r fb a power-on reset 12-bit r-2r dac b latch r1 2r r1a r2 2r r3 2r r3a r2a r2_3a r2 2r r3 2r r3b r2b r2_3b rfb 2r r1 2r rfb 2r r1b i out 2a i out 2b ldac 04463-001 clr r fb b figure 1.
important links for the ad5405 * last content update 10/02/2013 03:07 pm parametric selection tables find similar products by operating parameters data converters: overview of ad54xx devices ad5415 dual 12-bit, high bandwidth, multiplying dac with 4 quadrant resistors and serial interface ad5449 dual 12-bit, high bandwidth multiplying dac with serial interface documentation an-1085: multiplying dacsac/arbitrary reference applications an-912: driving a center-tapped transformer with a balanced current-output dac an-320a: cmos multiplying dacs and op amps combine to build programmable gain amplifier, part 1 an-320b: cmos multiplying dacs and op amps combine to build programmable gain amplifiers, part 2 an-137: a digitally programmable gain and attenuation amplifier design digital to analog converters ics solutions bulletin 4-quadrant multiplying d/a converters evaluation kits & symbols & footprints view the evaluation boards and kits page for documentation and purchasing symbols and footprints design collaboration community collaborate online with the adi support team and other designers about select adi products. follow us on twitter: www.twitter.com/adi_news like us on facebook: www.facebook.com/analogdevicesinc design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy ad5405 view price & packaging request evaluation board request samples check inventory & purchase find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
ad5405 rev. b | page 2 of 24 table of contents specifications ..................................................................................... 3 ? timing characteristics ................................................................ 5 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? te r m i no l o g y .................................................................................... 13 ? general description ....................................................................... 14 ? dac section ................................................................................ 14 ? circuit operation ....................................................................... 14 ? single-supply applications ....................................................... 15 ? adding gain ................................................................................ 15 ? divider or programmable gain element ................................ 16 ? reference selection .................................................................... 16 ? amplifier selection .................................................................... 16 ? parallel interface ......................................................................... 18 ? microprocessor interfacing ....................................................... 18 ? pcb layout and power supply decoupling ........................... 19 ? evaluation board for the dacs ................................................ 19 ? power supplies for the evaluation board ................................ 19 ? overview of ad54xx devices ....................................................... 22 ? outline dimensions ....................................................................... 23 ? ordering guide .......................................................................... 23 ? revision history 12/09rev. a to rev. b changes to figure 1 .......................................................................... 1 changes to table 2 and figure 2 ..................................................... 5 changes to table 4 and figure 4 ..................................................... 7 updated outline dimensions ....................................................... 23 changes to ordering guide .......................................................... 23 7/05rev. 0 to rev. a changed pin dac a/b to dac a /b ................................ universal changes to features list .................................................................. 1 changes to specifications ................................................................ 3 changes to timing characteristics ................................................ 5 change to absolute maximum ratings ......................................... 6 change to figure 7 and figure 8..................................................... 8 change to figure 12 ......................................................................... 9 change to figure 26 through figure 28 ..................................... 11 changes to general description section .................................... 14 change to figure 31 ....................................................................... 14 changes to table 5 through table 10 .......................................... 14 changes to figure 34 and figure 35 ............................................. 15 changes to figure 36 and figure 37 ............................................. 16 changes to microprocessor interfacing section ........................ 18 added figure 38 through figure 40............................................ 18 change to power supplies for the evaluation board section ... 19 updated outline dimensions ....................................................... 23 changes to ordering guide .......................................................... 23 7/04revision 0: initial version
ad5405 rev. b | page 3 of 24 specifications 1 v dd = 2.5 v to 5.5 v, v ref = 10 v, i out 2 = 0 v. temperature range for y version: ?40c to +125c. all specifications t min to t max , unless otherwise noted. dc performance is measured with op177, and ac performance is measured with ad8038, unless otherwise noted. table 1. parameter min typ max unit conditions static performance resolution 12 bits relative accuracy 1 lsb differential nonlinearity ?1/+2 lsb guaranteed monotonic gain error 25 mv gain error temperature coefficient 5 ppm fsr/c bipolar zero-code error 25 mv output leakage current 1 na data = 0x0000, t a = 25c, i out 1 15 na data = 0x0000, t a = ?40c to +125c, i out 1 reference input reference input range 10 v v ref a, v ref b input resistance 8 10 13 k input resistance tc = ?50 ppm/c v ref a-to-v ref b input resistance mismatch 1.6 2.5 % typ = 25c, max = 125c r1, r fb resistance 17 20 25 k input resistance tc = ?50 ppm/c r2, r3 resistance 17 20 25 k input resistance tc = ?50 ppm/c r2-to-r3 resistance mismatch 0.06 0.18 % typ = 25c, max = 125c input capacitance code 0 3.5 pf code 4095 3.5 pf digital inputs/output input high voltage, v ih 1.7 v v dd = 3.6 v to 5.5 v 1.7 v v dd = 2.5 v to 3.6 v input low voltage, v il 0.8 v v dd = 2.7 v to 5.5 v 0.7 v v dd = 2.5 v to 2.7 v output high voltage, v oh v dd ? 1 v v dd = 4.5 v to 5.5 v, i source = 200 a v dd ? 0.5 v v dd = 2.5 v to 3.6 v, i source = 200 a output low voltage, v ol 0.4 v v dd = 4.5 v to 5.5 v, i sink = 200 a 0.4 v v dd = 2.5 v to 3.6 v, i sink = 200 a input leakage current, i il 1 a input capacitance 4 10 pf dynamic performance reference-multiplying bw 10 mhz v ref = 3.5 v p-p, dac loaded all 1s output voltage settling time r load = 100 , c load = 15 pf, v ref = 10 v dac latch alternately loaded with 0s and 1s measured to 1 mv of fs 80 120 ns measured to 4 mv of fs 35 70 ns measured to 16 mv of fs 30 60 ns digital delay 20 40 ns interface time delay 10% to 90% settling time 15 30 ns rise and fall times digital-to-analog glitch impulse 3 nv-s ec 1 lsb change around major carry, v ref = 0 v multiplying feedthrough error dac latch loaded with all 0s, v ref = 3.5 v 70 db 1 mhz 48 db 10 mhz output capacitance 12 17 pf dac latches loaded with all 0s 25 30 pf dac latches loaded with all 1s
ad5405 rev. b | page 4 of 24 parameter min typ max unit conditions digital feedthrough 1 nv-sec feedthrough to dac output with cs high and alternate loading of all 0s and all 1s output noise spectral dens ity 25 nv/hz @ 1 khz analog thd 81 db v ref = 3. 5 v p-p, all 1s loaded, f = 1 khz digital thd clock = 10 mhz, v ref = 3.5 v 100 khz f out 61 db 50 khz f out 66 db sfdr performance (wideband) v ref = 3.5 v clock = 10 mhz 500 khz f out 55 db 100 khz f out 63 db 50 khz f out 65 db clock = 25 mhz 500 khz f out 50 db 100 khz f out 60 db 50 khz f out 62 db sfdr performance (narrow band) v ref = 3.5 v clock = 10 mhz 500 khz f out 73 db 100 khz f out 80 db 50 khz f out 87 db clock = 25 mhz 500 khz f out 70 db 100 khz f out 75 db 50 khz f out 80 db intermodulation distortion v ref = 3.5 v f 1 = 40 khz, f 2 = 50 khz 72 db clock = 10 mhz f 1 = 40 khz, f 2 = 50 khz 65 db clock = 25 mhz power requirements power supply range 2.5 5.5 v i dd 0.7 a t a = 25c, logic inputs = 0 v or v dd 0.5 10 a t a = ?40c to +125c, logic inputs = 0 v or v dd power supply sensitivity 0.001 %/% ?v dd = 5% 1 guaranteed by design and characterization, not subject to production test.
ad5405 rev. b | page 5 of 24 timing characteristics all input signals are specified with tr = tf = 1 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. v dd = 2.5 v to 5.5 v, v ref = 10 v, i out 2 = 0 v, temperature range for y version: ?40c to +125c. all specifications t min to t max , unless otherwise noted. table 2. parameter 1 limit at t min , t max unit conditions/comments write mode t 1 0 ns min r/ w -to- cs setup time t 2 0 ns min r/ w -to- cs hold time t 3 10 ns min cs low time t 4 10 ns min address setup time t 5 0 ns min address hold time t 6 6 ns min data setup time t 7 0 ns min data hold time t 8 5 ns min r/ w high to cs low t 9 7 ns min cs min high time t 14 10 ns typ cs rising-to- ldac falling time t 15 12 ns typ ldac pulse width t 16 10 ns typ cs rising-to- ldac rising time t 17 10 ns typ ldac falling-to- cs rising time data readback mode t 10 0 ns typ address setup time t 11 0 ns typ address hold time t 12 5 ns typ data access time 35 ns max t 13 5 ns typ bus relinquish time 10 ns max update rate 21.3 msps consists of cs min high time, cs low time, and output voltage settling time 1 guaranteed by design and characterization, not subject to production test. 04463-002 t 7 data valid t 6 t 2 cs r/w data t 1 t 2 t 13 t 12 t 3 t 8 t 9 daca/dacb t 4 t 5 t 11 t 10 ldac 2 ldac 1 1 asynchronous ldac update mode. 2 s ynchronous ldac update mode. t 16 t 14 t 15 t 17 data valid figure 2. timing diagram i ol 200 04463-003 figure 3. load circuit for data timing specifications
ad5405 rev. b | page 6 of 24 absolute maximum ratings transient currents of up to 100 ma do not cause scr latch-up. t a = 25c, unless otherwise noted. table 3. parameter rating v dd to gnd ?0.3 v to +7 v v ref a, v ref b, r fb a, r fb b to gnd ?12 v to +12 v i out 1, i out 2 to gnd ?0.3 v to +7 v logic inputs and output 1 ?0.3 v to v dd + 0.3 v operating temperature range automotive (y version) ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c 40-lead lfcsp, ja thermal impedance 30c/w lead temperature, soldering (10 sec) 300c ir reflow, peak temperature (<20 sec) 235c 1 overvoltages at dbx, ldac , cs , and r/ w are clamped by internal diodes. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensiti ve device. electrostatic charges as hi gh as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad5405 rev. b | page 7 of 24 pin configuration and fu nction descriptions pin 1 indicator ad5405 top view (not to scale) 1 r1a 2 r2a 3 r2_3a 4 r3a 5 v ref a 6 dgnd 7 ldac 8 dac a/b 9 nc 10 db11 notes 1. nc = no connect. 2. exposed pad must be connected to ground. db10 11 db9 12 db8 13 db7 14 db6 15 db5 16 db4 17 db3 18 db2 19 db1 20 30 r1b 29 r2b 28 r2_3b 27 r3b 26 v ref b 25 v dd 24 clr 23 r/w 22 cs 21 db0 40 r fb a 39 i out 2 a 38 i out 1a 37 nc 36 nc 35 nc 34 nc 33 i out 1 b 32 i out 2 b 31 r fb b 04463-004 figure 4. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 to 4 r1a, r2b, r2_3b, r3a dac a 4-quadrant resistors. allow a number of conf iguration modes, including bipolar operation with minimum of external components. 5, 26 v ref a, v ref b dac reference voltage input terminals. 6 dgnd digital ground pin. 7 ldac load dac input. allows asynch ronous or synchronous updates to the dac output. the dac is asynchronously updated when this sign al goes low. alternativel y, if this line is held permanently low, an automatic or synchronous update mode is selected whereby the dac is updated on the rising edge of cs . 8 dac a /b selects dac a or b. low selects dac a, and high selects dac b. 9, 34 to 37 nc not internally connected. 10 to 21 db11 to db0 parallel data bits 11 through 0. 22 cs chip select input. active low. used in conjunction with r/ w to load parallel data to the input latch or to read data from the dac register. edge sensitive; when pulled high, the dac data is latched. 23 r/ w read/write. when low, used in conjunction with cs to load parallel data. when high, used in conjunction with cs to read back contents of dac register. 24 clr active low control input. clears dac output and input and dac registers. 25 v dd positive power supply input. these parts can be operated from a supply of 2.5 v to 5.5 v. 27 to 30 r3b, r2_3b, r2b, r1b dac b 4-quadrant resistors. allow a number of conf iguration modes, including bipolar operation with a minimum of external components. 31, 40 r fb b, r fb a external amplifier output. 32 i out 2b dac a analog ground. this pin typically should be tied to the analog ground of the system, but can be biased to achieve single-supply operation. 33 i out 1b dac b current outputs. 38 i out 1a dac a current outputs. 39 i out 2a dac a analog ground. this pin typically should be tied to the analog ground of the system, but can be biased to achieve single-supply operation. epad exposed pad must be connected to ground.
ad5405 rev. b | page 8 of 24 typical performance characteristics ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 inl (lsb) 2000 1500 500 1000 0 2500 3000 3500 4000 code 04463-030 t a = 25c v ref = 10v v dd = 5v ?0.70 ?0.65 ?0.60 ?0.55 ?0.50 ?0.45 ?0.40 dnl (lsb) 65 34 27 8 9 reference voltage 04463-033 1 0 min dnl t a = 25c v dd = 5v figure 5. inl vs. code (12-bit dac) figure 8. dnl vs. reference voltage ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 dnl (lsb) 2000 1500 500 1000 0 2500 3000 3500 4000 code 04463-031 t a = 25c v ref = 10v v dd = 5v ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 error (mv) ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) 04463-034 v dd = 5v v dd = 2.5v v ref = 10v figure 6. dnl vs. code (12-bit dac) figure 9. gain error vs. temperature ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 inl (lsb) 65 34 2 78910 reference voltage 04463-032 max inl min inl t a = 25c v dd = 5v input voltage (v) current (ma) 8 5 0 5.0 7 6 3 1 4 2 4.54.03.53.02.52.01.5 1.00.50 t a = 25 c v dd = 5v v dd = 3v v dd = 2.5v 04463-013 figure 7. inl vs. reference voltage figure 10. supply current vs. logic input voltage
ad5405 rev. b | page 9 of 24 0 0.2 0.4 0.6 0.8 1.0 i out 1 leakage (na) 1.2 1.4 1.6 4020 ?20 0 ?40 60 80 100 120 temperature (c) 04463-036 i out 1 v dd = 5v i out 1 v dd = 3v figure 11. i out 1 leakage current vs. temperature 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 current ( a) ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) 04463-037 v dd = 5v v dd = 2.5v all 0s all 1s all 0s all 1s figure 12. supply current vs. temperature 0 2 4 6 8 10 12 14 i dd (ma) 10k 1k 10 100 1 100k 1m 10m 100m frequency (hz) 04463-038 t a = 25c loading zs to fs v dd = 5v v dd = 3v v dd = 2.5v figure 13. supply current vs. update rate ?102 ?66 ?54 ?42 ?30 ?18 ?6 6 1 100 1k 10k 100k 1m 10m 100m frequency (hz) gain (db) t a = 25 c loading zs to fs 0 ?60 ?48 ?36 ?24 ?12 ?84 ?72 ?78 ?90 ?96 t a = 25 c v dd = 5v v ref = 3.5v c comp =1.8pf amp = ad8038 all on db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 all off 04463-014 10 figure 14. reference multiplying bandwidth vs. frequency and code ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 gain (db) 10k 1k 10 100 1 100k 1m 10m 100m frequency (hz) 04463-029 t a = 25c v dd = 5v v ref = 3.5v c comp = 1.8pf amp = ad8038 figure 15. reference multiplying bandwidthall 1s loaded ?9 ?6 ?3 0 3 10k 100k 1m 10m 100m frequency (hz) t a = 25c v dd = 5v gain (db) 04463-015 v ref = 2v, ad8038 c c 1.47pf v ref = 2v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1.47pf v ref = 3.51v, ad8038 c c 1.8pf figure 16. reference multiplying bandwidth vs. frequency and compensation capacitor
ad5405 rev. b | page 10 of 24 ?0.010 ?0.005 0.005 0.025 0.035 0.045 0.015 0 0.020 0.030 0.040 0.010 output voltage (v) 0 20 40 60 80 100 120 140 160 180 200 time (ns) 04463-039 t a = 25c v ref = 0v amp = ad8038 c comp = 1.8pf 0x7ff to 0x800 0x800 to 0x7ff v dd = 5v v dd = 3v v dd = 3v v dd = 5v figure 17. midscale transition, v ref = 0 v output voltage (v) 0 20 40 60 80 100 120 140 160 180 200 time (ns) 04463-040 ?1.77 ?1.76 ?1.75 ?1.74 ?1.73 ?1.72 ?1.71 ?1.70 ?1.69 ?1.68 0x7ff to 0x800 0x800 to 0x7ff v dd = 5v v dd = 3v v dd = 3v v dd = 5v t a = 25c v ref = 3.5v amp = ad8038 c comp = 1.8pf figure 18. midscale transition, v ref = 3.5 v ?120 ?100 ?80 ?60 0 20 1 100 1k 10k 100k 1m 10m frequency (hz) ?40 ?20 t a = 25 c v dd = 3v amp = ad8038 full scale zero scale psrr (db) 04463-026 10 figure 19. power supply rejection ratio vs. frequency ?90 ?85 ?80 ?75 ?70 ?65 ?60 thd + n (db) 100 1k 1 10 10k 100k 1m frequency (hz) 04463-041 t a = 25c v dd = 3v v ref = 3.5v p-p figure 20. thd and noise vs. frequency 0 20 40 60 80 100 sfdr (db) 0 20 40 60 80 100 120 140 160 180 200 f out (khz) 04463-027 t a = 25c v ref = 3.5v amp = ad8038 mclk = 1mhz mclk = 200khz mclk = 0.5mhz figure 21. wideband sfdr vs. f out frequency 0 10 20 30 40 50 60 70 80 90 sfdr (db) 0 100 200 300 400 500 600 700 800 900 1000 f out (khz) 04463-028 mclk = 5mhz mclk = 10mhz mclk = 25mhz t a = 25c v ref = 3.5v amp = ad8038 figure 22. wideband sfdr vs. f out frequency
ad5405 rev. b | page 11 of 24 04463-018 ?90 ?70 ?50 ?30 ?10 sfdr (db) 0 frequency (mhz) ?80 ?60 ?40 ?20 0 t a = 25 c v dd = 5v amp = ad8038 65k codes 2 4 6 8 10 12 figure 23. wideband sfdr, f out = 100 khz, clock = 25 mhz 04463-019 ?100 ?70 ?50 ?30 ?10 sfdr (db) 0 frequency (mhz) ?80 ?60 ?40 ?20 0 t a = 25 c v dd = 5v amp = ad8038 65k codes 0.5 1.5 3.0 3.5 4.0 1.0 2.0 2.5 4.5 5.0 ?90 figure 24. wideband sfdr, f out = 500 khz, clock = 10 mhz 04463-020 ?90 ?70 ?50 ?30 ?10 sfdr (db) 0 frequency (mhz) ?80 ?60 ?40 ?20 0 0.5 1.5 3.0 3.5 4.0 1.0 2.0 2.5 4.5 5.0 t a = 25 c v dd = 5v amp = ad8038 65k codes figure 25. wideband sfdr, f out = 50 khz, clock = 10 mhz 04463-021 frequency (khz) t a = 25 c v dd = 3v amp = ad8038 65k codes ?100 ?70 ?50 ?30 ?10 sfdr (db) 250 750 300 350 400 650 700 ?80 ?60 ?40 ?20 0 ?90 450 500 550 600 figure 26. narrow-band spectral response, f out = 500 khz, clock = 25 mhz 04463-022 ?120 ?60 ?20 sfdr (db) 50 150 frequency (khz) 60 70 80 130 140 ?80 ?40 0 20 ?100 90 100 110 120 t a = 25 c v dd = 3v amp = ad8038 65k codes figure 27. narrow-band sfdr, f out = 100 khz, clock = 25 mhz 04463-023 frequency (khz) ?100 ?70 ?50 ?30 ?10 (db) 70 120 75 80 85 115 ?80 ?60 ?40 ?20 0 ?90 90 100 105 110 t a = 25 c v dd = 3v amp = ad8038 65k codes 95 figure 28. narrow-band imd, f out = 90 khz, 100 khz, clock = 10 mhz
ad5405 rev. b | page 12 of 24 100 1k 10k 100k frequency (hz) t a = 25 c amp = ad8038 full scale loaded to dac zero scale loaded to dac 04463-025 0 50 100 150 200 250 300 output noise (nv/ hz) midscale loaded to dac 04463-024 ?100 ?40 ?20 (db) ?50 ?30 ?10 ?90 ?60 ?70 ?80 0 400 frequency (khz) 50 300 350 100 150 200 250 0 t a = 25 c v dd = 5v amp = ad8038 65k codes figure 29. wideband imd, f out = 90 khz, 100 khz, clock = 25 mhz figure 30. output noise spectral density
ad5405 rev. b | page 13 of 24 terminology relative accuracy (endpoint nonlinearity) a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero and full scale and is normally expressed in lsbs or as a percentage of the full-scale reading. differential nonlinearity the difference in the measured change and the ideal 1 lsb change between two adjacent codes. a specified differential nonlinearity of ?1 lsb maximum over the operating temper- ature range ensures monotonicity. gain error (full-scale error) a measure of the output error between an ideal dac and the actual device output. for this dac, ideal maximum output is v ref ? 1 lsb. the gain error of the dac is adjustable to zero with an external resistance. output leakage current the current that flows into the dac ladder switches when they are turned off. for the i out 1 terminal, it can be measured by loading all 0s to the dac and measuring the i out 1 current. minimum current flows into the i out 2 line when the dac is loaded with all 1s. output capacitance capacitance from i out 1 or i out 2 to agnd. output current settling time the amount of time for the output to settle to a specified level for a full-scale input change. for this device, it is specified with a 100 resistor to ground. digital-to-analog glitch impulse the amount of charge injected from the digital inputs to the analog output when the inputs change state. this is typically specified as the area of the glitch in either pa-sec or nv-sec, depending on whether the glitch is measured as a current or voltage signal. digital feedthrough when the device is not selected, high frequency logic activity on the devices digital inputs is capacitively coupled through the device and produces noise on the i out pins and, subsequently, on the following circuitry. this noise is digital feedthrough. multiplying feedthrough error the error due to capacitive feedthrough from the dac reference input to the dac i out 1 terminal when all 0s are loaded to the dac. digital crosstalk the glitch impulse transferred to the outputs of a dac in response to a full-scale code change (all 0s to all 1s, or vice versa) in the input register of another dac. it is expressed in nv-sec. analog crosstalk the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s, or vice versa) while keeping ldac high and then pulsing ldac low and monitoring the output of the dac whose digital code has not changed. the area of the glitch is expressed in nv-sec. channel-to-channel isolation the portion of input signal from a dacs reference input that appears at the output of the other dac. it is expressed in decibels. total harmonic distortion (thd) the dac is driven by an ac reference. the ratio of the rms sum of the harmonics of the dac output to the fundamental value is the thd. usually only the lower-order harmonics are included, such as the second to the fifth harmonics. 1 2 5 2 4 2 3 2 2 v vvvv log20 +++ = thd intermodulation distortion (imd) the dac is driven by two combined sine wave references of frequencies fa and fb. distortion products are produced at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3 ... intermodulation terms are those for which m or n is not equal to 0. the second-order terms include (fa + fb) and (fa ? fb), and the third-order terms are (2fa + fb), (2fa ? fb), (f + 2fa + 2fb), and (fa ? 2fb). imd is defined as ( ) l fundamenta theofamplitude rms products distortion diffandsumtheofsumrms imd log20 = compliance voltage range the maximum range of (output) terminal voltage for which the device provides the specified characteristics.
ad5405 rev. b | page 14 of 24 general description dac section the ad5405 is a 12-bit, dual-channel, current-output dac consisting of a standard inverting r-2r ladder configuration. figure 31 shows a simplified diagram for a single channel of the ad5405. the feedback resistor r fb a has a value of 2r. the value of r is typically 10 k (with a minimum of 8 k and a maximum of 13 k). if i out 1a and i out 2a are kept at the same potential, a constant current flows into each ladder leg, regardless of digital input code. therefore, the input resistance presented at v ref a is always constant. v ref a i out 2a dac data latches and drivers 2r s1 2r s2 2r s3 2r s12 2r r r r i out1a r fb a r 04463-005 figure 31. simplified ladder configuration access is provided to the v ref , r fb , i out 1, and i out 2 terminals of the dac, making the device extremely versatile and allowing it to be configured for several operating modes, such as unipolar output, bipolar output, or single-supply mode. circuit operation unipolar mode using a single op amp, this dac can easily be configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in figure 32 . r fb 2r r1 2r ad5405 12-bit dac a r r1a r fb a v dd v ref a v out = 0v to ?v in a1 i out 2a i out 1a agnd c1 gnd agnd r2a r2_3a r3a r2 2r r3 2r a gnd 04463-006 notes 1. similar configuration for dac b. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. figure 32. unipolar operation when an output amplifier is connected in unipolar mode, the output voltage is given by n ref out dvv 2 ?= where: d is the fractional representation, in the range of 0 to 4,095, of the digital word loaded to the dac. n is the resolution of the dac. with a fixed 10 v reference, the circuit shown in figure 32 gives a unipolar 0 v to ?10 v output voltage swing. when v in is an ac signal, the circuit performs 2-quadrant multiplication. table 5 shows the relationship between digital code and the expected output voltage for unipolar operation. table 5. unipolar code digital input analog output (v) 1111 1111 1111 ?v ref (4,095/4,096) 1000 0000 0000 ?v ref (2,048/4,096) = ?v ref /2 0000 0000 0001 ?v ref (1/4,096) 0000 0000 0000 ?v ref (0/4,096) = 0 bipolar operation in some applications, it may be necessary to generate full 4-quadrant multiplying operation or a bipolar output swing. this can be easily accomplished by using another external amplifier, as shown in figure 33 . r fb 2r r1 2r ad5405 12-bit dac a r r1a r fb a v dd v ref a r2a r2_3a r3a a1 i out 2a i out 1a agnd c1 r2 2r r3 2r agnd gnd agnd a1 v in v out =?v in to +v in 04463-007 notes 1. similar configuration for dac b. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. figure 33. bipolar operation (4-quadrant multiplication) when in bipolar mode, the output voltage is given by ref n ref out vdvv ?= ? )2( 1 where: d is the fractional representation, in the range of 0 to 4,095, of the digital word loaded to the dac. n is the number of bits. when v in is an ac signal, the circuit performs 4-quadrant multiplication.
ad5405 rev. b | page 15 of 24 table 6 shows the relationship between the digital code and the expected output voltage for bipolar operation. table 6. bipolar code digital input analog output (v) 1111 1111 1111 +v ref (4,095/4,096) 1000 0000 0000 0 0000 0000 0001 ?v ref (4,095/4,096) 0000 0000 0000 ?v ref (4,096/4,096) stability in the i-to-v configuration, the i out of the dac and the inverting node of the op amp must be connected as close as possible, and proper pcb layout techniques must be used. because every code change corresponds to a step function, gain peaking may occur if the op amp has limited gain bandwidth product (gbp) and there is excessive parasitic capacitance at the inverting node. this parasitic capacitance introduces a pole into the open-loop response, which can cause ringing or instability in the closed-loop applications circuit. an optional compensation capacitor, c1, can be added in parallel with r fb a for stability, as shown in figure 32 and figure 33 . too small a value of c1 can produce ringing at the output, whereas too large a value can adversely affect the settling time. c1 should be found empirically, but 1 pf to 2 pf is generally adequate for the compensation. single-supply applications voltage-switching mode of operation figure 34 shows the dac operating in the voltage-switching mode. the reference voltage, v in , is applied to the i out 1a pin, i out 2a is connected to agnd, and the output voltage is available at the v ref a terminal. in this configuration, a positive reference voltage results in a positive output voltage, making single-supply operation possible. the output from the dac is voltage at a constant impedance (the dac ladder resistance). therefore, an op amp is necessary to buffer the output voltage. the reference input no longer sees a constant input impedance, but one that varies with code. therefore, the voltage input should be driven from a low impedance source. v out v dd gnd v in i out 2a i out 1a r fb a v dd v ref a r 2 r 1 04463-009 notes 1. similar configuration for dac b. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. figure 34. single-supply voltage-switching mode note that v in is limited to low voltages because the switches in the dac ladder no longer have the same source-drain drive voltage. as a result, their on resistance differs and degrades the integral linearity of the dac. also, v in must not go negative by more than 0.3 v, or an internal diode turns on, causing the device to exceed the maximum ratings. in this type of application, the full range of multiplying capability of the dac is lost. positive output voltage the output voltage polarity is opposite to the v ref polarity for dc reference voltages. to achieve a positive voltage output, an applied negative reference to the input of the dac is preferred over the output inversion through an inverting amplifier because of the resistors tolerance errors. to generate a negative reference, the reference can be level-shifted by an op amp such that the v out and gnd pins of the reference become the virtual ground and ?2.5 v, respectively, as shown in figure 35 . v out = 0v to +2.5v v dd = +5v gnd i out 2a i out 1a r fb a v dd v ref a c 1 gnd v in v out adr03 + 5v ?5v 12-bit dac ?2.5v 04463-010 notes 1. similar configuration for dac b. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. figure 35. positive voltage output with minimum components adding gain in applications where the output voltage must be greater than v in , gain can be added with an additional external amplifier, or it can be achieved in a single stage. consider the effect of temper- ature coefficients of the thin film resistors of the dac. simply placing a resistor in series with the r fb resistor causes mismatches in the temperature coefficients, resulting in larger gain temper- ature coefficient errors. instead, the circuit of figure 36 shows the recommended method for increasing the gain of the circuit. r1, r2, and r3 should have similar temperature coefficients, but they need not match the temperature coefficients of the dac. this approach is recommended in circuits where gains of greater than 1 are required.
ad5405 rev. b | page 16 of 24 v out v dd gnd i out 2a i out 1a v ref a r fb a v dd c 1 12-bit dac r3 r2 r1 v in r1 = r2r3 r2 + r3 gain = r2 + r3 r2 04463-011 notes 1. similar configuration for dac b. y be required 2. c1 phase compensation (1pf to 2pf) ma if a1 is a high speed amplifier. figure 36. increasing gain of current output dac divider or programmable gain element current-steering dacs are very flexible and lend themselves to many applications. if this type of dac is connected as the feedback element of an op amp and r fb a is used as the input resistor, as shown in figure 37 , the output voltage is inversely proportional to the digital input fraction, d. for d = 1 ? 2 ?n , the output voltage is () n in in out vdvv ? ??=?= 2 1 v out v dd gnd v in i out 2a ref i ou v a t 1a r fb a v dd notes 1. additional pins omitted for clarity . 04463-012 figure 37. current-steering dac used as a divider or programmable gain element as d is reduced, the output voltage increases. for small values of the digital fraction d , it is important to ensure that the amplifier does not saturate and that the required accuracy is met. for example, an 8-bit dac driven with the binary code 0x10 (0001 0000)that is, 16 decimalin the circuit of figure 37 should c ause the output voltage to be 16 times v in . however, if th weight in the range of 15.5/256 to 16.5/256 so that the possible n error or source in divider ust be counterbalanced by an the op amp through the dac. l mperature coefficient specification. this parameter not only affects the full-scale error, but also can affect the linearity - stem required to hold its overall the primary requirement for the current-steering mode is an e een he this ge in to . kly. e dac has a linearity specification of 0.5 lsb, d can have a output voltage is in the range of 15.5 v in to 16.5 v in a of 3%, even though the dac itself has a maximum error of 0.2%. dac leakage current is also a potential err circuits. the leakage current m opposite current supplied from because only a fraction, d, of the current into the v ref termina is routed to the i out 1 terminal, the output voltage changes as follows: output error voltage due to dac leakage = ( leakage r)/d where r is the dac resistance at the v ref terminal. for a dac leakage current of 10 na, r = 10 k, and a gain (that is, 1/d) of 16, the error voltage is 1.6 mv. reference selection when selecting a reference for use with the ad54xx series of current output dacs, pay attention to the references output voltage te (inl and dnl) performance. the reference temperature coef- ficient should be consistent with the system accuracy specifica tions. for example, an 8-bit sy specification to within 1 lsb over the temperature range 0c to 50c dictates that the maximum system drift with temperature should be less than 78 ppm/c. a 12-bit system with the same temperature range to overall specification within 2 lsbs requires a maximum drift of 10 ppm/c. choosing a precision reference with low output temperature coefficient minimizes this error source. table 7 lists some references available from analog devices that are suitable for use with this range of current output dacs. amplifier selection amplifier with low input bias currents and low input offset voltage. because of the code-dependent output resistance of th dac, the input offset voltage of an op amp is multiplied by the variable gain of the circuit. a change in this noise gain betw two adjacent digital fractions produces a step change in t output voltage due to the amplifiers input offset voltage. output voltage change is superimposed on the desired chan output between the two codes and gives rise to a differential linearity error, which, if large enough, could cause the dac be nonmonotonic the input bias current of an op amp also generates an offset at the voltage output as a result of the bias current flowing in the feedback resistor, r fb . most op amps have input bias currents low enough to prevent significant errors in 12-bit applications. common-mode rejection of the op amp is important in voltage-switching circuits, because it produces a code- dependent error at the voltage output of the circuit. most op amps have adequate common-mode rejection for use at 12-bit resolution. provided that the dac switches are driven from true wideband, low impedance sources (v in and agnd), they settle quic
ad5405 rev. b | page 17 of 24 onsequently, the slew rate and settling time of a voltage- the output op onfiguration, c n n ppli on) of the dac. this is done by using low in t nce fer amplifiers and c oard design. most single-supply circuits include ground as part of the analog signal range, which in turn requires an amplifier that can handle rail-to-rail signals. analog devices offers a wide range of ppl rs t . su le adi precision references . put voltage (v) l tolerance (%) mp drift (ppm/c) (ma) tput noise (v p-p) c switching dac circuit is determined largely by amp. to obtain minimum settling time in this c minimize apacitance at the v ref ode (the voltage output ode single-su in this a cati pu capacita buf areful b y amplifie , as listed in table 8 and able 9 . table 7 itab part no out initia te i ss ou package adr01 10 0.05 3 1 20 soic-8 adr01 10 0.05 9 1 20 tsot-23, sc70 adr02 5 0.06 3 1 10 soic-8 adr02 5 0.06 9 1 10 , sc70 tsot-23 adr03 2.5 0.10 3 1 6 soic-8 adr03 2.5 0.10 9 1 6 tsot-23, sc70 a dr06 3 0.10 3 1 10 soic-8 adr06 3 0.10 9 1 10 tsot-23, sc70 adr431 2.5 0.04 3 3.5 soic-8 0.8 adr435 5 0 .04 3 0.8 8 soic-8 adr391 2 0.16 0.12 .5 9 5 tsot-23 adr395 5 0.10 9 0.12 8 tsot-23 table 8. sui i precision op ps art no. supply voltage (v) v os (max) (v) i b (max) (na) z to 10 hz noise (v p-p) supply current (a) package table ad am p 0.1 h op97 2 to 20 25 0.1 0.5 600 soic-8 op1177 2.5 to 15 60 2 5 op, soic-8 0.4 00 ms ad8551 2.7 to 5 5 0. 9 05 1 75 msop, soic-8 ad8603 1.8 to 6 0.001 2.3 50 50 tsot ad8628 2.7 to 6 0.1 0.5 850 5 tsot, soic-8 table 9. suitable adi high speed op amps art no. supply voltage (v) bw @ acl (m hz) slew rate (v/s) vos (max) (v) i b (max) (na) package p ad8065 5 to 24 145 180 1,500 6,000 soic-8, sot-23, msop ad8021 2.5 to 12 490 120 1,000 10,500 soic-8, msop ad8038 3 to 12 350 425 3,000 750 soic-8, sc70-5 ad9631 3 to 6 320 1,300 10,000 7,000 soic-8
ad5405 rev. b | page 18 of 24 parallel interface data is loaded into the ad5405 in a 12-bit parallel word format. control lines cs and r/ w allow data to be written to or read from the dac register. a write event takes place when cs and r/ w are brought low, data available on the data lines fills the shift register, and the rising edge of cs latches the data and transfers the latched data-word to the dac register. the dac latches are not transparent; therefore, a write sequence must consist of a falling and rising edge on cs to ensure that data is loaded into the dac register and that its analog equivalent is reflected on the dac output. a read event takes place when r/ w is held high and cs is brought low. data is loaded from the dac register, goes back into the input register, and is output onto the data line, where it can be read back to the controller for verification or diagnostic purposes. the input and dac registers of these devices are not transparent; therefore, a falling and rising edge of cs is required to load each data-word. microprocessor interfacing adsp-21xx-to-ad5405 interface figure 38 shows the ad5405 interfaced to the adsp-21xx series of dsps as a memory-mapped device. a single wait state may be necessary to interface the ad5405 to the adsp-21xx, depending on the clock speed of the dsp. the wait state can be programmed via the data memory wait state control register of the adsp-21xx (see the adsp-21xx familys user manual for details). 04463-049 r/w db0 to db11 ad5405 1 address decoder cs data 0 to data 23 address bus addr 0 to adrr 13 adsp-21xx 1 data bus dms wr 1 additional pins omitted for clarity. figure 38. adsp21xx-to-ad5405 interface 8xc51-to-ad5405 interface figure 39 shows the interface between the ad5405 and the 8xc51 family of dsps. to facilitate external data memory access, the address latch enable (ale) mode is enabled. the low byte of the address is latched with this output pulse during access to the external memory. ad0 to ad7 are the multiplexed low order addresses and data bus; they require strong internal pull-ups when emitting 1s. during access to external memory, a8 to a15 are the high order address bytes. because these ports are open drained, they also require strong internal pull-ups when emitting 1s. 04463-051 r/w db0 to db11 ad5405 1 address decoder cs ad0 to ad7 address bus a8 to a15 8051 1 data bus wr 1 additional pins omitted for clarity. 8-bit latch ale figure 39. 8xc51-to-ad5405 interface adsp-bf5xx-to-ad5405 interface figure 40 shows a typical interface between the ad5405 and the adsp-bf5xx family of dsps. the asynchronous memory write cycle of the processor drives the digital inputs of the dac. the ams x line is actually four memory select lines. internal addr lines are decoded into ams 3C0 ; these lines are then inserted as chip selects. the rest of the interface is a standard handshaking operation. 04463-050 r/w db0 to db11 ad5405 1 address decoder cs data 0 to data 23 address bus addr 1 to adrr 19 adsp-bf5xx 1 data bus amsx awe 1 additional pins omitted for clarity. figure 40. adsp-bf5xx-to-ad5405 interface
ad5405 rev. b | page 19 of 24 pcb layout and power supply decoupling in any circuit where accuracy is important, careful consider- ation of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5405 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the dac is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. these dacs should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close as possible to the package, ideally right up against the device. the 0.1 f capacitor should have low effective series resistance (esr) and low effective series inductance (esi), like the common ceramic types of capacitors that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. low esr 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. components, such as clocks, that produce fast-switching signals should be shielded with digital ground to avoid radiating noise to other parts of the board, and they should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough on the board. a microstrip technique is by far the best, but its use is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to the ground plane, and signal traces are placed on the soldered side. it is good practice to use compact, minimum lead length pcb layout design. leads to the input should be as short as possible to minimize ir drops and stray inductance. the pcb metal traces between v ref and r fb should also be matched to minimize gain error. to maximize high frequency performance, the i-to-v amplifier should be located as close as possible to the device. evaluation board for the dacs the evaluation board consists of a dac and a current-to- voltage amplifier, the ad8065. included on the evaluation board is a 10 v reference, the adr01. an external reference may also be applied via an smb input. the evaluation kit consists of a cd-rom with self-installing pc software to control the dac. the software simply allows the user to write a code to the device. power supplies for the evaluation board the board requires 12 v and +5 v supplies. the +12 v v dd and ?12 v v ss are used to power the output amplifier; the +5 v is used to power the dac (v dd1 ) and transceivers (v cc ). both supplies are decoupled to their respective ground plane with 10 f tantalum and 0.1 f ceramic capacitors.
ad5405 rev. b | page 20 of 24 04463-045 figure 41. schematic of ad5405 evaluation board 04463-046 figure 42. component-side artwork
ad5405 rev. b | page 21 of 24 04463-047 figure 43. silkscreencomponent-side view (top layer) 04463-048 figure 44. solder-side artwork
ad5405 rev. b | page 22 of 24 overview of ad54xx devices table 10. part no. resolution no. dacs inl (lsb) interface package 1 features ad5424 8 1 0.25 parallel ru-16, cp-20 10 mhz bw, 17 ns cs pulse width ad5426 8 1 0.25 serial rm-10 10 mhz bw, 50 mhz serial ad5428 8 2 0.25 parallel ru-20 10 mhz bw, 17 ns cs pulse width ad5429 8 2 0.25 serial ru-10 10 mhz bw, 50 mhz serial ad5450 8 1 0.25 serial uj-8 10 mhz bw, 50 mhz serial ad5432 10 1 0.5 serial rm-10 10 mhz bw, 50 mhz serial ad5433 10 1 0.5 parallel ru-20, cp-20 10 mhz bw, 17 ns cs pulse width ad5439 10 2 0.5 serial ru-16 10 mhz bw, 50 mhz serial ad5440 10 2 0.5 parallel ru-24 10 mhz bw, 17 ns cs pulse width ad5451 10 1 0.25 serial uj-8 10 mhz bw, 50 mhz serial ad5443 12 1 1 serial rm-10 10 mhz bw, 50 mhz serial ad5444 12 1 0.5 serial rm-8 10 mhz bw, 50 mhz serial ad5415 12 2 1 serial ru-24 10 mhz bw, 50 mhz serial ad5405 12 2 1 parallel cp-40-1 10 mhz bw, 17 ns cs pulse width ad5445 12 2 1 parallel ru-20, cp-20 10 mhz bw, 17 ns cs pulse width ad5447 12 2 1 parallel ru-24 10 mhz bw, 17 ns cs pulse width ad5449 12 2 1 serial ru-16 10 mhz bw, 50 mhz serial ad5452 12 1 0.5 serial uj-8, rm-8 10 mhz bw, 50 mhz serial ad5446 14 1 1 serial rm-8 10 mhz bw, 50 mhz serial ad5453 14 1 2 serial uj-8, rm-8 10 mhz bw, 50 mhz serial ad5553 14 1 1 serial rm-8 4 mhz bw, 50 mhz serial clock ad5556 14 1 1 parallel ru-28 4 mhz bw, 20 ns wr pulse width ad5555 14 2 1 serial rm-8 4 mhz bw, 50 mhz serial clock ad5557 14 2 1 parallel ru-38 4 mhz bw, 20 ns wr pulse width ad5543 16 1 2 serial rm-8 4 mhz bw, 50 mhz serial clock ad5546 16 1 2 parallel ru-28 4 mhz bw, 20 ns wr pulse width ad5545 16 2 2 serial ru-16 4 mhz bw, 50 mhz serial clock ad5547 16 2 2 parallel ru-38 4 mhz bw, 20 ns wr pulse width 1 ru = tssop, cp = lfcsp, rm = msop, uj = tsot.
ad5405 rev. b | page 23 of 24 outline dimensions 1 40 10 11 31 30 21 20 4.25 4.10 sq 3.95 top view 6.00 bsc sq pin 1 indicator 5.75 bsc sq 12 max 0.30 0.23 0.18 0.20 ref seating plane 1.00 0.85 0.80 0.05 max 0.02 nom coplanarity 0.08 0.80 max 0.65 typ 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bot tom view) compliant to jedec standards mo-220-vjjd-2 072108-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 45. 40-lead lead frame chip scale package [lfcsp_vq] 6 mm 6 mm body, very thin quad (cp-40-1) dimensions shown in millimeters ordering guide model 1 resolution inl (lsb) temperature rang e package description package option ad5405ycp 12 1 ?40c to +125c 40-lead lfcsp_vq cp-40-1 ad5405ycpCreel 12 1 ?40c to + 125c 40-lead lfcsp_vq cp-40-1 ad5405ycpCreel7 12 1 ?40c to + 125c 40-lead lfcsp_vq cp-40-1 AD5405YCPZ 12 1 ?40c to +125c 40-lead lfcsp_vq cp-40-1 AD5405YCPZCreel 12 1 ?40c to + 125c 40-lead lfcsp_vq cp-40-1 AD5405YCPZCreel7 12 1 ?40c to +125c 40-lead lfcsp_vq cp-40-1 eval-ad5405eb evaluation kit 1 z = rohs compliant part.
ad5405 rev. b | page 24 of 24 notes ? 2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04463C0C12/09(b)

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