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50 mhz direct digital synthesizer, waveform generator data sheet ad9835 features 5 v power supply 50 mhz speed on-chip cos lookup table on-chip, 10-bit dac serial loading power-down option temperature range: ?40c to +85c 200 mw power consumption 16-lead tssop applications frequency stimulus/waveform generation frequency phase tuning and modulation low power rf/communications systems liquid and gas flow measurement sensory applications: proximity, motion, and defect detection test and medical equipment general description the ad9835 is a numerically-controlled oscillator employing a phase accumulator, a cos lookup table, and a 10-bit digital- to-analog converter integrated on a single cmos chip. modu- lation capabilities are provided for phase modulation and frequency modulation. clock rates of up to 50 mhz are supported. frequency accuracy can be controlled to one part in 4 billion. modulation is effected by loading registers through the serial interface. a power-down bit allows the user to power down the ad9835 when it is not in use; the power consumption reduces to 1.75 mw. this part is available in a 16-lead tssop package. similar dds products can be found at http://www.analog.com/dds . functional block diagram iout comp refin fs adjust refout a gnd a vdd dgnd dvdd mclk psel0 psel1 12 ad9835 on-board reference 10-bit dac phase0 reg phase1 reg phase2 reg phase3 reg full-scale control cos rom phase accumulator (32 bit) freq0 reg freq1 reg 16-bit data register sync fselect fselect bit selsrc sync 8 lsbs 8 msbs decode logic fsync sclk sdata serial register control register fselect/psel register defer register sync sync selsrc psel0 bit psel1 bit mux mux mux mux mux 09630-001 figure 1. rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?1998C2011 analog devices, inc. all rights reserved.
ad9835 data sheet rev. a | page 2 of 28 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? timing characteristics ................................................................ 5 ? absolute maximum ratings............................................................ 6 ? esd caution.................................................................................. 6 ? pin configuration and function descriptions............................. 7 ? typical performance characteristics ............................................. 9 ? terminology .................................................................................... 12 ? theory of operation ..................................................................... 13 ? circuit description......................................................................... 14 ? numerical controlled oscillator and phase modulator ....... 14 ? cos lookup table (lut) ........................................................ 14 ? digital-to-analog converter .................................................... 14 ? functional description .................................................................. 15 ? serial interface ............................................................................ 15 ? direct data transfer and deferred data transfer ................. 16 ? latency......................................................................................... 17 ? flowcharts ................................................................................... 17 ? applications information .............................................................. 20 ? grounding and layout .............................................................. 20 ? interfacing the ad9835 to microprocessors .......................... 20 ? ad9835-to-adsp-21xx interface ............................................ 20 ? ad9835-to-68hc11/68l11 interface...................................... 21 ? ad9835-to-80c51/80l51 interface......................................... 21 ? ad9835-to-dsp56002 interface .............................................. 21 ? evaluation board ............................................................................ 22 ? system demonstration platform.............................................. 22 ? ad9835 to sport interface..................................................... 22 ? xo vs. external clock................................................................ 22 ? power supply............................................................................... 22 ? evaluation board schematics and layout............................... 23 ? ordering information.................................................................... 26 ? bill of materials........................................................................... 26 ? outline dimensions ....................................................................... 27 ? ordering guide .......................................................................... 27 ? revision history 9/11rev. 0 to rev. a updated format..................................................................universal changes to features and applications........................................... 1 changes to specification statement ............................................... 3 changes to figure 2.......................................................................... 4 changes to timing characteristics statement ............................. 5 replaced evaluation board section; renumbered sequentially ..................................................................................... 22 changes to bill of materials .......................................................... 27 changes to ordering guide .......................................................... 28 7/98revision 0: initial version
data sheet ad9835 rev. a | page 3 of 28 specifications v dd = +5 v 5%; agnd = dgnd = 0 v; t a = t min to t max ; refin = refout; r set = 3.9 k; r load = 300 for iout, unless otherwise noted. also, see figure 2 . table 1. parameter 1 min typ max units test conditions/comments signal dac specifications resolution 10 bits update rate (f max ) 50 msps iout full scale 4 ma 4.75 ma output compliance 1.35 v dc accuracy integral nonlinearity 1 lsb differential nonlinearity 0.5 lsb dds specifications 2 dynamic specifications signal-to-noise ratio 50 db f mclk = 50 mhz, f out = 1 mhz total harmonic distortion ?52 dbc f mclk = 50 mhz, f out = 1 mhz spurious free dynamic range (sfdr) 3 f mclk = 6.25 mhz, f out = 2.11 mhz narrow band (50 khz) ?72 dbc wide band (2 mhz) ?50 dbc clock feedthrough ?60 dbc wake-up time 1 ms power-down option yes voltage reference internal reference @ +25 c 1.21 v t min to t max 1.131 1.29 v refin input impedance 10 m reference tc 100 ppm/c refout output impedance 300 logic inputs v inh , input high voltage dvdd ? 0.9 v v inl , input low voltage 0.9 v i inh , input current 10 a c in , input capacitance 10 pf power supplies f mclk = 50 mhz avdd 4.75 5.25 v min/v max dvdd 4.75 5.25 v min/v max i aa 5 ma max i dd 2.5 + 0.33/mhz ma typ i aa + i dd 4 40 ma max low power sleep mode 0.35 ma max 1 operating temperature range is as follows: b version: ?40c to +85c. 2 100% production tested. 3 f mclk = 6.25 mhz, frequency word = 5671c71c hex, f out = 2.11 mhz. 4 measured with the digital inputs static and equal to 0 v or dv dd. the ad9835 is tested with a ca pacitive load of 50 pf. the pa rt can be operated with higher capacitive loads, but the magnitude of the analog ou tput will be attenuated. see figure 7.
ad9835 data sheet rev. a | page 4 of 28 iout comp refin fs adjust refout 12 ad9835 on-board reference 10-bit dac sin rom full-scale control 300? 50pf r set 3.9k ? 10nf 10nf avdd 0 9630-002 figure 2. test circuit
data sheet ad9835 rev. a | page 5 of 28 timing characteristics v dd = +5 v 5%; agnd = dgnd = 0 v, unless otherwise noted. table 2. parameter limit at t min to t max (b version) units test conditions/comments t 1 20 ns min mclk period t 2 8 ns min mclk high duration t 3 8 ns min mclk low duration t 4 50 ns min sclk period t 5 20 ns min sclk high duration t 6 20 ns min sclk low duration t 7 15 ns min fsync to sclk falling edge setup time t 8 20 ns min fsync to sclk hold time sclk ? 5 ns max t 9 15 ns min data setup time t 10 5 ns min data hold time t 11 8 ns min fselect, psel0, psel1 se tup time before mclk rising edge t 11a 1 8 ns min fselect, psel0, psel1 setup time after mclk rising edge 1 see the section. pin configuration and function descriptions timing diagrams mclk t 2 t 1 t 3 09630-003 figure 3. master clock sclk fsync sdata t 5 t 4 t 6 t 7 t 8 t 10 t 9 d14 d15 d0 d1 d2 d15 d14 09630-004 figure 4. serial timing t 11a t 11 valid data valid data valid data mclk fselect psel0, psel1 09630-005 figure 5. control timing
ad9835 data sheet rev. a | page 6 of 28 absolute maximum ratings t a = +25c, unless otherwise noted. table 3. parameter rating avdd to agnd ?0.3 v to +7 v dvdd to dgnd ?0.3 v to +7 v avdd to dvdd ?0.3 v to +0.3 v agnd to dgnd ?0.3 v to +0.3 v digital i/o voltage to dgnd ?0.3 v to dvdd + 0.3 v analog i/o voltage to agnd ?0.3 v to avdd + 0.3 v operating temperature range industrial (b version) ?40c to +85c storage temperature range ?65c to +150c maximum junction temperature +150c tssop ja thermal impedance 158c/w lead temperature, soldering vapor phase (60 sec) +215c infrared (15 sec) +220c esd rating > 4500 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet ad9835 rev. a | page 7 of 28 pin configuration and fu nction descriptions fs adjust agnd iout avdd comp refin refout dvdd fselect psel1 psel0 dgnd mclk sclk sdata fsync 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ad9835 top view (not to scale) 09630-006 figure 6. pin configuration table 4. pin function descriptions pin no. mnemonic description analog signal and reference 1 fs adjust full-scale adjust control. a resistor (rset) is conne cted between this pin and agnd. this determines the magnitude of the full-scale dac current. the relationship between rset and the full-scale current is iout full-scale = 12.5 v refin /r set , where v refin = 1.21 v nominal, r set = 3.9 k typical. 2 refin voltage reference input. the ad9835 can be used with either the on-board reference, which is available from pin refout, or an external reference. the reference to be used is connected to the refin pin. the ad9835 accepts a reference of 1.21 v nominal. 3 refout voltage reference output. the ad9835 has an on-board reference of value 1.21 v nominal. the reference is made available on the refout pin. this reference is used as the reference to the dac by connecting refout to refin. refout should be decoupled with a 10 nf capacitor to agnd. 14 iout current output. this is a high impeda nce current source. a load resistor should be connected between iout and agnd. 16 comp compensation pin. this is a compensation pin for the in ternal reference amplifier. a 10 nf decoupling ceramic capacitor should be connected between comp and avdd. power supply 4 dvdd positive power supply for the digital section. a 0.1 f decoupling capacitor should be connected between dvdd and dgnd. dvdd can have a value of +5 v 5%. 5 dgnd digital ground. 13 agnd analog ground. 15 avdd positive power supply for the analog section. a 0.1 f decoupling capacitor should be connected between avdd and agnd. avdd can have a value of +5 v 5%. digital interface and control 6 mclk digital clock input. dds output frequencies are expressed as a binary fraction of the frequency of mclk. the output frequency accuracy and phase no ise are determined by this clock. 7 sclk serial clock, logic input. data is cl ocked into the ad9835 on each falling sclk edge. 8 sdata serial data in, logic input. the 16-bit serial data word is applied to this input. 9 fsync data synchronization signal, logic input. when this input is taken low, the internal lo gic is informed that a new word is being loaded into the device. 10 fselect frequency select input. fselect controls which frequenc y register, freq0 or freq1, is used in the phase accumulator. the frequency register can be selected using the pin fselect or the bit fselect. fselect is sampled on the rising mclk edge. fslect needs to be in steady state when an mclk rising edge occurs. if fselect changes value when a rising edge occurs, there is an uncertainty of one mclk cycle as to when control is transferred to the other frequency register. to avoid an y uncertainty, a change on fselect should not coincide with an mclk rising edge. when the bit is being used to select the frequency register, the pin fselect should be tied to dgnd.
ad9835 data sheet rev. a | page 8 of 28 pin no. mnemonic description 11, 12 psel0, psel1 phase select input. the ad9835 has four phase registers. these registers can be used to alter the value being input to the cos rom. the contents of the phase register ar e added to the phase accumulator output, the psel0 and psel1 inputs selecting the phase register to be used. altern atively, the phase register to be used can be selected using the psel0 and psel1 bits. like the fselect input, psel0 and psel1 are sampled on the rising mclk edge. therefore, these inputs need to be in steady state when an mclk rising edge occurs or there is an uncertainty of one mclk cycle as to when control is transferred to th e selected phase register. when the phase registers are being controlled by the psel0 and psel1 bits, the pins should be tied to dgnd.
data sheet ad9835 rev. a | page 9 of 28 typical performance characteristics output frequency (mhz) 0 ?12 16 02 sign a l a ttenu a tion (db) 4 6 8 10 12 14 ?2 ?4 ?6 ?8 ?10 c l = 82pf c l = 100pf c l = 150pf avdd = dvdd = +5v 09630-007 figure 7. signal attenuation vs. outp ut frequency for various capacitive loads (r l = 300 ) mclk frequency (mhz) 30 25 20 15 10 0 50 10 20 total current (ma) 40 30 5 t a = +25c avdd = dvdd = +5v 09630-008 figure 8. typical current co nsumption vs. mclk frequency mclk frequency (mhz) ? 64 ?66 ?68 ?70 ?72 ?76 ?74 50 10 20 sfdr [50khz] (db) 30 40 f out / f mclk = 1/3 avdd = dvdd = +5v 09630-009 figure 9. narrow-band sfdr vs. mclk frequency mclk frequency (mhz) 0 ?10 ?20 ?30 ?40 ?60 ?50 50 10 20 sfdr [2mhz] (db) 30 40 f out / f mclk = 1/3 avdd = dvdd = +5v 09630-010 figure 10. wideband sfdr vs. mclk frequency ? 20 ?30 ?40 ?50 ?60 ?80 ?70 0.463 0.124 0.044 0.204 0.284 sfdr [2mhz] (db) 0.084 0.244 0.324 avdd = dvdd = +5v 50mhz 30mhz 10mhz 0.164 f out /f mclk 09630-011 figure 11. wideband sfdr vs. f out /f mclk for various mclk frequencies mclk frequency (mhz) 56 55 54 53 52 50 50 10 20 snr (db) 30 40 51 f out /f mclk = 1/3 avdd = dvdd = +5v 09630-012 figure 12. snr vs. mclk frequency
ad9835 data sheet rev. a | page 10 of 28 70 60 50 40 30 10 20 0.124 0.204 snr (db) 0.084 0.164 0.244 0.284 0.324 avdd = dvdd = +5v 50mhz 30mhz 10mhz f out /f mclk 0.364 0.044 09630-013 figure 13. snr vs. f out /f mclk for various mclk frequencies rbw 1khz vbw 3khz st 50 sec 10db/div 0hz start 25mhz stop 09630-014 figure 14. f mclk = 50 mhz, f out = 2.1 mhz. frequency word = aco8312 rbw 1khz vbw 3khz st 50 sec 0hz start 25mhz stop 10db/div 09630-015 figure 15. f mclk = 50 mhz, f out = 3.1 mhz. frequency word = fdf3b64 rbw 1khz vbw 3khz st 50 sec 0hz start 25mhz stop 10db/div 09630-016 figure 16. f mclk = 50 mhz, f out = 7.1 mhz. frequency word = 245aicac rbw 1khz vbw 3khz st 50 sec 10db/di v 0hz start 25mhz stop 09630-017 figure 17. f mclk = 50 mhz, f out = 9.1 mhz. frequency word = 2e978d50 10db/div rbw 1khz vbw 3khz st 50 sec 0hz start 25mhz stop 09630-018 figure 18. f mclk = 50 mhz, f out = 11.1 mhz. frequency word = 38d4fdf4
data sheet ad9835 rev. a | page 11 of 28 10db/di v rbw 1khz vbw 3khz st 50 sec 0hz start 25mhz stop 09630-019 figure 19. f mclk = 50 mhz, f out = 13.1 mhz. frequency word = 43126e98 rbw 1khz vbw 3khz st 50 sec 10db/di v 0hz start 25mhz stop 09630-020 figure 20. f mclk = 50 mhz, f out = 16.5 mhz. frequency word = 547ae148
ad9835 data sheet rev. a | page 12 of 28 terminology integral nonlinearity this is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. the endpoints of the transfer function are zero scale, a point 0.5 lsb below the first code transition (000 . . . 00 to 000 . . . 01) and full scale, a point 0.5 lsb above the last code transition (111 . . . 10 to 111 . . . 11). the error is expressed in lsbs. differential nonlinearity this is the difference between the measured and ideal 1 lsb change between two adjacent codes in the dac. signal to (noise + distortion) signal to (noise + distortion) is measured signal to noise at the output of the dac. the signal is the rms magnitude of the fundamental. noise is the rms sum of all the non-fundamental signals up to half the sampling frequency (f mclk /2) but excluding the dc component. signal to (noise + distortion) is dependent on the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for a sine wave input is given by signal to (noise + distor tion) = (6.02n + 1.76) db where n is the number of bits. thus, for an ideal 10-bit converter, signal to (noise + distortion) = 61.96 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the rms value of the fundamental. for the ad9835, thd is defined as ( ) 1 2 6 2 5 2 4 2 3 2 2 log20 v vvvvv thd ++++ = where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonic. output compliance the output compliance refers to the maximum voltage that can be generated at the output of the dac to meet the specifica- tions. when voltages greater than that specified for the output compliance are generated, the ad9835 may not meet the specifications listed in the data sheet. spurious free dynamic range along with the frequency of interest, harmonics of the funda- mental frequency and images of the mclk frequency are present at the output of a dds device. the spurious free dynamic range (sfdr) refers to the largest spur or harmonic present in the band of interest. the wideband sfdr gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the bandwidth 2 mhz about the fundamental frequency. the narrow band sfdr gives the attenuation of the largest spur or harmonic in a bandwidth of 50 khz about the fundamental frequency. clock feedthrough there will be feedthrough from the mclk input to the analog output. clock feedthrough refers to the magnitude of the mclk signal relative to the fundamental frequency in the ad9835s output spectrum.
data sheet ad9835 rev. a | page 13 of 28 theory of operation sine waves are typically thought of in terms of their magnitude form a(t) = sin (t). however, these are nonlinear and not easy to generate except through piecewise construction. on the other hand, the angular information is linear in nature. that is, the phase angle rotates through a fixed angle for each unit of time. the angular rate depends on the frequency of the signal by the traditional rate of = 2 f. magnitude phase +1 0 ?1 2 0 09630-023 figure 21. sine wave knowing that the phase of a sine wave is linear and given a reference interval (clock period), the phase rotation for that period can be determined by phase = ?t solving for , = phase/ t = 2 f solving for f and substituting the reference clock frequency for the reference period (1/ f mclk = t), f = phase f mclk /2 the ad9835 builds the output based on this simple equation. a simple dds chip can implement this equation with three major subcircuits.
ad9835 data sheet rev. a | page 14 of 28 circuit description the ad9835 provides an exciting level of integration for the rf communications system designer. the ad9835 combines the numerical controlled oscillator (nco), cos lookup table, frequency and phase modulators, and a digital-to- analog converter on a single integrated circuit. the internal circuitry of the ad9835 consists of three main sections. these are ? numerical controlled oscillator (nco) and phase modulator ? cos lookup table ? digital-to-analog converter the ad9835 is a fully integrated direct digital synthesis (dds) chip. the chip requires one reference clock, one low precision resistor, and eight decoupling capacitors to provide digitally- created sine waves up to 25 mhz. in addition to the generation of this rf signal, the chip is fully capable of a broad range of simple and complex modulation schemes. these modulation schemes are fully implemented in the digital domain allowing accurate and simple realization of complex modulation algorithms using dsp techniques. numerical controlled oscillator and phase modulator this consists of two frequency select registers, a phase accumulator and four phase offset registers. the main component of the nco is a 32-bit phase accumulator, which assembles the phase component of the output signal. continuous time signals have a phase range of 0 to 2 . outside this range of numbers, the sinusoid functions repeat themselves in a periodic manner. the digital implementation is no different. the accumulator simply scales the range of phase numbers into a multibit digital word. the phase accumulator in the ad9835 is implemented with 32 bits. therefore, in the ad9835, 2 = 2 32 . likewise, the phase term is scaled into this range of numbers 0 < phase < 2 32 ? 1. making these substitutions into the equation above f = phase f mclk /2 32 where 0 < phase < 2 32 the input to the phase accumulator (that is, the phase step) can be selected either from the freq0 register or freq1 register and this is controlled by the fselect pin or the fselect bit. ncos inherently generate continuous phase signals, thus avoiding any output discontinuity when switching between frequencies. following the nco, a phase offset can be added to perform phase modulation using the 12-bit phase registers. the contents of this register are added to the most significant bits of the nco. the ad9835 has four phase registers, the resolution of these registers being 2 /4096. cos lookup table (lut) to make the output useful, the signal must be converted from phase information into a sinusoidal value. since phase information maps directly into amplitude, a rom lut converts the phase information into amplitude. to do this, the digital phase infor- mation is used to address a cos rom lut. although the nco contains a 32-bit phase accumulator, the output of the nco is truncated to 12 bits. using the full resolution of the phase accu- mulator is impractical and unnecessary as this would require a lookup table of 2 32 entries. it is necessary only to have sufficient phase resolution in the luts such that the dc error of the output waveform is dominated by the quantization error in the dac. this requires the lookup table to have two more bits of phase resolution than the 10-bit dac. digital-to-analog converter the ad9835 includes a high impedance current source 10-bit dac, capable of driving a wide range of loads at different speeds. full-scale output current can be adjusted, for optimum power and external load requirements, through the use of a single external resistor (r set ). the dac is configured for single-ended operation. the load resistor can be any value required, as long as the full-scale voltage developed across it does not exceed the voltage compliance range. since full-scale current is controlled by r set , adjustments to r set can balance changes made to the load resistor. however, if the dac full-scale output current is significantly less than 4 ma, the dacs linearity may degrade.
data sheet ad9835 rev. a | page 15 of 28 functional description serial interface the ad9835 has a serial interface, with 16 bits loaded during each write cycle. sclk, sdata, and fsync are used to load the word into the ad9835. when fsync is taken low, the ad9835 is informed that a word is being written to the device. the first bit is read into the device on the next sclk falling edge with the remaining bits being read into the device on the subsequent sclk falling edges. fsync frames the 16 bits; therefore, when 16 sclk falling edges have occurred, fsync should be taken high again. the sclk can be continuous, or alternatively, the sclk can idle high or low between write operations. when writing to a frequency/phase register, the first four bits identify whether a frequency or phase register is being written to, the next four bits contain the address of the destination register, while the 8 lsbs contain the data. table 5 shows the data structure for a 16-bit write to the ad9835. for examples on programming the ad9835 , see the an-621 and an-1108 application notes at www.analog.com . table 5. writing to the ad9835 data registers d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 c2 c1 c0 a3 a2 a1 a0 msb x 1 x 1 x 1 x 1 x 1 x 1 lsb 1 x = dont care. table 6. commands c3 c2 c1 c0 command 0 0 0 0 write 16 phase bits (present 8 bits + 8 bits in the defer register) to selected phasex reg. 0 0 0 1 write 8 phase bits to the defer register. 0 0 1 0 write 16 frequency bits (present 8 bits + 8 bits in the defer register) to selected the freqx reg. 0 0 1 1 write 8 frequency bits to the defer register. 0 1 0 0 bit d9 (psel0) and bit d10 (psel1) are used to select the phasex reg when selsrc = 1. when selsrc = 0, the phasex reg is selected using the psel0 and psel1 pins. 0 1 0 1 bit d11 is used to select the freqx reg when selsrc = 1. when selsrc = 0, the freqx reg is selected using the fselect pin. 0 1 1 0 to control the psel0, psel1, and fselect bits using only one write, this command is used. bit d9 and bit d10 are used to select the phasex reg, and bit 11 is used to select the freqx reg when selsrc = 1. when selsrc = 0, the phasex reg is selected using the psel0 and psel1 pins and the freqx reg is selected using the fselect pin. 0 1 1 1 reserved. it configures the ad9835 for test purposes. table 7. addressing the registers a3 a2 a1 a0 destination register 0 0 0 0 freq0 reg 8 l lsbs 0 0 0 1 freq0 reg 8 h lsbs 0 0 1 0 freq0 reg 8 l msbs 0 0 1 1 freq0 reg 8 h msbs 0 1 0 0 freq1 reg 8 l lsbs 0 1 0 1 freq1 reg 8 h lsbs 0 1 1 0 freq1 reg 8 l msbs 0 1 1 1 freq1 reg 8 h msbs 1 0 0 0 phase0 reg 8 lsbs 1 0 0 1 phase0 reg 8 msbs 1 0 1 0 phase1 reg 8 lsbs 1 0 1 1 phase1 reg 8 msbs 1 1 0 0 phase2 reg 8 lsbs 1 1 0 1 phase2 reg 8 msbs 1 1 1 0 phase3 reg 8 lsbs 1 1 1 1 phase3 reg 8 msbs
ad9835 data sheet rev. a | page 16 of 28 table 8. control registers register size description freq0 reg 32 bits frequency register 0. this defines the output frequency, when fselect = 0, as a fraction of the mclk frequency. freq1 reg 32 bits frequency register 1. this defines the output frequency, when fselect = 1, as a fraction of the mclk frequency. phase0 reg 12 bits phase offset register 0. when psel0 = psel1 = 0, the contents of this register are added to the output of the phase accumulator. phase1 reg 12 bits phase offset register 1. when psel0 = 1 and psel1 = 0, the contents of this register are added to the output of the phase accumulator. phase2 reg 12 bits phase offset register 2. when psel0 = 0 and psel1 = 1, the contents of this register are added to the output of the phase accumulator. phase3 reg 12 bits phase offset register 3. when psel0 = psel1 = 1, the contents of this register are added to the output of the phase accumulator. table 9. 32-bit frequency word 16 msbs 16 lsbs 8 h msbs 8 l msbs 8 h lsbs 8 l lsbs table 10. 12-bit frequency word 8 lsbs 4 msbs (the 4 msbs of the 8-bit word loaded = 0) direct data transfer and deferred data transfer within the ad9835 , 16-bit transfers are used when loading the destination frequency/phase register. there are two modes for loading a register, direct data transfer and a deferred data transfer. with a deferred data transfer, the 8-bit word is loaded into the defer register (8 lsbs or 8 msbs). however, this data is not loaded into the 16-bit data register; therefore, the destination register is not updated. with a direct data transfer, the 8-bit word is loaded into the appropriate defer register (8 lsbs or 8 msbs). immediately following the loading of the defer register, the contents of the complete defer register are loaded into the 16-bit data register and the destination register is loaded on the next mclk rising edge. when a destination register is addressed, a deferred transfer is needed first followed by a direct transfer. when all 16 bits of the defer register contain relevant data, the destination register can then be updated using 8-bit loading rather than 16-bit loading, that is, direct data transfers can be used. for example, after a new 16-bit word has been loaded to a destination register, the defer register will also contain this word. if the next write instruction is to the same destination register, the user can use direct data transfers immediately. when writing to a phase register, the 4 msbs of the 16-bit word loaded into the data register should be zero (the phase registers are 12 bits wide). to alter the entire contents of a frequency register, four write operations are needed. however, the 16 msbs of a frequency word are contained in a separate register to the 16 lsbs. therefore, the 16 msbs of the frequency word can be altered independent of the 16 lsbs. the phase and frequency registers to be used are selected using the fselect, psel0, and psel1 pins, or the corresponding bits can be used. bit selsrc determines whether the bits or the pins are used. when selsrc = 0, the pins are used, and when selsrc = 1, the bits are used. when clr is taken high, selsrc is set to 0 so that the pins are the default source. data transfers from the serial (defer) register to the 16-bit data register, and the fselect and psel registers, occur following the 16th falling sclk edge. table 11. controlling the ad9835 d15 d14 command 1 0 selects source of control for the phasex and freqx registers and enables synchronization. bit d13 is the sync bit. when this bit is high, reading of the fselect, psel0, and psel1 bits/ pins and the loading of the destination register with data is synchronized with the rising edge of mclk. the latency is increased by 2 mclk cycles when sync = 1. when sync = 0, the loading of the data and the sampling of fselect/psel0/psel1 occurs asynchronously. bit d12 is the select source bit (selsrc). when this bit equals 1, the phasex/freqx reg is selected using the fselect, psel0, and psel1 bits. when selsrc = 0, the phasex/freqx reg is selected using the fselect, psel0, and psel1 pins. 1 1 sleep, reset, and clr (clear). d13 is the sleep bit. when this bit equals 1, the ad9835 is powered down, internal clocks are disabled, and the current sources and refout of the dac are turned off. when sleep = 0, the ad9835 is powered up. when reset (d12) = 1, the phase accumulator is set to zero phase that corresponds to an analog output of midscale. when clr (d11) = 1, sync and selsrc are set to zero. clr resets to 0 automatically.
data sheet ad9835 rev. a | page 17 of 28 table 12. setting sync and selsrc d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 0 sync selsrc x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 1 x = dont care. table 13. power-down, resetting and clearing the ad9835 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 sleep reset clr x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 1 x = dont care. transfer of the data from the 16-bit data register to the destination register or from the fselect/psel register to the respective multiplexer occurs on the next mclk rising edge. because sclk and mclk are asynchronous, an mclk rising edge may occur while the data bits are in a transitional state. this can cause a brief spurious dac output if the register being written to is generating the dac output. to avoid such spurious outputs, the ad9835 contains synchronizing circuitry. when the sync bit is set to 1, the synchronizer is enabled and data transfers from the serial register (defer register) to the 16-bit data register, and the fselect/psel registers occur following a two-stage pipeline delay that is triggered on the mclk falling edge. the pipeline delay ensures that the data is valid when the transfer occurs. similarly, selection of the frequency/phase registers using the fselect/pselx pins is synchronized with the mclk rising edge when sync = 1. when sync = 0, the synchronizer is bypassed. selecting the frequency/phase registers using the pins is synchronized with mclk intern ally also when sync = 1 to ensure that these inputs are valid at the mclk rising edge. if times t 11 and t 11a are met, then the inputs will be at steady state at the mclk rising edge. however, if times t 11 and t 11a are violated, the internal synchronizing circuitry will delay the instant at which the pins are sampled, ensuring that the inputs are valid at the sampling instant (see figure 5 ). latency associated with each operation is a latency. when inputs fselect/psel change value, there is a pipeline delay before control is transferred to the selected register; there is a pipeline delay before the analog output is controlled by the selected register. when times t 11 and t 11a are met, psel0, psel1, and fselect have latencies of six mclk cycles when sync = 0. when sync = 1, the latency is increased to 8 mclk cycles. when times t 11 and t 11a are not met, the latency can increase by one mclk cycle. similarly, there is a latency associated with each write operation. if a selected frequency/phase register is loaded with a new word, there is a delay of 6 to 7 mclk cycles before the analog output will change (there is an uncertainty of one mclk cycle regarding the mclk rising edge at which the data is loaded into the destination register). when sync = 1, the latency is 8 or 9 mclk cycles. flowcharts the flowchart in figure 22 shows the operating routine for the ad9835 . when the ad9835 is powered up, the part should be reset, which resets the phase accumulator to zero so that the analog output is at midscale. to avoid spurious dac outputs while the ad9835 is being initialized, the reset bit should be set to 1 until the part is ready to begin generating an output. taking clr high sets sync and selsrc to 0 so that the fselect/pselx pins are used to select the frequency/phase registers, and the synchronization circuitry is bypassed. a write operation is needed to the sync/selsrc register to enable the synchronization circuitry or to change control to the fselect/ psel bits. reset does not reset the phase and frequency registers. these registers will contain invalid data and, therefore, should be set to a known value by the user. the reset bit is then set to 0 to begin generating an output. a signal will appear at the dac output 6 mclk cycles after reset is set to 0. the analog output is f mclk /2 32 freg, where freg is the value loaded into the selected frequency register. this signal is phase shifted by the amount specified in the selected phase register (2/4096 phasex reg, where phasex reg is the value contained in the selected phase register). control of the frequency/phase registers can be interchanged from the pins to the bits.
ad9835 data sheet rev. a | page 18 of 28 select data sources set fselect set psel0, psel1 initialization wait 6 mclk cycles (8 mclk cycles if sync = 1) dac output v out = v refin 6.25 r out /r set (1 + sin(2 (freg f mclk t/2 32 + phasereg/2 12 ))) change phase? no change f out ? change f out ? yes no yes no yes change fselect change phasereg? no yes change psel0, psel1 data write freg[0] = f out0 / f mclk 2 32 freg[1] = f out1 / f mclk 2 32 phasereg [3:0] = delta phase[0, 1, 2, 3] 09630-024 figure 22. flowchart for ad9835 initialization and operation initialization control register write set sleep reset = 1 clr = 1 set sync and/or selsrc to 1 yes no control register write sync = 1 and/or selsrc = 1 set pins or frequency/phase register write set fselect, psel0 and psel1 control register write sleep = 0 reset = 0 clr = 0 write initial data freg[0] = f out0 / f mclk 2 32 freg[1] = f out1 / f mclk 2 32 phasereg[3:0] = delta phase[0, 1, 2, 3] 09630-025 figure 23. initialization
data sheet ad9835 rev. a | page 19 of 28 data write deferred transfer write write 8 bits to defer register direct transfer write write present 8 bits and 8 bits in defer register to data register write another word to this register? write a word to another register change 8 bits only yes no change 16 bits no yes 09630-026 figure 24. data writes select data sources fselect/psel pins being used? yes selsrc = 0 set pins set fselect set psel0 set psel1 frequency/phase register write set fselect set psel0 set psel1 no selsrc = 1 09630-027 figure 25. selecting data sources
ad9835 data sheet rev. a | page 20 of 28 applications information the ad9835 contains functions that make it suitable for modulation applications. the part can be used to perform simple modulation such as fsk. more complex modulation schemes such as gmsk and qpsk can also be implemented using the ad9835 . in an fsk application, the two frequency registers of the ad9835 are loaded with different values; one frequency will represent the space frequency while the other will represent the mark frequency. the digital data stream is fed to the fselect pin, which will cause the ad9835 to modulate the carrier frequency between the two values. the ad9835 has four phase registers; this enables the part to perform psk. with phase shift keying, the carrier frequency is phase shifted, the phase being altered by an amount that is related to the bit stream being input to the modulator. the presence of four shift registers eases the interaction needed between the dsp and the ad9835 . the ad9835 is also suitable for signal generator applications. with its low current consumption, the part is suitable for applications in which it can be used as a local oscillator. grounding and layout the printed circuit board that houses the ad9835 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes which can be separated easily. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should only be joined in one place. if the ad9835 is the only device requiring an agnd to dgnd connection, then the ground planes should be connected at the agnd and dgnd pins of the ad9835 . if the ad9835 is in a system where multiple devices require agnd to dgnd connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the ad9835. avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the ad9835 to avoid noise coupling. the power supply lines to the ad9835 should use as large a track as is possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the other side. good decoupling is important. the analog and digital supplies to the ad9835 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. all analog and digital supplies should be decoupled to agnd and dgnd respectively with 0.1 mf ceramic capacitors in parallel with 10 mf tantalum capacitors. to achieve the best from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. in systems where a common supply is used to drive both the avdd and dvdd of the ad9835 , it is recommended that the systems avdd supply be used. this supply should have the recommended analog supply decoupling between the avdd pins of the ad9835 and agnd and the recommended digital supply decoupling capacitors between the dvdd pins and dgnd. interfacing the ad9835 to microprocessors the ad9835 has a standard serial interface that allows the part to interface directly with several microprocessors. the device uses an external serial clock to write the data/control information into the device. the serial clock can have a frequency of 20 mhz maximum. the serial clock can be continuous or it can idle high or low between write operations. when data/ control information is being written to the ad9835 , fsync is taken low and held low while the 16 bits of data are being written into the ad9835 . the fsync signal frames the 16 bits of information being loaded into the ad9835. ad9835-to-adsp-21xx interface figure 26 shows the serial interface between the ad9835 and the adsp-21xx. the adsp-21xx should be set up to operate in the sport transmit alternate framing mode (tfsw = 1). the adsp-21xx is programmed through the sport control register and should be configured as follows: internal clock operation (isclk = 1), active low framing (invtfs = 1), 16-bit word length (slen = 15), internal frame sync signal (itfs = 1), generate a frame sync for each write operation (tfsr = 1). transmission is initiated by writing a word to the tx register after the sport has been enabled. the data is clocked out on each rising edge of the serial clock and clocked into the ad9835 on the sclk falling edge. ad9835* fsync sdata sclk adsp-2101/ adsp-2103* tfs dt sclk *additional pins omitted for clarity. 09630-028 figure 26. adsp-2101/adsp-2103 to ad9835 interface
data sheet ad9835 rev. a | page 21 of 28 ad9835-to-68hc11/68l11 interface figure 27 shows the serial interface between the ad9835 and the 68hc11/68l11 microcontroller. the microcontroller is configured as the master by setting bit mstr in the spcr to 1 and, this provides a serial clock on sck while the mosi output drives the serial data line sdata. since the microcontroller does not have a dedicated frame sync pin, the fsync signal is derived from a port line (pc7). the setup conditions for correct operation of the interface are as follows: the sck idles high between write operations (cpol = 0), data is valid on the sck falling edge (cpha = 1). when data is being transmitted to the ad9835 , the fsync line is taken low (pc7). serial data from the 68hc11/68l11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. in order to load data into the ad9835 , pc7 is held low after the first eight bits are transferred and a second serial write operation is performed to the ad9835 . only after the second eight bits have been transferred should fsync be taken high again. ad9835* fsync sdata sclk 68hc11/68l11* pc7 mosi sck *additional pins omitted for clarity. 09630-029 figure 27. 68hc11/68l11-to- ad9835 interface ad9835-to-80c51/80l51 interface figure 26 shows the serial interface between the ad9835 and the 80c51/80l51 microcontroller. the microcontroller is operated in mode 0 so that txd of the 80c51/80l51 drives sclk of the ad9835 while rxd drives the serial data line sdata. the fsync signal is again derived from a bit programmable pin on the port (p3.3 being used in the diagram). when data is to be transmitted to the a ad9835, p3.3 is taken low. the 80c51/80l51 transmits data in 8-bit bytes thus, only eight falling sclk edges occur in each cycle. to load the remaining eight bits to the ad9835 , p3.3 is held low after the first eight bits have been transmitted and a second write operation is initiated to transmit the second byte of data. p3.3 is taken high following the completion of the second write operation. sclk should idle high between the two write operations. the 80c51/ 80l51 outputs the serial data in a format which has the lsb first. the ad9835 accepts the msb first (the 4 msbs being the control information, the next 4 bits being the address while the 8 lsbs contain the data when writing to a destination register). therefore, the transmit routine of the 80c51/80l51 must take this into account and rearrange the bits so that the msb is output first. ad9835* fsync sdata sclk 80c51/80l51* p3.3 rxd txd *additional pins omitted for clarity. 09630-030 figure 28. 80c51/80l51 to ad9835 interface ad9835-to-dsp56002 interface figure 29 shows the interface between the ad9835 and the dsp56002. the dsp56002 is configured for normal mode asynchronous operation with a gated internal clock (syn = 0, gck = 1, sckd = 1). the frame sync pin is generated internally (sc2 = 1), the transfers are 16 bits wide (wl1 = 1, wl0 = 0) and the frame sync signal will frame the 16 bits (fsl = 0). the frame sync signal is available on pin sc2 but, it needs to be inverted before being applied to the ad9835 . the interface to the dsp56000/dsp56001 is similar to that of the dsp56002. ad9835* fsync sdata sclk dsp56002* sc2 std sck *additional pins omitted for clarity. 09630-031 figure 29. ad9835 -to-dsp56002 interface
ad9835 data sheet rev. a | page 22 of 28 evaluation board system demonstration platform the system demonstration platform (sdp) is a hardware and software evaluation tool for use in conjunction with product evaluation boards. the sdp board is based on the black fin ? bf527 processor with usb connectivity to the pc through a usb 2.0 high speed port. note that the sdp board is sold separately from the ad9835 evaluation board. ad9835 to sport interface the analog devices sdp board has a sport serial port that is used to control the serial inputs to the ad9835 . the connections are shown in figure 30 . ad9835 fsync sdata sclk 09630-039 sport_tfs sport_tsclk sport_dto adsp-bf527 figure 30. sdp to ad9835 interface the ad9835 evaluation board allows designers to evaluate the high performance ad9835 dds modulator with a minimum of effort. the gui interface for the ad9835 evaluation board is shown in figure 31 . 09630-035 figure 31. ad9835 evaluation software the dds evaluation kit includes a populated, tested ad9835 pcb. software is available with the evaluation board that allows the user to easily program the ad9835 . the schematics and layout of the ad9835 evaluation board are shown in figure 32 through figure 36 . the software runs on any ibm-compatible pc that has microsoft? windows? 95, windows 98, windows me, windows 2000 nt?, or windows 7 installed. additional details can be found in the EVAL-AD9835SDZ data sheet (ug-319) that is available on the software cd and on the ad9835 product page. xo vs. external clock the ad9835 can operate with master clocks up to 50 mhz. a 50 mhz general oscillator is included on the evaluation board. however, this oscillator can be removed and, if required, an external cmos clock can be connected to the part. two options for the general oscillator are: ? ael 301 series crystals oscillators (ael crystals, ltd.) ? sg-310scn oscillators (epson toyocom corporation) power supply power to the ad9835 evaluation board can be provided from a usb connector or externally through pin connections. the power leads should be twisted to reduce ground loops.
data sheet ad9835 rev. a | page 23 of 28 evaluation board schematics and layout figure 32. ad9835 schematic, part a
ad9835 data sheet rev. a | page 24 of 28 09630-034 figure 33. ad9835 schematic, part b
data sheet ad9835 rev. a | page 25 of 28 09630-036 figure 34. component side view layer 1 09630-037 figure 35. component side view silkscreen 09630-038 figure 36. component side view layer 2, solder side
ad9835 data sheet rev. a | page 26 of 28 ordering information bill of materials table 14. reference designator description manufacturer part number c1, c3, c5, c6, c11 1 , c12, c13 1 0.1 f, 10%, 50 v, x7r, ceramic capacitor murata grm188r71h104ka93d c7 0.01 f, 10%, 10 v, 0603, x5r, capacitor kemet c0603c103k5ractu c2, c4 10 f, 10%,10 v, smd tantalum capacitor avx taja106k010r c8,c9 1 f, 10%,10 v,y5v, 0603, ceramic capacitor yageo cc0603zry5v6bb105 c10 0.1 f, 10%, 16 v, x7r, 0603, capacitor multicomp b0603r104kct clk 1 , fsel 1 , iout, psel1 1 , refin, psel0 1 straight pcb mount smb jack, 50 tyco 1-1337482-0 fsync, iout_, mclk , sclk, sdata red test point vero 20-313137 g2 copper short not appl icable not applicable j1 120-way connector, 0.6 mm pitch receptacle hrs (hirose) fx8-120s-sv(21) j2, j3 2-pin terminal block (5 mm pitch) campden ctb5000/2 lk3, lk5, lk6 3-pin sil header and shorting link harwin m20-9990345 and m7567-05 lk1 2-pin sil header and shorting link harwin m20-9990246 r7 1 , r8 1 , r9 1 10 k, 1%, 0603, smd resistor multicomp mc 0.063w 0603 10k r12 1 50 , 1%, 0603, smd resistor multicomp mc 0.063w 0603 50r r14 3.9 k, 1%, smd resistor multicomp mc 0.063w 0603 6k8 r15 300 , 1%, smd resistor multicomp mc 0.063w 0603 200r r17,r18 100 k, 1%, smd resistor multicomp mc 0.063w 0603 1% 100k r1, r2 1 , r3, r4 1 , r6 1 , r5, r11 1 , r10,r16 2 0 , 1%, 0603, smd resistor multicomp mc 0.063w 0603 0r r13 330 k, 5%, smd resistor multicomp mc 0.063w 0603 330kr u4 200 mw power 5 v, 50 mhz complete dds analog devices ad9835bruz u1 32 k i 2 c serial eeprom 8-lead msop micro chip 24lc32a-i/ms u5 3.3 v linear regulator analog devices adp3301arz-3.3 y2 50 mhz, 3 mm 2 mm smd clock oscillator ael crystals ael301 series 1 do not install. 2 dnp
data sheet ad9835 rev. a | page 27 of 28 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 37. 16-lead thin shrink small outline package (tssop) (ru-16) dimensions shown in millimeters ordering guide model 1, 2 temperature range package description pa ckage option ad9835bru ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 ad9835bru-reel ?40c to +85c 16-lead thin sh rink small outline package [tssop] ru-16 ad9835bru-reel7 ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 ad9835bruz ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 ad9835bruz-reel ?40c to +85c 16-lead thin sh rink small outline package [tssop] ru-16 ad9835bruz-reel7 ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 EVAL-AD9835SDZ evaluation board (to be used in conjunction with an sdp board) 1 z = rohs compliant part. 2 for the EVAL-AD9835SDZ, an sdp board is required.
ad9835 data sheet rev. a | page 28 of 28 notes ?1998C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09630-0-9/11(a)

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