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hanbit h m f8m8f 4v/4vt url: www.hbe.co.kr h anbit electronic s co., ltd. rev.02(august,2002) 1 note: p1 - a23(27pin) must be grounded general description the h m f8m8 f4v is a high - speed flash read only memory (from) module containing 8,388,608 words organized in a x8bit configuration. the module consists of four 2m x 8 from mounted on a 100 - pin, mmc connector fr4 - printed circu it board. c ommands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state - machine, which controls the erase and programming circuitry. write cycles also internally latc h addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 12.0v flash or eprom devices. four chips enable inputs, /cs(/cs0, /cs1, /cs2, /cs3) are used to enable the module s 4 chips inde pendently. output enable (/oe) and write enable (/we) can set the memory input and output. the host system can detect a program or erase operation is complete by observing the ready pin, or reading the dq7(data # polling) and dq6(toggle) status bits. whe n from module is disable condition the module is becoming power standby mode, system designer can get low - power design. all module components may be powered from a single + 3 v dc power supply and all inputs and outputs are lv ttl - compatible. features w part identifi cation - h m f8m8 f4v (bottom boot block configuration) - HMF8M8F4Vt (top boot block configuration) w access time: 8 0, 90, 120ns w high - density 8mbyte design w high - reliability, low - power design w single + 3v to 3.6 v power supply w 1 00 - pin designed 50 - pin fine pitch mmc connector p1,p2 w minimum 1 ,0 00,000 write/erase cycle w 20 - year data retention at 125 o c w flexible sector architecture w embedded algorithms w erase suspend / erase resume w the used device is am29lv116b options marking w tim ing 80 n s access - 80 90 n s access - 90 120 n s access - 120 w packages 100 - pin mmc f 50 - pin p1 connec tor 50 - pin p2 connector pin symbol pin symbol pin symbol pin symbol 1 vcc 26 vcc 1 vcc 2 6 vcc 2 nc 27 nc 2 nc 2 7 nc 3 nc 28 a19 3 /we 2 8 nc 4 a20 29 a18 4 nc 2 9 nc 5 nc 30 a17 5 ready 3 0 nc 6 nc 31 a16 6 nc 3 1 nc 7 nc 32 a15 7 nc 3 2 nc 8 vs s 33 vss 8 vss 3 3 vss 9 nc 34 a14 9 /oe 3 4 nc 10 nc 35 a13 1 0 / cs0 3 5 /cs2 11 nc 36 nc 1 1 / c s1 3 6 /cs3 12 nc 37 dq7 1 2 nc 3 7 nc 13 vss 38 vss 1 3 vss 3 8 vss 14 dq6 39 dq5 1 4 nc 3 9 nc 15 dq4 40 a12 1 5 nc 4 0 nc 16 dq3 41 a11 1 6 nc 4 1 nc 17 dq2 42 a10 1 7 /reset 4 2 nc 18 vss 43 vss 1 8 vss 4 3 vss 19 dq1 44 a9 1 9 nc 4 4 nc 20 dq0 45 a8 2 0 nc 4 5 nc 21 a0 46 a7 2 1 nc 4 6 nc 22 a1 47 a6 2 2 nc 4 7 nc 23 a2 48 a5 2 3 vss 4 8 vss 24 a3 49 a4 2 4 nc 4 9 nc 25 vcc 50 vcc 2 5 vcc 5 0 vcc flash - rom module 8mb yte ( 8 m x 8 - bit) C smm packages part no. hmf 8 m 8f4v,HMF8M8F4Vt p in assignment
hanbit h m f8m8f 4v/4vt url: www.hbe.co.kr h anbit electronic s co., ltd. rev.02(august,2002) 2 fun ctional block diagra m dq0 - dq7 a0 - a20 /we /oe a0 - 20 / we /oe dq 0 - 7 / ce u1 a0 - 20 /we /oe dq 0 - 7 /ce u3 a0 - 20 /we /oe dq 0 - 7 /ce u4 21 a0 - 20 /we / oe dq 0 - 7 /ce u2 8 / reset ready /cs3 /cs2 /cs1 / cs0
hanbit h m f8m8f 4v/4vt url: www.hbe.co.kr h anbit electronic s co., ltd. rev.02(august,2002) 3 truth table mode /c s /oe /we reset dq standby vcc 0.3v x x vcc 0.3v high - z reset x x x l high - z sector protect l h l v id d in, d out sector unpro tect l h l v id d in, d out read l l h h d out write l h l h d out note : x means don't care absolute maximum rat ings parameter rating voltage on any pin relative to vss - 0. 5 v to vcc +0 .5 v voltage on vcc supply relative to vss - 0.5v to + 4 .0v oupput short circuit current 200ma storage temperature - 65 o c to +150 o c operating temperature - 55 o c to +125 o c w stresses greater than those listed under " absolute maximum ratings" may cause permanent damage to the device. this is a stress rating on ly and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliabil ity. recommended operatin g conditions parameter range vcc for regulated supply voltage +3.0v to 3.6 v vcc for full voltage +2.7v to 3.6 v dc and operating cha racteristics parameter test conditions symbol min max units input load current v in = v ss to v cc , v cc = v cc max i l1 1. 0 m a output leakage current v out = v ss to v cc , v cc = v cc max i l0 1. 0 m a output high voltage i oh = - 2. 0 ma, vcc = vcc min v oh 0.85vcc v output low voltage i ol = 4.0ma, vcc = vcc min v ol 0.45 v vcc active read current /c e = v il , , /oe=v ih , f=5mhz i cc1 16 ma
hanbit h m f8m8f 4v/4vt url: www.hbe.co.kr h anbit electronic s co., ltd. rev.02(august,2002) 4 vcc active write current /ce = v il , /oe=v ih i cc2 3 0 ma vcc standby current /ce , reset =v cc 0.3v i cc3 5 ma vcc reset current reset= v ss 0.3v , i cc4 5 ma low vcc lock - out voltage v lko 2.3 2.5 v erase and programmi ng performance limits parameter min. typ. max. unit comments sector erase time - 0.7 15 sec excludes 00h programming prior to erasure byte programming time - 9 3 00 m s excludes system - level overhead chip programming time - 1 8 54 sec excludes system - level overhead tsop pin capacitance parameter symbol parameter descrip tion test setup typ. max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 contro l pin capacitance v in = 0 7.5 9 pf notes : test conditions t a = 25 o c, f=1.0 mhz. ac characteristics u read only operations characteristics parameter symbols jedec standard description test setup - 80 (note1) - 90 (note1) unit t avav t rc read cycle time min 80 90 ns t avqv t acc address to output delay /ce = v il /oe = v il max 80 90 ns t elqv t ce chip enable to output delay /oe = v il max 8 0 9 0 ns t glqv t oe chip enable to output delay max 80 90 ns
hanbit h m f8m8f 4v/4vt url: www.hbe.co.kr h anbit electronic s co., ltd. rev.02(august,2002) 5 t ehqz t df chip enab le to output high - z max 25 30 ns t ghqz t df output enable to output high - z max 25 30 ns t axqx t qh output hold time from addresses, /ce or /oe, whichever occurs first min 0 0 ns test conditions notes : test conditions : output load : 1ttl gat e and 100 pf input rise and fall times : 5 ns input pulse levels: 0v to 3.0v timing measurement reference level input : 1.5 v output : 1.5 v u erase/program operations parameter symbols jedec standard description - 80 - 9 0 unit t avav t wc write cycle t ime min 80 9 0 ns t avwl t as address setup time min 0 0 ns t wlax t ah address hold time min 45 45 ns t dvwh t ds data setup time min 35 45 ns t whdx t dh data hold time min 0 0 ns 3. 3 v device under test 2.7k w diodes = in3064 or equivalent 6.2k w in3064 or equivalent c l note : c l = 100pf including jig capacitance
hanbit h m f8m8f 4v/4vt url: www.hbe.co.kr h anbit electronic s co., ltd. rev.02(august,2002) 6 t oes output enable setup time min 0 0 ns t ghwl t ghwl read recove r time before write min 0 0 ns t elwl t cs /ce setup time min 0 0 ns t wheh t ch /ce hold time min 0 0 ns t wlwh t wp write pulse width min 35 3 5 ns t whwl t wph write pulse width high min 3 0 3 0 ns t whwh1 t whwh1 byte programming operation typ 9 9 m s typ 0.7 0.7 sec t whwh2 t whwh2 sector erase operation (note1) max 50 50 sec t vcs vcc setup time min 50 50 m s t rb recovery time from ry/by min 0 0 m s t busy program/erase valid to ry/by delay min 90 90 m s u alternate /ce controlled era se/program operations parameter symbols jedec standard description - 8 0 - 9 0 unit t avav t wc write cycle time min 8 0 9 0 ns t avel t as address setup time min 0 0 ns t elax t ah address hold time min 45 45 ns t dveh t ds data setup time min 3 5 45 n s t ehdx t dh data hold time min 0 0 ns t oes output enable setup time min 0 0 ns t ghel t ghel read recover time before write /oe high to /we low min 0 0 ns t wlel t ws /we setup time min 0 0 ns t ehwh t wh /we hold time min 0 0 ns t eleh t cp /ce pulse width min 3 5 35 ns t ehel t cph /ce pulse width high min 3 0 3 0 ns t whwh1 t whwh1 byte programming operation typ 9 9 m s t whwh2 t whwh2 sector erase operation (note) typ 0.7 0.7 sec
hanbit h m f8m8f 4v/4vt url: www.hbe.co.kr h anbit electronic s co., ltd. rev.02(august,2002) 7 u read operations timing u reset timing
hanbit h m f8m8f 4v/4vt url: www.hbe.co.kr h anbit electronic s co., ltd. rev.02(august,2002) 8 u program operations timing u chip/sector erase operation timings
hanbit h m f8m8f 4v/4vt url: www.hbe.co.kr h anbit electronic s co., ltd. rev.02(august,2002) 9 u data# polling times(during embedded algorithms) u toggle# bit timings (during embedded algorithms)
hanbit h m f8m8f 4v/4vt url: www.hbe.co.kr h anbit electronic s co., ltd. rev.02(august,2002) 10 u sector protect unprotect timeing diagram u alternate ce# controlled write operating timings
hanbit h m f8m8f 4v/4vt url: www.hbe.co.kr h anbit electronic s co., ltd. rev.02(august,2002) 11 package dimensions unit: mm - c onnector part no. HMF8M8F4V top: 50 - pin 0.6mm pitch free height plugs, amp part no. 316076 - 3 bottom: 50 - pin 0.6mm pitch free height receptacles, amp part no. 316077 - 3 90.17 5.08 3.70 3.70 25.00 3.70 17.60 3.70 5.08 p1 p2 1 25 26 50 1 25 26 50 main board 1.20 3.45 3.25 5.00
hanbit h m f8m8f 4v/4vt url: www.hbe.co.kr h anbit electronic s co., ltd. rev.02(august,2002) 12 o r dering information part number density org. package speed vcc func tion HMF8M8F4V 8mbyte 8mx 8bit 100 pin - mmc 80,90,120(ns) 3v bottom HMF8M8F4Vt 8mbyte 8mx 8bit 100 pin - mmc 80,90,120(ns) 3v top

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