View IA6805E2-PDW40I-00_7238522.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ia6805e2 29 august 2007 microprocessor unit as of production version 00 ia6805e2 microprocessor unit data sheet copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 1 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 features copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 2 of 33 1-888-824-4184 ? ? ? ? ? ? ? ? ? ? ? ? ? form, fit, and function compatible with the harris ? cdp6805e2ce and motorola ? mc146805e2 internal 8-bit timer with 7-bit programmable prescaler on-chip clock memory mapped i/o versatile interrupt handling true bit manipulation bit test and branch instruction vectored interrupts power-saving stop and wait modes fully static operation 112 bytes of ram packaging options available: 40 pin plastic dip or, 44 pin plastic leaded chip carrier, standard or rohs packages available the ia6805e2 is a "plug-and-play" drop -in replacement for the original ic. innovasic produces replacement ics using its miles tm , or managed ic lifetime extension system, cloning technology. this technology produces replacement ics far more complex than "emulation" while ensuring they are compatible with the original ic. miles tm captures the design of a clone so it ca n be produced even as silicon technology advances. miles tm also verifies the clone against the original ic so that even the "undocumented features" are duplicated. this data sheet documents all necessary engineering information about the ia6805e2 including functional and i/o descriptions, electrical characteristics, and applicable timing. package pinout a12 nc (6) as (1) reset_n (2) irq_n (3) li (4) ds (5) rw_n (7) pa7 (8) (9) pa5 (10) (11) (12) pa2 (13) pa1 (14) 40 pin dip ia6805e2 pb4 pb5 pb6 pb7 (20) vss (15) a12 (16) a11 (17) a10 (18) a9 (19) a8 (21) (22) (23) (24) b6 b7 (40) (39) (38) (37) (36) (35) (34) (33) (32) (31) (30) (29) (28) (27) (26) (25) pa0 b4 b5 b2 b3 b0 b1 pb2 pb3 pb0 pb1 osc2 timer vdd osc1 pa6 pa4 pa3 rw_n nc b2 44 pin lcc ia6805e2 (12) pa3 (7) as (8) pa7 (9) pa6 (10) pa5 (11) pa4 (13) pa2 (14) pa1 (15) pa0 (16) nc (17) nc pb1 pb7 pb6 pb5 pb3 pb2 a10 a11 (6) (5) (4) (3) (2) (1) (44) (43) (42) osc2 (41) timer (40) pb0 (34) (39) (38) (37) (36) (35) (33) (32) (31) (30) (29) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) vdd osc1 irq_n reset_n ds li a8 a9 b7 vss b5 b6 b4 b3 b1 b0 pb4
ia6805e2 29 august 2007 microprocessor unit as of production version 00 description the ia6805e2 (cmos) microprocessor unit (mpu) is a low cost, low power mpu. it features a cpu, on-chip ram, parallel i/o compatibility with pins programmable as input or output. the following paragraphs will further describe this system block diagram and design in more detail. program counter low 112x8 ram address drive mux bus drive cpu port a reg oscillator data dir reg port b reg data dir reg cpu control alu bus control stack pointer condition code register index register accumulator program counter high timer control prescaler timer/ counter pa0 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pb0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pa0 osc1 osc2 timer reset_n li irq_n b0 b7 b6 b5 b4 b3 b2 b1 a8 a12 a11 a10 a9 rw_n ds as 8a 5 6 5 8 8 x cc sp pch pcl port a i/o lines port b i/o lines multiplexed address data bus address bus address strobe data strobe read/write copyright ? 2007 ia211081401-03 www.innovasic.com customer support: figure 1. system block diagram page 3 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 i/o signal description the table below describes the i/o characteristics for each signal on the ic. the signal names correspond to the signal names on the pinout diagrams provided. sig nal nam e i/o description v dd and v s s (power and ground) n/a source: these two pins provide power to the chip. v dd provides +5 volts (0.5) power and v ss is ground. reset_n (reset) i ttl: input pin that can be used to reset the mpu's internal state by pulling the reset_n pin low. ir q _n (interrupt request) i ttl: input pin that is level and edge sensitive. can be used to request an interrupt sequence. li (load instruction) o t tl w ith slew rate control: output pin used to indicate that a next opcode fetch is in progress. used only for certain debugging and test systems. not connected in normal operation. overlaps data strobe (ds) signal. this output is capable of driving one standard ttl load and 50pf. d s (data strobe) o ttlwithslewratecontrol: output pin used to transfer data to or from a peripheral or memory. ds occurs anytime the mpu does a data read or write and during data transfer to or from internal memory. ds is available at f osc ?5 when the mpu is not in the w ait or stop mode. this output is capable of driving one standard ttl load and 130pf. r w _n (read/write) o t tl w ith slew rate control: output pin used to indicate the direction of data transfer from internal memory, i/o registers, and external peripheral devices and memories. indicates to a selected peripheral whether the mpu is to read (rw _n high) or write (rw _n low) data on the next data strobe. this output is capable of driving one standard ttl load and 130pf. as (address strobe) o ttlwithslewratecontrol: output strobe used to indicate the presence of an address on the 8-bit multiplexed bus. the as line is used to demultiplex the eight least significant address bits from the data bus. as is available at f osc ?5whenthe mpu is not in the w ait or stop modes. this output is capable of driving one standard ttl load and 130pf. pa0-pa7/pb0-pb7 (input/output lines) i/o ttlwithslewratecontrol: these 16 lines constitute input/output ports a and b. each line is individually programmed to be either an input or output under software control of the data direction register (ddr) as shown below in table 1 and figure 2 . the port i/o is programmed by writing the corresponding bit in the ddr to a "1" for output and a "0" for input. in the output mode the bits are latched and appear on the corresponding output pins. all the ddr's are initialized to a "0" on reset. the output port registers are not initialized on reset. each output is capable of driving one standard ttl load and 50pf. a8-a12 (high order address lines) o ttlwithslewratecontrol: these five outputs constitute the higher order non- multiplexed address lines. each output is capable of driving one standard ttl load and 130pf. b 0-b 7 (address/data bus) i/o ttlwithslewratecontrol: these bi-directional lines constitute the lower order addresses and data. these lines are multiplexed with address present at address strobe time and data present at data strobe time. w hen in the data mode, these lines are bi-directional, transferring data to and from memory and peripheral devices as indicated by the rw _n pin. as outputs, these lines are capable of driving one standard ttl load and 130 p f. timer i ttl: input used to control the internal timer/counter circuitry. o sc 1, o sc 2 (system clock) ttl oscillator input/output: these pins provide control input for the on-chip clock oscillator circuits. either a crystal or external clock is connected to these pins to provide a system clock. the crystal connection is shown in figure 3 .theosc1to bus transitions for system designs using oscillators slower than 5mhz is shown in figure 4 . crystal t he circuit shown in figure 3 is recommended when using a crystal. an external cmos oscillator is recommended when using crystals outside the specified ranges. to minimize output distortion and start-up stabilization time, the crystal and components should be mounted as close to the input pins as possible. external clock w hen an external clock is used, it should be applied to the osc1 input with the osc2 input not connected, as shown in figure 3 . i/o table 1 copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 4 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 i/o pin functions r/w-n ddr i/o pin functions 00 the i/o pin is in input mode. data is written into the output data latch. 01 data is written into the output data latch and output to the i/o pin. 10 the state of the i/o pin is read. 11 the i/o pin is in an output mode. the output data latch is read. i/o port circuitry and register configuration: data direction register bit i/o pin output latched output data bit input reg bit input i/o pin to and from cpu dda7 (ddb7) dda1 (ddb1) dda2 (ddb2) dda3 (ddb3) dda4 (ddb4) dda5 (ddb5) dda6 (ddb6) dda0 (ddb0) data direction a(b) register port a(b) register 74 5 630 12 pa7 (pb7) pa6 (pb6) pa5 (pb5) pa4 (pb4) pa3 (pb3) pa2 (pb2) pa1 (pb1) pa0 (pb0) pin $0004 ($0005) $0000 ($0001) figure 2. pa0-pa7/pb0-pb7 (input/output lines) copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 5 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 crystal parameters repres entative frequencies: 5.0 mhz 4.0 mhz 1.0 mhz r s max 50 75 400 c0 8 pf 7 pf 5 pf c1 0.02 pf 0.012 pf 0.008 pf q 50 k 40 k 30 k c osc1 15-30 pf 15-30 pf 15-40 pf c osc2 15-25 pf 15-25 pf 15-30 pf oscillator connections: l c1 39 c0 rs osc1 osc2 38 39 osc2 38 osc1 crystal circuit crystal oscillator connections t ol t t oh t olol osc1 pin ia6805e2 10 m c osc2 osc1 osc1 c osc2 38 39 osc1 ia6805e2 osc2 38 39 nc figure 3. osc1, osc2 (system clock) osc1 to bus transitions timing waveforms: osc1 as ds rw_n a[12:8] b[7:0] mpu read b[7:0] mpu write *read data "latched" on ds fall mux addr mpu read data* mux addr mpu write data figure 4. osc1, osc2 (system clock) copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 6 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 functional description memory: the mpu is capable of addressing 8192 bytes of memory and i/o registers. the locations are divided into internal memory space and ex ternal memory space as shown in figure 5. the first 128 bytes of memory contain internal port i/o locations, timer locations, and 112 bytes of ram. the mpu can read from or wri te to any of these locations. during program reads from on chip locations, the mpu accep ts data only from the addressed on chip location. any read data appearing on the input b us is ignored. the shared stack area is used during interrupts or subroutine calls. a maximum of 64 bytes of ram is available for stack usage. the stack pointer is set to $7f at power up. the unused bytes of the stack can be used for data storage or temporary work locations, but care must be taken to prevent it from being overwritten due to stacking from an interrupt or subroutine call. ram (112 bytes) i/o ports timer ram external memory space (8064 bytes) timer interrupt from wait state only timer interrupt external interrupt swi reset port a data register port b data register external memory space external memory space port a data direction register port b data direction register external memory space external memory space timer data register timer control register external memory space $1ff6 - $1ff7 $1ff8 - $1ff9 $1ffa - $1ffb $1ffc - $1ffd $1ffe - $1fff $0000 $007f $0080 $00ff $0100 63 64 127 0 127 128 255 256 8191 interrupt vectors access via page 0 direct address stack (64 bytes max) 0 1 2 3 4 5 6 7 8 9 10 15 16 figure 5. memory map copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 7 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 registers: the following paragraphs describe the registers contained in the mpu. figure 6 shows the programming model and figure 7 shows the interrupt stacking order. a x sp 1 0 0 0 0 0 0 h i n z c 70 cc condition code register carry/borrow half carry interrupt mask negative zero stack pointer program counter index register accumulator 70 12 0 78 pch pcl 12 6 0 4 0 fi g ure 6. pro g rammin g model note: since the stack pointer decrements during pushes, the pcl is stacked first, followed by pch, etc. pulling from the stack is in the reverse order. condition code register accumulator index register 1 1 1 i n t e r r u p t decreasing memory addresses stack pch 0 0 0 pcl r e t u r n increasing memory addresses unstack figure 7. interrupt stacking order copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 8 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 9 of 33 1-888-824-4184 ? a(accumulator): the accumulator is an 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. x(index register): the index register is an 8-bit register used duri ng the indexed addressing mode. it contains an 8-bit value used to create an effective address. the index register may also be used as a temporary storage area when not pe rforming addressing operations. pc(program counter): the program counter is a 13-bit register that hol ds the address of the next instruction to be performed by the mpu. sp(stack pointer): the stack pointer is a 13-bit register that hol ds the address of the next free location on the stack. during an mpu reset or the reset stack pointer (rsp) instruction, the stack pointer is set to location $007f. the seven most significant bits of the stack pointer are permanently set to 0000001. they are appended to the six least significant register bits to produce an address range down to location $0040. the stack pointer gets decremented as data is pushed onto the stack and incremented as data is remove d from the stack. the stack area of ram is used to store the return address on subroutine calls and the machine state during interrupts. the maximum number of locations for the stack pointer is 64 bytes. if the stack goes beyond this limit the stack pointer wraps around and points to its upper limit thereby losing the previously stored information. subroutine calls use 2 bytes of ram on the stack and interrupts use 5 bytes. cc(condition code register): the condition code register is a 5-bit register that indicates the results of the instruction just executed. the bit is set if it is high. a progra m can individually test these bits and specific actions can be taken as a result of their states . following is an explanation of each bit. c(carry bit): the carry bit indicates that a carry or borro w out of the arithmetic logical unit (alu) occurred during the last arithmetic instruction. this bit is also modified during bit test, shift, rotate, and branch types of instructions. z(zero bit): the zero bit indicates the result of the last ar ithmetic, logical, or data manipulation was zero . n(negative bit): the negative bit indicates the result to the last arithmetic, logical, or data manipulation was negative (bit 7 in the result is high).
ia6805e2 29 august 2007 microprocessor unit as of production version 00 copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 10 of 33 1-888-824-4184 ? i(interrupt mask bit) the interrupt mask bit indicates that both the external interrupt and the timer interrupt are disabled (masked). if an interrupt occurs while th is bit is set, the interrupt is latched and is processed as soon as the interrupt bit is cleared. h(half carry bit) the half carry bit indicates that a carry occu rred between bits 3 and 4 of the alu during an add or adc operation. resets: the mpu can be reset by initial power up or by the external reset pin (reset_n). por(power on reset) power on reset occurs on initial power up. it is strictly for power initialization conditions and should not be used to detect drops in the power supply voltage. there is a 1920 t cyc time out delay from the time the oscillator is detected. if the reset_n pin is still low at the end of the delay, the mpu will remain in the reset state until the external pin goes high. reset_n the reset_n pin is used to reset the mpu. th e reset pin must stay low for a minimum of t cyc to guarantee a reset. the reset_n pin is prov ided with a schmitt trigger to improve noise immunity capability. interrupts: the mpu can be interrupted with the external interrupt pin (irq_n), the internal timer interrupt request, or the software interrupt in struction. when any of these interrupts occur, normal processing is suspended at the end of the current instruction execution. the processor registers are saved on the stack (s tacking order shown in figure 7) and the interrupt mask (i) is set to prevent additiona l interrupts. normal processing resumes after the rti instruction causes the register conten ts to be recovered from the stack. when the current instruction is completed, the processor checks all pending hardware interrupts and if unmasked (i bit clear) proceeds with interrupt processing. otherwise, the next instruction is fetched and executed. masked interrupts are la tched for later interrupt service. external interrupts hold higher priority than timer interrupts. at the end of an instruction execution, if both an external interrupt and timer interru pt are pending, the external interrupt is serviced first. the swi gets executed with th e same priority as any other instruction if the hardware interrupts are masked (i bit set). figu re 8 shows the reset and interrupt processing flowchart.
ia6805e2 29 august 2007 microprocessor unit as of production version 00 i_cc <= 1 sp <= $007f ddrs <= 0 clr irq_n logic timer <= $ff prescaler <= $7f tcr <= $7f fetch instruction put 1ffe,1fff on address bus reset load pc from 1ffe/1fff execute all instruction cycles clear irq_n request latch load pc from: swi: 1ffc/1ffd irq_n: 1ffa/1ffb timer: 1ff8/1ff9 timer wait:1ff6/ 1ff7 i <= 1 stack pc, x, a, cc pc+1=>pc in reset ? i bit ? irq_n edge ? is fetched instruction an swi? tcr6=0 and tcr7=1? reset_n pin = low reset_n pin = low swi timer irq_n y y y y n n n n set clear fi g ure 8. reset and interru p t processin g flowchart copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 11 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 external interrupt: if the external interrupt pin irq_n is ?low? and the interrupt mask bit of the condition code register is cleared, the external interrupt occurs. when the interrupt is recognized, the current state of the machine is pushed onto th e stack and the condition code register i-bit gets set masking further interrupts until the pr esent one is serviced. the program counter is then loaded with the contents of the interrupt vector, which contains the location of the interrupt service routine. the contents of $1ffa and $1ffb specify the address for this service routine. a functional diagram of the external interrupt is shown in figure 9 and a mode diagram of the external interrupt is s hown in figure 10. the timing diagram shows two different treatments of the interrupt line (irq_n) to the processor. the first shows several interrupt lines ?wire ored? to form the interrupts at the processor. if the interrupt line (irq_n) remains low after servicing an interrupt, the next interrupt is recognized. the second shows single pulses on the interrupt line spaced far enough apart to be serviced. the minimum time between pulses is a function of the length of the interrupt service. after a pulse occurs, the next pulse should not occur until an rti has occurred. the time between pulses (t ilil ) is obtained by adding 20 instruction cycles to the total number of cycles it takes to complete the service routine including the rti instruction. d c q q r vdd interrupt pin power-on reset external interrupt being serviced external reset i bit (ccr) external interupt request fi g ure 9. interru p t functional dia g ram copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 12 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 figure 10. interrupt mode diagram timer interrupt: if the timer mask bit (tcr6) and the interrupt ma sk bit (i) of the condition code register are cleared, each time the timer decrements to zero ($01 to $00 transition) an interrupt request is generated. when the interrupt is recognized, the current state of the machine is pushed onto the stack and the condition code register i-bit gets set masking further interrupts until the present one is serviced. the program counter is then loaded with the contents of the timer interrupt vector, which contains the location of the timer interrupt service routine. the contents of $1ff8 and $1ff9 specify the address for this service routine. if the mpu is in the wait mode and a timer interrupt occurs, th en the contents of $1 ff6 and $1ff7 specify the service routine. when the timer interrupt service routine is complete, the software executes an rti instruction to restore the mach ine state and starts executing the interrupt program. software interrupt: software interrupt is an executable instruction regardless of the state of the interrupt mask bit (i) in the condition code register. swi is si milar to hardware interrupts. it executes after the other interrupts if the interrupt mask bi t is zero. the contents of $1ffc and $1ffd specify the address for this service routine . low power modes: the low power modes consist of the stop in struction and the wait instruction. the following paragraphs explain these modes of operation. copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 13 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 stop modes: the stop instruction places the mpu in low power consumption mode. the stop instruction disables clocking of most internal registers. timer control register bits 6 and 7 (tcr6 and tcr7) are altered to remove any pending timer interrupt requests and to disable any further timer interrupts. the ds and as output lines go ?low? and the rw_n line goes ?high?. the multiplexed address/data bus goes to the data input state. the high order address lines remain at the address of the next instruction. external interrupts are enabled by clearing the i bit in the condition code register. all othe r registers, memory, and i/o remain unaltered. only an external interrupt or reset will brin g the mpu out of the stop mode. figure 11 shows a flowchart of the stop function. tcr bit 7 <= 0 tcr bit 6 <= 1 clear i bit fetch external interrupt or reset vector stop external interrupt? reset? y n n y figure 11. stop function flowchart copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 14 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 wait mode: the wait instruction places the mpu in low power consumption mode. the wait instruction disables clocking of most internal registers. the ds and as output lines go ?low? and the rw_n line goes ?high?. the multiplexed address /data bus goes to the data input state. the high order address lines remain at the address of the next instruction. external interrupts are enabled by clearing the i bit in the condition code register. all other registers, memory, and i/o remain unaltered. only an external inte rrupt, timer interrupt, or reset will bring the mpu out of the wait mode. the timer may be enab led to allow a periodic exit from the wait mode. if an external and a timer interrupt occur at the same time, the external interrupt is serviced first. then, if the timer interrupt re quest is not cleared in the external interrupt routine, the normal timer interrupt (not the time r wait interrupt) is serviced since the mpu is no longer in the wait mode. figure 12 shows a flowchart of the wait function. oscillator active, clear i bit, timer clock active, fetch external interrupt, reset, or timer interrupt (from wait mode only) wait external interrupt? reset? y n n y timer interrupt? (tcr bit7 = 1) tcr bit 6 = 0? n y n y figure 12. wait function flowchart copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 15 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 timer: the mpu contains a single 8-bit software prog rammable counter driven by a 7-bit software programmable prescaler. the counter may be loaded under program control and decrements to zero. when the counter decrements to zero, the timer interrupt request bit in the timer control register (tcr7) is set. figure 13 s hows a block diagram of the timer. if the timer mask bit (tcr6) and the interrupt mask bit (i) of the condition code register are cleared, an interrupt request is generated. after completion of the current instruction, the current state of the machine is pushed onto the stack. the timer interrupt vector address is then fetched from locations $1ff8 and $1ff9 and the interrupt routine is executed, unless the mpu was in the wait mode in which case the interrupt vector address in locations $1ff6 and $1ff7 is fetched. power-on-reset causes the counter to set to $ff. note: 1. prescaler and counter are clocked on the falling edge of the internal clock (as) or external input. 2. counter is written to during data st robe (ds) and counts down continuously. timer (pin 37) tcr4 tcr5 tcr3 tcr2 tcr1 tcr0 2 - to - 1 mux prescaler (7 bits) counter (8 bits) interrupt control write read int clk ext clk interrupt internal_n / external internal clock enable / disable_n timer_n setting tcr3 clears prescaler to 1 software functions figure 13. timer block diagram copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 16 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 17 of 33 1-888-824-4184 ? the counter continues to count past zero, fa lling from $00 to $ff, and continues. the processor may read the counter at any time without disturbing the count by reading the timer data register (tdr). this allows a prog ram to determine the length of time since a timer interrupt has occurred. the timer interru pt request bit remains set until cleared by software. the interrupt is lost if this happens before the timer interrupt is serviced. the prescaler is a 7-bit divider used to extend the maximum length of the timer. tcr bits 0-2 are programmed to choose th e appropriate prescaler output, which is used as the count input. the prescaler is cleared by writing a ?1? into tcr bit 3, which avoids truncation errors. the processor cannot write to or read from the prescaler. timer input mode 1: when tcr4 = 0 and tcr5 = 0, the input to the timer is from an internal clock and the timer input is disabled. the internal clock mode can be used for periodic interrupt generation as well as a reference for frequency and event measurement. the internal clock is the instruction cycle clock and is coincident with address strobe (as) except during the wait instruction where it goes low. during the wait instruction the internal clock to the timer continues to run at its normal rate . timer input mode 2: when tcr4 = 1 and tcr5 = 0, the internal clock and timer input signal are anded to form the timer input. this mode can be used to measure external pulse widths. the external pulse turns on the internal clock for the duration of the pulse. the count accuracy in this mode is 1 clock. accuracy improves with longer input pulse widths. timer input mode 3: when tcr4 = 0 and tcr5 = 1, all inputs to the timer are disabled. timer input mode 4: when tcr4 = 1 and tcr5 = 1, the internal cloc k input to the timer is disabled and the timer input then comes from the external ti mer pin. the external clock can be used to count external events as well as to provide an external frequency for generating periodic interrupts.
ia6805e2 29 august 2007 microprocessor unit as of production version 00 tcr (timer control register ($0009)): an 8-bit register that controls functions such as configuring operation mode, setting ratio of the prescaler, and generating timer interrupt request signals. all bits except bit 3 are read/write. bits tcr5 - tcr0 are unaffected by reset_n. 76543210 tcr7 tcr6 tcr5 tcr4 tcr3 tcr2 tcr1 tcr0 reset: 01000000 tcr7 ? timer interrupt request used to indicate the timer interrupt when it is logic one. 1 ? set when the counter decrements to zero or under program control. 0 ? cleared on external reset, por, stop instruction, or program control . tcr6 ? timer interrupt mask used to inhibit the timer interrupt. 1 ? interrupt inhibited. set on external res et, por, stop instruction, or program control. 0 ? interrupt enabled. tcr5 ? external or internal selects input clock source. unaffected by reset. 1 ? external clock selected. 0 ? internal clock selected (as) (f osc /5). tcr4 ? timer external enable used to enable external timer pin or to enab le the internal clock. unaffected by reset. 1 ? enables external timer pin. 0 ? disables external timer pin. copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 18 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 tcr3 ? prescaler clear write only bit. writing a ?1? to this bit resets the prescaler to zero. a read of this location always indicates a zero. unaffected by reset. tcr2 , tcr1 , tcr0 ? prescaler select bits decoded to select one of eight outputs of the prescaler. unaffected by reset. trc2 trc1 trc0 reset 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 prescaler copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 19 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 instruction set description the mpu has 61 basic instructions divided into 5 types. the 5 types are register/memory, read- modify-write, branch, bit manipulation, and control. register/memory instructions: most of the following instructions use two operands. one is either the accumulator or the index register and the other is obtained from memory. the jump unconditional (jmp) and jump to subroutine (jsr) instructions have no register operand. function mnemonic load a from memory lda load x from memory ldx store a in memory sta store x in memory stx add memory to a add add memory and carry to a adc subtract memory sub subtract memory from a with borrow sbc and memory to a and or memory with a ora exclusive or memory with a eor arithmetic compare a with memory cmp arithmetic compare x with memory cpx bit test memory with a (logical compare) bit jump unconditional jmp jump to subroutine jsr read-modify-write instructions: these instructions read a memory or register lo cation, modify or test its contents and then write the modified value back to memory or the register. function mnemonic increment inc decrement dec clear clr complement com negate (2's complement) neg rotate left thru carry rol rotate right thru carry ror logical shift left lsl logical shift right lsr arithmetic shift right asr test for negative or zero tst copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 20 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 bit manipulation instructions: the mpu is capable of altering any bits resi ding in the first 256 bytes of memory. an additional feature allows the software to test an d branch on the state of any bit within these locations. for test and branch instructions the value of the bit tested is placed in the carry bit of the condition code register. function mnemonic n = 0?7 branch if bit n set brset n branch if bit n clear brclr n set bit n bset n clear bit n bclr n branch instructions: if a specific condition is met, the instruction branches. if not, no operation is performed. function mnemonic branch always bra branch never brn branch if higher bhi branch if lower or same bls branch if carry clear bcc branch if higher or same bhs branch if carry set bcs branch if lower blo branch if not equal bne branch if equal beq branch if half carry clear bhcc branch if half carry set bhcs branch if plus bpl branch if minus bmi branch if interrupt mask bit clear bmc branch if interrupt mask bit set bms branch if interrupt line low bil branch if interrupt line high bih branch to subroutine bsr copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 21 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 control instructions: these are used to control processor operation during program execution. they are register reference instructions. function mnemonic transfer a to x tax transfer x to a txa set carry bit sec clear carry bit clc set interrupt mask bit sei clear interrupt mask bit cli software interrupt swi return from subroutine rts return from interrupt rti reset stack pointer rsp no-operation nop stop stop wait wait copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 22 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 opcode map summary: the following table is an opcode map for the instructions used on the mpu. the legend following the table shows how to use the table. hi hi low low 5 5 3533659 234543 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 5 5 3 6 234543 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 553 234543 3btb2 bsc2rel 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 5 5 35336510 234543 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 5 5 353365 234543 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 553 234543 3btb2 bsc2rel 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 5 5 353365 234543 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 5 5 353365 2 45654 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 dir 3 ext 3 ix2 2 ix1 1 ix 5 5 353365 2234543 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 5 5 353365 2234543 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 5 5 353365 2234543 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 553 2234543 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 5 5 353365 2 23432 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 dir 3 ext 3 ix2 2 ix1 1 ix 5 5 343364 2656765 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 5 5 3 2 234543 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 5 5 35336522 45654 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 1 inh 2 dir 3 ext 3 ix2 2 ix1 1 ix ix1 ix2 ix branch read-modify-write control register/memory inh imm dir ext f 1111 btb bsc rel dir inh inh ix1 ix inh ror lsr 8 1000 7 0111 cmp cmp and lda cmp sbc cpx and cmp cmp cmp sbc sbc sbc sbc e 1110 f 1111 c 1100 d 1101 1010 ab 1011 9 1001 bit manipulation rts 5 0101 6 0110 0 0000 brset0 nega 2 0010 3 0011 4 0100 0 0000 bset0 bra neg negx neg neg rti sub sub sub sub sub sub brclr0 bclr0 brn 0 0000 1 0001 2 0010 brset1 bset1 bhi sbc swi 3 0011 cpx cpx cpx cpx 4 0100 5 0101 coma comx com com cpx bit bit eo r brclr1 bclr1 bls com bit lda lsra and and and and lsr brset2 bset2 bcc lsr lsrx bit brclr2 bclr2 bcs a 1010 9 1001 7 0111 6 0110 8 1000 bit bit eo r eo r rora rorx ror lda brset3 bset3 bne ror d 1101 lda lda lda sta sta sta eor c 1100 b 1011 e 1110 brclr3 bclr3 beq asr asra asrx asr asr t ax sta sta brset4 bset4 bhcc lsl lsla lslx lsl lsl clc eor eo r brclr4 bclr4 bhcs rol rola rolx rol rol sec adc adc adc adc adc adc brset5 bset5 bpl dec deca decx dec dec cli ora ora ora ora ora ora brclr5 bclr5 bmi sei add add add add add add brset6 bset6 bmc inc inca incx inc inc rsp j mp j mp j mp j mp j mp brclr6 bclr6 bms t st t sta t stx t st t st nop bsr j sr j sr j sr j sr j sr brset7 bset7 bil stop ldx ldx ldx ldx ldx ldx brclr7 bclr7 bih cl r clra clrx cl r clr wait t xa stx stx stx stx stx 6 0110 7 0111 8 1000 1 0001 2 0010 3 0011 4 0100 d 1101 e 1110 f 1111 1 0001 9 1001 a 1010 b 1011 c 1100 5 0101 abbreviations for address modes: copyright ? 2007 ia211081401-03 www.innovasic.com customer support: inh inherent a accumulator x index register imm immediate dir direct ext extended rel relative bsc bit set/clear sub 3 ix 1 f 1111 0 0000 opcode in hexadecimal opcode in binary address mode mnemonic bytes # of cycles btb bit test and branch ix indexed, no offset ix1 indexed, 1 byte offset ix2 indexed, 2 byte offset legend: page 23 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 ac/dc parameters absolute maximum ratings: supply voltage (v dd )........................?.?...????.?.???-0.3v to 6v input pin voltage (v in )?????????????...-0.3 to v dd +0.3v operating temperature????????????.??....-40 c to 85 c storage temperature range (t stg).................?........ ?.?...?- 55c to 150c esd protection (hbm)??????????????????5000v note: the specifications indicate levels where permanent damage to the device may occur. functional operation is not guarantee d under these conditions. operation at absolute maximum conditions for extended periods may adversely affect the long-term reliab ility of the device. dc characteristics (v dd =4.5 to 5.5 vdc, v ss =0, t a =t l to t h ), unless otherwise specified copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 24 of 33 1-888-824-4184 ? a a symbol parameter min max unit v dd supply voltage 4.5 5.5 v v ol -0.4v v oh 3.5 - v i ol -2m i oh --2m v ih high level input voltage 2 - v v il low level input voltage - 0.8 v i ih high level input current - 1 a i il low level input current - -1 a vt- schmitt negative threshold 1.1 - v vt+ schmitt positive threshold - 1.87 v frequency of operation f osc crystal - 5 mhz f osc external clock dc 5 mhz dc characteristics output current output voltage, i load 2 ma
ia6805e2 29 august 2007 microprocessor unit as of production version 00 copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 25 of 33 1-888-824-4184 ? control timing v ss =0v, t a =t l to t h v = 5.0v 10% dd f osc = 5mhz parameters sym min typ max unit i/o port timing ? input setup time (figure 14) t pvasl 196 - - ns input hold time (figure 14) t aslpx 0 - - ns output delay time (figure 14) t aslpv - - 0 ns interrupt setup time (figure 15) t ilasl 0.4 - - s crystal oscillator startup time (figure 16) t oxov - 5 100 ms wait recovery startup time (figure 17) t ivash - - 2 s stop recovery startup time (figure 18) t ilash - - 2 s required interrupt release (figure 15) t dslih - - 1.0 s timer pulse width (figure 17) t th , t tl 0.5 - - t cyc reset pulse width (figure 16) t rl 1.05 - - s timer period (figure 17) t tltl 1.0 - - t cyc interrupt pulse width low (figure10) t ilih 1.0 - - t cyc interrupt pulse period (figure 10) t ilil * - - t cyc oscillator cycle period (1/5 of t cyc ) (figure 3) t olol 200 - - ns osc1 pulse width high (figure 3) t oh 75 - - ns osc1 pulse width low (figure 3) t ol 75 - - ns *the minimum period of t ilil should not be less than the number of t cyc cycles it takes to execute the interrupt service routine plus 20 t cyc cycles.
ia6805e2 29 august 2007 microprocessor unit as of production version 00 bus timing v ss =0v, t a =t l to t h (figure 19) num v = 5.0v 10% dd f = 5mhz osc 1 ttl, 100pf load unit parameters min max 1 cycle time 1000 dc ns 2 pulse width, ds low 587 - ns 3 pulse width, ds high 403 - ns 4 clock transition - 4 ns 8 rw_n 9 - ns 9 non-muxed address hold 97 - ns 11 rw_n delay from ds fall - 40 ns 16 non-muxed address delay from as rise - 11 ns 17 mpu read data setup 18 - ns 18 read data hold 0 ns 19 mpu data delay, write - 0 ns 21 write data hold 204 - ns 23 muxed address delay from as rise - 26 ns 24 muxed address valid to as fall 185 - ns 25 muxed address hold 103 - ns 26 delay ds fall to as rise 190 - ns 27 pulse width, as high 203 - ns 28 delay, as fall to ds rise 185 - ns v low = 0.8v, v high = v dd ? 2.0v, v dd = 5.0v 10% t a = t l to t h , c l on port = 50pf, f osc = 5mhz address_strobe port_input port_output t pvasl t aslpx t aslpv *note *note: the address strobe of the first cycle of the next instruction. fi g ure 14. i/o port timin g copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 26 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 a s ds a dd_bus_unmux[8:12] irq_n__tcr7_n mux_add_data[0:7] rw_n 1f (ff) 1f (ff) sp pcl sp-1 pch sp-2 x sp-3 a sp-4 cc new pch new pcl 80 n0 n1 n3 n2 n4 n5 n6 n7 n8 n9 t ilasl t dslih next op code address int routine starting address int routine last address fa (irq) f8 (timer) fb (irq) f9 (timer) 1st op int routine rti op code (note) next op code note: t dslih - the interrupting device must release the irq_n line with in this time to prevent subsequent recognition of the same interrupt. figure 15. irq_n and tcr 7 _n interrupt timing figure 16. power-on-reset and reset_n timing copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 27 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 int_ext_clk tcr7 a s ds a [12:8] b[7:0] rw_n op code addr a ddress + 1 1f (ff) 1f (ff) 8f sp pcl sp-1 pch sp-2 x sp-3 a sp-4 cc f6 new pch f7 new pcl t th t tl t ivash n1 n2 n3 n4 n5 n6 n7 n0 t tltl timer counter=$00 1st op code int routine int routine starting a ddress op code a ddress a ddr + 1 wait op code figure 17. timer interrupt aft er wait instruction timing int_ext_clk tcrb7 a s ds a [12:8] b[7:0] rw_n op code addr a ddress + 1 1f (ff) 1f (ff) 8e sp pcl sp-1 pch sp-2 x sp-3 a sp-4 cc f6 new pch f7 new pcl t th t tl t ivash n1 n2 n3 n4 n5 n6 n7 n0 t tltl timer counter=$00 1st op code int routine int routine starting a ddress op code a ddress a ddr + 1 stop op code fi g ure 18. interru p t recover y from stop instruction timin g copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 28 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 1 2 3 4 4 8 8 9 9 11 16 valid addr valid addr valid write data valid read data 17 11 18 18 19 21 23 24 25 25 26 27 28 as ds rw_n a[12:8] b[7:0] write b[7:0] read 4 4 4 4 26 23 21 23 figure 19. bus timing copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 29 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 packaging information pdip packaging lead 1 identifier 1 lead count direction e1 e top ea eb c side view (width) lead count 40 (in inches) symbol min max a-. 2 0 0 a1 .015 - b .015 .020 b1 .040 .060 c .008 .012 d 1.980 2.065 e .580 .610 e1 .520 .560 e .100 typ ea .580 - eb - .686 l .100 min d l a1 a b b1 e side view (length) copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 30 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 plcc packaging lead count 44 (in millimeters) symbol min max a 4.20 4.57 a1 2.29 3.04 d1 16.51 16.66 d2 14.99 16.00 d3 12.70 bsc e1 16.51 16.66 e2 14.99 16.00 e3 12.70 bsc e1 . 2 7 b s c d 17.40 17.67 e 17.40 17.65 .10 .51 min. r 1.14 / .64 seating plane a1 e .81 / .66 a .53 / .33 d2 / e2 side view d d1 e e1 bottom view d3 e3 pin 1 identifier & zone 1.22/1.07 2 plcs top view copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 31 of 33 1-888-824-4184 ?
ia6805e2 29 august 2007 microprocessor unit as of production version 00 copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 32 of 33 1-888-824-4184 ? ordering information the ia6805e2 is available in two pack age styles, both standa rd and rohs compliant, listed in the table below. other packages and temperature grades may be available for additional cost and lead time. order number temperature grade package type IA6805E2-PDW40I-00 industrial 40 lead plastic dip, 600 mil wide ia6805e2-pdw40i-r-00 (rohs compliant) industrial 40 lead plastic dip, 600 mil wide ia6805e2-plc44i-00 industrial 44 lead plastic leaded chip carrier ia6805e2-plc44i-r-00 (rohs compliant) industrial 44 lead plastic leaded chip carrier cross reference to original manufacturers innovasic part number motorola ? part number harris? part number ia6805e2-pdw40i ? mc146805e2cp ? cdp6805e2ce ? mc146805e2p ? cdp6805e2e ia6805e2-plc44i ? mc146805e2cfn ? cdp6805e2cq ? mc146805e2fn ? cdp6805e2q
ia6805e2 29 august 2007 microprocessor unit as of production version 00 copyright ? 2007 ia211081401-03 www.innovasic.com customer support: page 33 of 33 1-888-824-4184 ? errata production version 00 1. functional differences between ia6805e 2 and harris and motorola versions: a. stop mode on ia6805e2 will not halt oscillator. recovery from stop will be quicker. b. there is a functional difference between th e ia6805e2 and the original device instruction sets regarding instructio ns for bset and bclr. analysis: the instructions, bset and bclr (bit set and bit clear), are not supposed to affect the carry flag in the condition code register but in the ia6805e2 they do. any situ ations where the bset or bclr commands are executed between a decision type instruction (branches) based on the carry flag and the instruction that was to update the carr y flag should be considered suspect. workaround: the workaround selected by the particular user is code depend ent. software will need to be revised to address the instruction set issues noted above. c. there is a functional differe nce between the ia6805e2 and the original device regarding the external timer input. analysis: the original device is edge sensitive on this input (negative edge). the ia6805e has a synchronizing register on this input. if the stimulus to this input is a negative pulse less than a clock cycle wide, it is possible that this event will be missed by the timer circuit. workaround: the workaround selected by the particular user is situation dependent. the input pulse either needs to be a minimum of 1 clock cycle wide or the pulse needs to be centered on the falling edge of the input clock. 2. observations: a. original data sheets for motorola and harris are inconsistent when describing timer input mode 2. original parts and innovasic will a nd together the timer input with the inverse of the internal clock (as). b. original harris part would unpredictably ?pre-i ncrement? timer counter when writing to timer registers. ia6805e2 will not. c. original harris part displays incorrect address on external pins during intermediate cycles (not a functional problem) of multi-cycle instructions when accessing memory at page boundaries. ia6805e2 will not. d. execution of illegal op-codes on the ia6805e2 will forc e a system reset. on the original harris and motorola parts, ex ecution of illegal op-codes would produce unpredictable results.

▲Up To Search▲

Price & Availability of IA6805E2-PDW40I-00

	To Download IA6805E2-PDW40I-00 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .