features ? 4 independent 1.0 amp switches ? 600 volts isolation between switches ? operates from a 5 volt logic and 15 volt bias ? d.c. trip level 1.3 amps ? switches are designed to withstand electro-magnetic pulse (emp) ? functions and operates from -55c to +125c in military environments ? processed and screened to mil-std-883 specifications act 2100-400 microprocessor controlled aeroflexcircuit technology? 8/27/96 block diagram smart switch 2 smart switch 3 smart switch 4 trip smart switch 1 600 volt isolation sense on/off & trip 2 8 4 switch control latch on/off and trip switch status read 8 bit a 1 a 0 cs init write preset/clear 1-4 4 4 8 s 1 + s 1 C s 2 + s 3 + s 4 + s 2 C s 3 C s 4 C data 0-7 quad solid state relay the ACT2100-400 is a microprocessor controlled, quad solid state relay that incorpora tes fully isolated switch control and built-in test. the hybrid provides 600 volts isolation between control inputs and switch outputs. internal control and status registers provide analog switch function which operates via simple i/o commands. 1 circuit technology
aeroflex circuit technology? 8/27/96 description the ACT2100-400 is a quad solid state relay. the device has been designed to provide an interface which operates as a simple computer i/o port. the switches are controlled by a single data word which the processor writes to an internal control latch. in addition to the basic switch function on/off and trip flags provide the operational status of each of the four switches. these signals are internally contained in an 8 bit status register which is accessible by an i/o read command. the switches may also be controlled asynchronously (without write strobes) by use of separate initialization pins. these may also be used for power-up control in a microprocessor based system. switch control the ACT2100-400 has four independent fully isolated switches which may be used as high side or low side drivers. the isolated design allows the user to parallel devices or place them in series as required for the specific application. control of the switch is via i/o write (address 0) or asynchronous control lines. the ACT2100-400 has an internal switch control latch which is updated via subsystem i/o write as illustrated in figure 2. once the i/o write is completed the switch is latched into the off or on state. the switch may also be controlled via individual preset and clear lines. these lines asynchronously drive the switch control latch without the need for a write strobe. the p reset/clear inputs are enabled by the initialize pin. switch status each switch in the act 2100-400 is monitored for circuit trip and on/off. this data is contained in a 8 bit status register which is accessible via an i/o read (address 0) command. the timing for the i/o read is shown in figure 1. the trip and on/off flags are provided to the system to assess the operational capability of the switch versus the status of the controlled load. the trip bit is set high when the switch has conducted between 1.1 to 3 amps of current based on the time to trip curve in figure 3. the over current dc trip point is typically 1.3 amps. 2 table 1 absolute maximum ratings supply voltage (v cc ) pin 20 -0.5 to +7.0 volts dc supply voltage (v ee ) pin 1 -.5 to +18 volts dc logic input voltage pins 2-9, 12-19 -0.5 to v cc +.5 volts dc switch point voltage pins 39-40, 29-32, 21-22 -600 to +600 volts (200 ns) 80 volts dc storage temperature range -65c to +150 c table 2 recommended operating conditions supply voltage (v cc ) pin 20 +5.0 vdc 10% supply voltage (v ee ) pin 1 +14.25 to +15.75 vdc logic input maximum voltage (high) pins 2-9, 12-19 +3.3 v logic input minimum voltage (low) pins 2-9, 12-19 +0.8 v switch point voltage pins 39-40, 29-32, 21-22 60 vdc operating temperature range -55c to +125 c
aeroflex circuit technology? 8/27/96 3 table 3 timing characteristics read cycle write cycle parameter sym min max units parameter sym min max units pulse width t pw 100 - nsec pulse width t pw 100 - nsec data delay t d - 50 nsec set-up time t s 25 - nsec hold time t h 10 - nsec hold time t h 10 - nsec aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa data switch control write / cs valid figure 1 t pw t su t h aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa status data read / cs valid figure 2 t pw t d t h timing waveforms table 4 switch data parameter sym min max units dc continous rated current i c - 1 amps dc trip current (for time to trip refer to figure 3) i ot 1.1 1.5 amps on resistance r on - 0.6 ohms output leakage current at 80 vdc i l - 40 a switch turn-on time t sd -2msec isolation v iso 600 - volts
aeroflex circuit technology? 8/27/96 table 5 bus bit definition address = 0 bit write cycle read cycle d0 s1 on/off 0 = on s1 on/off status (bit = 0)(when switch on) d1 not used s1 trip status (bit = 1)(when short circuit protection active)) d2 s2 on/off 0 = on s2 on/off status d3 not used s2 trip status d4 s3 on/off 0 = on s3 on/off status d5 not used s3 trip status d6 s4 on/off 0 = on s4 on/off status d7 not used s4 trip status address = 1 (wrap around) d0 C d7 bit = 1 or 0 whatever was written in the write cycle will be read address = 2 d0 x \1 0 = command on (signal being sent from the control side to isolation driver) d1 x not used d2 x 0 = command on (signal being sent from the control side to isolation driver) d3 x not used d4 x 0 = command on (signal being sent from the control side to isolation driver) d5 x not used d6 x 0 = command on (signal being sent from the control side to isolation driver) d7 x not used \1 x = dont care. during a write cycle (address 2) it shall be considered as if the init is enabled. 4 table 6 built-in test status (bit) switch control (closed/open) trip status on/off status conclusion 1 0 1 normal (off) 0 0 0 normal (on) 011 switch tripped off due to excessive load current note: all other trip and on/off status combinations are indicative of switch, bit or load failures
aeroflex circuit technology? 8/27/96 table 7a C pin numbers & functions ACT2100-400 pin # function pin # function 1v ee 21 s4- 2 cs 22 s4+ 3 init 23 nc 4 db0 24 nc 5 db1 25 nc 6 preset/clear 1 26 a1 7 preset/clear 2 27 a0 8 db2 28 nc 9 db3 29 s3- 10 v ee return 30 s3+ 11 v cc return 31 s2- 12 db4 32 s2+ 13 db5 33 nc 14 preset/clear 3 34 nc 15 preset/clear 4 35 nc 16 db6 36 nc 17 db7 37 nc 18 write 38 nc 19 read 39 s1- 20 v cc 40 s1+ 5 table 7b model ACT2100-400 dual in line package .016 .100 typ 40 20 top view 2.140 .010 .020 1 21 1.900 .005 .900 .010 1.140 .010 .120 .010 .120 .010 .180 .010 pin numbers are for reference only .300 max
aeroflex circuit technology? 8/27/96 circuit technology 35 south service road plainview n.y. 11803 tele: (516) 694-6700 fax: (516) 694-6715 ordering information ACT2100-400 specifications subject to change without notice. 6 3400 3200 3000 2800 2600 2400 2200 2000 1800 1600 1400 1200 1000 800 600 1101001000 time (ms ) i load (ma) no trip region trip region figure 3 nominal time to trip curve 1.3 amps
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