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spi ? -/i 2 c ? -compatible, 10-bit digital temperature sensor and 8-channel adc adt7411 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features 10-bit temperature-to-digital converter 10-bit 8-channel adc dc input bandwidth input range: 0 v to 2.25 v and 0 v to v dd temperature range: ?40c to +120c temperature sensor accuracy of 0.5c supply range: 2.7 v to 5.5 v power-down current : <10 a internal 2.25 v ref option double-buffered input logic i 2 c, spi, qspi?, microwire?, and dsp compatible 4-wire serial interface smbus packet error checking (pec) compatible 16-lead qsop applications portable battery-powered instruments pcs smart battery chargers telecommunications systems electronic test equipment domestic appliances process controls pin configuration 1 2 3 4 5 6 7 8 nc = no connect 16 15 14 13 12 11 10 9 ain5 nc cs d+/ain1 v dd gnd ain6 ain8 ain4 scl/sclk int/int d?/ain2 ain3 dout/add sda/din ain7 top view (not to scale) adt7411 02882-005 figure 1. general description the adt7411 1 combines a 10-bit temperature-to-digital converter and a 10-bit 8-channel adc in a 16-lead qsop. this includes a band gap temperature sensor and a 10-bit adc to monitor and digitize the temperature reading to a resolution of 0.25c. the adt7411 operates from a single 2.7 v to 5.5 v supply. the input voltage on the adc channels has a range of 0 v to 2.25 v and the input bandwidth is dc. the reference for the adc channels is derived internally. the adt7411 provides two serial interface options: a 4-wire serial interface compatible with spi, qspi, microwire, and dsp interface standards, and a 2-wire smbus/i 2 c interface. it features a standby mode that is controlled via the serial interface. the adt7411s wide supply voltage range, low supply current, a nd s pi-/i 2 c-compatible interface make it ideal for a variety of applications, including pcs, office equipment, and domestic appliances. 1 protected by u.s. patent number s: 6,169,442; 5,867,012; 5,764174.
adt7411 rev. b | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 pin configuration ............................................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 functional block diagram .............................................................. 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and functional descriptions .......................... 8 ter mi nolo g y ...................................................................................... 9 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 13 power-up calibration ................................................................ 13 conversion speed ....................................................................... 13 functional description .................................................................. 14 analog inputs ............................................................................. 14 functional descriptionmeasurement .................................. 15 adt7411 registers .................................................................... 19 serial interface ............................................................................ 29 outline dimensions ....................................................................... 35 ordering guide .......................................................................... 35 revision history 12/06Crev. a to rev. b updated format..................................................................universal changes to features.......................................................................... 1 changes to table 1............................................................................ 3 changes to table 2............................................................................ 7 changes to theory of operation section.................................... 13 changes to figure 20...................................................................... 14 changes to table 7.......................................................................... 20 changes to table 16 title............................................................... 22 changes to internal t high limit register (read/write) [address = 25h] section ................................................................ 25 changes to internal t low limit register (read/write) [address = 26h] section ................................................................ 26 changes to external t high /ain1 v high limit register (read/write) [address = 27h] section ........................................ 26 changes to external t low /ain1 v low limit register (read/write) [address = 28h] section ........................................ 26 changes to serial interface selection section............................. 29 changes to spi serial interface section....................................... 30 changes to read operation section ............................................ 32 changes to ordering guide .......................................................... 35 3/04Crev. 0 to rev. a f ormat updated..................................................................universal change to equation........................................................................ 17 8/03Crevision 0: initial version
adt7411 rev. b | page 3 of 36 specifications v dd = 2.7 v to 5.5 v, gnd = 0 v, unless otherwise noted. temperature ranges are ?40c to +120c. table 1. parameter 1 min typ max unit conditions/comments adc dc accuracy maximum v dd = 5 v. resolution 10 bits total unadjusted error (tue) 2 3 % of fsr v dd = 2.7 v to 5.5 v. 2 % of fsr v dd = 3.3 v (10%). offset error 0.5 % of fsr gain error 2 % of fsr adc bandwidth dc hz analog inputs input voltage range 0 2.25 v ain1 to ain8. c4 = 0 in control configuration 3. 0 v dd v ain1 to ain8. c4 = 1 in control configuration 3. dc leakage current 1 a input capacitance 5 20 pf input resistance 10 m thermal characteristics internal reference used. averaging on. internal temperature sensor accuracy @ v dd = 3.3 v 10% 1.5 c t a = 85c. 0.5 3 c t a = 0c to 85c. 2 5 c t a = ?40c to +120c. accuracy @ v dd = 5 v 5% 2 3 c t a = 0c to 85c. 3 5 c t a = ?40c to +120c. resolution 10 bits equivalent to 0.25c. long-term drift 0.25 c drift over 10 years if part is operated at 55c. external temperature sensor external transistor = 2n3906. accuracy @ v dd = 3.3 v 10% 1.5 c t a = 85c. 3 c t a = 0c to 85c. 5 c t a = ?40c to +120c. accuracy @ v dd = 5 v 5% 2 3 c t a = 0c to 85c. 3 5 c t a = ?40c to +120c. resolution 10 bits equivalent to 0.25c. output source current 180 a high level. 11 a low lev el. conversion times single-channel mode. slow adc v dd /ain 11.4 ms averaging (16 samples) on. 712 s averaging off . internal temperature 11.4 ms averaging (16 samples) on. 712 s averaging off . external temperature 24.22 ms averaging (16 samples) on. 1.51 ms averaging off . fast adc v dd /ain 712 s averaging (16 samples) on. 44.5 s averaging off . internal temperature 2.14 ms averaging (16 samples) on. 134 s averaging off . external temperature 14.25 ms averaging (16 samples) on. 890 s averaging off .
adt7411 rev. b | page 4 of 36 parameter 1 min typ max unit conditions/comments round robin update rate 2 time to complete one measurement cycle thr ough all channels. slow adc @ 25c averaging on 125.4 ms ain1 and ain2 are selected on pin 7 and pin 8. averaging off 17.1 ms ain1 and ain2 are selected on pin 7 and pin 8. averaging on 140.36 ms d+ and dC are selected on pin 7 and pin 8. averaging off 12.11 ms d+ and d? are selected on pin 7 and pin 8. fast adc @ 25c averaging on 9.26 ms ain1 and ain2 are selected on pin 7 and pin 8. averaging off 578.96 s ain1 and ain2 are selected on pin 7 and pin 8. averaging on 24.62 ms d+ and d? are selected on pin 7 and pin 8. averaging off 3.25 ms d+ and d? are selected on pin 7 and pin 8. on-chip reference 3 reference voltage 2.2662 2.28 2.2938 v temperature coefficient 80 ppm/c digital inputs 1 , 3 input current 1 a v in = 0 v to v dd . v il , input low voltage 0.8 v v ih , input high voltage 1.89 v pin capacitance 3 10 pf all digital inputs. scl, sda glitch rejection 50 ns input filtering suppresses n oise spikes of less than 50 ns. digital outputs output high voltage, v oh 2.4 v i source = i sink = 200 a. output low voltage, v ol 0.4 v i ol = 3 ma. output high current, i oh 1 ma v oh = 5 v. output capacitance, c out 50 pf int/ int output saturation voltage 0.8 v i out = 4 ma. i 2 c timing characteristics 4 , 5 serial clock period, t 1 2.5 s fast-mode i 2 c. see figure 2 . data in setup time to scl high, t 2 50 ns data out stable after scl low, t 3 0 ns see figure 2 . sda low setup time to scl low (start condition), t 4 50 ns see figure 2 . sda high hold time after scl high (stop condition), t 5 50 ns see figure 2 . sda and scl fall time, t 6 300 ns see figure 2 . sda and scl rise time, t 7 300 6 ns see figure 2 . spi timing characteristics 1 , 3 , 7 cs to sclk setup time, t 1 0 ns see figure 3 . sclk high pulse width, t 2 50 ns see figure 3 . sclk low pulse width, t 3 50 ns see figure 3 . data access time after sclk falling edge, t 4 7 35 ns see figure 3 . data setup time prior to sclk rising edge, t 5 20 ns see figure 3 . data hold time after sclk rising edge, t 6 0 ns see figure 3 . cs to sclk hold time, t 7 0 ns see figure 3 . cs to dout high impedance, t 8 40 ns see figure 3 .
adt7411 rev. b | page 5 of 36 parameter 1 min typ max unit conditions/comments power requirements v dd 2.7 5.5 v v dd settling time 50 ms v dd settles to within 10% of its final voltage level. i dd (normal mode) 8 3 ma v dd = 3.3 v, v ih = v dd and v il = gnd. 2.2 3 ma v dd = 5 v, v ih = v dd and v il = gnd. i dd (power-down mode) 10 a v dd = 3.3 v, v ih = v dd and v il = gnd. 10 a v dd = 5 v, v ih = v dd and v il = gnd. power dissipation 10 mw v dd = 3.3 v. using normal mode. 33 w v dd = 3.3 v. using shutdown mode. 1 see the terminology section. 2 round robin is the continuous sequential measurement of the following channels: v dd , internal temperature, external temper ature (ain1, ain2), ain3, ain4, ain5, ain6, ain7, and ain8. 3 guaranteed by design and characterization, not production tested. 4 the sda and scl timing is measured with the input fi lters turned on so as to meet the fast-mode i 2 c specification. switching off the input filters improves the transfer rate but has a negative effect on the emc behavior of the part. 5 guaranteed by design. not tested in production. 6 the interface is also capable of handling the i 2 c standard mode rise time specification of 1000 ns. 7 all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ), and timed from a voltage level of 1.6 v. 8 i dd specification is valid for full-scale analog input voltages. interface in active. adc active. load currents excluded. scl t 4 t 2 t 1 t 3 t 5 t 6 sda data in sda data out 02882-002 t 7 figure 2. i 2 c bus timing diagram t 1 t 2 t 3 t 5 t 6 t 4 t 7 t 8 d7 cs sclk din dout d6d5d4d3d2d1d0xx xxxxx x x x x x x x x x d7d6 d5 d4d3d2d1 d0 02882-003 figure 3. spi bus timing diagram 200a i oh 1.6v to output pin c l 50pf 200a i ol 02882-004 figure 4. load circuit for access time and bus relinquish time
adt7411 rev. b | page 6 of 36 functional block diagram 7 d+/ain1 8 d?/ain2 9 ain3 14 ain4 2 ain5 1 ain6 16 ain7 15 ain8 v dd value register 12 sda/din 5 gnd 6 v dd 13 scl/sclk 11 dout/add 4 cs address pointer register digital mux t high limit registers limit comparator t low limit registers v dd limit registers ain high limit registers ain low limit registers control config. 1 register control config. 2 register control config. 3 register interrupt mask registers status registers on-chip temperature sensor internal temperature value register external temperature value register v dd sensor adt7411 analog mux a-to-d converter int/int ain4 value register ain3 value register ain2 value register ain1 value register ain7 value register ain6 value register ain5 value register 10 spi/smbus interface ain8 value register digital mux 02882-001 figure 5.
adt7411 rev. b | page 7 of 36 absolute maximum ratings table 2. parameter rating v dd to gnd ?0.3 v to +7 v analog input voltage to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v operating temperature range ?40c to +120c storage temperature range ?65c to +150c junction temperature 16-lead qsop 150c power dissipation 1 (t jmax ? t a )/ ja thermal impedance 2 ja junction-to-ambient 105.44c/w jc junction-to-case 38.8c/w ir reflow soldering peak temperature 220c (0c/5c) time at peak temperature 10 sec to 20 sec ramp-up rate 2c/sec to 3c/sec ramp-down rate ?6c/sec ir reflow soldering (pb-free package) peak temperature 260c (+0c) time at peak temperature 20 sec to 40 sec ramp-up rate 3c/sec maximum ramp-down rate ?6c/sec maximum time 25c to peak temperature 8 minutes maximum 1 values relate to package being used on a 4-layer board. 2 junction-to-case resistance is applicable to components featuring a preferential flow direction, for ex ample, components mounted on a heat sink. junction-to-ambient resistance is more useful for air-cooled pcb- mounted components. table 3. i 2 c address selection add pin i 2 c address low 1001 000 float 1001 010 high 1001 011 stresses above those listed under absolute maximum ratings ma y cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adt7411 rev. b | page 8 of 36 pin configuration and fu nctional descriptions 1 2 3 4 5 6 7 8 nc = no connect 16 15 14 13 12 11 10 9 ain5 nc cs d+/ain1 v dd gnd ain6 ain8 ain4 scl/sclk int/int d?/ain2 ain3 dout/add sda/din ain7 top view (not to scale) adt7411 02882-005 figure 6. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 ain6 analog input. single-ended analog input ch annel . input range is 0 v to 2.25 v or 0 v to v dd . 2 ain5 analog input. single-ended analog input ch annel . input range is 0 v to 2.25 v or 0 v to v dd . 3 nc no connection. 4 cs spiactive low control input. this is the frame synchronization signal for the input data. when cs goes low, it enables the input register and data is tr ansferred in on the rising edges and o ut on the falling edges of the subsequent serial clocks. it is recommended that this pin be tied high to v dd when operating the serial interface in i 2 c mode. 5 gnd ground reference point for all circuitry on the part. analog and digital ground. 6 v dd positive supply voltage, 2.7 v to 5.5 v. the supply should be decoupled to ground. 7 d+/ain1 positive connection to external temperature sensor /a nalog input. single-ended analog input channel. input range is 0 v to 2.25 v or 0 v to 5 v. 8 d?/ain2 negative connection to external temperature sensor/a nal og input. single-ended analog input channel. input range is 0 v to 2.25 v or 0 v to 5 v. 9 ain3 analog input. single-ended analog input ch annel . input range is 0 v to 2.25 v or 0 v to v dd . 10 int/ int overlimit interrupt. the output polarity of this pin can be set to give an active low or active high interrupt when temperature, v dd , or ain limits are exceeded. default is active low. open-drain output needs a pull-up resistor. 11 dout/add doutspi serial data output. lo g ic output. data is clocked out of any register at this pin. data is clocked out on the falling edge of sclk. open-drain output needs a pull-up resistor. addi 2 c serial bus address selection pin. logic input. a low on this pin gives the address 1001 000, while leaving it floating gives the address 1001 010 and setting it high gives the address 1001 011. the i 2 c address set up by the add pin is not latched by the device until after this addr ess has been sent twice. on the eighth scl cycle of the second valid communication, the serial bus address is latched in. any subsequent changes on this pin have no effect on the i 2 c serial bus address. 12 sda/din sdai 2 c serial data input. i 2 c serial data to be loaded into the parts re gisters is provided on this input. an open- drain configuration needs a pull-up resistor. dinspi serial data input. serial data to be loaded into the parts re gisters is provided on this input. data is clocked into a register on the rising edge of sclk. an open-drain configuration needs a pull-up resistor. 13 scl/sclk serial clock input. this is the clock inp ut f or the serial port. the serial clock is used to clock data out of any register of the adt7411 and to clock data into any register that ca n be written to. an open-drain configuration needs a pull- up resistor. 14 ain4 analog input. single-ended analog input ch annel . input range is 0 v to 2.25 v or 0 v to v dd . 15 ain8 analog input. single-ended analog input ch annel . input range is 0 v to 2.25 v or 0 v to v dd . 16 ain7 analog input. single-ended analog input ch annel . input range is 0 v to 2.25 v or 0 v to v dd .
adt7411 rev. b | page 9 of 36 terminology relative accuracy relative accuracy or integral nonlinearity (inl) is a measure of th e maximum deviation, in lsbs, from a straight line passing through the endpoints of the adc transfer function. a typical inl vs. code plot can be seen in figure 10 . tot a l un a dju s te d e r ror ( t u e ) total unadjusted error is a comprehensive specification that in cludes the sum of the relative accuracy error, gain error, and offset error under a specified set of conditions. offset error this is a measure of the offset error of the adc. it can be ne gative or positive. it is expressed in mv. gain error this is a measure of the span error of the adc. it is the de viation in slope of the actual adc transfer characteristic from the ideal expressed as a percentage of the full-scale range. offset error drift this is a measure of the change in offset error with changes in t emperature. it is expressed in ppm of full-scale range/c. gain error drift this is a measure of the change in gain error with changes in t emperature. it is expressed in ppm of full-scale range/c. long-term temperature drift this is a measure of the change in temperature error with the p assage of time. it is expressed in degrees celsius. the concept of long-term stability has been used for many years to describe by what amount an ics parameter would shift during its lifetime. this is a concept that has been typically applied to both voltage references and monolithic temperature sensors. unfortunately, ics cannot be evaluated at room temperature (25c) for 10 years or so to determine this shift. as a result, manufacturers typically perform accelerated lifetime testing of ics by operating ics at elevated temperatures (between 125c and 150c) over a shorter period (typically between 500 hours and 1,000 hours). because of this operation, the lifetime of an ic is significantly accelerated due to the increase in rates of reaction within the semiconductor material. dc power supply rejection ratio (psrr) the power supply rejection ratio (psrr) is defined as the ratio o f the power in the adc output at full-scale frequency f to the power of a 100 mv sine wave applied to the v dd supply of frequency fs. psrr (db) = 10 log( pf / pfs ) where: pf is th e power at frequency f in adc output. pfs is th e power at frequency fs coupled into the v dd supply. round robin this term describes the adt7411 cycling through the available m easurement channels in sequence, taking a measurement on each channel.
adt7411 rev. b | page 10 of 36 typical performance characteristics 2.00 2.73.13.53.94.34.75.1 2.9 3.3 3.7 4.1 4.5 4.9 5.3 5.5 v cc (v) i cc (ma) 1.75 1.80 1.85 1.90 1.95 adc off 0 2882-006 figure 7. supply current vs. supply voltage at 25c ?10 ac psrr (db) ?60 ?50 ?40 ?30 ?20 0 1 10 100 frequency (khz) 100mv ripple on v cc v ref = 2.25v v dd = 3.3v temperature = 25c 02882-007 figure 8. psrr vs. supply ripple frequency 7 2.72.93.13.33.53.73.94.14.34.54.74.95.15.35.5 v cc (v) i cc (a) 0 1 2 3 4 5 6 02882-008 figure 9. power-down current vs. supply voltage at 25c 1.0 0 200 400 600 800 1000 adc code inl error (lsb) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 02882-009 figure 10. adc inl with ref = v dd (3.3 v) temperature (c) ?30 0 40 85 120 1.5 temperature error (c) ?1.0 ?0.5 0 0.5 1.0 external temperature @ 3.3v internal temperature @ 5v internal temperature @ 3.3v external temperature @ 5v 02882-010 figure 11. temperature error at 3.3 v and 5 v error (lsb) ?1 0 1 2 3 ?2 ?3 ?4 v dd = 3.3v ?40 ?20 0 temperature (c) 20 40 60 80 100 120 gain error offset error 02882-011 figure 12. adc offset error and gain error vs. temperature
adt7411 rev. b | page 11 of 36 15 temperature error (c) ?10 ?5 0 5 10 ?15 ?20 ?25 01020 pcb leakage resistance (m ? ) 30 40 50 60 70 80 90 100 v dd = 3.3v temperature = 25c d+ to gnd d+ to v cc 0 2882-012 figure 13. external temperature error vs. pcb leakage resistance 10 temperature error (c) 0 2 4 6 8 ?2 ?4 ?6 noise frequency (hz) v dd = 3.3v common-mode voltage = 100mv 1 100 200 300 400 500 600 02882-013 figure 14. external temperature error vs. com mon-mode noise frequency v dd (v) error (lsb) 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 ?3 ?2 ?1 0 1 2 3 offset error gain error 02882-014 figure 15. adc offset error and gain error vs. v dd temperature error (c) ?60 ?50 ?40 ?30 ?20 ?10 0 v dd = 3.3v 0 5 10 15 20 25 capacitance (nf) 30 35 40 45 50 0 2882-015 figure 16. external temperature error vs. capacitance between d+ and d? 70 temperature error (c) 20 30 40 50 60 10 0 ?10 1 100 200 noise frequency (mhz) 300 400 500 600 v dd = 3.3v differential-mode voltage = 100mv 0 2882-016 figure 17. external temperature error vs. differential mode noise frequency noise frequency (hz) 250mv v dd = 3.3v 1 100 200 300 400 500 600 0.6 temperature error (c) ?0.4 ?0.2 0 0.2 0.4 ?0.6 02882-017 figure 18. internal temperature error vs. power supply noise frequency
adt7411 rev. b | page 12 of 36 140 temperature (c) 40 60 80 100 120 20 0 10 20 time (s) 30 40 50 0 60 external temperature t e m p e r a t u r e o f e n v i r o n m e n t c h a n g e d h e r e internal temperature 0 2882-018 figure 19. temperature sensor response to thermal shock
adt7411 rev. b | page 13 of 36 theory of operation after the power-up calibration routine, the adt7411 goes into idle mode. in this mode, the device is not performing any measurements and is fully powered up. to begin monitoring, write to the control configuration 1 r egister (address 18h) and set bit c0 = 1. the adt7411 goes into its power-up default measurement mode, which is round robin. the device performs measurements in the following channel sequence: 1. v dd channel 2. i nternal temperature sensor channel 3. e xternal temperature sensor channel (or ain1 and ain2 if external diode is not set up) 4. ain3 5. ain4 6. ain5 7. ain6 8. ain7 9. ain8 once it finishes taking measurements on the ain8 channel, the de vice immediately loops back to start taking measurements on the v dd channel and repeats the same cycle as before. this loop continues until the monitoring is stopped by resetting bit c0 of the control configuration 1 register to 0. it is also possible to continue monitoring as well as switching to single-channel mode by writing to the control configuration 2 register (address 19h) and setting bit c4 = 1. further explanations of the single-channel and round robin measurement modes are given in the single-channel measurement and round robin m easurement sections. all measurement channels have a veraging enabled on them at power-up. averaging forces the device to take an average of 16 readings before giving a final measured result. to disable averaging and consequently decrease the conversion time by a factor of 16, set c5 = 1 in the control configuration 2 register. there are eight single-ended analog input channels on the adt7411: ai n1 to ain8. ain1 and ain2 are multiplexed with the external temperature sensors d+ and d? terminals. bits c1 and c2 of the control configuration 1 register (address 18h) are used to select between ain1/2 and the external temperature sensor. the input range on the analog input channels is dependent on whether the adc reference used is the internal v ref or v dd . to meet linearity specifications, it is recommended that the maximum v dd value is 5 v. bit c4 of the control configuration 3 register is used to select between the internal reference and v dd as the analog inputs adc reference. the dual serial interface defaults to the i 2 c protocol on power- up. to select and lock in the spi protocol, follow the selection process as described in the serial interface selection section. the i 2 c protocol cannot be locked in, while the spi protocol on selection is automatically locked in. the interface can only be switched back to i 2 c when the device is powered off and on. when using i 2 c, the cs pin should be tied to either v dd or gnd. there are a number of different operating modes on the adt7411 de vices and all of them can be controlled by the configuration registers. these features consist of enabling and disabling interrupts, polarity of the int/ int pin, enabling and disabling the averaging on the measurement channels, smbus timeout, and software reset. power-up calibration it is recommended that no communication to the part is initiated until approximately 5 ms after v dd has settled to within 10% of its final value. it is generally accepted that most systems take a maximum of 50 ms to power up. power-up time is directly related to the amount of decoupling on the voltage supply line. during the 5 ms after v dd has settled, the part is performing a calibration routine; any communication to the device interrupts this routine and can cause erroneous temperature measurements. if it is not possible to have v dd at its nominal value by the time 50 ms elapses or that communication to the device starts prior to v dd settling, then it is recommended that a measurement be taken on the v dd channel before a temperature measurement is taken. the v dd measurement is used to calibrate out any temperature measurement error due to different supply voltage values. conversion speed the internal oscillator circuit used by the adc has the capability to output two different clock frequencies. this means that the adc is capable of running at two different speeds when doing a conversion on a measurement channel. therefore, the time taken to perform a conversion on a channel can be reduced by setting c0 of the control configuration 3 register (address 1ah). this increases the adc clock speed from 1.4 hz to 22 khz. at the higher clock speed, the analog filters on the d+ and d? input pins (external temperature sensor) are switched off. this is why the power-up default setting is to have the adc working at the slow speed. the typical times for fast and slow adc speeds are given in table 1 . the adt7411 powers up with averaging on. this means every cha nnel is measured 16 times and internally averaged to reduce noise. the conversion time can also be reduced by turning the averaging off. this is done by setting bit c5 of the control configuration 2 register (address 19h) to a 1.
adt7411 rev. b | page 14 of 36 functional description analog inputs single-ended inputs the adt7411 offers eight single-ended analog input channels. the analog input range is from 0 v to 2.25 v or 0 v to v dd . to maintain the linearity specification, it is recommended that the maximum v dd value be set at 5 v. selection between the two input ranges is done by bit c4 of the control configuration 3 register (address 1ah). setting this bit to 0 sets up the analog input adc reference to be sourced from the internal voltage reference of 2.25 v. setting the bit to 1 sets up the adc reference to be sourced from v dd . the adc resolution is 10 bits and is mostly suitable for dc in put signals or very slowly varying ac signals. bit c1 and bit c2 of the control configuration 1 register (address 18h) are used to set up pin 7 and pin 8 as ain1 and ain2. figure 20 s hows the overall view of the 8-channel analog input path. m u l t i p l e x e r 10-bit adc to adc value register ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 02882-019 figure 20. octal analog input path converter operation the analog input channels use a successive approximation adc based around a capacitor dac. figure 21 and figure 22 show sim plified schematics of the adc. figure 21 shows the adc d uring acquisition phase. sw2 is closed and sw1 is in position a. the comparator is held in a balanced condition and the sampling capacitor acquires the signal on ain. control logic cap dac acquisition phase sampling capacitor comparator int v ref ref v dd a in sw1 a b sw2 ref/2 02882-021 figure 21. adc acquisition phase when the adc eventually goes into conversion phase (see figure 22 ) sw2 opens and sw1 moves to position b, causing th e comparator to become unbalanced. the control logic and the dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. figure 24 shows the adc transfer function for sin gle-ended analog inputs. control logic cap dac conversion phase sampling capacitor comparator int v ref ref v dd a in sw1 a b sw2 ref/2 0 2882-022 figure 22. adc conversion phase c1 d+ low-pass filter f c = 65khz bias diode v dd to adc v out+ v out? remote sensing transistor (2n3906) optional capacitor, up to 3nf max. can be added to improve high frequency noise rejection in noisy environments d? i n i i bias 02882-020 figure 23. signal conditioning for external diode temperature sensor
adt7411 rev. b | page 15 of 36 adc transfer function the output coding of the adt7411 analog inputs is straight binary. the designed code transitions occur midway between successive integer lsb values (that is, 1/2 lsb, 3/2 lsb). the lsb is v dd /1024 or int v ref /1024, int v ref = 2.25 v. the ideal transfer characteristic is shown in figure 24 . 111...111 111...110 111...000 011...111 +v ref ? 1lsb 0v 1/2 lsb analog input adc code 1lsb = int v ref /1024 1lsb = v dd /1024 000...010 000...001 000...000 0 2882-023 figure 24. transfer function to work out the voltage on any analog input channel, the following method is used. 1 lsb = reference (v)/1024 convert the value read back from the ain value register into de cimal. ain voltage = ain value (d) lsb size where d is t he decimal. example: internal reference used. therefore, v ref = 2.25 v. ain value = 51 2d 1 lsb size = 2.2 5 v/1024 = 2.197 10 ?3 ain voltage = 512 2.197 10 ?3 = 1.125 v analog input esd protection figure 26 shows the input structure that provides esd protec- t ion on any of the analog input pins. the diode provides the main esd protection for the analog inputs. care must be taken that the analog input signal never drops below the gnd rail by more than 200 mv. if this happens, the diode becomes forward biased and starts conducting current into the substrate. the 4 pf capacitor is the typical pin capacitance and the resistor is a lumped component made up of the on resistance of the multiplexer switch. bias diode internal sense transistor v dd to adc v out+ v out? i n i i bias 02882-024 figure 25. top level structure of int ernal temperature sensor 4pf a in 100 ? 02882-025 figure 26. equivalent analog input esd circuit ain interrupts the measured results from the ain inputs are compared with the ain v high (greater than comparison) and v low (less than or equal to comparison) limits. an interrupt occurs if the ain inputs exceed or equal the limit registers. these voltage limits are stored in on-chip registers. note that the limit registers are eight bits long while the ain conversion result is 10 bits long. if the voltage limits are not masked out, any out-of-limit comparisons generate flags that are stored in the interrupt status 1 register (address 00h) and one or more out-of-limit results will cause the int/ int output to pull either high or low, depending on the output polarity setting. it is good design practice to mask out interrupts for channels that are of no concern to the application. figure 27 shows the interrupt s tructure for the adt7411. it shows a block diagram representation of how the various measurement channels affect the int/ int pin. functional descriptionmeasurement temperature sensor the adt7411 contains an adc with special input signal conditioning to enable operation with external and on-chip diode temperature sensors. when the adt7411 is operating in single-channel mode, the adc continually processes the measurement taken on one channel only. this channel is preselected by bit c0 to bit c3 in the control configuration 2 register (address 19h). when in round robin mode, the analog input multiplexer sequentially selects the v dd input channel, on-chip temperature sensor to measure its internal temperature, the external temperature sensor, or an ain channel, and then the rest of the ain channels. these signals are digitized by the adc and the results stored in the various value registers.
adt7411 rev. b | page 16 of 36 the measured results from the temperature sensors are compared with the internal and external t high and t low limits. these temperature limits are stored in on-chip registers. if the temperature limits are not masked out, any out-of-limit comparisons generate flags that are stored in interrupt status 1 register. one or more out-of-limit results causes the int/ int output to pull either high or low, depending on the output polarity setting. theoretically, the temperature measuring circuit can measure t emperatures from C128c to +127c with a resolution of 0.25c. however, temperatures outside t a are outside the guaranteed operating temperature range of the device. temperature measurement from C128c to +127c is possible using an external sensor. temperature measurement is initiated by three methods. the f irst method is applicable when the part is in single-channel measurement mode. the temperature is measured 16 times and internally averaged to reduce noise. in single-channel mode, the part is continuously monitoring the selected channel, that is, as soon as one measurement is taken, another one is started on the same channel. the total time to measure a temperature channel with the adc operating at slow speed is typically 11.4 ms (712 s 16) for the internal temperature sensor and 24.22 ms (1.51 ms 16) for the external temperature sensor. the new temperature value is stored in two 8-bit registers and ready for reading by the i 2 c or spi interface. the user has the option of disabling the averaging by setting bit 5 in the control configuration 2 register (address 19h). the adt7411 defaults on power-up with the averaging enabled. the second method is applicable when the part is in round ro bin measurement mode. the part measures both the internal and external temperature sensors as it cycles through all possible measurement channels. the two temperature channels are measured each time the part runs a round robin sequence. in round robin mode, the part is continuously measuring all channels. temperature measurement is also initiated after every read o r write to the part when the part is in either single-channel measurement mode or round robin measurement mode. once serial communication has started, any conversion in progress is stopped and the adc is reset. conversion starts again immediately after the serial communication has finished. the temperature measurement proceeds normally as previously described. watchdog limit comparisons interrupt mask registers control configuration register 1 interrupt status register 1 (temp and ain1 to ain4) interrupt status register 2 (v dd and ain5 to ain8) status bits status bits read reset s/w reset internal temp int/int (latched output) int/int enable bit external temp v dd diode fault ain1 to ain4 ain5 to ain8 02882-026 figure 27. adt7411 interrupt structure
adt7411 rev. b | page 17 of 36 v dd monitoring the adt7411 also has the capability of monitoring its own power supply. the part measures the voltage on its v dd pin to a resolution of 10 bits. the resulting value is stored in two 8-bit registers, with the 2 lsbs stored in register address 03h and the 8 msbs stored in register address 06h. this allows the user to have the option of just doing a 1-byte read if 10-bit resolution is not important. the measured result is compared with the v high and v low limits. if the v dd interrupt is not masked out then any out-of-limit comparison generates a flag in the interrupt status 2 register, and one or more out-of-limit results causes the int/ int output to pull either high or low, depending on the output polarity setting. measuring the voltage on the v dd pin is regarded as monitoring a channel along with the internal, external, and ain channels. the user can select the v dd channel for single-channel measurement by setting bit c4 = 1 and by setting bit c0 to bit c2 to all 0s in the control configuration 2 register. when measuring the v dd value, the reference for the adc is sourced from the internal reference. table 5 shows the data fo rmat. as the maximum v dd voltage measurable is 7 v, internal scaling is performed on the v dd voltage to match the 2.25 v internal reference value. the following is an example of how the transfer function works. adc reference = 2.25 v 1 lsb = adc reference /210 = 2.25/1024 = 2.197 mv scale factor = full scale vcc / adc reference = 7/2.25 = 3.11 conversion result = vd d /( scale factor lsb size ) = 5/(3.11 2.197 mv) = 2dbh table 5. v dd data format, v ref = 2.25 v digital o utput v dd value (v) binary hex 2.5 01 0110 1110 16e 2.7 01 1000 1011 18b 3.0 01 1011 0111 1b7 3.5 10 0000 0000 200 4.0 10 0100 1001 249 4.5 10 1001 0010 292 5.0 10 1101 1011 2db 5.5 11 0010 0100 324 6.0 11 0110 1101 36d 6.5 11 1011 0110 3b6 7.0 11 1111 1111 3ff on-chip reference the adt7411 has an on-chip 1.125 v band gap reference that is gained up by a switched capacitor amplifier to give an output of 2.25 v. the amplifier is powered up for the duration of the device monitoring phase and is powered down once monitoring is disabled. this saves on current consumption. the internal reference is used as the reference for the adc. round robin measurement upon power-up, the adt7411 goes into round robin mode but monitoring is disabled. setting bit c0 of the configuration 1 register to 1 enables conversions. it sequences through all available channels, taking a measurement from each in the following order: v dd , internal temperature sensor, external temperature sensor/(ain1 and ain2), ain3, ain4, ain5, ain6, ain7, and ain8. pin 7 and pin 8 can be configured as either external temperature sensor pins or standalone analog input pins. once conversion is completed on the ain8 channel, the device loops around for another measurement cycle. this method of taking a measurement on all the channels in one cycle is called round robin. setting bit 4 of the control configuration 2 register (address 19h) disables the round robin mode and in turn sets up the single-channel mode. the single- channel mode is where only one channel, for example, the internal temperature sensor, is measured in each conversion cycle. the time taken to monitor all channels will normally not be of in terest, as the most recently measured value can be read at any time. for applications where the round robin time is important, typical times at 25c are given in table 1 . single-channel measurement setting bit c4 of the control configuration 2 register enables the single-channel mode and allows the adt7411 to focus on one channel only. a channel is selected by writing to bit c0 to bit c3 in the control configuration 2 register. for example, to select the v dd channel for monitoring, write to the control configuration 2 register and set c4 to 1 (if not done so already), then write all 0s to bit c0 to bit c3. all subsequent conversions are done on the v dd channel only. to change the channel selection to the internal temperature channel, write to the control configuration 2 register and set c0 = 1. when measuring in single-channel mode, conversions on the channel selected occur directly after each other. any communication to the adt7411 stops the conversions, but they are restarted once the read or write operation is completed.
adt7411 rev. b | page 18 of 36 temperature measurement method internal temperature measurement the adt7411 contains an on-chip, band gap temperature sensor whose output is digitized by the on-chip adc. the temperature data is stored in the internal temperature value register. as both positive and negative temperatures can be measured, the temperature data is stored in twos complement format, as shown in table 6 . the thermal characteristics of the m easurement sensor could change and therefore an offset is added to the measured value to enable the transfer function to match the thermal characteristics. this offset is added before the temperature data is stored. the offset value used is stored in the internal temperature offset register. external temperature measurement the adt7411 can measure the temperature of one external diode sensor or diode-connected transistor. the forward voltage of a diode or diode-connected transistor, o perated at a constant current, exhibits a negative temperature coefficient of about ?2 mv/c. unfortunately, the absolute value of v be varies from device to device, and individual calibration is required to null this out, so the technique is unsuitable for mass production. the technique used in the adt7411 is to measure the change in v be when the device is operated at two different currents. this is given by v be = kt / q in ( n ) where: k is b oltzmanns constant. q is t he charge on the carrier. t is t he absolute temperature in kelvin. n is t he ratio of the two currents. figure 23 shows the input signal conditioning used to measure t he output of an external temperature sensor. this figure shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors, but it could equally well be a discrete transistor. if a discrete transistor is used, the collector is not grounded and s hould be linked to the base. if a pnp transistor is used, the base is connected to the d? input and the emitter to the d+ input. if an npn transistor is used, the emitter is connected to the d? input and the base to the d+ input. a 2n3906 is recommended as the external transistor. to prevent ground noise from interfering with the me asurement, the more negative terminal of the sensor is not referenced to ground but is biased above ground by an internal diode at the d? input. as the sensor is operating in a noisy environment, c1 is provided as a noise filter. see the layout c onsiderations section for more information on c1. to me asure v be , the sensor is switched between operating currents of i, and n i. the resulting waveform is passed through a low-pass filter to remove noise, then to a chopper- stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a dc voltage proportional to v be . this voltage is measured by the adc to give a temperature output in 10-bit twos complement format. to further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. layout considerations digital boards can be electrically noisy environments, and care must be taken to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor. the following precautions should be taken: 1. p lace the adt7411 as close as possible to the remote sensing diode. provided that the worst noise sources, such as clock generators, data/address buses, and crts, are avoided, this distance can be 4 inches to 8 inches. 2. ro ute the d+ and d? tracks close together, in parallel, with grounded guard tracks on each side. provide a ground plane under the tracks if possible. 3. u se wide tracks to minimize inductance and reduce noise pickup. a 10 mil track minimum width and spacing is recommended (see figure 28 ). gnd d+ d? gnd 10 mil 10 mil 10 mil 10 mil 10 mil 10 mil 10 mil 02882-027 figure 28. arrangement of signal tracks 4. try to minimize the number of copper/solder joints, which can cause thermocouple effects. where copper/solder joints are used, make sure that they are in both the d+ and d? path and at the same temperature. thermocouple effects should not be a major problem as 1c co rresponds to about 240 v, and thermocouple voltages are about 3 v/c of temperature difference. unless there are two thermocouples with a big temperature differential between them, thermocouple voltages should be much less than 200 mv.
adt7411 rev. b | page 19 of 36 5. place 0.1 f bypass and 2200 pf input filter capacitors close to the adt7411. 6. i f the distance to the remote sensor is more than 8 inches, the use of twisted-pair cable is recommended. this works up to about 6 feet to 12 feet. 7. f or long distances (up to 100 feet) use shielded twisted- pair cable, such as belden #8451 microphone cable. connect the twisted pair to d+ and d? and the shield to gnd close to the adt7411. leave the remote end of the shield unconnected to avoid ground loops. because the measurement technique uses switched current s ources, excessive cable and/or filter capacitance can affect the measurement. when using long cables, the filter capacitor can be reduced or removed. cable resistance can also introduce errors. a series resistance of 1 in troduces about 0.5c error. temperature value format one lsb of the adc corresponds to 0.25c. the adc can theoretically measure a temperature span of 255c. the internal temperature sensor is guaranteed to a low value limit of ?40c. it is possible to measure the full temperature span using the external temperature sensor. the temperature data format is shown in table 6 . the result of the internal or external temperature measurements is s tored as twos complement format in the temperature value registers and is compared with limits programmed into the internal or external high and low registers. table 6. temperature data format (internal and external tem perature) temperature (c) digital output ?40 11 0110 0000 ?25 11 1001 1100 ?10 11 1101 1000 ?0.25 11 1111 1111 0 00 0000 0000 +0.25 00 0000 0001 +10 00 0010 1000 +25 00 0110 0100 +50 00 1100 1000 +75 01 0010 1100 +100 01 1001 0000 +105 01 1010 0100 +125 01 1111 0100 temperature conversion formula: positive temperature = adc co de /4 negative temperature = ( adc cod e 1 ? 512)/4 1 db9 is removed from the adc code. interrupts the measured results from the internal temperature sensor, external temperature sensor, v dd pin, and ain inputs are compared with their t high /v high (greater than comparison) and t low /v low (less than or equal to comparison) limits. an interrupt occurs if the measurement exceeds or equals the limit registers. these limits are stored in on-chip registers. note that the limit registers are eight bits long while the conversion results are 10 bits long. if the limits are not masked out, then any out- of-limit comparisons generate flags that are stored in the interrupt status 1 register (address 00h) and the interrupt status 2 register (address 01h). one or more out-of limit results causes the int/ int output to pull either high or low depending on the output polarity setting. it is good design practice to mask out interrupts for channels that are of no concern to the application. figure 27 shows the interrupt structure for the adt7411. i t gives a block diagram representation of how the various measurement channels affect the int/ int pin. adt7411 registers the adt7411 contains registers that are used to store the results of external and internal temperature measurements, v dd value measurements, analog input measurements, high and low temperature limits, supply voltage and analog input limits, configure multipurpose pins, and generally control the device. see table 7 for a detailed description of these registers. the register map is divided into registers of 8 bits. each register has i ts own individual address but some consist of data that is linked with other registers. these registers hold the 10-bit conversion results of measurements taken on the temperature, v dd , and ain channels. for example, the msbs of the v dd measurement are stored in register address 06h while the two lsbs are stored in register address 03h. the link involved between these types of registers is that when the lsb register is read first, the msb registers associated with that lsb register are locked out to prevent any updates. to unlock these msb registers the user has only to read any one of them, which has the effect of unlocking all previously locked out msb registers. therefore, for the example given above, if register 03h is read first, msb register 06h and register 07h would be locked out to prevent any updates to them. if register 06h is read this register, then register 07h would be subsequently unlocked. lock associated msb registers first read command lsb register output data 02882-028 figure 29. phase 1 of 10-bit read
adt7411 rev. b | page 20 of 36 unlock associated msb registers second read command msb register output data 02882-029 figure 30. phase 2 of 10-bit read if an msb register is read first, its corresponding lsb register is not locked out, thus leaving the user with the option of just reading back 8 bits (msb) of a 10-bit conversion result. reading an msb register first does not lock out other msb registers, and likewise reading an lsb register first does not lock out other lsb registers. table 7. adt7411 registers rd/wr address name power- on defau lt 00h interrupt status 1 00h 01h interrupt status 2 00h 02h reserved 03h internal temperature and v dd lsbs 00h 04h external temperature and ain1 to ain 4 lsbs 00h 05h ain5 to ain8 lsbs 00h 06h v dd msbs xxh 07h internal temperature msbs 00h 08h external temperature msbs/ain1 msbs 00h 09h ain2 msbs 00h 0ah ain3 msbs 00h 0bh ain4 msbs 00h 0ch ain5 msbs 00h 0dh ain6 msbs 00h 0eh ain7 msbs 00h 0fh ain8 msbs 00h 10h-17h reserved 18h control configuration 1 08h 19h control configuration 2 00h 1ah control configuration 3 00h 1bh-1ch reserved 1dh interrupt mask 1 00h 1eh interrupt mask 2 00h 1fh internal temperature offset 00h 20h external temperature offset 00h 21h reserved 22h reserved 23h v dd v high limit c7h 24h v dd v low limit 62h 25h internal t high limit 64h 26h internal t low limit c9h 27h external t high /ain1 v high limits ffh 28h external t low /ain1 v low limits 00h 29h-2ah reserved 2bh ain2 v high limit ffh 2ch ain2 v low limit 00h 2dh ain3 v high limit ffh rd/wr a ddress name power- on defau lt 2eh ain3 v low limit 00h 2fh ain4 v high limit ffh 30h ain4 v low limit 00h 31h ain5 v high limit ffh 32h ain5 v low limit 00h 33h ain6 v high limit ffh 34h ain6 v low limit 00h 35h ain7 v high limit ffh 36h ain7 v low limit 00h 37h ain8 v high limit ffh 38h ain8 v low limit 00h 39h-4ch reserved 4dh device id 02h 4eh manufacturers id 41h 4fh silicon revision xxh 50h-7eh reserved 00h 7f spi lock status 00h 80hn-ffh reserved 00h interrupt status 1 register (read-only) [address = 00h] this 8-bit read-only register reflects the status of some of the interrupts that can cause the int/ int pin to go active. this register is reset by a read operation provided that any out-of- limit event is corrected. it is also reset by a software reset. table 8. interrupt status 1 register d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up.
adt7411 rev. b | page 21 of 36 table 9. bit function d0 1 when internal temperature value exceeds t high limit. any internal temperature reading greater than the set limit causes an out-of-limit event. d1 1 when internal temperature value exceeds t low limit. any internal temperature reading less than or equal to the set limit causes an out-of-limit event. d2 this status bit is linked to the configuration of pin 7 and p in 8. if configured for external temperature sensor, this bit is 1 when external temperature value exceeds t high limit. the default value for this limit re gister is C1c, so any external temperature reading greater than the limit set causes an out-of-limit event. if configured for ain1 and ain2, this bit is 1 when the ain1 input voltage exceeds v high or v low limits. d3 1 when external temperature value exceeds t low limit. the default value for this limit register is 0c, so any external temperature reading less than or equal to the limit set causes an out-of-limit event. d4 1 indicates a fault (open or short) for the external temp sensor. d5 1 when ain2 voltage is greater than corresponding v high limit. 1 when ain2 voltage is less than or equal to corresponding v low limit. d6 1 when ain3 voltage is greater than corresponding v high limit. 1 when ain3 voltage is less than or equal to corresponding v low limit. d7 1 when ain4 voltage is greater than corresponding v high limit. 1 when ain4 voltage is less than or equal to corresponding v low limit. interrupt status 2 register (read-only) [address = 01h] this 8-bit read-only register reflects the status of the v dd and ain5 to ain8 interrupts that can cause the int/ int pin to go active this register is reset by a read operation provided that any out-of-limit event is corrected it is also reset by a softare reset table 10. interrupt status 2 register d7 d6 d5 d4 d3 d2 d1 d0 n/a n/a n/a 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. table 11. bit function d0 1 when ain5 voltage is greater than the corresponding v high limit. 1 when ain5 voltage is less than or equal to the corresponding v low limit. d1 1 when ain6 voltage is greater than the corresponding v high limit. 1 when ain6 voltage is less than or equal to the corresponding v low limit. d2 1 when ain7 voltage is greater than the corresponding v high limit. 1 when ain7 voltage is less than or equal to the corresponding v low limit. d3 1 when ain8 voltage is greater than the corresponding v high limit. 1 when ain8 voltage is less than or equal to the corresponding v low limit. d4 1 when v dd value is greater than the corresponding v high limit. 1 when v dd is less than or equal to the corresponding v low limit. d5:d7 reserved internal temperature value/v dd value register lsbs (read-only) [address = 03h] this internal temperature value and v dd value register is an 8-bit read-only register it stores the to lsbs of the 10-bit temperature reading from the internal temperature sensor and also the to lsbs of the 10-bit supply voltage reading table 12. internal temperature/v dd lsbs d7 d6 d5 d4 d3 d2 d1 d0 n/a n/a n/a n/a v1 lsb t1 lsb n/a n/a n/a n/a 0 1 0 1 0 1 0 1 1 default settings at power-up. table 13. bit function d0 lsb of internal temperature value d1 b1 of internal temperature value d2 lsb of v dd value d3 b1 of v dd value external temperature value and ain1 to ain4 register lsbs (read-only) [address = 04h] this is an 8-bit read-only register bit d2 to bit d7 store the to lsbs of the analog inputs ain2 to ain4 bit d0 and bit d1 are used to store the to lsbs of either the external temperature value or ain1 input value the type of input for d0 and d1 is selected by bit 1 and bit 2 of the control configuration 1 register table 14. external temperature and ain1to ain4 lsbs d7 d6 d5 d4 d3 d2 d1 d0 a4 a4 lsb a3 a3 lsb a2 a2 lsb t/a t/a lsb 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. table 15. bit function d0 lsb of external temperature value or ain1 value d1 bit 1 of external temperature value or ain1 value d2 lsb of ain2 value d3 bit 1 of ain2 value d4 lsb of ain3 value d5 bit 1 of ain3 value d6 lsb of ain4 value d7 bit 1 of ain4 value
adt7411 rev. b | page 22 of 36 ain5 to ain8 registers lsbs (read-only) [address = 05h] this is an 8-bit read-only register. bit d0 to bit d7 store the two lsbs of the analog inputs ain5 to ain8. the msbs are stored in register 0ch to register 0fh. table 16. ain5 to ain8 lsbs d7 d6 d5 d4 d3 d2 d1 d0 a8 a8 lsb a7 a7 lsb a6 a6 lsb a5 a5 lsb 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. table 17. bit function d0 lsb of ain5 value d1 bit 1 of ain5 value d2 lsb of ain6 value d3 bit 1 of ain6 value d4 lsb of ain7 value d5 bit 1 of ain7 value d6 lsb of ain8 value d7 bit 1 of ain8 value v dd value register msbs (r ead-only) [address = 06h] this 8-bit read-only register stores the supply voltage value. the eight msbs of the 10-bit value are stored in this register. table 18. v dd value msbs d7 d6 d5 d4 d3 d2 d1 d0 v9 v8 v7 v6 v5 v4 v3 v2 x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 1 loaded with v dd value after power-up. internal temperature value register msbs (read-only) [address = 07h] this 8-bit read-only register stores the internal temperature value from the internal temperature sensor in twos complement format. this register stores the eight msbs of the 10-bit value. table 19. internal temperature value msbs d7 d6 d5 d4 d3 d2 d1 d0 t9 t8 t7 t6 t5 t4 t3 t2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. external temperature value or ain1 register msbs (read-only) [address = 08h] this 8-bit read-only register stores, if selected, the external temperature value or the analog input ain1 value. selection is done in control configuration 1 register. the external temperature value is stored in twos complement format. the eight msbs of the 10-bit value are stored in this register. table 20. external temperatur e value/analo g inputs msbs d7 d6 d5 d4 d3 d2 d1 d0 t/a9 t/a8 t/a7 t/a6 t/a5 t/a4 t/a3 t/a2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. ain2 register msbs (read) [address = 09h] this 8-bit read register contains the eight msbs of the ain2 analog input voltage word. the value in this register is combined with bit d2 and bit d3 of the external temperature value and ain1 to ain4 register lsbs, address 04h, to give the full 10-bit conversion result of the analog value on the ain2 pin. table 21. ain2 msbs d7 d6 d5 d4 d3 d2 d1 d0 msb a8 a7 a6 a5 a4 a3 a2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. ain3 register msbs (read) [address = 0ah] this 8-bit read register contains the eight msbs of the ain3 analog input voltage word. the value in this register is combined with bit d4 and bit d5 of the external temperature value and ain1 to ain4 register lsbs, address 04h, to give the full 10-bit conversion result of the analog value on the ain3 pin. table 22. ain3 msbs d7 d6 d5 d4 d3 d2 d1 d0 msb a8 a7 a6 a5 a4 a3 a2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. ain4 register msbs (read) [address = 0bh] this 8-bit read register contains the eight msbs of the ain4 analog input voltage word. the value in this register is combined with bit d6 and bit d7 of the external temperature value and ain1 to ain4 register lsbs, address 04h, to give the full 10-bit conversion result of the analog value on the ain4 pin. table 23. ain4 msbs d7 d6 d5 d4 d3 d2 d1 d0 msb a8 a7 a6 a5 a4 a3 a2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. ain5 register msbs (read) [address = 0ch] this 8-bit read register contains the eight msbs of the ain5 analog input voltage word. the value in this register is combined with bit d0 and bit d1 of the ain5 to ain8 register lsbs, address 05h, to give the full 10-bit conversion result of the analog value on the ain5 pin. table 24. ain5 msbs d7 d6 d5 d4 d3 d2 d1 d0 msb a8 a7 a6 a5 a4 a3 a2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up.
adt7411 rev. b | page 23 of 36 ain6 register msbs (read) [address = 0dh] this 8-bit read register contains the eight msbs of the ain6 analog input voltage word. the value in this register is combined with bit d2 and bit d3 of the ain5 to ain8 register lsbs, address 05h, to give the full 10-bit conversion result of the analog value on the ain6 pin. table 25. ain6 msbs d7 d6 d5 d4 d3 d2 d1 d0 msb a8 a7 a6 a5 a4 a3 a2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. ain7 register msbs (read) [address = 0eh] this 8-bit read register contains the eight msbs of the ain7 analog input voltage word. the value in this register is combined with bit d4 and bit d5 of the ain5 to ain8 register lsbs, address 05h, to give the full 10-bit conversion result of the analog value on the ain7 pin. table 26. ain7 msbs d7 d6 d5 d4 d3 d2 d1 d0 msb a8 a7 a6 a5 a4 a3 a2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. ain8 register msbs (read) [address = 0fh] this 8-bit read register contains the eight msbs of the ain8 analog input voltage word. the value in this register is combined with bit d6 and bit d7 of the ain5 to ain8 register lsbs, address 05h, to give the full 10-bit conversion result of the analog value on the ain8 pin. table 27. ain8 msbs d7 d6 d5 d4 d3 d2 d1 d0 msb a8 a7 a6 a5 a4 a3 a2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. control configuration 1 register (read/write) [address = 18h] this configuration register is an 8-bit read/write register that is used to set up some of the operating modes of the adt7411. table 28. control configuration 1 d7 d6 d5 d4 d3 d2 d1 d0 pd c6 c5 c4 c3 c2 c1 c0 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 default settings at power-up. table 29. bit function c0 this bit enables/disables conversions in round robin and single -channel mode. adt7411 powers up in round robin mode, but monitoring is not initiated until this bit is set. default = 0. 0 = stop monitoring. 1 = start monitoring. c2:c1 selects between the two different analog inputs on p in 7 and pin 8. the adt7411 powers up with ain1 and ain2 selected. 00: ain1 and ain2 selected. 01: undefined. 10: external tdm selected. 11: undefined. c3 reserved. write 1 only to this bit. c4 reserved. write 0 only. c5 0: enable int/ int output. 1: disable int/int output. c6 configures int/ int output polarity. 0: active low. 1: active high. pd power-down bit. setting this bit to 1 puts the adt7411 in to standby mode. in this mode, the analog circuitry is fully powered down, but the serial interface is still operational. to power up the part again, write 0 to this bit. control configuration 2 register (read/write) [address = 19h] this configuration register is an 8-bit read/write register that is used to set up some of the operating modes of the adt7411. table 30. control configuration 2 d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up.
adt7411 rev. b | page 24 of 36 table 31. bit function c3:c0 in single-channel mode, these bits select between v dd , the internal temperature sensor, external temperature sensor/ain1, ain2 to ain8 for conversion. the default is v dd . 0000 = v dd . 0001 = internal temperature sensor. 0010 = external temperature sensor/ain1. (bit c1 and bit c2 of c ontrol configuration 1 affect this selection.) 0011 = ain2. 0100 = ain3. 0101 = ain4. 0110 = ain5. 0111 = ain6. 1000 = ain7. 1001 = ain8. 1010 to 1111 = reserved. c4 selects between single-channel and round robin c onversion cycle. default is round robin. 0 = round robin. 1 = single-channel. c5 default condition is to average every measurement on all ch annels 16 times. this bit disables this averaging. channels affected are temperature, analog inputs, and v dd . 0 = enable averaging. 1 = disable averaging. c6 smbus timeout on the serial clock puts a 25 ms limit on the pulse width of the clock , ensuring that a fault on the master scl does not lock up the sda line. 0 = disable smbus timeout. 1 = enable smbus timeout. c7 software reset. setting this bit t o a 1 causes a software reset. all registers reset to their default settings. control configuration 3 register (read/write) [address = 1ah] this configuration register is an 8-bit read/write register that is used to set up some of the operating modes of the adt7411. table 32. control configuration 3 d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 default settings at power-up. table 33. bit function c0 selects between fast and normal adc conversion speeds. 0 = adc clock at 1.4 khz. 1 = adc clock at 22.5 khz. d+ and d? analog filters ar e disabled. c1:c2 reserved. only write 0s. c3 reserved. write only 1 to this bit. c4 selects the adc reference to be either internal v ref or v dd for analog inputs. 0 = int v ref 1 = v dd c5:c7 reserved. only write 0s. interrupt mask 1 register (read/write) [address = 1dh] this mask register is an 8-bit read/write register that can be used to mask out any interrupts that can cause the int/ int pin to go active. table 34. interrupt mask 1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. table 35. bit function d0 0 = enable internal t high interrupt 1 = disable internal t high interrupt d1 0 = enable internal t low interrupt 1 = disable internal t low interrupt d2 0 = enable external t high interrupt or ain1 interrupt 1 = disable external t high interrupt or ain1 interrupt d3 0 = enable external t low interrupt 1 = disable external t low interrupt d4 0 = enable external te mpera ture fault interrupt 1 = disable external temperature fault interrupt d5 0 = enable ain2 interrupt 1 = disable ain2 interrupt d6 0 = enable ain3 interrupt 1 = disable ain3 interrupt d7 0 = enable ain4 interrupt 1 = disable ain4 interrupt
adt7411 rev. b | page 25 of 36 interrupt mask 2 register (read/write) [address = 1eh] this mask register is an 8-bit read/write register that can be used to mask out any interrupts that can cause the int/ int pin to go active. table 36. interrupt mask 2 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. table 37. bit function d0 0 = enable ain5 interrupt 1 = disable ain5 interrupt d1 0 = enable ain6 interrupt 1 = disable ain6 interrupt d2 0 = enable ain7 interrupt 1 = disable ain7 interrupt d3 0 = enable ain8 interrupt 1 = disable ain8 interrupt d4 0 = enable v dd interrupts 1 = disable v dd interrupts d5:d7 reserved. only write 0s internal temperature offset register (read/write) [address = 1fh] this register contains the offset value for the internal temperature channel. a twos complement number can be written to this register, which is then added to the measured result before it is stored or compared to limits. in this way, a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. from a software point of view, this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change. because it is an 8-bit register, the temperature resolution is 1c. table 38. internal temperature offset d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. external temperature offset register (read/write) [address = 20h] this register contains the offset value for the external temperature channel. a twos complement number can be written to this register, which is then added to the measured result before it is stored or compared to limits. in this way, a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. from a software point of view, this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change. because it is an 8-bit register, the temperature resolution is 1c. table 39. external temperature offset d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. v dd v high limit register (read/write) [address = 23h] this limit register is an 8-bit read/write register that stores the v dd upper limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured v dd value has to be greater than the value in this register. the default value is 5.46 v. table 40. v dd v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 default settings at power-up. v dd v low limit register (read/write) [address = 24h] this limit register is an 8-bit read/write register that stores the v dd lower limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured v dd value has to be less than or equal to the value in this register. the default value is 2.7 v. table 41. v dd v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 1 1 1 0 1 0 1 0 1 1 1 0 1 1 default settings at power-up. internal t high limit register (read/write) [address = 25h] this limit register is an 8-bit read/write register that stores the twos complement of the internal temperature upper limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured internal temperature value has to be greater than the value in this register. because it is an 8-bit register, the temperature resolution is 1c. the default value is 100c. positive temperature = li mit register code (d) negative temperature = limit register code (d) ? 256 table 42. internal t high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 1 1 1 0 1 0 1 1 1 0 1 0 1 1 default settings at power-up.
adt7411 rev. b | page 26 of 36 internal t low limit register (read/write) [address = 26h] this limit register is an 8-bit read/write register that stores the twos complement of the internal temperature lower limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured internal temperature value has to be more negative than or equal to the value in this register. because it is an 8-bit register, the temperature resolution is 1c. the default value is ?55c. positive temperature = li mit register code (d) negative temperature = li mit register code (d) ? 256 table 43. internal t low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 1 default settings at power-up. external t high /ain1 v high limit register (read/write) [address = 27h] if pin 7 and pin 8 are configured for the external temperature sensor, this limit register is an 8-bit read/write register that stores the twos complement of the external temperature upper limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured external temperature value has to be greater than the value in this register. because it is an 8-bit register, the temperature resolution is 1c. the default value is ?1c. positive temperature = li mit register code (d) negative temperature = li mit register code (d) ? 256 if pin 7 and pin 8 are configured for ain1 and ain2 single- ende d inputs, this limit register is an 8-bit read/write register that stores the ain1 input upper limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured ain1 value has to be greater than the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. because the power-up default settings for pin 7 and pin 8 are ain1 and ain2 single-ended inputs, the default value for this limit register is full-scale voltage. table 44. ain1 v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 default settings at power-up. external t low /ain1 v low limit register (read/write) [address = 28h] if pin 7 and pin 8 are configured for the external temperature sensor, this limit register is an 8-bit read/write register that stores the twos complement of the external temperature lower limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured external temperature value has to be more negative than or equal to the value in this register. because it is an 8-bit register, the temperature resolution is 1c. the default value is 0c. positive temperature = li mit register code (d) negative temperature = li mit register code (d) ? 256 if pin 7 and pin 8 are configured for ain1 and ain2 single- ende d inputs, this limit register is an 8-bit read/write register that stores the ain1 input lower limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured ain1 value has to be less than or equal to the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. because the power-up default settings for pin 7 and pin 8 are ain1 and ain2 single-ended inputs, the default value for this limit register is 0 v. table 45. ain1 v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. ain2 v high limit register (read/write) [address = 2bh] this limit register is an 8-bit read/write register that stores the ain2 input upper limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured ain2 value has to be greater than the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. the default value is full-scale voltage. table 46. ain2 v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 default settings at power-up.
adt7411 rev. b | page 27 of 36 ain2 v low limit register (read/write) [address = 2ch] this limit register is an 8-bit read/write register that stores the ain2 input lower limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured ain2 value has to be less than or equal to the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. the default value is 0 v. table 47. ain2 v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. ain3 v high limit register (read/write) [address = 2dh] this limit register is an 8-bit read/write register that stores the ain3 input upper limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured ain3 value has to be greater than the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. the default value is full-scale voltage. table 48. ain3 v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 default settings at power-up. ain3 v low limit register (read/write) [address = 2eh] this limit register is an 8-bit read/write register that stores the ain3 input lower limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured ain3 value has to be less than or equal to the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. the default value is 0 v. table 49. ain3 v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. ain4 v high limit register (read/write) [address = 2fh] this limit register is an 8-bit read/write register that stores the ain4 input upper limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured ain4 value has to be greater than the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. the default value is full-scale voltage. table 50. ain4 v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 default settings at power-up. ain4 v low limit register (read/write) [address = 30h] this limit register is an 8-bit read/write register that stores the ain4 input lower limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured ain4 value has to be less than or equal to the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. the default value is 0 v. table 51. ain4 v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. ain5 v high limit register (read/write) [address = 31h] this limit register is an 8-bit read/write register that stores the ain5 input upper limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured ain5 value has to be greater than the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. the default value is full-scale voltage. table 52. ain5 v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 default settings at power-up. ain5 v low limit register (read/write) [address = 32h] this limit register is an 8-bit read/write register that stores the ain5 input lower limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured ain5 value has to be less than or equal to the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. the default value is 0 v. table 53. ain5 v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up.
adt7411 rev. b | page 28 of 36 ain6 v high limit register (read/write) [address = 33h] this limit register is an 8-bit read/write register that stores the ain3 input upper limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured ain6 value has to be greater than the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. the default value is full-scale voltage. table 54. ain6 v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 default settings at power-up. ain6 v low limit register (read/write) [address = 34h] this limit register is an 8-bit read/write register that stores the ain6 input lower limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured ain6 value has to be less than or equal to the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. the default value is 0 v. table 55. ain6 v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. ain7 v high limit register (read/write) [address = 35h] this limit register is an 8-bit read/write register that stores the ain7 input upper limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured ain7 value has to be greater than the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. the default value is full-scale voltage. table 56. ain7 v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 default settings at power-up. ain7 v low limit register (read/write) [address = 36h] this limit register is an 8-bit read/write register that stores the ain7 input lower limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured ain7 value has to be less than or equal to the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. the default value is 0 v. table 57. ain7 v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. ain8 v high limit register (read/write) [address = 37h] this limit register is an 8-bit read/write register that stores the ain8 input upper limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured ain8 value has to be greater than the value in this register. as it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. the default value is full- scale voltage. table 58. ain8 v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 default settings at power-up. ain8 v low limit register (read/write) [address = 38h] this limit register is an 8-bit read/write register that stores the ain8 input lower limit that causes an interrupt and activates the int/ int output (if enabled). for this to happen, the measured ain8 value has to be less than or equal to the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. the default value is 0 v. table 59. ain8 v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 default settings at power-up. device id register (read-only) [address = 4dh] this 8-bit read-only register gives a unique identification number for this part. adt7411 = 02h. manufacturers id register (read-only) [address = 4eh] this register contains the manufacturers identification number. analog devices, inc. is 41h. silicon revision register (read-only) [address = 4fh] this register is divided into the four lsbs representing the stepping and the four msbs representing the version. the stepping contains the manufacturers code for minor revisions or steppings to the silicon. the version is the adt7411 version number, 0100b (4h).
adt7411 rev. b | page 29 of 36 spi lock status register (read-only) [address = 7fh] bit d0 (lsb) of this read-only register indicates whether the spi interface is locked or not. writing to this register causes the device to malfunction. default value is 00h. 0 = i 2 c interface. 1 = spi interface selected and locked. serial interface there are two serial interfaces that can be used on this part: i 2 c and spi. the device powers up with the serial interface in i 2 c mode, but it is not locked into this mode. to stay in i 2 c mode, it is recommended that the user tie the cs line to either v cc or gnd. it is not possible to lock the i 2 c mode, but it is possible to select and lock the spi mode. to select and lock the interface into the spi mode, a number of p ulses must be sent down the cs (pin 4) line. the following section describes how this is done. once the spi communication protocol is locked in, it cannot be unlo cked while the device is still powered up. bit d0 of the spi lock status register (address 7fh) is set to 1 when a successful spi interface lock is accomplished. to reset the serial interface, the user must power down the part and power up again. a software reset does not reset the serial interface. serial interface selection the cs line controls the selection between i 2 c and spi. figure 33 shows the selection process necessary to lock the spi in terface mode. to communicate to the adt7411 using the spi protocol, send t hree pulses down the cs line, as shown in figure 33 . on the t hird rising edge (marked as c in figure 33 ), the part selects a nd locks the spi interface. communication to the device is now limited to the spi protocol. as per most spi standards, the cs line must be low during every spi communication to the adt7411, and high at all other times. typical examples of how to connect the dual interface as i 2 c or spi are shown in figure 31 and figure 32 . adt7411 cs sda scl add v dd v dd i 2 c address = 1001 000 10k ? 10k ? 02882-030 figure 31. typical i 2 c interface connection adt7411 sclk dout cs v dd lock and select spi spi framing edge 820 ? 820 ? 820 ? din 02882-031 figure 32. typical spi interface connection the following sections describe in detail how to use the i 2 c and spi protocols associated with the adt7411. i 2 c serial interface like all i 2 c compatible devices, the adt7411 has a 7-bit serial address. the four msbs of this address for the adt7411 are set to 1001. the three lsbs are set by pin 11, add. the add pin can be configured three ways to give three different address options: low, floating, and high. setting the add pin low gives a serial bus address of 1001 000, leaving it floating gives the address 1001 010, and setting it high gives the address 1001 011. the recommended pull-up resistor value is 10 k. there is an enable/disable bit for the smbus timeout. when this i s enabled, the smbus times out after 25 ms of no activity. to enable it, set bit 6 of the control configuration 2 register. the power-up default is with the smbus timeout disabled. the adt7411 supports smbus packet error checking (pec) a nd its use is optional. it is triggered by supplying the extra clocks for the pec byte. the pec is calculated using crc-8. the frame clock sequence (fcs) conforms to crc-8 by the polynomial c ( x ) = x 8 + x 2 + x 1 +1 consult the smbus specification for more information. the serial bus protocol operates as follows: 1. the mast er initiates a data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line sda while the serial clock line scl remains high. this indicates that an address/data stream follows. all slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (msb first) plus an r/ w bit, which determines the direction of the data transfer, that is, whether data is written to or read from the slave device.
adt7411 rev. b | page 30 of 36 the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. all other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. if the r/ w bit is 0, the master writes to the slave device. if the r/ w bit is 1, the master reads from the slave device. 2. da ta is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the receiver of data. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low-to-high transition when the clock is high can be interpreted as a stop signal. 3. w hen all data bytes are read or written, stop conditions are established. in write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. in read mode, the master device pulls the data line high during the low period before the ninth clock pulse. this is known as no acknowledge. the master then takes the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition. any number of bytes of data can be transferred over the s erial bus in one operation, but it is not possible to mix read and write in one operation. this is because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. the i 2 c address set up by the add pin is not latched by the device until after this address is sent twice. on the eighth scl cycle of the second valid communication, the serial bus address is latched in. this is the scl cycle directly after the device has seen its own i 2 c serial bus address. any subsequent changes on this pin will have no effect on the i 2 c serial bus address. writing to the adt7411 depending on the register being written to, there are two different writes for the adt7411. it is not possible to do a block write to this part, that is, no i 2 c auto-increment. writing to the address pointer register for a subsequent read to read data from a particular register, the address pointer register must contain the address of that register. if it does not, the correct address must be written to the address pointer register by performing a single-byte write operation, as shown in figure 34 . the write operation consists of the serial bus addr ess followed by the address pointer byte. no data is written to any of the data registers. a read operation is then performed to read the register. writing data to a register all registers are 8-bit registers so only one byte of data can be written to each register. writing a single byte of data to one of these read/write registers consists of the serial bus address, the data register address written to the address pointer register, followed by the data byte written to the selected data register (see figure 35 ). to write to a different register, another start o r repeated start is required. if more than one byte of data is sent in one communication operation, the addressed register is repeatedly loaded until the last data byte is sent. reading data from the adt7411 reading data from the adt7411 is done in a one-byte operation. reading back the contents of a register is shown in figure 36 . the register address was previously set up by a sin gle-byte write operation to the address pointer register. to read from another register, write to the address pointer register again to set up the relevant register address. therefore, block reads are not possible, that is, no i 2 c auto-increment. spi serial interface the spi serial interface of the adt7411 consists of four wires: cs , sclk, din, and dout. the cs is used to select the device when more than one device is connected to the serial clock and data lines. the cs is also used to distinguish between any two separate serial communications (see figure 41 for a graphical exp lanation). the sclk is used to clock data in and out of the part. the din line is used to write to the registers, and the dout line is used to read data back from the registers. the recommended pull-up resistor value is between 500 and 820 . strong pull-ups are needed when serial clock speeds that are close to the maximum limit are used or when the spi interface lines are experiencing large capacitive loading. larger resistor values can be used for pull-up resistors when the serial clock speed is reduced.
adt7411 rev. b | page 31 of 36 a b cs (start high) spi locked on third rising edge c spi framing edge a b cs (start low) spi locked on third rising edge c spi framing edge 02882-032 30ns min 30ns min figure 33. serial interfaceselecting and locking spi protocol 0 11 00 r/w scl sda frame 1 serial bus address byte frame 2 address pointer register byte ack. by adt7411 ack. by adt7411 stop by master start by master a2a1a p7p6p5p4p3p2p1p0 9 19 1 02882-033 figure 34. i 2 cwriting to the address pointer register to select a register for a subsequent read operation frame 1 serial bus address byte frame 2 address pointer register byte ack. by adt7411 ack. by adt7411 ack. by adt7411 stop by master frame 3 data byte sda (continued) scl (continued) scl s d a start by master 1 0 0 1 a2 a1 a0 p7 p6 p5 p4 p3 p2 p1 p0 9 d7 d6 d5 d4 d3 d2 d1 d0 r/w 19 1 9 1 02882-034 figure 35. i 2 cwriting to the address pointer register followed by a single byte of data to the selected register 1 sda start by master stop by master no ack. by master ack. by adt7411 scl 9 0 0 1 a2 a1 a0 r/w d7 d6 d5 d4 d3 d2 d1 d0 frame 1 serial bus address byte frame 2 single data byte from adt7411 19 1 02882-035 figure 36. i 2 creading a single byte of data from a selected register
adt7411 rev. b | page 32 of 36 the part operates in a slave mode and requires an externally applied serial clock to the sclk input. the serial interface is designed to allow the part to be interfaced to systems that provide a serial clock that is synchronized to the serial data. there are two types of serial operation: a read and a write. c ommand words are used to distinguish between a read and a write operation. these command words are given in table 60 . a ddress auto-incrementing is possible in spi mode. table 60. spi command words write read 90h (1001 0000) 91h (1001 0001) write operation figure 37 shows the timing diagram for a write operation to the adt7411. da ta is clocked into the registers on the rising edge of sclk. when the cs line is high, the din and dout lines are in three-state mode. only when the cs goes from a high to a low does the part accept any data on the din line. in spi mode, the address pointer register is capable of auto-incrementing to the next register in the register map without having to load the address pointer register each time. in figure 37 , the register addr ess portion of the diagram gives the first register that is written to. subsequent data bytes are written into sequential writable registers. therefore, after each data byte is written into a register, the address pointer register auto-increments its value to the next available register. the address pointer register auto- increments from 00h to 3fh and then loops back to start over again at 00h. read operation figure 38 to figure 40 show the timing diagrams of correct read o perations. to read back from a register, first write to the address pointer register with the address to be read from. this operation is shown in figure 38 . figure 39 shows the procedure f or reading back a single byte of data. the read command is first sent to the part during the first eight clock cycles. as the read command is being sent, irrelevant data is output onto the dout line. during the following eight clock cycles the data contained in the register selected by the address pointer register is output onto the dout line. data is output onto the dout line on the falling edge of sclk. figure 40 shows the procedure w hen reading data from two sequential registers. multiple data reads are possible in spi interface mode as the addr ess pointer register is auto-incremental. the address pointer register auto-increments from 00h to 3fh and loops back to start over again at 00h when it reaches 3fh. smbus/spi int/ int the adt7411 int/ int output is an interrupt line for devices that want to trade their ability to master for an extra pin. the adt7411 is a slave-only device and uses the smbus/spi int/ int to signal the host device that it wants to talk. the smbus/spi int/ int on the adt7411 is used as an over/under limit indicator. the int/ int pin has an open-drain configuration that allows the outputs of several devices to be wired-and together when the int/ int pin is active low. use c6 of the control configuration 1 register to set the active polarity of the int/ int output. the power-up default is active low. the int/ int output can be disabled or enabled by setting c5 of the control configuration 1 register to 1 or 0, respectively. the int/ int output becomes active when either the internal temperature value, the external temperature value, v dd value, or any of the ain input values exceed the values in their corresponding t high /v high or t low /v low registers. the int/ int output goes inactive again when a conversion result is the measured value back within the trip limits and when the status register associated with the out-of-limit event is read. the two interrupt status registers show which event caused the int/ int pin to go active. the int/ int output requires an external pull-up resistor. this can be connected to a voltage different from v dd , provided the maximum voltage rating of the int/ int output pin is not exceeded. the value of the pull-up resistor depends on the application but should be large enough to avoid excessive sink currents at the int/ int output, which can heat the chip and affect the temperature reading. smbus alert response the int/ int pin behaves the same way as an smbus alert pin when the smbus/i 2 c interface is selected. it is an open-drain output and requires a pull-up to v dd . several int/ int outputs can be wire-and together so that the common line goes low if one or more of the int/ int outputs goes low. the polarity of the int/ int pin must be set for active low for a number of outputs to be wire-and together.
adt7411 rev. b | page 33 of 36 d7 d6 d5 d4 d3 d2 d1 d6 d5 d4 d3 d2 d1 d0 d0 d7 start 18 1 8 cs sclk din stop d7 d6 d5 d4 d3 d2 d1 d0 1 8 cs (continued) sclk (continued) data byte register address write command din (continued) 02882-036 figure 37. spiwriting to the address po inter register followed by a single byte of data to the selected register d7 din d6 d5 d4 d3 d2 d1 d6 d5 d4 d3 d2 d1 d0 d0 d7 sclk start write command register address 18 1 8 cs stop 02882-037 figure 38. spiwriting to the addre ss pointer register to select a regi ster for subsequent read operation d7 d6 d5 d4 d3 d2 d1 x x x x x x x d0 x cs sclk din dout start read command data byte 1 18 1 8 x xxxx x x d6 d5 d4 d3 d2 d1 d0 xd7 stop 02882-038 figure 39. spireading a single byte of data from a selected register
adt7411 rev. b | page 34 of 36 d7 d6 d5 d4 d3 d2 d1 x x x x x x x d0 x cs sclk din dout start read command 18 1 8 x xx x x x x d6 d5 d4 d3 d2 d1 d0 xd7 cs (continued) sclk (continued) din (continued) dout (continued) stop data byte 2 data byte 1 x x x x x x x x 1 8 d7 d6 d5 d4 d3 d2 d1 d0 02882-039 figure 40. spireading two bytes of data from two sequential registers cs spi read operation write operation 02882-040 figure 41. spicorrect use of cs during spi communications the int/ int output can operate as an smbalert function. slave devices on the smbus can normally not signal to the master that they want to talk, but the smbalert function allows them to do so. smbalert is used in conjunction with the smbus general call address. one or more int/ int outputs can be connected to a common smbalert line connected to the master. when the smbalert line is pulled low by one of the devices, the procedure shown in figure 42 occurs. master receives smbalert start alert response address rd ack device address master sends ara and read command device sends its address no ack stop 02882-041 figure 42. int/ int responds to smbalert ara 1. smbalert is pulled low. 2. m aster initiates a read operation and sends the alert response address (ara = 0001 100). this is a general call address that must not be used as a specific device address. 3. the de vice whose int/ int output is low responds to the alert response address and the master reads its device address. as the device address is seven bits long, an lsb of 1 is added. the address of the device is now known and it can be interrogated in the usual way. 4. i f more than one devices int/ int output is low, the one with the lowest device address has priority, in accordance with normal smbus specifications. 5. on ce the adt7411 responds to the alert response address, it resets its int/ int output, provided that the condition that caused the out-of-limit event no longer exists and the status register associated with the out-of-limit event is read. if the smbalert line remains low, the master sends the ara again. it continues to do this until all devices whose smbalert outputs were low have responded. master receives smbalert start alert response address rd ack device address master sends ara and read command device sends its address device ack ack pec no ack stop master ack master nack device sends its pec data 02882-042 figure 43. int/ int responds to smbalert ara with packet error checking
adt7411 rev. b | page 35 of 36 outline dimensions compliant to jedec standards mo-137-ab 16 9 8 1 pin 1 seating plane 0.010 0.004 0.012 0.008 0.025 bsc 0.010 0.006 0.050 0.016 8 0 coplanarity 0.004 0.065 0.049 0.069 0.053 0.197 0.193 0.189 0.158 0.154 0.150 0.244 0.236 0.228 figure 44. 16-lead shrink small outline package [qsop] (r q-16) dimensions shown in inches ordering guide model temperature r ange package descri pt ion package option ordering quantity ADT7411ARQ ?40c to +120c 16-lead qsop rq-16 n/a ADT7411ARQ-reel ?40c to +120c 16-lead qsop rq-16 2,500 ADT7411ARQ-reel7 ?40c to +120c 16-lead qsop rq-16 1,000 ADT7411ARQz 1 ?40c to +120c 16-lead qsop rq-16 n/a ADT7411ARQz-reel 1 ?40c to +120c 16-lead qsop rq-16 2,500 ADT7411ARQz-reel7 1 ?40c to +120c 16-lead qsop rq-16 1,000 eval-adt7411ebz 1 evaluation boar d 1 z = pb-free part.
adt7411 rev. b | page 36 of 36 notes purchase of licensed i 2 c components of analog devices, inc. or one of its sublicensed associated companies conveys a license for the purchaser under t he philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c02882-0-12 /06(b)

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