View MT4JSF6464HY-1G5XX_7281563.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

products and specifications discussed herein ar e subject to change by micron without notice. 512mb (x64, sr) 204-pin ddr3 sdram sodimm features pdf: 09005aef82b2f090/source: 09005aef82b2f012 micron technology, inc., reserves the right to change products or specifications without notice. jsf4c64_64x64hy.fm - rev. b 3/08 en 1 ?2007 micron technology, inc. all rights reserved. ddr3 sdram sodimm mt4jsf6464h ? 512mb for component data sheets, refer to micron?s web site: www.micron.com features ? ddr3 functionality and oper ations supported as per the component data sheet ? 204-pin, small-outline dual in-line memory module (sodimm) ? fast data transfer rates: pc3-10600, pc3-8500, or pc3-6400 ? 512mb (64 meg x 64) ?v dd = 1.5v 0.075v ?v ddspd = +3.0v to +3.6v ? nominal and dynamic on-die termination (odt) for data, strobe, and mask signals ? single rank ?on-board i 2 c temperature sensor with integrated serial presence-detect (spd) eeprom ?8 internal device banks ? fixed burst chop (bc) of 4 and burst length (bl) of 8 via the mode register set (mrs) ? selectable bc4 or bl8 on-the-fly (otf) ? gold edge contacts ?pb-free ? fly-by topology ? terminated control, command, and address bus figure 1: 204-pin sodimm (mo-268 r/c c) notes: 1. contact micron for industrial temperature module offerings. 2. not recommended for new designs. options marking ? operating temperature 1 ? commercial (0c t a +70c) none ? industrial (?40c t a +85c) i ?package ? 204-pin dimm y ? frequency/cas latency ? 1.5ns @ cl = 8 (ddr3-1333) -1g5 ? 1.5ns @ cl = 9 (ddr3-1333) -1g4 ? 1.5ns @ cl = 10 (ddr3-1333) 2 -1g3 ? 1.87ns @ cl = 7 (ddr3-1066) -1g1 ? 1.87ns @ cl = 8 (ddr3-1066) -1g0 ? 2.5ns @ cl = 5 (ddr3-800) 2 -80c ? 2.5ns @ cl = 6 (ddr3-800) 2 -80b pcb height: 30.0mm (1.18in) table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) cl = 10 cl = 9 cl = 8 cl = 7 cl = 6 cl = 5 -1g5 pc3-10600 1333 1333 1333 1066 800 800 12 12 48 -1g4 pc3-10600 1333 1333 1066 1066 800 ? 13.5 13.5 49.5 -1g3 pc3-10600 1333 ? 1066 ? 800 ? 15 15 51 -1g1 pc3-8500 ? ? 1066 1066 800 ? 13.125 13.125 50.625 -1g0 pc3-8500 ? ? 1066 ? 800 ? 15 15 52.5 -80c pc3-6400 ? ? ? ? 800 800 12.5 12.5 50 -80b pc3-6400 ? ? ? ? 800 ? 15 15 52.5
pdf: 09005aef82b2f090/source: 09005aef82b2f012 micron technology, inc., reserves the right to change products or specifications without notice. jsf4c64_64x64hy.fm - rev. b 3/08 en 2 ?2007 micron technology, inc. all rights reserved 512mb (x64, sr) 204-pin ddr3 sdram sodimm features notes: 1. the data sheet for the base devi ce can be found on micron?s web site. 2. all part numbers end with a two-place code (not shown) that desi gnates component and pcb revisions. con sult factory for current revision codes. example: mt4jsf6464hy-1g1b1 . table 2: addressing parameter 512mb refresh count 8k row address 8k (a[12:0]) device bank address 8 (ba[2:0]) device configuration 1gb (64 meg x 16) column address 1k (a[9:0]) module rank address 1 (s0#) table 3: part numbers and timing parameters ? 512mb modules base device: mt41j64m16, 1 1gb ddr3 sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt4jsf6464h(i)y-1g5__ 512mb 64 meg x 64 10.6 gb/s 1.5ns/1333 mt/s 8-8-8 mt4jsf6464h(i)y-1g4__ 512mb 64 meg x 64 10.6 gb/s 1.5ns/1333 mt/s 9-9-9 mt4jsf6464h(i)y-1g3__ 512mb 64 meg x 64 10.6 gb/s 1.5ns/1333 mt/s 10-10-10 mt4jsf6464h(i)y-1g1__ 512mb 64 meg x 64 8.5 gb/s 1.87ns/1066 mt/s 7-7-7 mt4jsf6464h(i)y-1g0__ 512mb 64 meg x 64 8.5 gb/s 1.87ns/1066 mt/s 8-8-8 mt4jsf6464h(i)y-80c__ 512mb 64 meg x 64 6.4 gb/s 2.5ns/800 mt/s 5-5-5 mt4jsf6464h(i)y-80b__ 512mb 64 meg x 64 6.4 gb/s 2.5ns/800 mt/s 6-6-6
pdf: 09005aef82b2f090/source: 09005aef82b2f012 micron technology, inc., reserves the right to change products or specifications without notice. jsf4c64_64x64hy.fm - rev. b 3/08 en 3 ?2007 micron technology, inc. all rights reserved 512mb (x64, sr) 204-pin ddr3 sdram sodimm pin assignments and descriptions pin assignments and descriptions table 4: pin assignments 204-pin ddr3 sodimm front 204-pin ddr3 sodimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1v ref dq 53 dq19 105 v dd 157 dq42 2 v ss 54 v ss 106 v dd 158 dq46 3v ss 55 v ss 107 a10 159 dq43 4 dq4 56 dq28 108 ba1 160 dq47 5 dq0 57 dq24 109 ba0 161 v ss 6 dq5 58 dq29 110 ras# 162 v ss 7 dq1 59 dq25 111 v dd 163 dq48 8 v ss 60 v ss 112 v dd 164 dq52 9v ss 61 v ss 113 we# 165 dq49 10 dqs0# 62 dq3# 114 s0# 166 dq53 11 dm0 63 dm3 115 cas# 167 v ss 12 dqs0 64 dq3 116 odt0 168 v ss 13 v ss 65 v ss 117 v dd 169 dqs6# 14 v ss 66 v ss 118 v dd 170 dm6 15 dq2 67 dq26 119 nf 171 dqs6 16 dq6 68 dq30 120 nc 172 v ss 17 dq3 69 dq27 121 nc 173 v ss 18 dq7 70 dq31 122 nc 174 dq54 19 v ss 71 v ss 123 v dd 175 dq50 20 v ss 72 v ss 124 v dd 176 dq55 21 dq8 73 cke0 125 nc 177 dq51 22 dq12 74 nc 126 v ref ca 178 v ss 23 dq9 75 v dd 127 v ss 179 v ss 24 dq13 76 v dd 128 v ss 180 dq60 25 v ss 77 nc 129 dq32 181 dq56 26 v ss 78 nc 130 dq36 182 dq61 27 dqs1# 79 ba2 131 dq33 183 dq57 28 dm1 80 nf 132 dq37 184 v ss 29 dqs1 81 v dd 133 v ss 185 v ss 30 reset# 82 v dd 134 v ss 186 dqs7# 31 v ss 83 a12 135 dqs4# 187 dm7 32 v ss 84 a11 136 dm4 188 dqs7 33 dq10 85 a9 137 dqs4 189 v ss 34 dq14 86 a7 138 v ss 190 v ss 35 dq11 87 v dd 139 v ss 191 dq58 36 dq15 88 v dd 140 dq38 192 dq62 37 v ss 89 a8 141 dq34 193 dq59 38 v ss 90 a6 142 dq39 194 dq63 39 dq16 91 a5 143 dq35 195 v ss 40 dq20 92 a4 144 v ss 196 v ss 41 dq17 93 v dd 145 v ss 197 sa0 42 dq21 94 v dd 146 dq44 198 event# 43 v ss 95 a3 147 dq40 199 v ddspd 44 v ss 96 a2 148 dq45 200 sda 45 dqs2# 97 a1 149 dq41 201 sa1 46 dm2 98 a0 150 v ss 202 scl 47 dqs2 99 v dd 151 v ss 203 v tt 48 v ss 100 v dd 152 dqs5# 204 v tt 49 v ss 101 ck0 153 dm5 50 dq22 102 ck1 154 dqs5 51 dq18 103 ck0# 155 v ss 52 dq23 104 ck1# 156 v ss
pdf: 09005aef82b2f090/source: 09005aef82b2f012 micron technology, inc., reserves the right to change products or specifications without notice. jsf4c64_64x64hy.fm - rev. b 3/08 en 4 ?2007 micron technology, inc. all rights reserved 512mb (x64, sr) 204-pin ddr3 sdram sodimm pin assignments and descriptions table 5: pin descriptions symbol type description a[12:0] input address inputs: provide the row address for acti vate commands, and the column address and auto precharge bit (a10) for re ad/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low, bank selected by ba[2:0]) or all ba nks (a10 high). if only one bank is to be precharged, the bank is selected by ba. a12 is also used for bc4/bl8 identification as ?bl on-the-fly? during cas commands. the address inputs al so provide the op-code during the mode register command set . a[12:0] address the 1gb ddr3 devices. ba[2:0] input bank address inputs: ba[2:0] define the de vice bank to which an activate, read, write, or precharge command is being appl ied. ba[2:0] define which mode register (mr0, mr1, mr2, and mr3) is loaded during the load mode command. ck0, ck0# input clock: ck and ck# are differential clock inputs. all control, command , and address input signals are sampled on the crossing of the posi tive edge of ck and the negative edge of ck#. output data (dq, dqs, and dqs#) is referenced to the crossings of ck and ck#. cke0 input clock enable: cke enables (registered high) and di sables (registered low) internal circuitry and cloc ks on the dram. dm[7:0] input input data mask: dm is an input mask signal for wr ite data. input data is masked when dm is sampled high, along with the input data, during a write access. dm is sampled on both edges of the dqs. although the dm pins are input-only, the dm loading is designed to match that of the dq and dqs pins. odt0 input on-die termination: odt enables (registered high) and disables (registered low) termination resistance intern al to the ddr3 sdram. when enabled in normal operation, odt is only applied to the following pins : dq, dqs, dqs#, and dm. the odt input will be ignored if disabled via the load mode command. ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. reset# input (lvcmos) reset: reset# is an active low cmos input refe renced to v ss .the reset# input receiver is a cmos input defined as a ra il-to-rail signal with dc high 0.8 v dd q and dc low 0.2 v dd q. reset# assertion and deassertion are asynchronous. system applications will most likely be unterminated, h eavily loaded, and have very sl ow slew rates. a slow slew rate receiver design is reco mmended along with implementing on-chip noise filtering to prevent false triggering (reset# assert ion minimum pulse width is 100ns). s0# input chip select: s# enables (registered low) and di sables (registered high) the command decoder. sa[1:0] input serial address inputs: these pins are used to configure the temperature sensor/spd eeprom address range on the i 2 c bus. scl input serial clock for temperature sensor/spd eeprom: scl is used to synchronize the communication to and from the temperature sensor/spd eeprom. dq[63:0] i/o data input/output: bidirectional data bus. dqs[7:0], dqs#[7:0] i/o data strobe: dqs and dqs# are differential data st robes. output with read data. edge- aligned with read data. input with writ e data. center-aligned with write data. sda i/o serial data: sda is a bidirectional pin used to tr ansfer addresses and data into and out of the temperature sensor/spd eeprom on the module on the i 2 c bus. event# output (open drain) temperature event: the event# pin is asserted by the temperature sensor when critical temperature thresholds have been exceeded. v dd supply power supply: 1.5v 0.075v. the component v dd and v dd q are connected to the module v dd . v ddspd supply temperature sensor/spd eeprom power supply: +3.0v to +3.6v. v ref ca supply reference voltage: control, command, and address (v dd /2). v ref dq supply reference voltage: dq, dm (v dd /2). v ss supply ground.
pdf: 09005aef82b2f090/source: 09005aef82b2f012 micron technology, inc., reserves the right to change products or specifications without notice. jsf4c64_64x64hy.fm - rev. b 3/08 en 5 ?2007 micron technology, inc. all rights reserved 512mb (x64, sr) 204-pin ddr3 sdram sodimm pin assignments and descriptions v tt supply termination voltage: used for control, command, and address (v dd /2). nc ? no connect: these pins are not connected on the module. nf ? no function: connected within th e module, but provides no functionality. table 5: pin descriptions (continued) symbol type description
pdf: 09005aef82b2f090/source: 09005aef82b2f012 micron technology, inc., reserves the right to change products or specifications without notice. jsf4c64_64x64hy.fm - rev. b 3/08 en 6 ?2007 micron technology, inc. all rights reserved 512mb (x64, sr) 204-pin ddr3 sdram sodimm functional block diagram functional block diagram figure 2: functional block diagram notes: 1. the zq ball on each ddr3 compon ent is connected to an external 240 1 percent resistor that is tied to ground. it is used for the calibration of the component?s odt and output driver. udqs# udqs udm dq dq dq dq dq dq dq dq ldqs# ldqs ldm dq dq dq dq dq dq dq dq zq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqs1# dqs1 dm1 dqs2# dqs2 dm2 dqs3# dqs3 dm3 dqs4# dqs4 dm4 dqs5# dqs5 dm5 dqs6# dqs6 dm6 dqs7# dqs7 dm7 cs# cs# cs# cs# u1 u2 u3 u4 s0# udqs# udqs udm dq dq dq dq dq dq dq dq ldqs# ldqs ldm dq dq dq dq dq dq dq dq zq ldqs# ldqs ldm dq dq dq dq dq dq dq dq udqs# udqs udm dq dq dq dq dq dq dq dq zq ldqs# ldqs ldm dq dq dq dq dq dq dq dq udqs# udqs udm dq dq dq dq dq dq dq dq zq ba[2:0] a[12:0] ras# cas# we# cke0 odt0 reset# ba[2:0]: ddr3 sdram a[12:0]: ddr3 sdram ras#: ddr3 sdram cas#: ddr3 sdram we#: ddr3 sdram cke0: ddr3 sdram odt0: ddr3 sdram reset#: ddr3 sdram ddr3 sdram x 4 ck0 ck0# ck1 ck1# v ref ca v ss ddr3 sdram ddr3 sdram v dd control, command, and address termination v ddspd temperature sensor/spd eeprom v tt ddr3 sdram ddr3 sdram v ref dq clock, control, command, and address line terminations: dqs0# dqs0 dm0 u5 v ss v ss v ss v ss a0 temperature sensor/ spd eeprom a1 a2 sa0 sa1 sda scl evt event# v ss cke0, a[12:0], ras#, cas#, we#, odt0, ba[2:0], s0# ddr3 sdram v tt ck ck# ddr3 sdram v dd
pdf: 09005aef82b2f090/source: 09005aef82b2f012 micron technology, inc., reserves the right to change products or specifications without notice. jsf4c64_64x64hy.fm - rev. b 3/08 en 7 ?2007 micron technology, inc. all rights reserved 512mb (x64, sr) 204-pin ddr3 sdram sodimm general description general description the mt4jsf6464h ddr3 sdram module is a high-speed, cmos dynamic random access 512mb memory module organized in a x64 configuration. this ddr3 sdram module uses internally configured, 8-bank 1gb ddr3 sdram devices. ddr3 sdram modules use double data rate architecture to achieve high-speed opera- tion. the double data rate architecture is essentially an 8 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr3 sdram module effectively consists of a single 8 n -bit-wide, one-clock-cycle data transfer at the internal dram core and eight corre- sponding n -bit-wide, one-half-clock-cycle da ta transfers at the i/o pins. the differential data strobe (dqs, dqs#) is transmitted externally, along with data, for use in data capture at the ddr3 sdram input receiver. dqs is center-aligned with data for writes. the read data is transmitted by the ddr3 sdram and edge-aligned to the data strobes. ddr3 sdram modules operate fr om a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. control, command, and address signals are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. fly-by topology these ddr3 modules use faster clock speed s than earlier ddr technologies, making signal quality more important than ever. for improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each dram is connected to a single trace and terminated (rather than a tree structure, wh ere the termination is off the module near the connector). inherent to fly-by topology , the timing skew between the clock and dqs signals can be easily accounted for by using the write leveling feature of ddr3. temperature sensor with serial presence-detect eeprom thermal sensor operations the temperature from the integrated thermal sensor is monitored and converted into a digital word via the i 2 c bus. system designers can use the user-programmable registers to create a custom temperature-sensing solution based on system requirements. programming and configuration details comply with jedec standard no. 21-c, page 4.7-1, ?mobile platform memory modu le thermal sensor component specifica- tion.?
pdf: 09005aef82b2f090/source: 09005aef82b2f012 micron technology, inc., reserves the right to change products or specifications without notice. jsf4c64_64x64hy.fm - rev. b 3/08 en 8 ?2007 micron technology, inc. all rights reserved 512mb (x64, sr) 204-pin ddr3 sdram sodimm general description serial presence-detect eeprom operation ddr3 sdram modules incorporate serial presence-detect. the spd data is stored in a 256-byte eeprom. the first 128 bytes are prog rammed by micron to comply with jedec specification jc-45 ?appendix x: serial presence detect (spd) for ddr3 sdram modules? (pending approval). these bytes id entify module-specific timing parameters, configuration information, and physical attributes. user-specific information can be written into the remaining 128 bytes of st orage. system read/write operations between the master (system logic) and the slave eeprom device occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (data) signals, together with sa[1:0], which provide four unique dimm/eeprom addr esses. write protect (wp) is connected to v ss , permanently disabling hardware write protect.
pdf: 09005aef82b2f090/source: 09005aef82b2f012 micron technology, inc., reserves the right to change products or specifications without notice. jsf4c64_64x64hy.fm - rev. b 3/08 en 9 ?2007 micron technology, inc. all rights reserved 512mb (x64, sr) 204-pin ddr3 sdram sodimm electrical specifications electrical specifications stresses greater than those listed in ta ble 6 may cause perman ent damage to the module. this is a stress rating only, and func tional operation of the module at these or any other conditions outside those indicated in each device?s data sheet is not implied. exposure to absolute maximum rating cond itions for extended periods may adversely affect reliability. notes: 1. v tt termination voltage in excess of the stated limit will adve rsely affect the command and address signals? voltage margin and will reduce timing margins. 2. t a and t c are simultaneous requirements. 3. for further information, refer to technical note tn-00-08: ?thermal applications,? available on micron?s web site. 4. the refresh rate is requir ed to double when 85c < t c 95c. table 6: absolute maximum ratings symbol parameter min max units v dd v dd supply voltage relative to v ss ?0.4 +1.975 v v in , v out voltage on any pin relative to v ss ?0.4 +1.975 v table 7: operating conditions symbol parameter min nom max units notes v dd v dd supply voltage 1.425 1.5 1.575 v i vtt termination reference current from v tt ?600 ? +600 ma v tt termination reference voltage (dc) ? command/address bus 0.49 v dd - 20mv 0.5 v dd 0.51 v dd + 20mv v 1 i i input leakage current; any input 0v v in v dd ; v ref input 0v v in 0.95v (all other pins not under test = 0v) address inputs, ras#, cas#, we#, s#, cke, odt, ba, ck, ck# ?8 0 +8 a dm ?2 0 +2 i oz output leakage current; 0v v out v dd q; dq and odt are disabled; odt is high dq, dqs, dqs# ?5 0 +5 a i vref v ref supply leakage current; v ref dq = v dd /2 or v ref ca = v dd /2 (all other pins not under test = 0v) ?4 0 +4 a t a module ambient operating temperature commercial 0 ? +70 c 2, 3 industrial ?40 ? +85 c t c ddr3 sdram component case operating temperature commercial 0 ? +85 c 2, 3, 4 industrial ?40 ? +95 c
pdf: 09005aef82b2f090/source: 09005aef82b2f012 micron technology, inc., reserves the right to change products or specifications without notice. jsf4c64_64x64hy.fm - rev. b 3/08 en 10 ?2007 micron technology, inc. all rights reserved 512mb (x64, sr) 204-pin ddr3 sdram sodimm electrical specifications dram operating conditions recommended ac operating conditions are given in the ddr3 component data sheets. component specifications are available on micron?s web site. module speed grades correlate with component speed grades, as shown in table 8. design considerations simulations micron memory modules are designed to op timize signal integr ity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. however, good sign al integrity starts at the system level. micron encourages designers to simulate th e signal characteristics of the system?s memory bus to ensure adequate signal integrity of the entire memory system. power operating voltages are specified at the dram , not at the edge connector of the module. designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. table 8: module and component speed grades ddr3 components may exceed th e listed module speed grades module speed grade component speed grade -1g5 -15f -1g4 -15e -1g3 -15 -1g1 -187e -1g0 -187 -80c -25e -80b -25
pdf: 09005aef82b2f090/source: 09005aef82b2f012 micron technology, inc., reserves the right to change products or specifications without notice. jsf4c64_64x64hy.fm - rev. b 3/08 en 11 ?2007 micron technology, inc. all rights reserved 512mb (x64, sr) 204-pin ddr3 sdram sodimm electrical specifications i dd specifications ta bl e 9 : dd r3 i dd specifications and conditions ? 512mb values are for the mt41j64m16 ddr3 sdram only an d are computed from values specified in the 1gb (64 meg x 16) component data sheet parameter symbol 1333 1066 800 units operating current 0: one bank activate-to-precharge i dd 0 440 400 360 ma operating current 1: one bank activate-to-read-to-precharge i dd 1 600 440 440 ma precharge power-down current: slow exit i dd 2p 40 40 40 ma precharge power-down current: fast exit i dd 2p 100 100 100 ma precharge quiet standby current i dd 2q 200 180 160 ma precharge standby current i dd 2n 220 200 180 ma active power-down current i dd 3p 140 120 100 ma active standby current i dd 3n 240 220 200 ma burst read operating current i dd 4r 1,080 920 840 ma burst write operating current i dd 4w 1,300 920 840 ma refresh current i dd 5b 960 880 800 ma self refresh temperature current: max t c = 85c i dd 6242424ma self refresh temperature current (srt-enabled): max t c = 95c i dd 6et 36 36 36 ma all banks interlea ved read current i dd 7 1,680 1,520 1,400 ma
pdf: 09005aef82b2f090/source: 09005aef82b2f012 micron technology, inc., reserves the right to change products or specifications without notice. jsf4c64_64x64hy.fm - rev. b 3/08 en 12 ?2007 micron technology, inc. all rights reserved 512mb (x64, sr) 204-pin ddr3 sdram sodimm temperature sensor with serial presence-detect eeprom temperature sensor with se rial presence-detect eeprom the temperature sensor continuously monitors the module?s temperature and can be read back at any time over the i 2 c bus shared with the spd eeprom. event# pin the temperature sensor also adds the event# pin (open drain). not used by the spd eeprom, event# is a temperature sensor output used to flag critical events that can be set up in the sensor?s configuration register. event# has three defined modes of operation: interrupt mode, compare mode, and critical temperature mode. the open-drain output of event# under the three separate operating modes is illustrated in figure 3 on page 13. event thresholds are programmed in the 0x01 register using a hysteresis. the alarm window provides a comparison window, with upper and lower limits set in the alarm upper boundary register and the alarm lower boundary register, respectively. when the alarm window is enabled, event# will trigger whenever the temperature is outside the min or max values set by the user. the interrupt mode enables software to re set event# after a critical temperature threshold has been detected. threshold points are set in the configuration register by the user. this mode triggers the critical temper ature limit and both the min and max of the temperature window. table 10: temperature sensor with serial pr esence-detect eeprom operating conditions parameter/condition symbol min max units supply voltage v ddspd +3.0 +3.6 v supply current: v dd = 3.3v i dd ?+2.0ma input high voltage: logic 1; scl, sda v ih +1.45 v ddspd + 1 v input low voltage: logic 0; scl, sda v il ?+0.55v output low voltage: i out = 2.1ma v ol ?+0.4v input current i in ?5.0 +5.0 a temperature sensing range ? ?40 +125 c temperature sensor accuracy (initial release) ? ?2.0 +2.0 c temperature sensor accuracy ? ?1.0 +1.0 c table 11: sensor and eeprom serial interface timing parameter/condition symbol min max units time bus must be free before a new transition can start t buf 4.7 ? s sda fall time t f20300ns sda rise time t r ? 1,000 ns data hold time t hd:dat 200 900 ns start condition hold time t h:sta 4.0 ? s clock high period t high 4.0 50 s clock low period t low 4.7 ? s scl clock frequency f scl 10 100 khz data setup time t su:dat 250 ? ns start condition setup time t su:sta 4.7 ? s stop condition setup time t su:sto 4.0 ? s
pdf: 09005aef82b2f090/source: 09005aef82b2f012 micron technology, inc., reserves the right to change products or specifications without notice. jsf4c64_64x64hy.fm - rev. b 3/08 en 13 ?2007 micron technology, inc. all rights reserved 512mb (x64, sr) 204-pin ddr3 sdram sodimm temperature sensor with serial presence-detect eeprom the compare mode is similar to the interrupt mode, except event# cannot be reset by the user and only returns to the logic high state when the temperature falls below the programmed thresholds. critical temperature mode triggers event# only when the temperature has exceeded the programmed critical trip point. when the critical trip point has been reached, the temperature sensor goes into comparator mode, and the critical event# cannot be cleared through software. sm bus slave subaddress decoding the temperature sensor?s physical address differs from the spd eeprom?s physical address: 0011 for a0, a1, a2, and rw# in binary where a2, a1, and a0 are the three slave subaddress pins and the rw# bit is the read/write flag. if the slave base address is fixed for the temperature sensor/spd eeprom, then the pins set the subaddress bits of the slave address, enabling the devices to be located anywhere within the eight slave address locations. for example, they could be set from 30h to 3eh. figure 3: event# pin functionality time temperature c riti c al alarm win d ow (max) alarm win d ow (min) event# interrupt mo d e event# c omparator mo d e event# c riti c al temperature only mo d e c lears event hysteresis affects these trip points
pdf: 09005aef82b2f090/source: 09005aef82b2f012 micron technology, inc., reserves the right to change products or specifications without notice. jsf4c64_64x64hy.fm - rev. b 3/08 en 14 ?2007 micron technology, inc. all rights reserved 512mb (x64, sr) 204-pin ddr3 sdram sodimm temperature sensor with serial presence-detect eeprom pointer register the pointer register selects which of the 16-bit registers is being accessed in subsequent read and write operations. this register is a write-only register. capability register the capability register indicates the features and functionality supported by the temper- ature sensor. this register is a read-only register. table 12: temperature sensor registers name address power-on default pointer register not applicable undefined capability register 0x00 0x0001 configuration register 0x01 0x0000 alarm temperature upper boundary register 0x02 0x0000 alarm temperature lower bo undary register 0x03 0x0000 critical temperature register 0x04 0x0000 temperature register 0x05 undefined table 13: pointer register bits 0?7 bit 7 6 5 4 3 2 1 0 0000register select register select register select register select table 14: pointer register bits 0?2 descriptions bit register 2 1 0 0 0 0 capability register 0 0 1 configuration register 0 1 0 alarm temperature upper boundary register 0 1 1 alarm temperature lower boundary register 1 0 0 critical temperature register 1 0 1 temperature register table 15: capability register (address: 0x00) bit 15 14 13 12 11 10 9 8 rfu rfu rfu rfu rfu rfu rfu rfu bit 7 6 5 4 3 2 1 0 rfu rfu rfu temperature resolution wider range precision has alarm and critical temperature
pdf: 09005aef82b2f090/source: 09005aef82b2f012 micron technology, inc., reserves the right to change products or specifications without notice. jsf4c64_64x64hy.fm - rev. b 3/08 en 15 ?2007 micron technology, inc. all rights reserved 512mb (x64, sr) 204-pin ddr3 sdram sodimm temperature sensor with serial presence-detect eeprom configuration register table 16: capability register bit descriptions bit description 0 basic capability 1: has alarm and critical trip point capabilities 1accuracy 0: 2c over the active range and 3c over the monitor range 1: 1c over the active range and 2c over the monitor range 2wider range 0: temperatures lower than 0c are clamped to a binary value of 0 1: temperatures below 0c can be read 4:3 temperature resolution 00: 0.5c lsb 01: 0.25c lsb 10: 0.125c lsb 11: 0.0625c lsb 15:5 0: must be set to zero table 17: configuration register (address: 0x01) bit 15 14 13 12 11 10 9 8 rfu rfu rfu rfu rfu hysteresis shutdown mode bit 7 6 5 4 3 2 1 0 critical lock bit alarm lock bit clear event event output status event output control critical event only event polarity event mode table 18: configuration register bit descriptions bit description notes 0 event mode 0: comparator mode 1: interrupt mode event mode cannot be changed if either of the lock bits is set. 1 event# polarity 0: active low 1: active high event# polarity cannot be chan ged if either of the lock bits is set. 2 critical event only 0: event# trips on alarm or critical temperature event 1: event# trips only if critical temperature is reached 3 event output control 0: event output disabled 1: event output enabled 4event status 0: event# has not been asserted by this device 1: event# is being asserted due to an alarm window or critical temper ature condition this is a read-only field in the register. the event causing the event can be determined from the read temperature register.
pdf: 09005aef82b2f090/source: 09005aef82b2f012 micron technology, inc., reserves the right to change products or specifications without notice. jsf4c64_64x64hy.fm - rev. b 3/08 en 16 ?2007 micron technology, inc. all rights reserved 512mb (x64, sr) 204-pin ddr3 sdram sodimm temperature sensor with serial presence-detect eeprom figure 4: hysteresis notes: 1. t h is the value set in the alarm temp erature upper boundary trip register. 2. t l is the value set in the alarm temp erature lower boun dary trip register. 3. hyst is the value set in the hysteresis bits of the configuration register. 5 clear event 0: no effect 1: clears the event when the temperature sensor is in the interrupt mode 6 alarm window lock bit 0: alarm trips are not locked and can be changed 1: alarm trips are locked and cannot be changed 7 critical trip lock bit 0: critical trip is not locked and can be changed 1: critical trip is locked and cannot be changed 8 shutdown mode 0: enabled 1: shutdown the shutdown mode is a power-saving mode that disables the temperature sensor. 10:9 hysteresis enable 00: disable 01: enable at 1.5c 10: enable at 3c 11: enable at 6c when enabled, a hysteresis is applied to temperature movement around the trip points. as an example, if the hysteresis register is enabled to a delta of 6c, the preset trip points will to ggle when the temperature reaches the programmed valu e. these values will reset when the temperature drop s below the trip points minus the set hysteresis level. in this case, this would be critical temperature minus 6c. the hysteresis is applied both to the above alarm window and to the below alarm window bits found in the read-only temperature register. event# is also affected by this register. table 18: configuration register bit descriptions (continued) bit description notes t h 1 t l 2 t h - hyst 3 t l - hyst below win d ow b it a b ove win d ow b it
pdf: 09005aef82b2f090/source: 09005aef82b2f012 micron technology, inc., reserves the right to change products or specifications without notice. jsf4c64_64x64hy.fm - rev. b 3/08 en 17 ?2007 micron technology, inc. all rights reserved 512mb (x64, sr) 204-pin ddr3 sdram sodimm temperature sensor with serial presence-detect eeprom temperature format the temperature trip point registers and temperature readout register use a ?2?s complement? format to enable negative numbers. the least significant bit (lsb) is equal to 0.0625c or 0.25c depending on which register is referenced. as an example, assuming an lsb of 0.0625c: ? a value of 0x018c would equal 24.75c ? a value of 0x06c0 would equal 108c ? a value of 0x1e74 would equal ?24.75c temperature trip point registers the upper and lower temperature boundary registers are used to set the maximum and minimum values of the alarm window. lsb for these registers is 0.25c. all rfu bits in the register will always report zero. critical temperature register the critical temperature register is used to set the maximum temperature above the alarm window. the lsb for this register is 0.25c. all rfu bits in the register will always report zero. table 19: hysteresis condition below alarm window bit above alarm window bit temperature gradient critical temperature temperature gradient critical temperature sets falling t l - hyst rising t h clears rising t l falling t h - hyst table 20: alarm temperature lower boundary register (address: 0x02) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000msb lsb rfu rfu alarm window upper boundary temperature table 21: alarm temperature lower boundary register (address: 0x03) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000msb lsb rfu rfu alarm window lower boundary temperature table 22: critical temperature register (address: 0x04) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000msb lsb rfu rfu critical temperature trip point
pdf: 09005aef82b2f090/source: 09005aef82b2f012 micron technology, inc., reserves the right to change products or specifications without notice. jsf4c64_64x64hy.fm - rev. b 3/08 en 18 ?2007 micron technology, inc. all rights reserved 512mb (x64, sr) 204-pin ddr3 sdram sodimm temperature sensor with serial presence-detect eeprom temperature register the temperature register is a read-only regi ster that provides the current temperature detected by the temperature sensor. the lsb fo r this register is 0.0625c with a resolu- tion of 0.0625c. the most significant bit (m sb) is 128c in the readout section of this register. the upper three bits of the register are used to monitor the trip points that are set in the previous three registers. serial presence-detect data for the latest serial presence-detec t data, refer to micron?s spd page: www.micron.com/spd . table 23: temperature register (address: 0x05) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 above critical trip above alarm window below alarm window msb lsb temperature table 24: temperature register bit descriptions bit description 13 below alarm window 0: temperature is equal to or above the lower boundary 1: temperature is below alarm window 14 above alarm window 0: temperature is equal to or below the upper boundary 1: temperature is above alarm window 15 above critical trip point 0: temperature is below critical trip point 1: temperature is above critical trip point
8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of thei r respec- tive owners. this data sheet contains minimum and maximum limits specified ov er the power supply and temperat ure range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometime s occur. 512mb (x64, sr) 204-pin ddr3 sdram sodimm module dimensions pdf: 09005aef82b2f090/source: 09005aef82b2f012 micron technology, inc., reserves the right to change products or specifications without notice. jsf4c64_64x64hy.fm - rev. b 3/08 en 19 ?2007 micron technology, inc. all rights reserved. module dimensions figure 5: 204-pin ddr3 sodimm notes: 1. all dimensions are in millimeters (i nches); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference only. 2.45 (0.096) max pin 1 67.75 (2.667) 67.45 (2.656) 20.0 (0.787) typ 1.8 (0.071) (2x) 0.60 (0.024) typ 0.45 (0.018) typ 2.0 (0.079) r (2x) pin 203 pin 204 pin 2 front view 2.0 (0.079) typ 6.0 (0.236) typ 63.60 (2.504) typ 2.55 (0.10) typ 1.0 (0.039) typ 30.15 (1.187) 29.85 (1.175) back view 1.1 (0.043) 0.9 (0.035) 39.0 (1.535) typ 21.0 (0.827) typ 3.0 (0.12) typ 4.0 (0.157) typ 24.8 (0.976) typ u1 u2 u3 u4 u5 no components this side of module

▲Up To Search▲

Price & Availability of MT4JSF6464HY-1G5XX

	To Download MT4JSF6464HY-1G5XX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .