View ELECTRONICTHEATRECONTROLSINC-MTV016_7310781.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

myson technology mtv016 enhanced on-screen-display controller this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. mtv016 revision 2.0 01/01 /199 9 1/11 features horizontal sync input up to 100 khz. on-chip pll circuitry up to a 90 mhz pixel rate for multi-sync operation. programmable horizontal resolutions u p to 1524 dots per display row. 538-byte display registers to control full screen display. full screen display consists of 10 (rows) by 24 ( columns) characters. 12 x 18 dot matrix per character. 128 built-in characters and graphic symbols, and character by character color selection. maximum of 8 colors selectable per display row. double character height and/or width control. programmable positioning for display screen center. bordering and shadowing effect for display. programmable vertical character height (18 to 71 lines) for multi-sync operation. 4 programmable background windows with multi-level windowing effect. software clear function for display frame buffer. hsync and vsync input polarity selectable. auto detection for input edge distortion between hsync and vsync inputs. half tone and fast blankin g output. software force blank function for display frame. compatible with both spi bus and i 2 c interface through pin selection. 16-pin pdip package. general description mtv016 is designed for use in monitor applications to display the built-in characters or symbols onto a monitor screen. the display operation occurs by transferring data and control information in the micro- controller to ram through a serial data interface. it can execute a full screen display automatically and specific functions such as character bordering, shadowing, double height and width, font by font color control, frame positioning, frame size control by character height and horizontal display resolution, and windowing effect. block diagram serial data interface address bus administrator vertical display control display & row control registers colour encoder windows & frame control wr wg wb ccs2 fbkgc blank ccs0 ccs1 blink vclkx data vertd hord ch 8 8 7 bsen shadow osdenb hsp vsp horizontal display control phase lock loop 8 lpn cws vclks 5 data cws chs 5 ccs0 ccs1 blink craddr 7 luma border arwdb hdren vclkx hord 7 ch chs vertd 7 8 lpn nrow vdren 5 rcaddr daddr waddr 5 9 5 arwdb hdren vdren nrow data daen raen,caen 8 2 character rom luminance & bordger generator vdd vss vdda vssa rout gout bout fbkg htone hflb rp vco vflb ssb sck sda vsp hsp
myson technology mtv016 mtv016 revision 2.0 01/01/1999 2 / 11 1.0 connection diagram (16-pin pdip 300 mil package) vssa vco rp vdda hflb ssb sda sck mtv016-n vss rout gout bout fbkg htone vflb vdd 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 2.0 pin descriptions name i/o pin# function vssa - 1 analog ground. used for internal analog circuitry. vco i/o 2 voltage control oscillator. used to control the internal oscillator frequency by dc voltage input from an external low pass filter. rp i/o 3 bias resistor. used to regulate the appropriate bias current for the internal oscillator to resonate at a specific dot frequency. vdda - 4 analog power supply. positive 5 v dc supplies for internal analog circuitry. a 0.1uf decoupling capacitor should be connected across vdda and vssa. hflb i 5 horizontal input. used to input the horizontal synchronizing signal. it is negative edge triggered and has an internal 100 k w pull-up resistor. ssb i 6 serial interface enable. used to enable the serial data and to select i 2 c or spi bus operation. if this pin is left floating, the i 2 c bus is enabled, otherwise the spi bus is enabled. sda i 7 serial data input. transfers data through this pin to the internal display and control registers. it has an internal 100 k w pull-up resistor. sck i 8 serial clock input. used to synchronize the data transfer. it has an internal 100 k w pull-up resistor. vdd - 9 digital power supply. positive 5 v dc supply for internal digital circuitry and a 0.1uf decoupling capacitor should be connected across vdd and vss. vflb i 10 vertical input. used to input the vertical synchronizing signal. it is negative triggered and has an internal pull-up resistor. htone o 11 half tone output. used to attenuate the external r, g, b amplifiers gain for the transparent windowing effect. fbkg o 12 fast blanking output. used to cut off the external r, g, b signals while this chip is displaying characters or windows. bout o 13 blue color output. a blue color video signal output. gout o 14 green color output. it is a green color video signal output. rout o 15 red color output. a red color video signal output. vss - 16 digital ground. used for internal digital circuitry.
myson technology mtv016 mtv016 revision 2.0 01/01/1999 3 / 11 3.0 functional descriptions 3.1 serial data interface the serial data interface receives data transmitted from an external controller. there are 2 types of bus that can be accessed through the serial data interface: spi bus and i 2 c bus. 3.1.1 spi bus while ssb pin is pulled to "high" or "low" level, the spi bus operation is selected. a valid transmission should be started by pulling ssb to "low" level, enabling mtv016 in receiving mode, and retaining "low" level until the last cycle for a complete data packet transfer. the protocol is shown in figure 2: figure 2. data transmission protocol there are 3 transmission formats as shown below: format (a) r - c - d ? r - c - d ? r - c - d .......... format (b) r - c - d ? c - d ? c - d ? c - d ....... format (c) r - c - d ? d ? d ? d ? d ? d ......... r=row address, c=column address, d=display data 3.1.2 i 2 c bus the i 2 c bus operation is only selected when the ssb pin is left floating. a valid transmission should begin by writing the slave address 7ah, which is the mask option, to mtv016. the protocol is shown in figure 3: sck sda fist byte ?@?@?@?@?@ start ack second byte last byte ack stop b7 b6 b0 b7 b0 figure 3. data transmission protocol (i 2 c) there are 3 transmission formats as shown below: format (a) s - r - c - d ? r - c - d ? r - c - d .......... format (b) s - r - c - d ? c - d ? c - d ? c - d ....... format (c) s - r - c - d ? d ? d ? d ? d ? d ........ s=slave address, r=row address, c=column address, d=display data each arbitrary length of data packet consists of 3 portions: row address (r), column address (c) and display data (d). format (a) is suitable for updating small amounts of data, which will be allocated to different row and column addresses. format (b) is recommended for updating data that has the same row address but a different column address. massive data updating or a full screen data change should use format (c) to increase transmission efficiency. the row and column address will be incremented automatically when format (c) is applied. furthermore, the undefined locations in display or font ram should be filled with dummy data. ms b lsb ssb sck sda first byte last byte
myson technology mtv016 mtv016 revision 2.0 01/01/1999 4 / 11 there are 2 types of data that should be accessed through the serial data interface: address bytes and attribute bytes. the protocol is the same for both except for bit 6 of the row address. the msb (b7) bit is used to distinguish row and column addresses when transferring data from the external controller. bit 6 of the row address is used to distinguish the address byte when it is set to "0" and the attribute byte when it is set to "1", or to differentiate the column address for formats (a), (b) and (c), respectively. the configuration of transmission formats is shown in table 1: table 1. configuration of transmission formats address b7 b6 b5 b4 b3 b2 b1 b0 format row 1 0 x x r3 r2 r1 r0 a,b,c column ab 0 0 x c4 c3 c2 c1 c0 a,b address bytes column c 0 1 x c4 c3 c2 c1 c0 c row 1 1 x x r3 r2 r1 r0 a,b,c column ab 0 0 x c4 c3 c2 c1 c0 a,b attribute bytes column c 0 1 x c4 c3 c2 c1 c0 c initiate row col c col ab da c da ab 1, x 0, 1 0, 0 x, x x, x 0, 1 1, x 1, x format (a) format (b) format (c) x, x 0, x input = b7, b6 0, 0 figure 4. transmission state diagram the data transmission is permitted to change from format (a) to formats (b) and (c), or from format (b) to format (a), but not from format (c) back to formats (a) and (b). the alternation between formats is configured as the state diagram shown in figure 4. 3.2 address bus administrator the administrator manages bus address arbitration of internal registers during external data writing. the external data , which is written to registers through the serial data interface, must be synchronized by internal display timing. in addition, the administrator also provides automatic incrementing to the address bus when external writing using format (c). 3.3 vertical display control the vertical display control can generate different vertical display sizes for most display standards in current monitors. the vertical display size is calculated with the information of the double character height bit (chs) and the vertical display height control register (ch6-ch0). the algorithm of repeating
myson technology mtv016 mtv016 revision 2.0 01/01/1999 5 / 11 character line displays is shown in tables 2 and 3. the programmable vertical size range is 180 lines to a maximum of 1420 lines. the vertical display center for a full screen display may be figured out according to the information of the vertical starting position register (vertd) and vflb input. the vertical delay starting from the leading edge of vflb is calculated using the following equation: vertical delay time = (vertd * 4 + 1) * h h = one horizontal line display time table 2. repeat line weight of character ch6 - ch0 repeat line weight ch6,ch5=11 +18*3 ch6,ch5=10 +18*2 ch6,ch5=0x +18 ch4=1 +16 ch3=1 +8 ch2=1 +4 ch1=1 +2 ch0=1 +1 table 3. repeat line number of character repeat line # repeat line weight 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +1 - - - - - - - - v - - - - - - - - - +2 - - - - v - - - - - - - v - - - - - +4 - - v - - - v - - - v - - - v - - - +8 - v - v - v - v - v - v - v - v - - +16 - v v v v v v v v v v v v v v v v - +17 v v v v v v v v v v v v v v v v v - +18 v v v v v v v v v v v v v v v v v v note:" v " means the nth line in the character would be repeated once, while " - " means the nth line in the character would not be repeated. 3.4 horizontal display control the horizontal display control is used to generate control timing for horizontal displays based on double character width bit (cws), horizontal positioning register (hord), horizontal resolution register (horr) and hflb input. a horizontal display line consists of (horr*12) dots, including 288 dots for 24 display characters; the remaining dots are for a blank region. the horizontal delay starting from the hflb leading edge is calculated using the following equation: horizontal delay time = (hord * 6 + 49) * p - phase error detection pulse width p = one pixel display time = one horizontal line display time / (horr*12) 3.5 phase lock loop (pll) on-chip pll generates system clock timing (vclk) by tracking the input hflb and horizontal resolution register (horr). the frequency of vclk is determined using the following equation: vclk freq = hflb freq * horr * 12 the vclk frequency ranges from 5mhz to 90mhz and is selected by vco1and vco0. in addition, when hflb input is not present for mtv016, the pll will generate a specific system clock, approximately 2.5mhz, by a built-in oscillator to ensure data integrity. 3.6 display & row control registers
myson technology mtv016 mtv016 revision 2.0 01/01/1999 6 / 11 the internal ram contains display and row control registers. the display registers have 240 locations that are allocated between row 0/column 0 and row 9/column 23, as shown in figure 5. each display register has a blink bit, and its corresponding character address on the address byte and 2 color selection bits on the attribute bytes. the row control register is allocated between columns 28 and 31 for rows 0 to 9; it is used to set character size and color attribute for each respective row. if double width character is chosen, only even column characters may be displayed on-screen and the odd column characters will be hidden. column # row # 0 23 24 27 28 31 0 1 8 9 display registers reserved row ctrl reg column # 0 2 3 5 6 8 9 11 12 17 row 10 window1 window2 window3 window4 frame ctrl reg figure 5. memory map register descriptions ( i) display register address byte b7 b6 b5 b4 b3 b2 b1 b0 blink ? craddr ? blink - enables a blinking effect when this bit is set to " 1 ". the blinking alternates every 32 frames. craddr - defines the display character address and graphic symbols in rom. a ttribute byte b7 b6 b5 b4 b3 b2 b1 b0 ccs1 ccs0 - - - - - - ccs1, ccs0 - these bits are used to select character color. color 1 will be selected if these bits are set to 0/0, color 2 will be selected if these bits are set to 0/1, color 3 will be selected if these bits are set to 1/0 and color 4 will be selected if these bits are set to 1/1. color 1, color 2, color 3 and color 4 are defined in the respective row control registers.
myson technology mtv016 mtv016 revision 2.0 01/01/1999 7 / 11 (ii) row control registers b7 b6 b5 b4 b3 b2 b1 b0 coln 28 r1 g1 b1 r2 g2 b2 chs cws b7 - 2 color 1 is defined by r1, g1, b1 and color 2 by r2, g2, b2. b1 chs - defines double height character to the respective row. b0 cws - defines double width character to the respective row. b7 b6 b5 b4 b3 b2 b1 b0 coln 29 r3 g3 b3 r4 g4 b4 - - b7 - 2 color 3 is defined by r3, g3, b3 and color 4 by r4, g4, b4. b7 b6 b5 b4 b3 b2 b1 b0 coln 30 r5 g5 b5 r6 g6 b6 - - b7 - 2 color 5 and color 6 are defined by r5, g5, b5 and r6, g6, b6, respectively. when a window is overlapping with the character and the corresponding ccs2 is set to "1", color 5, color 6, color 7 and color 8 should be chosen. b7 b6 b5 b4 b3 b2 b1 b0 coln 31 r7 g7 b7 r8 g8 b8 - - b7 - 2 color 7 is defined by r7, g7, b7 and color 8 by r8, g8, b8. 3.7 character rom the character rom contains 128 built-in characters and symbols from address 0 to 127. each character and symbol consists of a 12x18-dot matrix. the detailed pattern structures for each character and symbol are shown in section 10.0 . 3.8 luminance & border generator there are 2 shift registers included in the design that can shift out of luminance and bo r der dots to the color encoder. the bo r dering and shadowing feature is configured in this block. for a bo r dering effect, the character will be enveloped with blackedge on 4 sides. for a shadowing effect, the character is enveloped with blackedge on the right and bottom sides only. 3.9 window and frame control the display frame position is completely controlled by the contents of vertd and hord. the window size and position control are specified in columns 0 to 11 on row 10 of the memory map, as shown in figure 5. window 1 has the highest priority and window 4 the least, when 2 windows are overlapping. more detailed information is described as follows: ( i) window control registers row 10 b7 b6 b5 b4 b3 b2 b1 b0 column 0,3,6or 9 msb row start addr lsb msb row end addr lsb
myson technology mtv016 mtv016 revision 2.0 01/01/1999 8 / 11 b7 b6 b5 b4 b3 b2 b1 b0 column 1,4,7or 10 msb col start addr lsb wen ccs2 - b7 b6 b5 b4 b3 b2 b1 b0 column 2,5,8or 11 msb col end addr lsb r g b start (end) addr - these addresses are used to specify the window size. it should be noted that when the start address is greater than the end address, the window will be disabled. wen - enables the window display. ccs2 - extends the character color selection to include 8 colors. (ii) frame control registers row 10 b7 b6 b5 b4 b3 b2 b1 b0 column 12 msb vertd lsb vertd - specifies the starting position for the vertical display. the total number of steps is 256 and each step is incremented by 4 horizontal display lines. the initial value is 4 after power-up. row 10 b7 b6 b5 b4 b3 b2 b1 b0 column 13 msb hord lsb hord - defines the starting position for horizontal display. the total number of steps is 256 and each step is incremented by 6 dots. the initial value is 15 after power-up. b7 b6 b5 b4 b3 b2 b1 b0 column14 - ch6 ch5 ch4 ch3 ch2 ch1 ch0 ch6-ch0 - defines the character vertical height; the height is programmable from 18 to 71 lines. the character vertical height is at least 18 lines if the content of ch6-ch0 is less than 18. for example, when the content is " 2 ", the character vertical height is regarded as equal to 20 lines. and if the content of ch4-ch0 is greater than or equal to 18, it will be regarded as equal to 17. see tables 2 and 3 for a detailed description of this operation. b7 b6 b5 b4 b3 b2 b1 b0 column15 - msb horr lsb horr - specifies the resolution of a horizontal display line, and the increment of each step is 12 dots. that is, the pixels' number per h line is equal to horr*12. it is recommended that horr be greater than or equal to 30 and smaller than 90m / (hfreq*12). the initial value is 40 after power-up. b7 b6 b5 b4 b3 b2 b1 b0 column16 osden bsen shadow hsp vsp blank ramclr fbkgc osden - activates the osd operation when this bit is set to "1". the initial value is 0 after power-up. bsen - enables the bordering and shadowing effect.
myson technology mtv016 mtv016 revision 2.0 01/01/1999 9 / 11 shadow - activates the shadowing effect if this bit is set, otherwise the bordering is chosen. vsp - = 1 t accepts positive polarity vsync input. = 0 t accepts negative polarity vsync input. hsp - = 1 t accepts positive polarity hsync input. = 0 t accepts negative polarity hsync input. blank - forces the fbkg pin output to high while this bit is set to "1". ramclr - clears all address bytes of display registers and wen bits of window control registers when this bit is set to "1". the initial value is 0 after power-up. fbkgc - defines the output configuration for the fbkg pin. when it is set to "0", the fbkg outputs "high" during the display of characters or windows, otherwise it outputs "high" only during the display of characters. b7 b6 b5 b4 b3 b2 b1 b0 column17 test - - - - selvcl vco1 vco0 test - = 0 t normal mode. = 1 t test mode, not allowed in applications. selvcl - enables auto detection for horizontal and vertical sync input edge distortion when the bit is set to "1". the initial value is 1 after power-up. vco1, vco0 - selects the appropriate curve partitions of vco frequency to voltage, based on hflb input and horizontal resolution register (horr). = (0, 0) t 5mhz < hflb freq * horr * 12 < 30mhz = (0, 1) t 30mhz < hflb freq * horr * 12 < 55mhz = (1, 0) t 55mhz < hflb freq * horr * 12 < 75mhz = (1, 1) t 75mhz < hflb freq * horr * 12 < 90mhz the initial value is 0/0 after power-up. 3.11 color encoder the decoder generates the video output to rout, gout and bout by integrating window color, bo r der blackedge, luminance output and color selection output (ccs0, ccs1, ccs2) to form the desired video outputs. 4.0 absolute maximum ratings dc supply voltage (vdd, vdda) -0.3 to +7 v voltage with respect to ground -0.3 to vdd+0.3 v storage temperature -65 to +150 o c ambient operating temperature 0 to +70 o c 5.0 operating conditions dc supply voltage (vdd, vdda) +4.75 to +5.25 v operating temperature 0 to +70 o c
myson technology mtv016 mtv016 revision 2.0 01/01/1999 10 / 11 6.0 electrical characteristics (under operating conditions) symbol parameter conditions(notes) min. max. unit v ih input high voltage - 0.7 * vdd vdd+0.3 v v il input low voltage - vss-0.3 0.3 * vdd (0.2 * vdd for ssb pin ) v v oh output high voltage i oh < -24 ma vdd-0.8 - v v ol output low voltage i ol < 24 ma - 0.5 v i cc supply current vin = vdd, i load = 0ua - 25 ma 7.0 switching characteristics (under operating conditions) symbol parameter min. typ. max. unit f hflb hflb input frequency 15 - 100 khz t r output rise time - - 5 ns t f output fall time - - 5 ns t bcsu ssb to sck set-up time 200 - - ns t bch ssb to sck hold time 100 - - ns t dcsu sda to sck set-up time 200 - - ns t dch sda to sck hold time 100 - - ns t sckh dck high time 500 - - ns t sckl dck low time 500 - - ns tsu: sta start condition set-up time 500 - - ns thd: sta start condition hold time 500 - - ns tsu: sto stop condition set-up time 500 - - ns thd: sto stop condition hold time 500 - - ns 8.0 timing diagrams ssb sck sda t sckl t sck h t bcs u t dcs u t dc h t bc h figure 6. data interface timing (spi) sck sda t su:sta t sckh t hd:sta t sckl t dcsu t dch t su:sto t hd:sto figure 7. data interface timing (i 2 c)
myson technology mtv016 mtv016 revision 2.0 01/01/1999 11 / 11 9.0 characters and symbol pattern please see attachment. 10.0 package dimension 16 pin 300mil mtv 016 75 +/-20 90 +/-20 250 +/-4 55 +/-20 90 +/-20 312 +/-12 65 +/-4 55 +/-4 310max 350 +/-20 10 r10max (4x) 100typ 18 +/-2typ 60 +/-5typ 115 min 750 +/-10 15 min 35 +/-5 7 typ r40 15 max

▲Up To Search▲

Price & Availability of ELECTRONICTHEATRECONTROLSINC-MTV016

	To Download ELECTRONICTHEATRECONTROLSINC-MTV016 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .