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? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron ? s production data sheet specifications. 09005aef80a3e031 mt9m001_ds.fm - rev. a 8/03 en 1 ?2003 micron technology, inc. 1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary ? 1/2-inch 1.3 megapixel cmos active-pixel digital image sensor mt9m001 micron part number: MT9M001C12STC features ? array format (5:4): 1,280h x 1,024v (1,310,720 active pixels). total (incl. dark pixels): 1,312h x 1,048v (1,374,976 pixels) pixel size and type: 5.2m x 5.2m active-pixel photodiode-type color filter array: rgb bayer primary color filters optical format: 1/2-inch supply voltage: 3.0v to 3.6v, 3.3v nominal frame rate: 30 fps progressive scan; programmable data rate: 48 mhz at 48 mhz master clock responsivity (green pixels): 1.8 v/lux-sec with source illumination at 550nm snr max : 45db dynamic range: 61db shutter: electronic rolling shutter (ers) window size: sxga; programmable to any smaller format (vga, qvga, cif, qcif, etc.) programmable controls: gain, frame rate, frame size adc: on-chip, 10 bit power consumption: nominal: 325mw at maximum data rate (3.3v) standby: 275w package: 48-pin clcc dark current at 25c: 20 elec/sec q. e. (green): 52% temporal noise: 10e saturation voltage: 1.2v pixel capacity: 40ke conversion gain: 32 uv/e esd tolerances: 2,000v hbm, 200v mm description the micron ? imaging mt9m001 is an sxga-format with a 1/2-inch cmos active-pixel digital image sen- sor. the active imaging pixel array of 1,280h x 1,024v. it incorporates sophisticated camera functions on-chip such as windowing, column and row skip mode, and snapshot mode. it is programmable through a simple two-wire serial interface. the sensor can be operated in its default mode or programmed by the user for frame size, exposure, gain setting, and other parameters. the default mode out- puts an sxga-size image at 30 frames per second (fps). an on-chip analog-to-digital converter (adc) provides 10 bits per pixel. frame_valid and line_valid sig- nals are output on dedicated pins, along with a pixel clock that is synchronous with valid data.
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 2 ?2003 micron technology, inc. figure 1: 48-pin clcc figure 2: sensor architecture block diagram 1 2 3 4 5 6 48474645 44 43 19 20 21 22 23 24 25 26 27 28 29 30 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32 31 standby trigger nc reset_bar nc nc oe_bar nc a gnd v aa a gnd a gnd nc frame_valid line_valid strobe d gnd v dd d out <9> d out <8> d out <7> d out <6> d out <5> pix_clk nc v aa a gnd v dd d gnd d out <0> d out <1> d out <2> d out <3> d out <4> clk_in nc nc d gnd v dd nc nc vaa_pix a gnd a gnd sclk sdata nc d gnd row decode row drivers 1048 1312 sclk sdata clk_in vaa_pix + oe_bar reset_bar trigger standby v dd d gnd v aa a gnd column decode strobe d out <0:9> pix_clk line_valid frame_valid defect correction 10-bit adc gain control adc timing pga 1x-15x 7 bit register bank windowing exposure gain biasing digital block row and column timing serial interface column s/h pixel array 1,280 x 1,024 1,312 x 1,048 full offset correction
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 3 ?2003 micron technology, inc. table 1: pin descriptions pin numbers symbol type description 29 clk_in input clock in: master clock into sensor (48 mhz maximum). 13 oe_bar input output enable: oe_bar when high places outputs d out <0?9>, frame_valid, line_valid, pix_clk, and strobe into a tri-state configuration. 10 reset_bar input reset: activates (low) asynchronous reset of sensor. all registers assume factory defaults. 46 sclk input serial clock: clock for serial interface. 7 standby input standby: activates (high) standby mode, disables analog bias circuitry for power saving mode. 8 trigger input trigger: activates (high) snapshot sequence. 45 sdata input/output serial data: serial data bus, requires 1.5 k ? resistor to 3.3v for pull-up. 24?28, 32?36 d out <0?9> output data out: pixel data output bits 0?9, d out <9> (msb), d out <0> (lsb). 41 frame_valid output frame valid: output is pulsed high during frame of valid pixel data. 40 line_valid output line valid: output is pulsed high during line of selectable valid pixel data (see reg0x20 for options). 31 pix_clk output pixel clock: pixel data outputs are valid during falling edge of this clock. frequency = (master clock). 39 strobe output strobe: output is pulsed high to indicate sensor reset operation of pixel array has completed. 15, 17, 18, 21, 47, 48 a gnd supply analog ground: provide isolated ground for analog block and pixel array. 5, 23, 38, 43 d gnd supply digital ground: provide isolated ground for digital block. 16, 20 v aa supply analog power: provide power supply for analog block, 3.3v 0.3v. 1vaa_pixsupply analog pixel power: provide power supply for pixel array, 3.3v 0.3v (3.3v). 4, 22, 37 v dd supply digital power: provide power supply for digital block, 3.3v 0.3v. 2, 3, 6, 9, 11, 12, 14, 19, 30, 42, 44 nc ? no connect: these pins must be left unconnected.
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 4 ?2003 micron technology, inc. pixel data format pixel array structure the mt9m001 pixel array is configured as 1,312 col- umns by 1,048 rows (shown in figure 3). the first 16 columns and the first eight rows of pixels are optically black, and can be used to monitor the black level. the last seven columns and the last seven rows of pixels are also optically black. the black row data is used inter- nally for the automatic black level adjustment. how- ever, the black rows can also be read out by setting the sensor to raw data output mode (reg0x20, bit 11 = 1). there are 1,289 columns by 1,033 rows of optically active pixels, which provides a four-pixel boundary around the sxga (1,280 x 1,024) image to avoid boundary effects during color interpolation and cor- rection. figure 3: pixel array description the mt9m001 uses a bayer color pattern, as shown in figure 4. the even-numbered rows contain green and red color pixels, and odd numbered rows contain blue and green color pixels. likewise, the even num- bered columns contain green and blue color pixels, and odd numbered columns contain red and green color pixels. figure 4: pixel color pattern detail (top right corner) output data format the mt9m001 image data is read out in a progres- sive scan. valid image data is surrounded by horizontal blanking and vertical blanking, as shown in figure 5. the amount of horizontal blanking and vertical blank- ing is programmable through reg0x05 and reg0x06, respectively. line_valid is high during the shaded region of the figure. frame_valid timing is described in the next section. (1311, 1047) 16 black columns 7 black rows 8 black rows (0, 0) 7 black columns sxga (1,280 x 1,024) + 4 pixel boundary for color correction + additional active column + additional active row = 1,289 x 1,033 active pixels pixel (8, 16) black pixels column readout direction . . . ... row readout direction g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 5 ?2003 micron technology, inc. figure 5: spatial illustration of image readout output data timing the data output of the mt9m001 is synchronized with the pix_clk output. when line_valid is high, one 10-bit pixel datum is output every pix_clk period. figure 6: timing example of pixel data the rising edges of the pix_clk signal are nomi- nally timed to occur on the rising d out edges. this allows pix_clk to be used as a clock to latch the data. d out data is valid on the falling edge of pix_clk. the pix_clk is high while master clock is high and then low while master clock is low. it is continuously enabled, even during the blanking period. figure 7: row timing and frame_valid/line_valid signals p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image horizontal blanking vertical blanking vertical/horizontal blanking line_valid pix_clk d out 9-d out 0 . . . . . . . . . . . . . . . . p 0 (9:0) p 1 (9:0) p2 (9:0) p 3 (9:0) p 4 (9:0) p n-1 (9:0) p n (9:0) valid image data blanking blanking p1 a q a q ap2 . . . . . . . . . number of master clocks frame_valid line_valid
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 6 ?2003 micron technology, inc. frame timing formulas note: 1. row skip mode should have no effect on the integration time. column skip mode changes the effective value of column size (reg0x04) as follows: column skip 2 => r4eff = (int(r4 / 4) x 2) + 1 column skip 4 => r4eff = (int(r4 / 8) x 2) + 1 column skip 8 => r4eff = (int(r4 / 16) x 2) + 1 where the int() function truncates to the next lowest integer. now use r4eff in the equation for row time instead of r4 2. default for reg0x05 = 9. however, sensor ignores any value for reg0x05 less than 19. sensor timing is shown above in terms of pixel clock and master clock cycles (please refer to figure 6). the recommended master clock frequency is 48 mhz. the vertical blank and total frame time equations assume that the number of integration rows (bits 13 through 0 of reg0x09) is less than the number of active plus blanking rows (reg0x03 + 1 + reg0x06 + 1). if this is not the case, the number of integration rows must be used instead to determine the frame time, as shown in ta b l e 3 . table 2: frame timing parameter name equation (master clock) default timing notes a active data time (reg0x04 + 1) 1,280 pixel clocks = 26.7s 1 p 1 frame start blanking (242) 242 pixel clocks = 5.04s p 2 frame end blanking (2 + reg0x05 - 19) (min reg0x05 value = 19) 2 pixel clocks = 0.042s 2 q = p 1 + p 2 horizontal blanking (244 + reg0x05 - 19) (min reg0x05 value = 19) 244 pixel clocks = 5.08s 2 a + q row time ((reg0x04 + 1) + (244 + reg0x05 - 19)) 1,524 pixel clocks = 31.75s v vertical blanking (reg0x06 + 1) x (a + q) (min reg0x06 value = 15) 39,624 pixel clocks = 825.5s n rows x (a + q) frame valid time (reg0x03 + 1) x (a + q) 1,560,576 pixel clocks = 32.51ms f total frame time (reg0x03 + 1 + reg0x06 + 1) x (a + q) 1,600,200 pixel clocks = 33.34ms table 3: frame time ? long integration time parameter name equation (master clock) default timing v ? vertical blanking (long integration time) (reg0x09 ? reg0x03) x (a + q) 39,624 pixel clocks = 82.5s f ? total frame time (long integration time) (reg0x09 + 1) x (a + q) 1,600,200 pixel clocks = 33.34ms
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 7 ?2003 micron technology, inc. serial bus description registers are written to and read from the mt9m001 through the two-wire serial interface bus. the sensor is a two-wire serial interface slave and is controlled by the two-wire serial interface clock (sclk), which is driven by the two-wire serial interface master. data is transferred into and out through the mt9m001 two- wire serial interface data (sdata) line. the sdata line is pulled up to 3.3v off-chip by a 1.5k ? resistor. either the slave or master device can pull the sdata line down ? the two-wire serial interface protocol deter- mines which device is allowed to pull the sdata line down at any given time. protocol the two-wire serial interface bus defines several dif- ferent transmission codes, as follows: a start bit the slave device eight-bit address a(an) (no) acknowledge bit an eight-bit message a stop bit sequence a typical read or write sequence begins by the mas- ter sending a start bit. after the start bit, the master sends the slave device's eight-bit address. the last bit of the address determines if the request will be a read or a write, where a ? 0 ? indicates a write and a ? 1 ? indi- cates a read. the slave device acknowledges its address by sending an acknowledge bit back to the master. if the request was a write, the master then transfers the eight-bit register address to which a write should take place. the slave sends an acknowledge bit to indi- cate that the register address has been received. the master then transfers the data eight bits at a time, with the slave sending an acknowledge bit after each eight bits. the mt9m001 uses 16-bit data for its internal reg- isters, thus requiring two eight-bit transfers to write to one register. after 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. the master stops writing by sending a start or stop bit. a typical read sequence is executed as follows. first the master sends the write-mode slave address and eight-bit register address, just as in the write request. the master then sends a start bit and the read-mode slave address. the master then clocks out the register data eight bits at a time. the master sends an acknowl- edge bit after each eight-bit transfer. the register address is auto-incremented after every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. bus idle state the bus is idle when both the data and clock lines are high. control of the bus is initiated with a start bit, and the bus is released with a stop bit. only the master can generate the start and stop bits. start bit the start bit is defined as a high-to-low transition of the data line while the clock line is high. stop bit the stop bit is defined as a low-to-high transition of the data line while the clock line is high. slave address the eight-bit address of a two-wire serial interface device consists of seven bits of address and 1 bit of direction. a ? 0 ? in the lsb (least significant bit) of the address indicates write mode, and a ? 1 ? indicates read mode. data bit transfer one data bit is transferred during each clock pulse. the serial interface clock pulse is provided by the mas- ter. the data must be stable during the high period of the two-wire serial interface clock ? it can only change when the serial clock is low. data is transferred eight bits at a time, followed by an acknowledge bit. acknowledge bit the master generates the acknowledge clock pulse. the transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver indicates an acknowledge bit by pulling the data line low during the acknowledge clock pulse. no-acknowledge bit the no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. a no-acknowledge bit is used to terminate a read sequence.
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 8 ?2003 micron technology, inc. two-wire serial interface sample write and read sequences 16-bit write sequence a typical write sequence for writing 16 bits to a reg- ister is shown in figure 8. a start bit given by the mas- ter, followed by the write address, starts the sequence. the image sensor will then give an acknowledge bit and expects the register address to come first, followed by the 16-bit data. after each eight-bit transfer, the image sensor will give an acknowledge bit. all 16 bits must be written before the register will be updated. after 16 bits are transferred, the register address is automatically incremented so that the next 16 bits are written to the next register. the master stops writing by sending a start or stop bit. figure 8: timing diagram showing a write to reg0x09 with the value 0x0284 16-bit read sequence a typical read sequence is shown in figure 9. first the master has to write the register address, as in a write sequence. then a start bit and the read address specifies that a read is about to happen from the regis- ter. the master then clocks out the register data eight bits at a time. the master sends an acknowledge bit after each eight-bit transfer. the register address should be incremented after every 16 bits is trans- ferred. the data transfer is stopped when the master sends a no-acknowledge bit. figure 9: timing diagram showing a read from reg0x09; returned value 0x0284 sclk sdata start ack 0xba addr ack ack ack stop reg0x09 1000 0100 0000 0010 sclk sdata start ack 0xba addr 0xbb addr 0000 0010 reg0x09 ack ack ack stop 1000 0100 nack
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 9 ?2003 micron technology, inc. registers register map note: 1. 1 = always 1 0 = always 0 d = programmable 2. previous version used the data format of 1000 0100 0001 0001; hex value of 0x8401. 3. in default mode, calibration values start at ? 0 ? but are set via dark level calibration. table 4: register list and default values note 1 register # (hex) description data format (binary) default value (hex) notes 0x00 chip version 1000 0100 0001 0001 0x8411 2 0x01 row start 0000 0ddd dddd dddd 0x000c 0x02 column start 0000 0ddd dddd dddd 0x0014 0x03 row size (window height) 0000 0ddd dddd dddd 0x03ff 0x04 col size (window width) 0000 0ddd dddd dddd 0x04ff 0x05 horizontal blanking 0000 0ddd dddd dddd 0x0009 0x06 vertical blanking 0000 0ddd dddd dddd 0x0019 0x07 output control 0000 0000 0d00 00dd 0x0002 0x09 shutter width 00dd dddd dddd dddd 0x0419 0x0b restart 0000 0000 0000 000d 0x0000 0x0c shutter delay 0000 0ddd dddd dddd 0x0000 0x0d reset 0000 0000 0000 000d 0x0000 0x1e read options 1 1000 dddd 00dd dd00 0x8000 0x20 read options 2 dd01 0dd1 d00d d10d 0x1104 0x2b green1 gain 0000 0000 0ddd dddd 0x0008 0x2c blue gain 0000 0000 0ddd dddd 0x0008 0x2d red gain 0000 0000 0ddd dddd 0x0008 0x2e green2 gain 0000 0000 0ddd dddd 0x0008 0x35 global gain 0000 0000 0ddd dddd 0x0008 0x5f cal threshold dddd dddd d0dd dddd 0x0904 0x60 cal green1 0000 000d dddd dddd 0x0000 3 0x61 cal green2 0000 000d dddd dddd 0x0000 3 0x62 cal ctrl d00d d100 1001 1ddd 0x0498 0x63 cal red 0000 000d dddd dddd 0x0000 3 0x64 cal blue 0000 000d dddd dddd 0x0000 3 0xf1 chip enable 0000 0000 0000 00dd 0x0001
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 10 ?2003 micron technology, inc. table 5: register description register bit description chip id 0x00 0 ? 15 this register is read-only and gives the chip identification number: 0x8411. window control these registers control the size of the window. 0x01 0 ? 10 first row to be read out ? default = 0x000c (12). 0x02 0 ? 10 first column to be read out ? default = 0x0014 (20). register value must be an even number. 0x03 0 ? 10 window height (number of rows - 1) ? default = 0x03ff (1023). minimum value for 0x03 = 0x0002. 0x04 0 ? 10 window width (number of columns - 1) ? default = 0x04ff (1279). register value must be an odd number. minumum value for 0x04 = 0x0003. blanking control these registers control the blanking time in a row (called column fill-in or horizontal blanking) and between frames (vertical blanking). horizontal blanking is specified in terms of pixel clocks. vertical blanking is specified in terms of row readout times. the actual imager timing can be calculated using table 2, frame timing, on page 6. 0x05 0 ? 10 horizontal blanking ? default = 0x0009 (9 pixels). 0x06 0 ? 10 vertical blanking ? default = 0x0019 (25 rows). output control this register controls various features of the output format for the sensor. 0x07 0 synchronize changes (copied to reg0xf1, bit1). 0 = normal operation. update changes to registers that affect image brightness (integration time, integration delay, gain, horizontal blanking and vertical blanking, window size, row/column skip or row mirror) at the next frame boundary. the ? frame boundary ? is 8 row_times before the rising edge of frame_valid. (if ? show dark rows ? is set, it will be coincident with the rising edge of frame_valid.) 1 = do not update any changes to these settings until this bit is returned to ? 0. ? 1 chip enable (copied to reg0xf1, bit0). 1 = normal operation. 0 = stop sensor readout. when this is returned to ? 1, ? sensor readout restarts at the starting row in a new frame. the digital power consumption can then also be reduced to less than 5ua by turning off the master clock. 2 reserved ? default is 0; set to zero at all times. 3 reserved ? default is 0; set to zero at all times. 6 override pixel data. 0 = normal operation. 1 = output programmed test data (see reg0x32). first valid columns will output contents of test data register; second columns will output inverted data. third columns will output noninverted data, fourth inverted, etc.
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 11 ?2003 micron technology, inc. pixel integration control these registers (along with the window sizing and blanking registers) control the integration time for the pixels. the actual total integration time ( t int) is: t int = reg0x09 x row time - overhead time - reset delay, where: row time = ((reg0x04 + 1) + 244 + reg0x05 - 19) pixel clock periods overhead time = 180 pixel clock periods reset delay = 4 x reg0x0c pixel clock periods if the value in reg0x0c exceeds (row time - 548)/4 pixel clock cycles, the row time will be extended by (4 x reg0x0c - (row time - 548)) pixel clock cycles. in this expression, the row time term, reg0x09 x ((number of columns) + 244 + horizontal blanking register - 19), corresponds to the number of rows integrated. the overhead time (180 pixel clocks) is the overhead time between the read cycle and the reset cycle, and the final term is the effect of the reset delay. typically, the value of reg0x09 is limited to the number of rows per frame (which includes vertical blanking rows) such that the frame rate is not affected by the integration time. if reg0x09 is increased beyond the total number of rows per frame, the mt9m001 will add additional blanking rows as needed. a second constraint is that t int must be adjusted to avoid banding in the image from light flicker. under 60hz flicker, this means t int must be a multiple of 1/120 of a second. under 50hz flicker, t int must be a multiple of 1/100 of a second. 0x09 0 ? 13 number of rows of integration ? default = 0x0419 (1049). 0x0c 0 ? 10 shutter delay ? default = 0x0000 (0). this is the number of master clocks times four that the timing and control logic waits before asserting the reset for a given row. frame restart 0x0b 0 setting bit 0 to ? 1 ? of reg0x0b will cause the sensor to abandon the readout of the current frame and restart from the first row. this register automatically resets itself to 0x0000 after the frame restart. the first frame after this event is considered to be a "bad frame" (see description for reg0x20, bit0). reset 0x0d 0 this register is used to reset the sensor to its default, power-up state. to put the mt9m001 in reset mode first write a ? 1 ? into bit 0 of this register, then write a ? 0 ? into bit 0 to resume operation. read mode 1 in read mode 1, this register is used to control many aspects of the readout of the sensor. table 5: register description (continued) register bit description
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 12 ?2003 micron technology, inc. 0x1e 0 reserved ? default is 0; set to zero at all times. 1 reserved ? default is 0; set to zero at all times. 2 column skip 4 ? default is 0 (disable). 1 = enable. 3 row skip 4 ? default is 0 (disable). 1 = enable. 4 column skip 8 ? default is 0 (disable). 1 = enable. 5 row skip 8 ? default is 0 (disable). 1 = enable. 6 reserved ? default is 0; do not change. 7 reserved ? default is 0; do not change. 8 snapshot mode ? default is 0 (continuous mode). 1 = enable (wait for trigger; trigger can come from outside signal (trigger pin on the sensor) or from serial interface register restart, i.e. programming a ? 1 ? to bit 0 of reg0x0b. 9 strobe enable ? default is 0 (no strobe signal). 1 = enable strobe (signal output from the sensor during the time all rows are integrating. see strobe width for more information). 10 strobe width ? default is 0 (strobe signal width at minimum length, 1 row of integration time, prior to line valid going high). 1 = extend strobe width (strobe signal width extends to entire time all rows are integrating). 0x1e 11 strobe override ? default is 0 (strobe signal created by digital logic). 1 = override strobe signal (strobe signal is set high when this bit is set, low when this bit is set low. it is assumed that strobe enable is set to ? 0 ? if strobe override is being used). 12 reserved ? default is 0; do not change. 13 reserved ? default is 0; do not change. 14 reserved ? default is 0; do not change. 15 reserved ? default is 1; do not change. read mode 2 this register is used to control many aspects of the readout of the sensor. table 5: register description (continued) register bit description
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 13 ?2003 micron technology, inc. 0x20 0 no bad frames ? 1 = output all frames (including bad frames). 0 (default) = only output good frames. a bad frame is defined as the first frame following a change to: window size or position, horizontal blanking, row or column skip, or mirroring. 1 reserved ? default is 0; do not change. 2 reserved ? default is 1; set to ? 1 ? at all times. 3 column skip ? 1= read out two columns, and then skip two columns (for example, col 0, col 1, col 4, col 5 ? ). 0 = normal readout (default). 4 row skip ? 1 = read out two rows, and then skip two rows (for example, row 0, row 1, row 4, row 5 ? ). 0 = normal readout (default). 5 reserved ? default is 0; do not change. 6 reserved ? default is 0; set to zero at all times. 7 flip row ? 1 = readout starting 1 row later (alternate color pair). 0 (default) = normal readout. 8 reserved ? default is 1; set to ? 1 ? at all times. 9 1 = "continuous" line_valid (continue producing line_valid during vertical blanking). 0 = normal line_valid (default, no line_valid during vertical blanking). 10 1 = line_valid = "continuous" line_valid xor frame_valid. 0 = line_valid determined by bit 9. 11 reserved ? default is 0; do not change. 12 reserved ? default is 1; do not change. 13 reserved ? default is 0; do not change. 14 reserved ? default is 0; do not change. 15 mirror row ? 1 = read out from bottom to top (upside down). 0 (default) = normal readout (top to bottom). gain settings the gain is individually controllable for each color in the bayer pattern as shown in the register chart. formula for gain setting: gain 8 gain = (bit[6] + 1) x (bit[5-0] x 0.125) gain > 8 (bit[6] = 1 and bit[5] = 1) gain = 8.0 + bit[2-0] since bit[6] of the gain registers are multiplicative factors for the gain settings, there are alternative ways of achieving certain gains. some settings offer superior noise performance to others, despite the same overall gain. the following lists the recommended gain settings: gain increments recommended settings 1.000 to 4.000 0.125 0x08 to 0x20 4.25 to 8.00 0.25 0x51 to 0x60 9.0 to 15.0 1.0 0x61 to 0x67 0x2b 6 ? 0 green1 gain ? default = 0x08 (8) = 1x gain. 0x2c 6 ? 0 blue gain ? default = 0x08 (8) = 1x gain. 0x2d 6 ? 0 red gain ? default = 0x08 (8) = 1x gain. 0x2e 6 ? 0 green2 gain ? default = 0x08 (8) = 1x gain. table 5: register description (continued) register bit description
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 14 ?2003 micron technology, inc. 0x35 6 ? 0 global gain ? default = 0x08 (8) = 1x gain. this register can be used to set all four gains at once. when read, it will return the value stored in reg0x2b. black level calibration these registers are used in the black level calibration. their functionality is described in detail in the next section. 0x5f 5 ? 0 thres_lo ? lower threshold for black level in adc lsbs ? d efault = 000100. 7 1 = override automatic thres_hi and thres_lo adjust (thres_hi always = bits 14 ? 8; thres_lo always = bits 5 ? 0). default = 0 = automatic thres_hi and thres_lo adjustment. 14-8 thres_hi ? maximum allowed black level in adc lsbs (default = thres_lo + 5). black level maximum is set to this value when bit 7 = 1; black level maximum is reset to this value after every black level average restart if bit 15 = 1 and bit 7 = 0. 15 no gain dependence. 1 = thres_lo is set by the programmed value of bits 5 ? 0, thres_hi is reset to the programmed value (bits 14 ? 8) after every black level average restart. 0 = thres_lo and thres_hi are set automatically, as described above. 0x60 8 ? 0 cal green1 ? analog offset correction value for green 1, bits 0 ? 7 sets magnitude, bit 8 set sign. 0 = positive. 1 = negative. 0x61 8 ? 0 cal green2 ? analog offset correction value for green 2, bits 0 ? 7 sets magnitude, bit 8 set sign. 0 = positive. 1 = negative. 0x62 0x62 0 manual override of black level correction. 1 = override automatic black level correction with programmed values. 0 = normal operation (default). 2 ? 1 force/disable black level calibration. 00 = apply black level calibration during adc operation only (default). 10 = apply black level calibration continuously. x1= disable black level correction (offset correction voltage = 0.0v). (in this case, no black level correction is possible). 4 ? 3 reserved ? default is 1; do not change. 6 ? 5 reserved ? default is 0; do not change. 7 reserved ? default is 1; do not change. 9 ? 8 reserved ? default is 0; do not change. 10 reserved ? default is 1; do not change. 11 1 = do not reset the upper threshold after a black level recalculation sweep. 0 = reset the upper threshold after a black level recalculation sweep (default). 12 1 = start a new running digitally filtered average for the black level (this is internally reset to ? 0 ? immediately), and do a rapid sweep to find the new starting point. 0 = normal operation (default). 14 ? 3 reserved ? default is 0; set to zero at all times. 15 1 = do not perform the rapid black level sweep on new gain settings. 0 = normal operation. 0x63 8 ? 0 cal red ? analog offset correction value for red, bits 0 ? 7 sets magnitude, bit 8 set sign. 0 = positive. 1 = negative. 0x64 8 ? 0 cal blue ? analog offset correction value for blue, bits 0 ? 7 sets magnitude, bit 8 set sign. 0 = positive. 1 = negative. table 5: register description (continued) register bit description
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 15 ?2003 micron technology, inc. chip enable and two-wire serial interface write synchronize. 0xf1 0 mirrors the functionality of reg0x07 bit1 (chip enable). 1 = normal operation. 0 = stop sensor readout; when this is returned to ? 1, ? sensor readout restarts at the starting row in a new frame. 1 mirrors the functionality of reg0x07 bit0 (synchronize changes). 0 = normal operation, update changes to registers that affect image brightness (integration time, integration delay, gain, horizontal blanking and vertical blanking, window size, row/column skip, or row/column mirror) at the next frame boundary. 1 = do not update any changes to these settings until this bit is returned to ? 0. ? table 5: register description (continued) register bit description
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 16 ?2003 micron technology, inc. feature description signal path the mt9m001 signal path consists of two stages, a programmable gain stage and a programmable analog offset stage. programmable gain stage the gain settings can be independently adjusted for the colors green1, blue, red, and green2 and are pro- grammed through registers 0x2b, 0x2c, 0x2d, and 0x2e, respectively. a total programmable gain of 15 is available and can be calculated using the following for- mula: gain 1 to 8: gain = (bit[6] + 1) x (bit[5-0] x 0.125) for gain higher than eight, the user would need to set bit[6-5] = 11 and use the lower 3 lsb ? s bit[2-0] to set the higher gain values. the formula for obtaining gain greater than eight is as follows: total gain = 8 + bit[2-0] for example, for total gain = 12, the value to pro- gram is bit[6-0] = 1100100. the maximum total gain = 15, i.e. bit[6-0] = 1100111. the gain circuitry in the mt9m001 is designed to offer signal gains from one to 15. the minimum gain of one corresponds to the lowest setting where the pixel signal is guaranteed to saturate the adc under all specified operating conditions. any reduction of the gain below this value may cause the sensor to saturate at adc output values less than the maximum, under certain conditions. it is recommended that this guide- line be followed at all times. since bit[6] of the gain registers are multiplicative factors for the gain settings, there are alternative ways of achieving certain gains. some settings offer superior noise performance to others, despite the same overall gain. recommended gain settings are listed in table 6. figure 10: signal path programmable analog offset stage the programmable analog offset stage corrects for analog offset that might be present in the analog sig- nal. the analog offset settings can be independently adjusted for the colors green1, green2, red, and blue and are programmed through registers 0x60, 0x61, 0x63, and 0x64, respectively. the user would need to program register 0x62 appropriately to enable the ana- log offset correction. the lower eight bits (bit[7-0]) determines the abso- lute value of the analog offset to be corrected and bit[8] determines the sign of the correction. when bit[8] is ? 1 ? , the sign of the correction is negative and vice versa. the analog value of the correction relative to the analog gain stage can be determined from the follow- ing formula: analog offset (bit[8] = 0) = bit[7-0] x 2mv analog offset (bit[8] = 1) = - (bit[7-0] x 2mv) x + pixel output (signal minus reset) offset correction voltage (reg0x60, reg0x61, reg0x63, reg0x64) (signed lower 9bits) x 2mv 10-bit adc adc data (9:0) gain selection (reg0x2b - 0x2e) table 6: recommended gain settings at 48 mhz nominal gain increments recommended settings 1 to 4.000 0.125 0x08 to 0x20 4.25 to 8.00 0.25 0x51 to 0x60 9 to 15 1.0 0x61 to 0x67
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 17 ?2003 micron technology, inc. column and row mirror image by setting bit 15 of reg0x20, the readout order of the columns will be reversed, as shown in figure 11. figure 11: readout of six rows in normal and row mirror output mode by setting bits 15 and 7 of reg0x20 the readout order of the rows will be reversed, as shown in figure 12. figure 12: readout of six rows in normal and row mirror output mode column and row skip by setting bit 3 of reg0x20, only half of the columns set will be read out. an example is shown in figure 13. only columns with bit 1 equal to ? 0 ? will be read out (xxxxxxx0x). the row skip works in the same way and will only read out rows with bit 1 equal to ? 0. ? row skip mode is enabled by setting bit 4 of reg0x20. for both row and column skips, the number of rows or columns read out will be half of what is set in reg0x03 or reg0x04, respectively. figure 13: readout of eight pixels in normal and column skip output mode d out 9 ? d out 0 frame_valid normal readout row0 (9:0) row1 (9:0) row2 (9:0) row3 (9:0) row4 (9:0) row5 (9:0) d out 9 ? d out 0 reverse readout row5 (9:0) row4 (9:0) row3 (9:0) row2 (9:0) row1 (9:0) row0 (9:0) d out 9 ? d out 0 frame_valid normal readout row0 (9:0) row1 (9:0) row2 (9:0) row3 (9:0) row4 (9:0) row5 (9:0) d out 9 ? d out 0 reverse readout row5 (9:0) row6 (9:0) row4 (9:0) row3 (9:0) row2 (9:0) row1 (9:0) d out 9 ? d out 0 line_valid normal readout g0 (9:0) r0 (9:0) g1 (9:0) r1 (9:0) g2 (9:0) r2 (9:0) g3 (9:0) r3 (9:0) d out 9 ? d out 0 line_valid column skip readout g0 (9:0) r0 (9:0) g2 (9:0) r2 (9:0)
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 18 ?2003 micron technology, inc. black level calibration the mt9m001 has automatic black level calibration on-chip which can be overridden by the user, as described below and shown in figure 14. the automatic black level calibration measures the average value of 256 pixels from two dark rows of the chip for each of the four colors. the pixels are averaged as if they were light-sensitive and passed through the appropriate color gain. this average is then digitally filtered over many frames. for each color, the new filtered average is compared to a minimum acceptable level (to screen for too low a black level) and a maximum acceptable level. if the average is lower than the minimum acceptable level, the offset correction voltage for that color is increased by one offset lsb (offset lsbs do not match adc lsbs; yypically, one offset lsb is approximately 2mv). if it is above the maximum level, the level is decreased by 1 lsb (2mv). the upper threshold is automatically adjusted upwards whenever an upward shift in the black level from below the minimum results in a new black level above the maximum. this prevents black level oscillation from below the minimum to above the maximum. the lower threshold is increased with the maximum gain setting (out of all four colors), accord- ing to the formula described under reg0x5f. this pre- vents clipping of the black level. whenever the gain or any of the readout timing reg- isters is changed (shutter width, vertical blanking, number of rows or columns, or the shutter delay) or if the black level recalculation bit, reset bit or restart bit is set, the running digitally filtered average is reset to the first average of the dark pixels. the digital filtering over many frames is then restarted. whenever the gain or the readout timing registers are changed, the upper threshold is restored to its default value. after changes to the sensor configuration, large shifts in the black level calibration can result. to quickly adapt to this shift, a rapid sweep of the black level during the dark-row readout is performed on the first frame after certain changes to the sensor registers. any changes to the registers listed above will cause this recalculation. the data from this sweep allows the sen- sor to choose an accurate new starting point for the running average. this procedure can be disabled as described under reg0x5f. figure 14: black level calibration flow chart x + pixel output (signal minus reset) offset correction voltage (color-wise) 10-bit adc adc data (9:0) gain selection (color-wise)
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 19 ?2003 micron technology, inc. table 7: black level registers register bit description reg0x5f this register controls the operation of the black level calibration thresholds. 15 no gain dependence. 1 = thres_lo is set by the programmed value of bits 5 ? 0, thres_hi is reset to the programmed value (bits 14 ? 8) after every black level average restart. 0 = thres_lo and thres_hi are set automatically as described below. 14 ? 8 thres_hi ? maximum allowed black level in adc lsbs (default = thres_lo + 5). black level maximum is set to this value when bit 7 = 1, black level maximum is reset to this value after every black level average restart if bit 15 = 1 and bit 7 = 0. 7 1 = override automatic thres_hi and thres_lo adjust (thres_hi always = bits 14 ? 8, thres_lo always = bits 5 ? 0). 0 = automatic thres_hi and thres_lo adjustment. 5 ? 0 thres_lo ? lower threshold for black level in adc lsbs. under default automatic operation (bit 7 = 0, bit 15 = 0), thres_lo = reggain max /4 x (reggain max , bit 6 +1) x (reggain max , bit 7 +1), where reggain max is the maximum of the four independent gain register settings. whenever a jump in the calibration causes the black level data to change from below thres_lo to above thres_hi, thres_hi is adjusted according to the following: if new black level < 64: thres_hi = thres_lo + 2 + (2 x delta), where delta = new black level - thres_lo if new black level > 63 and < 119: thres_hi = new black level + 4 if new black level > 119: thres_hi = 123 after any recalculation of the black level and average restart, thres_hi is reset to either thres_lo + 5 (automatic, default mode), thres_hi (bit 7 = 1). reg0x62, bit 11 will override this. reg0x62 this register is used to control the automatic black level calibration circuitry. 15 1 = do not perform the rapid black level sweep on new gain settings. 0 = normal operation. 14 reserved ? default is 0; do not change. 13 reserved ? default is 0; do not change. 12 1 = start a new running digitally filtered average for the black level (this is internally reset to ? 0 ? immediately), and do a rapid sweep to find the new starting point. 11 1 = do not reset the upper threshold after a black level recalculation sweep. 0 = reset the upper threshold after a black level recalculation sweep (default). 10 ? 3 reserved ? default is 1; do not change. 2 ? 1 force/disable black level calibration. 00 = apply black level calibration during adc operation only (default). 10 = apply black level calibration continuously. x1 = disable black level correction (offset correction voltage = skew voltage = 0.0v). (in this case, no black level correction is possible). 0 manual override of black level correction. 1 = override automatic black level correction with programmed values. 0 = normal operation (default).
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 20 ?2003 micron technology, inc. reg0x60, reg0x61, reg0x63, reg0x64 these registers contain the 9-bit signed black level calibration values for the four colors in the bayer pattern. in normal operation, these values are calculated at the beginning of each frame. however, if reg0x62, bit 0 is set to ? 1, ? these registers can be written to, overriding the automatic black level calculation. this feature can be used in conjunction with readout of the black rows (reg0x20, bit 11) if the user would like to use an external black level calibration circuit. the offset correction voltage is generated according to the following formula: offset correction voltage = (9-bit signed calibration value, -256 to 255) x (2mv x enable bit) adc input voltage = pixel output voltage x analog gain - offset correction voltage table 7: black level registers (continued) register bit description
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 21 ?2003 micron technology, inc. still image capture with external synchronization in continuous mode video image capture, the trig- ger signal should be held low or ? 0. ? to c apture a still image, the sensor must first be put into snapshot mode by programming a ? 1 ? in register 0x1e, bit 8. in snapshot mode, the sensor waits for a trigger signal (frame_valid, line_valid signals are low, pixel clock signal continues). when the trigger signal is received (active high), one frame is read out (a trig- ger signal can also be achieved by programming a restart ? for example, program a ? 1 ? to bit 0 of reg0x0b). the reset, readout timing for that frame will be the same as for a continuous frame with similar reg- ister settings; the only difference is that only one frame is read out. general timing for the snapshot mode is shown in figure 15. figure 15: general timing for snapshot mode line_valid signal by setting bit 9 and 10 of reg0x20 the line valid sig- nal can get three different output formats. the formats are shown when reading out four rows and two vertical blanking rows (figure 16). in the last format, the line_valid signal is the xor between the continu- ously line_valid signal and the frame_valid sig- nal. figure 16: different line_valid formats trigger reset row 1 reset row reset row x strobe readout max strobe length (all rows integrating) min strobe length (1 row time) default frame_valid line_valid continuously frame_valid line_valid xor frame_valid line_valid
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 22 ?2003 micron technology, inc. electrical specifications note: 1. to place the chip in standby mode, first raise standby to v dd , then wait two master clock cycles before turning off the master clock. two master clock cycles are required to place the analog circuitry into standby, low-power mode. table 8: dc electrical characteristics (v pwr = 3.3 0.3v; t a = 25 c) symbol definition condition min typ max units notes v ih input high voltage v pwr - 0.3 3.3 v pwr + 0.3 v v il input low voltage -0.3 0.0 0.8 v i in input leakage current no pull-up resistor; v in = v pwr or v gnd -15 0.8 15 a v oh output high voltage v pwr - 0.2 3.3 v v ol output low voltage 0.0 0.2 v i oz tri-state output leakage current 15 a i pwr a analog quiescent supply current default settings tbd 85 tbd ma i pwr d digital quiescent supply current clk_in = 48 mhz; default setting, c load = 10pf 16 20 24 ma i pwr a standby analog standby supply current stdby = v dd tbd tbd tbd a 1 i pwr d standby digital standby supply current stdby = v dd , clk_in = 0 mhz tbd 9 tbd a 1 i pwr d standby clkon digital standby supply current with clock on stdby = v dd , clk_in = 27 mhz tbd tbd tbd a table 9: ac electrical characteristics (v pwr = 3.3 0.3v; t a = 25 c; clk_in at 48 mhz) symbol definition condition min typ max units fclk_in input clock frequency clock 148mhz duty cycle 45/55 50/50 55/45 min/max t r inputclock rise time tbd tbd tbd min/max t f input clock fall time tbd tbd ns t plh p clk_in to pix_clk propagation delay, low- to-high c load = 10pf tbd tbd tbd ns t phl p clk_in to pix_clk propagation delay, high- to-low c load = 10pf tbd tbd tbd ns t phl d clk_in to d out <9-0> propagation delay, low-to-high c load = 10pf tbd tbd tbd ns t phl d clk_in to d out <9-0> propagation delay, high-to-low c load = 10pf tbd tbd tbd ns t oh data hold time tbd tbd tbd ns t plh f , l clk_in to frame_valid and line_valid propagation, low-to-high c load = 10pf tbd tbd tbd ns t phl f , l clk_in to frame_valid and line_valid propagation, high-to-low tbd tbd tbd ns
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 23 ?2003 micron technology, inc. propagation delay for frame_valid and line_valid signals the line_valid and frame_valid signals change on the same falling master clock edge as the data out- put. the line_valid goes high on the same rising master clock edge as the output of the first valid pixel ? s data and returns low on the same master clock rising edge as the end of the output of the last valid pixel ? s data. as shown in the ? output data format ? on page 4 and ? output data timing ? on page 5, frame_valid goes high 242 pixel clocks prior to the time that the first line_valid goes high. it returns low at a time corresponding to (2 + reg0x05-19 pixel clocks) after the last line_valid goes low. note that the data outputs change on the rising edge of the master clock. figure 17: propagation delays for frame_valid and line_valid signals figure 18: propagation delays for pix_clk and data out signals clk_in frame_valid line_valid clk_in frame_valid line_valid t plh fl t r t phl fl t r clk_in pix_clk t plh d , t plh d d out (9:0) d out (9:0) t oh t plh p t plh p t r t f d out (9:0) d out (9:0) d out (9:0)
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 24 ?2003 micron technology, inc. two-wire serial bus timing the two-wire serial bus operation requires certain minimum master clock cycles between transitions. these are specified in the following diagrams in master clock cycles. figure 19: serial host interface start condition timing figure 20: serial host interface stop condition timing note: all timing are in units of master clock cycle. figure 21: serial host interface data timing for write note: sdata is driven by an off-chip transmitter. figure 22: serial host interface data timing for read note: sdata is pulled low by the sensor, or allowed to be pulled high by a pull-up resistor off-chip. figure 23: acknowledge signal timing after an 8-bit write to the sensor figure 24: acknowledge signal timing after an 8-bit read from the sensor note: after a read, the master receiver must pull down sdata to acknowledge receipt of data bits. when read sequence is complete, the master must generate a no acknowledge by leaving sdata to float high. on the following cycle, a start or stop bit may be used. sclk 5 sdata 4 sclk 5 sdata 4 sclk 4 sdata 4 sclk 5 sdata sclk sensor pulls down sdata pin 6 sdata 3 sclk sensor tri-states sdata pin (turns off pull down) 7 sdata 6
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 25 ?2003 micron technology, inc. quantum efficiency figure 25: quantum efficiency 0 10 20 30 40 50 60 350 400 450 500 550 600 650 700 750 blue green red quantum efficiency (%) wavelength (nm)
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 26 ?2003 micron technology, inc. image center offset and orientation figure 26: image center offset note: 1. x and y coordinates referenced to center of die. 2. die center = package center. 3. image center offset from package center (x = 0.015mm, y = 0.712mm). (v col_te s t_in) pixel array micron imaging logo 7 7 18 18 19 19 6 6 31 42 30 43 42 31 30 43 1 1 48 48 a gnd vaa_pix nc scan_en nc 2 3nc v dd 4 5d gnd nc 44 45 sdata sclk 46 47 a gnd standby trigger 8 9 nc reset_bar 10 11 nc nc 12 13 oe_bar nc 14 15 vadc_test_in v aa 16 17 a gnd nc nc v aa 20 21 a gnd v dd 22 23 d gnd d out <0> 24 25 d out <1> d out <2> 26 27 d out <3> d out <4> 28 29 clk_in nc pix_clk d out <5> 32 33 d out <6> d out <7> 34 35 d out <8> d out <9> 36 37 v dd d gnd 38 39 strobe line_valid 40 41 frame_valid vcol_test_in 0.015 mm image center die center and package center 0.712 mm pixel (20,12) pixel (0,0) black and boundary pixels die table 10: optical area dimensions optical area pixel x-dimension y-dimension sxga center of pixel (20, 12) 3,340.70m 3,372.45m center of pixel (1299, 1035) -3,315.2m -1,952.35m
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. mt9m001_ds.fm - rev. a 8/03 en 27 ?2003 micron technology, inc. figure 27: package drawings top view 1 48 14.22 + 0.3/-0.15 sq. bottom view side view j d c i a glass 1: 0.50 +/- 0.05 glass 2: 0.55 +/- 0.05 g b e f h mm description nominal min max a die thickness 0.725 0.705 0.745 b glass thickness 0.525 0.450 0.600 c base layer thickness 0.510 0.460 0.560 d dam thickness 1.140 1.010 1.270 e die attach bondline thickness 0.035 0.020 0.050 f glass attach bondline thickness 0.035 0.020 0.050 g sensor array to outer glass lid 0.940 0.685 1.195 h sensor array to inner glass lid (air gap) 0.415 0.235 0.595 i sensor array to seating plane 1.270 1.185 1.355 j package total thickness 2.210 1.940 2.480 48 1 pin no. 1 index 1.016 +/- 0.178 2.159 +/- 0.254 11.176 +/- 0.127 1.016 +/- 0.0762 1.52 +/- 0.254/-0.127 0.508 +/- -0.0762
1/2-inch 1.3 megapixel cmos active-pixel digital image sensor preliminary 09005aef80a3e031 micron technology, inc., reserves the right to change products or specifications without notice.. mt9m001_ds.fm - rev. a 8/03 en 28 ?2003 micron technology, inc ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks and/or service marks of micron technology, inc. all other trademarks are the property of their respective owners. figure 28: optical orientation data sheet designation preliminary: this data sheet contains initial characterization limits that are subject to change upon full charac- terization of production devices. up pin 1 pixel array top of board bottom of board

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Price & Availability of MT9M001C12STC

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