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freescale semiconductor technical data document number: mc56f8006 rev. 4, 06/2011 ? freescale semiconductor, inc., 2009?2011. all rights reserved. freescale reserves the right to change the deta il specifications as may be required to permit improvements in the design of its products. mc56f8006/mc56f8002 48-pin lqfp case: 932-03 7 x 7 mm 2 28-pin soic case: 751f-05 7.5 x 18 mm 2 32-pin lqfp case: 873a-03 7 x 7 mm 2 32-pin psdip case: 1376-02 9 x 28.5 mm 2 this document applies to parts marked with 2m53m. the 56f8006/56f8002 is a member of the 56800e core-based family of digital signal contro llers (dscs). it combines, on a single chip, the processing power of a dsp and the functionality of a microcontroller with a flexible set of peripherals to create a cost-eff ective solution. because of its low cost, configuration flex ibility, and compact program code, the 56f8006/56f8002 is well-suited for many applications. it includes many peripherals that are especially useful for cost-sensitive applications, including: ? industrial control ? home appliances ? smart sensors ? fire and security systems ? switched-mode power supply and power management ?power metering ? motor control (acim, bldc, pmsm, sr, and stepper) ? handheld power tools ? arc detection ? medical device/equipment ? instrumentation ? lighting ballast the 56800e core is based on a dual harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per in struction cycle. the mcu-style programming model and optimized instruction set allow straightforward generation of efficient, compact dsp and control code. the instruction set is also highly efficient for c compilers to enable rapid development of optimized control applications. the 56f8006/56f8002 supports program execution from internal memories. two data operands can be accessed from the on-chip data ram per instruction cycle. the 56f8006/56f8002 also offers up to 40 general-purpos e input/output (gpio) lines, depending on peripheral configuration. the 56f8006/56f8002 digital signal controller includes up to 16 kb of program flash and 2 kb of unified data/program ram. program flash memory can be independently bulk erased or erased in small pa ges of 512 bytes (256 words). on-chip features include: ? up to 32 mips at 32 mhz core frequency ? dsp and mcu functionality in a unified, c-efficient architecture ? on-chip memory ? 56f8006: 16 kb (8k x 16) flash memory ? 56f8002: 12 kb (6k x 16) flash memory ? 2 kb (1k x 16) unified data/program ram ? one 6-channel pwm module ? two 28-channel, 12-bit analog-to-digital converters (adcs) ? two programmable gain amplifiers (pga) with gain up to 32x ? three analog comparators ? one programmable interval timer (pit) ? one high-speed serial comm unication interface (sci) with lin slave functionality ? one serial peripheral interface (spi) ? one 16-bit dual timer (2 x 16 bit timers) ? one programmable delay block (pdb) ? one smbus compatible inter-integrated circuit (i 2 c) port ? one real time counter (rtc) ? computer operating properly (cop)/watchdog ? two on-chip relaxation oscillators ? 1 khz and 8 mhz (400 khz at standby mode) ? crystal oscillator ? integrated power-on reset (por) and low-voltage interrupt (lvi) module ? jtag/enhanced on-chip emulation (once?) for unobtrusive, real-time debugging ? up to 40 gpio lines ? 28-pin soic, 32-pin lqfp, 32-pin psdip, and 48-pin lqfp packages mc56f8006/mc56f8002 digital signal controller
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 2 table of contents 1 mc56f8006/mc56f8002 family configuration . . . . . . . . . . . .3 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3.1 56f8006/56f8002 features . . . . . . . . . . . . . . . . . . . . . .4 3.2 award-winning development environment. . . . . . . . . . .8 3.3 architecture block diagram. . . . . . . . . . . . . . . . . . . . . . .9 3.4 product documentation . . . . . . . . . . . . . . . . . . . . . . . .11 4 signal/connection descriptions . . . . . . . . . . . . . . . . . . . . . . .11 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.3 56f8006/56f8002 signal pins . . . . . . . . . . . . . . . . . . .17 5 memory maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.2 program map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.3 data map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 5.4 interrupt vector table and reset vector . . . . . . . . . . . .31 5.5 peripheral memory-mapped registers . . . . . . . . . . . . .32 5.6 eonce memory map . . . . . . . . . . . . . . . . . . . . . . . . . .33 6 general system control information . . . . . . . . . . . . . . . . . . .34 6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.2 power pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.3 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.4 on-chip clock synthesis . . . . . . . . . . . . . . . . . . . . . . . .34 6.5 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 6.6 system integration module (sim) . . . . . . . . . . . . . . . . .37 6.7 pwm, pdb, pga, and adc connections. . . . . . . . . . .38 6.8 joint test action group (jtag)/enhanced on-chip emulator (eonce) . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 7 security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 7.1 operation with security enabled. . . . . . . . . . . . . . . . . .40 7.2 flash access lock and unlock mechanisms . . . . . . . .40 7.3 product analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 8 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 8.1 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41 8.2 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . 42 8.3 thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . 43 8.4 recommended operating conditions . . . . . . . . . . . . . 45 8.5 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . 46 8.6 supply current characteristics . . . . . . . . . . . . . . . . . . 51 8.7 flash memory characteristics . . . . . . . . . . . . . . . . . . . 53 8.8 external clock operation timing. . . . . . . . . . . . . . . . . 53 8.9 phase locked loop timing . . . . . . . . . . . . . . . . . . . . . 54 8.10 relaxation oscillator timing . . . . . . . . . . . . . . . . . . . . 54 8.11 reset, stop, wait, mode select, and interrupt timing. 56 8.12 external oscillator (xosc) characteristics . . . . . . . . . 56 8.13 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . 57 8.14 cop specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.15 pga specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.16 adc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8.17 hscmp specifications . . . . . . . . . . . . . . . . . . . . . . . . 68 8.18 optimize power consumption . . . . . . . . . . . . . . . . . . . 68 9 design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.1 thermal design considerations . . . . . . . . . . . . . . . . . 70 9.2 electrical design considerations. . . . . . . . . . . . . . . . . 71 9.3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10 package mechanical outline drawings . . . . . . . . . . . . . . . . . 73 10.1 28-pin soic package . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.2 32-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.3 48-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.4 32-pin psdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 appendix a interrupt vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 appendix b peripheral register memory map and reset value . . . . . . . 86
mc56f8006/mc56f8002 family configuration mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 3 1 mc56f8006/mc56f8002 family configuration mc56f8006/mc56f8002 device comparison in table 1 . table 1. mc56f8006 series device comparison feature mc56f8006 mc56f8002 28-pin 32-pin 48-pin 28-pin flash memory size (kbytes) 16 12 ram size (kbytes) 2 analog comparators (acmp) 3 analog-to-digital converters (adc) 2 unshielded adc inputs 6776 shielded adc inputs 9 11 17 9 total number of adc input pins 1 1 some adc inputs share the same pin. see ta b l e 4 . 15 18 24 15 programmable gain amplifiers (pga) 2 pulse-width modulator (pwm) outputs 6 pwm fault inputs 3443 inter-integrated circuit (iic) 1 serial peripheral interface (spi) 1 high speed serial communications interface (sci) 1 programmable interrupt timer (pit) 1 programmable delay block (pdb) 1 16-bit multi-purpose timers (tmr) 2 real-time counter (rtc) 1 computer operating properly (cop) timer yes phase-locked loop (pll) yes 1 khz on-chip oscillator yes 8 mhz (400 khz at standby mode) on-chip rosc yes crystal oscillator yes power management controller (pmc) yes ieee 1149.1 joint test action group (jtag) interface yes enhanced on-chip emulator (eonce) ieee 1149.1 joint test action group (jtag) interface ye s
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 block diagram freescale semiconductor 4 2 block diagram figure 1 shows a top-level block diagram of the mc56f8006/mc56f8002 digital signal controller. package options for this family are described later in this document. italics indicate a 56f8002 device parameter. figure 1. mc56f8006/mc56f8002 block diagram 3 overview 3.1 56f8006/56f8002 features 3.1.1 core ? efficient 16-bit 56800e family digital signal controller (dsc) engine with dual harvard architecture ? as many as 32 million instructions per second (mips) at 32 mhz core frequency ? 155 basic instructions in conjunction with up to 20 address modes ? single-cycle 16 ? 16-bit parallel multiplier-accumulator (mac) ? four 36-bit accumulators, including extension bits ? 32-bit arithmetic and logic multi-bit shifter program controller and hardware looping unit data alu 16 x 16 + 36 ? 36-bit mac three 16-bit input registers four 36-bit accumulators address generation unit bit manipulation unit 16-bit 56800e core interrupt controller 4 unified data / program ram 2kb pdb cdbr spi ipbus bridge r/w control memory pa b cdbw jtag/eonce port or gpiod digital reg analog reg low-voltage supervisor v dd v ss v dda v ssa 4 reset 6 dual gp timer adca 4 24 total clock generator* system integration module rosc pwm outputs pwm cop/ watchdog adcb flash memory 16 kbytes flash 12 kbytes flash pga/adc sci 2 3 cmp0 2 cmp2 2 cmp or gpiod cmp1 2 crystal oscillator power management controller programmable i 2 c 2 pit delay block 3 40 gpio are muxed with all other func pins. pmc 3 fault inputs pdb xab1 xab2 system bus control pa b cdbr cdbw xdb2 osc rtc note: all pins are muxed with other peripheral pins. 2
overview mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 5 ? parallel instruction set with unique dsp addressing modes ? hardware do and rep loops ? three internal address buses ? four internal data buses ? instruction set supports dsp and controller functions ? controller-style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stack with depth limited only by memory ? jtag/enhanced on-chip emulation (eonce) for unobtrusive, processor speed?independent, real-time debugging 3.1.2 operation range ? 1.8 v to 3.6 v operation (power supplies and i/o) ? from power-on-reset: approximately 1.9 v to 3.6 v ? ambient temperature operating range: ? ?40 c to 125 c 3.1.3 memory ? dual harvard architecture permits as many as thr ee simultaneous accesses to program and data memory ? flash security and protection that prevent unauthorized users from ga ining access to the internal flash ? on-chip memory ? 16 kb of program flash for 56f8006 and 12 kb of program flash for 56f8002 ? 2 kb of unified data/program ram ? eeprom emulation capability using flash 3.1.4 interrupt controller ? five interrupt priority levels ? three user programmable priority levels for each interrupt source: level 0, 1, 2 ? unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, swi3 instruction. maskable level 3 interrupts include: eo nce step counter, eonce breakpoint unit, eonce trace buffer ? lowest-priority software interrupt: level lp ? allow nested interrupt that higher priority level interrup t request can interrupt lower priority interrupt subroutine ? the masking of interrupt priority level is managed by the 56800e core ? one programmable fast interrupt that can be assigned to any interrupt source ? notification to system integration module (sim) to restart clock out of wait and stop states ? ability to relocate interrupt vector table 3.1.5 peripheral highlights ? one multi-function, six-output pulse width modulator (pwm) module ? up to 96 mhz pwm operating clock ? 15 bits of resolution ? center-aligned and edge-aligned pwm signal mode ? phase shifting pwm pulse generation
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 overview freescale semiconductor 6 ? four programmable fault inputs with programmable digital filter ? double-buffered pwm registers ? separate deadtime insertions for rising and falling edges ? separate top and bottom pulse-width correction by means of software ? asymmetric pwm output within both center aligned and edge aligned operation ? separate top and botto m polarity control ? each complementary pwm signal pair allows selection of a pwm supply source from: ? pwm generator ? internal timers ? analog comparator outputs ? two independent 12-bit analog-to-digital converters (adcs) ? 2 x 14 channel external inputs plus seven internal inputs ? support simultaneous and software triggering conversions ? adc conversions can be synchronized by pwm and pdb modules ? sampling rate up to 400 ksps for 10- or 12-bit conversion result; 470 ksps for 8-bit conversion result ? two 16-word result registers ? two programmable gain amplifier (pgas) ? each pga is designed to am plify and convert diff erential signals to a single-ende d value fed to one of the adc inputs ? 1x, 2x, 4x, 8x, 16x, or 32x gain ? software and hardware triggers are available ? integrated sample/hold circuit ? includes additional calibration features: ? offset calibration eliminates any errors in the internal reference used to generate the vdda/2 output center point ? gain calibration can be used to veri fy the gain of the overall datapath ? both features require software correction of the adc result ? three analog comparators (cmps) ? selectable input source includes external pins, internal dacs ? programmable output polarity ? output can drive timer input, pwm fault input, pwm source, external pin output, and trigger adcs ? output falling and rising edge detection able to generate interrupts ? one dual channel 16-bit multi-purpose timer module (tmr) ? two independent 16-bit counter/timers with cascading capability ? up to 96 mhz operating clock ? each timer has capture and compare and quadrature decoder capability ? up to 12 operating modes ? four external inputs an d two external outputs ? one serial communicatio n interface (sci) with lin slave functionality ? up to 96 mhz operating clock ? full-duplex or single-wire operation ? programmable 8- or 9- bit data format ? two receiver wakeup methods: ? idle line ? address mark
overview mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 7 ? 1/16 bit-time noise detection ? one serial peripheral interface (spi) ? full-duplex operation ? master and slave modes ? programmable length transactions (2 to 16 bits) ? programmable transmit and recei ve shift order (msb as fi rst or last bit transmitted) ? maximum slave module frequency = module clock frequency/2 ? one inter-integrated circuit (i 2 c) port ? operates up to 400 kbps ? supports master and slave operation ? supports 10-bit address mode and broadcasting mode ? supports smbus, version 2 ? one 16-bit programmable interval timer (pit) ? 16 bit counter with programmable counter modulo ? interrupt capability ? one 16-bit programmable delay block (pdb) ? 16 bit counter with programmable counter modulo and delay time ? counter is initiated by positive transition of internal or external trigger pulse ? supports two independently controlled delay pulses used to synchronize pga and adc conversions with input trigger event ? two pdb outputs can be ored together to schedule two conversions from one input trigger event ? pdb outputs can be can be used to schedule precise edge placement for a pulsed output that generates the control signal for the cmp windowing comparison ? supports continuous or single shot mode ? bypass mode supported ? computer operating properly (cop)/watchdog time r capable of selecting different clock sources ? programmable prescaler and timeout period ? programmable wait, stop, and partial powerdown mode operation ? causes loss of reference reset 128 cycles after loss of reference clock to the pll is detected ? choice of clock sources from four sources in support of en60730 and iec61508: ? on-chip relaxation oscillator ? external crystal oscillat or/external clock source ? system clock (ipbus up to 32 mhz) ? on-chip low power 1 khz oscillator ? real-timer counter (rtc) ? 8-bit up-counter ? three software selectable clock sources ? external crystal oscillat or/external clock source ? on-chip low-power 1 khz oscillator ? system bus (ipbus up to 32 mhz) ? can signal the device to exit power down mode ? phase lock loop (pll) provides a high- speed clock to the co re and peripherals ? provides 3x system clock to pwm and dual timer and sci ? loss of lock interrupt ? loss of reference clock interrupt
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 overview freescale semiconductor 8 ? clock sources ? on-chip relaxation oscillator with two user selectab le frequencies: 400 khz for low speed mode, 8 mhz for normal operation ? on-chip low-power 1 khz oscillator can be se lected as clock source to the rtc and/or cop ? external clock: crystal oscillator, ceram ic resonator, and external clock source ? power management controller (pmc) ? on-chip regulator for digital and analog circuitry to lower cost and reduce noise ? integrated power-on reset (por) ? low-voltage interrupt with a user select able trip voltage of 1.81 v or 2.31 v ? user selectable brown-out reset ? run, wait, and stop modes ? low-power run, wait, and stop modes ? partial power down mode ? up to 40 general-purpose i/o (gpio) pins ? individual control for each pin to be in peripheral or gpio mode ? individual input/output direction control for each pin in gpio mode ? hysteresis and configurable pullup device on all input pins ? configurable slew rate and drive strength and optional input low pass filters on all output pins ? 20 ma sink/source current ? jtag/eonce debug programming interface for real-time debugging ? ieee 1149.1 joint test action group (jtag) interface ? eonce interface for real-time debugging 3.1.6 power saving features ? three low power modes ? low-speed run, wait, and stop modes: 200 khz ip bus clock provided by rosc ? low-power run, wait, and stop modes: cl ock provided by external 32?38.4 khz crystal ? partial power down mode ? low power external oscillator can be used in any low-power mode to provi de accurate clock to active peripherals ? low power real time counter for use in run, wait, and stop modes with internal and external clock sources ? 32 ? s typical wakeup time from partial power down modes ? each peripheral can be indivi dually disabled to save power 3.2 award-winning development environment processor expert tm (pe) provides a rapid application design (rad) t ool that combines easy-to-use component-based software application creation with an expert knowledge system. the codewarrior integrated development environment is a sophisticated tool for code navigation, compiling, and debugging. a complete set of evaluation modules (evms), demonstration bo ard kit, and development system cards support concurrent engineering. together, pe, codewarrior, and evms create a complete, scalable tool s solution for easy, fast, and efficient development. a full set of programmable peripherals ? pwm, pgas, adcs, sci, spi, i 2 c, pit, timers, and analog comparators ? supports various applications. each peripheral can be independently shut do wn to save power. any pin in these peripherals can also be used as general-purpose input/outputs (gpios).
overview mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 9 3.3 architecture block diagram the 56f8006/56f8002?s architecture is shown in figure 2 and figure 3 . figure 2 illustrates how the 56800e system buses communicate with internal memories and the ipbus interface a nd the internal connections among each unit of the 56800e core. figure 3 shows the peripherals and control blocks connected to the ipbus bridge. please see the system integration module (sim) section in the mc56f8006 reference manual for information about which signals are multiplexed with those of other peripherals. figure 2. 56800e core block diagram data dsp56800e core arithmetic logic unit (alu) xab2 pab pdb cdbw cdbr xdb2 program memory data/ ipbus interface bit- manipulation unit n3 m01 address xab1 generation unit (agu) pc la la2 hws0 hws1 fira omr sr fisr lc lc2 instruction decoder interrupt unit looping unit program control unit alu1 alu2 mac and alu a1 a2 a0 b1 b2 b0 c1 c2 c0 d1 d2 d0 y1 y0 x0 enhanced jtag tap r2 r3 r4 r5 sp r0 r1 n y multi-bit shifter once? program ram
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 overview freescale semiconductor 10 figure 3. peripheral subsystem second clcok source reste gpioa7 gpioa6 gpioa5 gpioa4 gpioa3 gpioa2 gpioa1 gpioa0 port a gpiob7 gpiob6 gpiob5 gpiob4 gpiob3 gpiob2 gpiob1 gpiob0 port b gpioc7 gpioc6 gpioc5 gpioc4 gpioc3 gpioc2 gpioc1 gpioc0 port c gpiod3 gpiod2 gpiod1 gpiod0 port d pdb i2c pwm cmp2 adca pga0 ana15 adcb pga1 anb15 cmp1 cmp0 pwm input mux dual timer (tmr) sci spi sim rtc pmc intc cop occs cosc rosc crystal 1khz system clock ipbus bridge gpio mux gpiof3 gpiof2 gpiof1 gpiof0 port f gpioe7 gpioe6 gpioe5 gpioe4 gpioe3 gpioe2 gpioe1 gpioe0 port e pwm synch trigger a trigger b pretrigger a pretrigger b
signal/connection descriptions mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 11 3.4 product documentation the documents listed in table 2 are required for a complete description and proper design with the 56f8006/56f8002. documentation is available from local freescale distributo rs, freescale semiconductor sales offices, freescale literature distribution centers, or online at http://www.freescale.com . 4 signal/connection descriptions 4.1 introduction the input and output signals of the 56f8006/56f8002 are organized into functional groups, as detailed in table 3 . table 4 summarizes all device pins. in table 4 , each table row describes the signal or sign als present on a pin, sorted by pin number. table 2. 56f8006/56f8002 device documentation topic description order number dsp56800e reference manual detailed description of the 56800e family architecture, 16-bit digital signal controller core processor, and the instruction set dsp56800erm 56f800x peripheral reference manual detailed description of peripherals of the 56f8006 and 56f8002 devices mc56f8006rm 56f80x serial bootloader user guide detailed description of the serial bootloader in the 56f800x family of devices tbd 56f8006/56f8002 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions (this document) mc56f8006 56f8006/56f8002 errata details any chip issues that might be present mc56f8006e table 3. functional group pin allocations functional group number of pins in 28 soic number of pins in 32 lqfp number of pins in 32 psdip number of pins in 48 lqfp power inputs (v dd , v dda ) 2224 ground (v ss , v ssa ) 3334 reset 1 1 pins may be shared with other peripherals. see ta b l e 4 . 1111 pulse width modulator (pwm) ports 1 10 12 12 12 serial peripheral interface (spi) ports 1 5777 serial communications interface 0 (sci) ports 1 4555 inter-integrated circuit interface (i 2 c) ports 1 6777 analog-to-digital converter (adc) inputs 1 16 18 18 24 high speed analog comparator inputs 1 13 15 15 25 programmable gain amplifiers (pga) 1 4444 dual timer module (tmr) ports 1 8 101010 programmable delay block (pdb) 1 ??? 1 clock 1 5555 jtag/enhanced on-chip emulation (eonce 1 )4444
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 signal/connect ion descriptions freescale semiconductor 12 in table 4 , peripheral pins in bold identify reset state. table 4. 56f8006/56f8002 pins pin number pin name peripherals 28 soic 32 lqfp 32 psdip 48 lqfp gpio i 2 c sci spi adc pga comp dual timer pwm power and ground jtag misc. 261291gpiob6 /rxd/sda/ana13 and cmp0_p2/clkin b6 sda rxd ana13 1 cmp0_p2 clkin 272302gpiob1 /ss /sda/ana12 andcmp2_p3 b1 sda ss ana12 1 cmp2_p3 3313gpiob7 /txd/scl/ana11 and cmp2_m3 b7 scl txd ana11 1 cmp2_m3 4324gpiob5 /t1/fault3/sclk b5 sclk t1 fault3 5gpioe0e0 6gpioe1 /anb9 and cmp0_p1 e1 anb9 1 cmp0_p1 28 5 1 7 anb8 and pga1+ and cmp0_m2/ gpioc4 c4 anb8 1 pga1+ cmp0_m2 8gpioe2 /anb7 and cmp0_m1 e2 anb7 1 cmp0_m1 1 6 2 9 anb6 and pga1? and cmp0_p4/ gpioc5 c5 anb6 1 pga1? cmp0_p4 10 gpioc7 /anb5 and cmp1_m2 c7 anb5 1 cmp1_m2 2 7 3 11 anb4 and cmp1_p1 /gpioc6/pwm2 c6 anb4 1 cmp1_p1 pwm2 38 412 v dda v dda 49 513 v ssa v ssa 14 gpioe3 /ana10 and cmp2_m1 e3 ana10 1 cmp2_m1 5 10 6 15 ana9 and pga0? and cmp2_p4/ gpioc2 c2 ana9 1 pga0? cmp2_p4 16 gpioe5/ ana8 and cmp2_p1 e5 ana8 1 cmp2_p1 6 11 7 17 ana7 and pga0+ and cmp2_m2/ gpioc1 c1 ana7 1 pga0+ cmp2_m2 18 gpioe4/ana6 and cmp2_p2 e4 ana6 1 cmp2_p2 7 12 8 19 ana5 and cmp1_m1/ gpioc0/fault0 c0 ana5 1 cmp1_m1 fault0 813 9 20 v ss v ss 21 v dd v dd 9141022 tck/ gpiod2/ana4 and cmp1_p2/cmp2_out d2 ana4 1 cmp1_p2, cmp2_out tck 10 15 11 23 reset / gpioa7 a7 reset 11 16 12 24 gpiob3/ mosi/tin3/ana3 and anb3/pwm5/cmp1_out b3 mosi ana3 1 and anb3 1 cmp1_out tin3 pwm5 17 13 25 gpiob2 /miso/tin2/ana2 and anb2/cmp0_out b2 miso ana2 and anb2 cmp0_out tin2 12 18 14 26 gpioa6/ fault0/ana1 and anb1/scl/txd/clko_1 a6 scl txd ana1 and anb1 fault0 clko_1 13 19 15 27 gpiob4/ t0/clko_0/miso/ sda/rxd/ana0 and anb0 b4 sda rxd miso ana0 and anb0 t0 clko_0
signal/connection descriptions mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 13 4.2 pin assignment mc56f8006 and mc56f8002 28-pin small outlin e ic (28soic) assignment is shown in figure 4 ; mc56f8006 32-pin low-profile quad flat pack (32lqfp) is shown in figure 5 ; mc56f8006 32-pin plastic shrink dual in-line package (psdip) is shown in figure 6 ; mc56f8006 48-pin low-profile quad flat pack (48lqfp) is shown in figure 7 . 28 gpioe6 e6 14 20 16 29 gpioa5/ pwm5/fault2 or ext_sync/tin3 a5 tin3 pwm5, fault2 or ext_ sync 30 v ss v ss 31 v dd v dd 15 21 17 32 gpiob0/ sclk/scl/anb13/ pwm3/t1 b0 scl sclk anb13 t1 pwm3 16 22 18 33 gpioa4/ pwm4/sda/fault1 /tin2 a4 sda tin2 pwm4, fault1 34 gpioe7/ cmp1_m3 e7 cmp1_m3 23 19 35 gpioa2 /pwm2 a2 pwm2 17 24 20 36 gpioa3/ pwm3/txd/extal a3 txd pwm3 extal 18 25 21 37 gpiof0 /xtal f0 xtal 19 26 22 38 v dd v dd 20 27 23 39 v ss v ss 40 gpiof1 /cmp1_p3 f1 cmp1_p3 41 gpiof2 /cmp0_m3 f2 cmp0_m3 42 gpiof3 /cmp0_p3 f3 cmp0_p3 21 28 24 43 gpioa1 /pwm1 a1 pwm1 22 29 25 44 gpioa0 /pwm0 a0 pwm0 23 30 26 45 tdi /gpiod0/anb12/ss / tin2/cmp0_out d0 ss anb12 cmp0_out tin2 tdi 46 gpioc3/ ext_trigger c3 ext_ trgger 24 31 27 47 tms/ gpiod3/anb11/t1/ cmp1_out d3 anb11 cmp1_out t1 tms 25 32 28 48 tdo / gpiod1/anb10/t0/ cmp2_out d1 anb10 cmp2_out t0 tdo 1 shielded adc input. table 4. 56f8006/56f8002 pins (continued) pin number pin name peripherals 28 soic 32 lqfp 32 psdip 48 lqfp gpio i 2 c sci spi adc pga comp dual timer pwm power and ground jtag misc.
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 signal/connect ion descriptions freescale semiconductor 14 figure 4. top view, mc56f8006/mc56f8002 28-pin soic package anb6 & pga1? & cmp0_p4/gpioc5 anb4 & cmp1_p1/gpioc6/pwm2 v dda v ssa ana9 & pga0? & cmp2_p4/gpioc2 ana7 & pga0+ & cmp2_m2/gpioc1 ana5 and cmp1_m1/gpioc0/fault0 v ss tck/gpiod2/ana4 & cmp1_p2/cmp2_out reset /gpioa7 gpiob3/mosi/tin3/ana3 & anb3/pwm5/cmp1_out gpioa6/fault0/ana1 & anb1/scl/txd/clko_1 gpiob4/t0/clko_0/miso/sda/rxd/ana0 & anb0 gpioa5/pwm5/fault2 or ext_sync/tin3 anb8 & pga1+ & cmp0_m2/gpioc4 gpiob1/ss /sda/ana12 & cmp2_p3 gpiob6/rxd/sda/ana13 & cmp0_p2/clkin tdo/gpiod1/anb10/t0/cmp2_out tms/gpiod3/anb11/t1/cmp1_out tdi/gpiod0/anb12/ss /tin2/cmp0_out gpioa0/pwm0 gpioa1/pwm1 v ss v dd gpiof0/xtal gpioa3/pwm3/txd/extal gpioa4/pwm4/sda/fault1/tin2 gpiob0/sclk/scl/anb13/pwm3/t1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
signal/connection descriptions mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 15 figure 5. top view, mc56f8006 32-pin lqfp package orientation mark gpiob6/rxd/sda/ana13 & cmp0_p2/clkin gpiob1/ss /sda/ana12 & cmp2_p3 gpiob7/txd/scl/ana11 & cmp2_m3 gpiob5/t1/fault3/sclk anb8 and pga1+ & cmp0_m2/gpioc4 anb6 and pga1? & cmp0_p4/gpioc5 anb4 & cmp1_p1/gpioc6/pwm2 v dda v ssa ana9 and pga0? & cmp2_p4/gpioc2 ana7 and pga0+ & cmp2_m2/gpioc1 ana5 and cmp1_m1/gpioc0/fault0 v ss tck/gpiod2/ana4 & cmp1_p2/cmp2_out reset /gpioa7 gpiob3/mosi/tin3/ana3 & anb3/pwm5/cmp1_out gpioa3/pwm3/txd/extal gpioa2/pwm2 gpiob0/sclk/scl/anb13/pwm3/t1 gpioa5/pwm5/fault2 or ext_sync/tin3 gpiob4/t0/clko_0/miso/sda/rxd/ana0 & anb0 gpioa6/fault0/ana1 & anb1/scl/txd/clko_1 gpiob2/miso/tin2/ana2 & anb2/cmp0_out tdo/gpiod1/anb10/t0/cmp2_out tms/gpiod3/anb11/t1/cmp1_out tdi/gpiod0/anb12/ss /tin2/cmp0_out gpioa0/pwm0 gpioa1/pwm1 v ss v dd gpiof0/xtal gpioa4/pwm4/sda/fault1/tin2 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 signal/connect ion descriptions freescale semiconductor 16 figure 6. top view, mc56f8006 32-pin psdip package !."and0'!#-0?-'0)/# !."and0'!n#-0?0'0)/# !."#-0?0'0)/#07- 6$$! 633! !.!0'!n#-0?0'0)/# !.!0'!#-0?-'0)/# !.!#-0?-'0)/#&!5,4 633 4#+'0)/$!.!#-0?0#-0?/54 2%3%4'0)/! '0)/"-/3)4).!.!!."07-#-0?/54 '0)/"-)3/4).!.!!."#-0?/54 '0)/!&!5,4!.!!."3#,48$#,+/? '0)/"4#,+/?-)3/3$!28$!.!!." '0)/!07-&!5,4or%84?39.#4). '0)/"4&!5,43#,+ '0)/"48$3#,!.!#-0?- '0)/"333$!!.!#-0?0 '0)/"28$3$!!.!#-0?0#,+). 4$/'0)/$!."4#-0?/54 4-3'0)/$!."4#-0?/54 4$)'0)/$!."334).#-0?/54 '0)/!07- '0)/!07- 633 6$$ '0)/&84!, '0)/!07-48$%84!, '0)/!07- '0)/!07-3$!&!5,44). '0)/"3#,+3#,!."07-4
signal/connection descriptions mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 17 figure 7. top view, mc56f8006 48-pin lqfp package 4.3 56f8006/56f8002 signal pins after reset, each pin is configured for it s primary function (listed firs t). any alternate fu nctionality must be programmed via the gpio module?s peripheral enable register s (gpio_x_per) and sim module?s (gps_xn) gpio peripheral sel ect registers. if clkin or xtal is selected as device exte rnal clock input, the clk_mod bit in the occs oscillator control register (osctl) needs to be set too. ext_sel bit in osctl selects clkin or xtal. orientation mark gpiob6/rxd/sda/ana13 & cmp0_p2/clkin gpiob1/ss /sda/ana12 & cmp2_p3 gpiob7/txd/scl/ana11 & cmp2_m3 gpiob5/t1/fault3/sclk anb8 and pga1+ & cmp0_m2/gpioc4 anb6 and pga1? & cmp0_p4/gpioc5 anb4 & cmp1_p1/gpioc6/pwm2 v dda v ssa ana9 and pga0? & cmp2_p4/gpioc2 ana7 & pga0+ & cmp2_m2/gpioc1 ana5 & cmp1_m1/gpioc0/fault0 v ss tck/gpiod2/ana4 & cmp1_p2/cmp2_out reset /gpioa7 gpiob3/mosi/tin3/ana3 & anb3/pwm5/cmp1_out gpioa3/pwm3/txd/extal gpioa2/pwm2 gpiob0/sclk/scl/anb13/pwm3/t1 gpioa5/pwm5/fault2 or ext_sync/tin3 gpiob4/t0/clko_0/miso/sda/rxd/ana0 & anb0 gpioa6/fault0/ana1 & anb1/scl/txd/clko_1 gpiob2/miso/tin2/ana2 & anb2/cmp0_out tdo/gpiod1/anb10/t0/cmp2_out tms/gpiod3/anb11/t1/cmp1_out tdi/gpiod0/anb12/ss /tin2/cmp0_out gpioa0/pwm0 gpioa1/pwm1 v ss v dd gpiof0/xtal gpioa4/pwm4/sda/fault1/tin2 gpioe0 gpioe1/anb9 & cmp0_p1 gpioe2/anb7 & cmp0_m1 gpioc7/anb5 & cmp1_m2 gpioe3/ana10 & cmp2_m1 gpioe5/ana8 & cmp2_p1 gpioe4/ana6 & cmp2_p2 v dd vss gpioe6 v dd gpioe7/cmp1_m3 gpiof3/cmp0_p3 gpiof2/cmp0_m3 gpiof1/cmp1_p3 gpioc3/ext_trigger 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 signal/connect ion descriptions freescale semiconductor 18 table 5. 56f8006/56f8002 signal and package information signal name 28 soic 32 lqfp 32 psdi p 48 lqfp type state during reset signal description v dd 21 supply supply i/o power ? this pin supplies 3.3 v power to the chip i/o interface. v dd 31 v dd 19 26 22 38 v ss 8 13 9 20 supply supply i/o ground ? these pins provide ground for chip i/o interface. v ss 30 v ss 20 27 23 39 v dda 3 8 4 12 supply supply analog power ? this pin supplies 3.3 v power to the analog modules. it must be connected to a clean analog power supply. v ssa 4 9 5 13 supply supply analog ground ? this pin supplies an analog ground to the analog modules. it must be connected to a clean power supply. reset (gpioa7) 10 15 11 23 input input/ output input, internal pullup enabled reset ? this input is a direct hardware reset on the processor. when reset is asserted low, the device is initialized and placed in the reset state. a schmitt-trigger input is used for noise immunity. the internal reset signal is deasserted synchronous with the internal clocks after a fixed number of internal clocks. port a gpio ? this gpio pin can be individually programmed as an input or output pin. reset functionality is disabled in this mode and the chip can be reset only vi a por, cop reset, or software reset. after reset, the default state is reset . gpioa0 (pwm0) 22 29 25 44 input/ output output input, internal pullup enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. pwm0 ? the pwm channel 0. after reset, the default state is gpioa0. gpioa1 (pwm1) 21 28 24 43 input/ output output input, internal pullup enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. pwm1 ? the pwm channel 1. after reset, the default state is gpioa1. gpioa2 (pwm2) 23 19 35 input/ output output input, internal pullup enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. pwm2 ? the pwm channel 2. after reset, the default state is gpioa2.
signal/connection descriptions mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 19 gpioa3 (pwm3) (txd) (extal) 17 24 20 36 input/ output output output analog input input, internal pullup enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. pwm3 ? the pwm channel 3. txd ? the sci transmit data outpu t or transmit/receive in single wire operation. extal ? external crystal oscill ator input. this input can be connected to a 32.768 khz or 1?16 mhz external crystal or ceramic resonator. when used to supply a source to the internal pll, the crystal/resonator must be in the 4 mhz to 8 mhz range. tie this pin low or configure as gpio if xtal is being driven by an external clock source. if using a 32.768 khz crystal, place the crystal as close as possible to device pins to speed startup. after reset, the default state is gpioa3. gpioa4 (pwm4) (sda) (fault1) (tin2) 16 22 18 33 input/ output output input/open- drain output input input input, internal pullup enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. pwm4 ? the pwm channel 4. sda ? the i 2 c serial data line. fault1 ? pwm fault input 1used for disabling selected pwm outputs in cases where fault conditions originate off-chip. tin2 ? dual timer module channel 2 input after reset, the default state is gpioa4. gpioa5 (pwm5) (fault2/ ext_sync) (tin3) 14 20 16 29 input/ output output input/ output input input, internal pullup enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. pwm5 ? the pwm channel 5. fault2 ? pwm fault input 2 used for disabling selected pwm outputs in cases where fault conditions originate off-chip. ext_sync ? when not being used as a fault input, this pin can be used to receive a pulse to reset the pwm counter or to generate a positive pulse at the start of every pwm cycle. tin3 ? dual timer module channel 3 input after reset, the default state is gpioa5. table 5. 56f8006/56f8002 signal and package information (continued) signal name 28 soic 32 lqfp 32 psdi p 48 lqfp type state during reset signal description
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 signal/connect ion descriptions freescale semiconductor 20 gpioa6 (fault0) (ana1 & anb1) (scl) (txd) (clko_1) 12 18 14 26 input/ output input analog input input/open- drain output output output input, internal pullup enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. fault0 ? pwm fault input 0 used for disabling selected pwm outputs in cases where fault conditions originate off-chip. ana1 and anb1 ? analog input to channel 1 of adca and adcb. scl ? the i 2 c serial clock txd ? the sci transmit data outpu t or transmit/receive in single wire operation. clko_1 ? this is a buffered clock output; the clock source is selected by clockout select (clk osel) bits in the clock output select register (clk out) in the sim. when used as an analog input, the signal goes to the ana1 and anb1. after reset, the default state is gpioa6. gpiob0 (sclk) (scl) (anb13) (pwm3) (t1) 15 21 17 32 input/ output input/ output input/open- drain output analog input output input/ output input, internal pullup enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. sclk ? the spi serial clock. in master mode, this pin serves as an output, clocking slaved listeners. in slave mode, this pin serves as the data clock input. scl ? the i 2 c serial clock. anb13 ? analog input to channel 13 of adcb pwm3 ? the pwm channel 3. t1 ? dual timer module channel 1 input/output. after reset, the default state is gpiob0. table 5. 56f8006/56f8002 signal and package information (continued) signal name 28 soic 32 lqfp 32 psdi p 48 lqfp type state during reset signal description
signal/connection descriptions mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 21 gpiob1 (ss ) (sda) (ana12 and cmp2_p3) 27 2 30 2 input/ output input/ output input/open- drain output analog input input, internal pullup enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. ss ? ss is used in slave mode to indicate to the spi module that the current transfer is to be received. sda ? the i 2 c serial data line. ana12 and cmp2_p3 ? analog input to channel 12 of adca and positive input 3 of analog comparator 2. when used as an analog input, the signal goes to the ana12 and cmp2_p3. after reset, the default state is gpiob1. gpiob2 (miso) (tin2) (ana2 and anb2) (cmp0_ out) 17 13 25 input/ output input/ output input/ output analog input output input, internal pullup enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. miso ? master in/slave out. in ma ster mode, this pin serves as the data input. in slave mode, this pin serves as the data output. the miso line of a slave device is plac ed in the high-impedance state if the slave device is not selected. tin2 ? dual timer module channel 2 input. ana2 and anb2 ? analog input to channel 2 of adca and adcb. cmp0_out? analog comparator 0 output. when used as an analog input, the signal goes to the ana2 and anb2. after reset, the default state is gpiob2. table 5. 56f8006/56f8002 signal and package information (continued) signal name 28 soic 32 lqfp 32 psdi p 48 lqfp type state during reset signal description
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 signal/connect ion descriptions freescale semiconductor 22 gpiob3 (mosi) (tin3) (ana3 and anb3) (pwm5) (cmp1_ out 11 16 12 24 input/ output input/ output input/ output input output output input, internal pullup enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. mosi ? master out/slave in. in mast er mode, this pin serves as the data output. in slave mode, this pin serves as the data input. tin3 ? dual timer module channel 3 input. ana3 and anb3 ? analog input to channel 3 of adca and adcb. pwm5 ? the pwm channel 5. cmp1_out? analog comparator 1 output. when used as an analog input, the signal goes to the ana3 and anb3. after reset, the default state is gpiob3. gpiob4 (t0) (clko_0) (miso) (sda) (rxd) (ana0 and anb0) 13 19 15 27 input/ output input/ output output input/ output input/open- drain output input analog input input, internal pullup enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. t0 ? dual timer module channel 0 input/output. clko_0 ? this is a buffered clock output; the clock source is selected by clockout select (clk osel) bits in the clock output select register (clkout) of the sim. miso ? master in/slave out. in ma ster mode, this pin serves as the data input. in slave mode, this pin serves as the data output. the miso line of a slave device is plac ed in the high-impedance state if the slave device is not selected. sda ? the i 2 c serial data line. rxd ? the sci receive data input. ana0 and anb0 ? analog input to channel 0 of adca and adcb. when used as an analog input, the signal goes to the ana0 and anb0. after reset, the default state is gpiob4. table 5. 56f8006/56f8002 signal and package information (continued) signal name 28 soic 32 lqfp 32 psdi p 48 lqfp type state during reset signal description
signal/connection descriptions mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 23 gpiob5 (t1) (fault3) (sclk) 4 32 4 input/ output input/ output input input input, internal pullup enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. t1 ? dual timer module channel 1 input/output. fault3 ? pwm fault input 3 used for disabling selected pwm outputs in cases where fault conditions originate off-chip. sclk ? spi serial clock. in master mode, this pin serves as an output, clocking slaved listeners. in slave mode, this pin serves as the data clock input. after reset, the default state is gpiob5. gpiob6 (sda) (ana13 and cmp0_p2) (clkin) 26 1 29 1 input/ output input/open- drain output analog input input input, internal pullup enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. sda ? the i 2 c serial data line. ana13 and cmp0_p2 ? analog input to channel 13 of adca and positive input 2 of analog comparator 0. external clock input ? this pin serves as an external clock input. when used as an analog input, the signal goes to the ana13 and cmp0_p2. after reset, the default state is gpiob6. gpiob7 (txd) (scl) (ana11 and cmp2_m3) 3 31 3 input/ output input/ output input/open- drain output analog input input, internal pullup enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. txd ? the sci transmit data outpu t or transmit/receive in single wire operation. scl ? the i 2 c serial clock. ana11 and cmp2_m3 ? analog input to channel 11 of adca and negative input 3 of analog comparator 2. when used as an analog input, the signal goes to the ana11 and cmp2_m3. after reset, the default state is gpiob7. table 5. 56f8006/56f8002 signal and package information (continued) signal name 28 soic 32 lqfp 32 psdi p 48 lqfp type state during reset signal description
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 signal/connect ion descriptions freescale semiconductor 24 ana5 and cmp1_m1 (gpioc0) (fault0) 7 12 8 19 analog input analog input input analog input ana5 and cmp1_m1? analog input to channel 5 of adca and negative input 1 of analog comparator 1. port c gpio ? this gpio pin can be individually programmed as an input or output pin. fault0 ? pwm fault input 0 is used for disabling selected pwm outputs in cases where fault conditions originate off-chip. when used as an analog input, the signal goes to the ana5 and cmp1_m1. after reset, the default state is ana5 and cmp1_m1. ana7 and pga0+ and cmp2_m2 (gpioc1) 6 11 7 17 analog input input/ output analog input ana7 and pga0+ and cmp2_m2 ? analog input to channel 7 of adca and pga0 positive input and negative input 2 of analog comparator 2. port c gpio ? this gpio pin can be individually programmed as an input or output pin. when used as an analog input, the signal goes to the ana7 and pga0+ and cmp2_m2. after reset, the default state is ana7 and pga0+ and cmp2_m2. ana9 and pga0? and cmp2_p4 (gpioc2) 5 10 6 15 analog input input/ output analog input ana9 and pga0? and cmp2_p4 ? analog input to channel 9 of adca and pga0 negative input and positive input 4 of analog comparator 2. port c gpio ? this gpio pin can be individually programmed as an input or output pin. when used as an analog input, the signal goes to the ana9 and pga0? and cmp2_p4. after reset, the default state is ana9 and pga0? and cmp2_p4. gpioc3 (ext_ trigger) 46 input/ output input input, internal pullup enabled port c gpio ? this gpio pin can be individually programmed as an input or output pin. ext_trigger ? pdb external trigger input. after reset, the default state is gpioc3. table 5. 56f8006/56f8002 signal and package information (continued) signal name 28 soic 32 lqfp 32 psdi p 48 lqfp type state during reset signal description
signal/connection descriptions mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 25 anb8 and pga1+ and cmp0_m2 (gpioc4) 28 5 1 7 analog input input/ output analog input anb8 and pga1+ and cmp0_m2 ? analog input to channel 8 of adcb and pga1 positive input and negative input 2 of analog comparator 0. port c gpio ? this gpio pin can be individually programmed as an input or output pin. when used as an analog input, the signal goes to the anb8 and pga1+ and cmp0_m2. after reset, the default state is anb8 and pga1+ and cmp0_m2. anb6 and pga1? and cmp0_p4 (gpioc5) 1 6 2 9 input/ output analog input analog input anb6 and pga1? and cmp0_p4 ? analog input to channel 6 of adcb and pga1 negative input and positive input 4 of analog comparator 0. port c gpio ? this gpio pin can be individually programmed as an input or output pin. when used as an analog input, the signal goes to the anb6 and pga1? and cmp0_p4. after reset, the default state is anb6 and pga1? and cmp0_p4. anb4 and cmp1_p1 (gpioc6) (pwm2) 2 7 3 11 analog input input/ output output analog input anb4 and cmp1_p1 ? analog input to channel 4 of adcb and positive input 1 of analog comparator 1. port c gpio ? this gpio pin can be individually programmed as an input or output pin. pwm2 ? the pwm channel 2. when used as an analog input, the signal goes to the anb4 and cmp1_p1. after reset, the default state is anb4 and cmp1_p1. gpioc7 (anb5 and cmp1_m2) 10 input/ output analog input input, internal pullup enabled port c gpio ? this gpio pin can be individually programmed as an input or output pin. anb5 and cmp1_m2 ? analog input to channel 5 of adcb and negative input 2 of analog comparator 1. after reset, the default state is gpioc7. table 5. 56f8006/56f8002 signal and package information (continued) signal name 28 soic 32 lqfp 32 psdi p 48 lqfp type state during reset signal description
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 signal/connect ion descriptions freescale semiconductor 26 tdi (gpiod0) (anb12) (ss ) (tin2) (cmp0_ out) 23 30 26 45 input input/ output analog input input input output input, internal pullup enabled test data input ? this input pin provides a serial input data stream to the jtag/eonce port. it is sampled on the rising edge of tck and has an on-chip pullup resistor. port d gpio ? this gpio pin can be individually programmed as an input or output pin. anb12 ? analog input to channel 12 of adcb ss ? ss is used in slave mode to indicate to the spi module that the current transfer is to be received. tin2 ? dual timer module channel 2 input. cmp1_out ? analog co mparator 1 output. after reset, the default state is tdi. tdo (gpiod1) (anb10) (t0) (cmp2_ out) 25 32 28 48 output input/ output analog input input/ output output output, tri-stated, internal pullup enabled test data output ? this three-stat eable output pin provides a serial output data stream from the jtag/eonce port. it is driven in the shift-ir and shift-dr controller states, and changes on the falling edge of tck. port d gpio ? this gpio pin can be individually programmed as an input or output pin. anb10 ? analog input to channel 10 of adcb. t0 ? dual timer module channel 0 input/output. cmp2_out ? analog co mparator 2 output. after reset, the default state is tdo. tck (gpiod2) (ana4 and cmp1_p2) (cmp2_ out) 9 14 10 22 input input/ output analog input output input, internal pullup enabled test clock input ? this input pin provides a gated clock to synchronize the test logic and shi ft serial data to the jtag/eonce port. the pin is connected internally to a pullup resistor. a schmitt-trigger input is used for noise immunity. port d gpio ? this gpio pin can be individually programmed as an input or output pin. ana4 and cmp1_p2 ? analog input to channel 4 of adca and positive input 2 of analog comparator 1. cmp2_out ? analog co mparator 2 output. after reset, the default state is tck. table 5. 56f8006/56f8002 signal and package information (continued) signal name 28 soic 32 lqfp 32 psdi p 48 lqfp type state during reset signal description
signal/connection descriptions mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 27 tms (gpiod3) (anb11) (t1) (cmp1_ out) 24 31 27 47 input input/ output analog input input/ output output input, internal pullup enabled test mode select input ? this input pin is used to sequence the jtag tap controller?s state machine. it is sampled on the rising edge of tck and has an on-chip pullup resistor. port d gpio ? this gpio pin can be individually programmed as an input or output pin. anb11 ? analog input to channel 11 of adcb. t1 ? dual timer module channel 1 input/output. cmp1_out ? analog co mparator 2 output. after reset, the default state is tms. always tie the tms pin to vdd through a 2.2 k ? resistor. gpioe0 5 input/ output input, internal pullup enabled port e gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is gpioe0. gpioe1 (anb9 and cmp0_p1) 6 input/ output analog input input, internal pullup enabled port e gpio ? this gpio pin can be individually programmed as an input or output pin. anb9 and cmp0_p1 ? analog input to channel 9 of adcb and positive input 1 of analog comparator 0. after reset, the default state is gpioe1. gpioe2 (anb7 and cmp0_m1) 8 input/ output analog input input, internal pullup enabled port e gpio ? this gpio pin can be individually programmed as an input or output pin. anb7 and cmp0_m1 ? analog input to channel 7 of adcb and negative input 1 of analog comparator 0. after reset, the default state is gpioe2. gpioe3 (ana10 and cmp2_m1) 14 input/ output analog input input, internal pullup enabled port e gpio ? this gpio pin can be individually programmed as an input or output pin. ana10 and cmp2_m1 ? analog input to channel 10 of adca and negative input 1 of analog comparator 2. after reset, the default state is gpioe3. gpioe4 (ana6 and cmp2_p2) 18 input/ output analog input input, internal pullup enabled port e gpio ? this gpio pin can be individually programmed as an input or output pin. ana6 and cmp2_p2 ? analog input to channel 6 of adca and positive input 2 of analog comparator 2. after reset, the default state is gpioe4. table 5. 56f8006/56f8002 signal and package information (continued) signal name 28 soic 32 lqfp 32 psdi p 48 lqfp type state during reset signal description
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 signal/connect ion descriptions freescale semiconductor 28 gpioe5 (ana8 and cmp2_p1) 16 input/ output analog input input, internal pullup enabled port e gpio ? this gpio pin can be individually programmed as an input or output pin. ana8 and cmp2_p1? analog input to channel 8 of adca and positive input 1 of analog comparator 2. after reset, the default state is gpioe5. gpioe6 28 input/ output input, internal pullup enable port e gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is gpioe6. gpioe7 (cmp1_m3) 34 input/ output analog input input, internal pullup enabled port e gpio ? this gpio pin can be individually programmed as an input or output pin cmp1_m3 ? analog input to both negative input 3 of analog comparator 1. after reset, the default state is gpioe7. gpiof0 (xtal) 18 25 21 37 input/ output analog input/ output input, internal pullup enabled port f gpio ? this gpio pin can be individually programmed as an input or output pin. xtal ? external crystal oscillator output. this output connects the internal crystal oscillator output to an external crystal or ceramic resonator. after reset, the default state is gpiof0. gpiof1 (cmp1_p3) 40 input/ output analog input input, internal pullup enabled port f gpio ? this gpio pin can be individually programmed as an input or output pin cmp1_p3 ? analog input to both positive input 3 of analog comparator 1. after reset, the default state is gpiof1 gpiof2 (cmp0_m3) 41 input/ output analog input input, internal pullup enabled port f gpio ? this gpio pin can be individually programmed as an input or output pin. cmp0_m3 ? analog input to both negative input 3 of analog comparator 0. after reset, the default state is gpiof2. gpiof3 (cmp0_p3) 42 input/ output analog input input, internal pullup enabled port f gpio ? this gpio pin can be individually programmed as an input or output pin. cmp0_p3 ? analog input to both positive input 3 of analog comparator 0. after reset, the default state is gpiof3. table 5. 56f8006/56f8002 signal and package information (continued) signal name 28 soic 32 lqfp 32 psdi p 48 lqfp type state during reset signal description
memory maps mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 29 5 memory maps 5.1 introduction the 56f8006/56f8002 device is based on the 56800e core. it us es a dual harvard-style arch itecture with two independent memory spaces for data and program. on-chi p ram is shared by both data and progra m spaces and flash memory is used only in program space. this section provides memory maps for: ? program address space, including the interrupt vector table ? data address space, including the eonc e memory and peri pheral memory maps on-chip memory sizes for the device are summarized in table 6 . flash memories? restrictions are identified in the ?use restrictions? column of table 6 . 5.2 program map the 56f8006/56f8002 series provide up to 16 kb on-chip flash memory . it primarily accesses thro ugh the progr am memory buses (pab; pdb). pab is used to select program memory addresses; instruction fetches are performed over pdb. data can be read and written to program memory space th rough primary data memory buses: cdbw for data write and cdbr for data read. accessing program memory space over the data memory buses ta kes longer access time compared to accessing data memory space. the special move instructions are provided to support these accesses. the benef it is that non time critical constants or tables can be stored and accessed in program memory. the program memory map is shown in table 7 and table 8 . table 6. chip memory configurations on-chip memory 56f8006 56f8002 use restrictions program flash (pflash) 8k x 16 or 16 kb 6k x 16 or 12 kb erase/program via flash interface unit and word writes to cdbw unified ram (ram) 1k x 16 or 2 kb 1k x 16 or 2 kb usable by the program and data memory spaces table 7. program memory map 1 for 56f8006 at reset 1 all addresses are 16-bit word addresses. begin/end address memory allocation p: 0x1f ffff p: 0x00 8800 reserved p: 0x00 83ff p: 0x00 8000 on-chip ram 2 : 2 kb 2 this ram is shared with data space st arting at address x: 0x00 0000; see figure 8 . p: 0x00 7fff p: 0x00 2000 reserved p: 0x00 1fff p: 0x00 0000 ? internal program flash: 16 kb ? interrupt vector table locates from 0x00 0000 to 0x00 0065 ? cop reset address = 0x00 0002 ? boot location = 0x00 0000
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 memory maps freescale semiconductor 30 5.3 data map the 56f8006/56f8002 series contain a dual access memory. it can be accessed from core primary data buses (xab1; cdbw; cdbr) and secondary data buses (xab2; xdb2). addresses in data memory are selected on the xab1 and xab2 buses. byte, word, and long data transfers occur on the 32-bit cdbr and cdbw buses. a second 16-bit read operation can be performed in parallel on the xdb2 bus. peripheral registers and on-chip jtag/eon ce controller registers are memory-map ped into data memory access. a special direct address mode is suppor ted for accessing a first 64-location in data me mory by using a single word instruction. the data memory map is shown in table 9 . table 8. program memory map 1 for 56f8002 at reset (continued) 1 all addresses are 16-bit word addresses. begin/end address memory allocation p: 0x1f ffff p: 0x00 8800 reserved p: 0x00 83ff p: 0x00 8000 on-chip ram 2 : 2 kb 2 this ram is shared with data space st arting at address x: 0x00 0000; see figure 9 . p: 0x00 7fff p: 0x00 2000 reserved p: 0x00 1fff p: 0x00 0800 ? internal program flash: 12 kb ? interrupt vector table locates from 0x00 0800 to 0x00 0865 ? cop reset address = 0x00 0802 ? boot location = 0x00 0800 p: 0x00 07ff p: 0x00 0000 reserved table 9. data memory map 1 1 all addresses are 16-bit word addresses. begin/end address memory allocation x:0xff ffff x:0xff ff00 eonce 256 location s allocated x:0xff feff x:0x01 0000 reserved x:0x00 ffff x:0x00 f000 on-chip peripherals 4096 locations allocated x:0x00 efff x:0x00 8800 reserved x:0x00 87ff x:0x00 8000 reserved x:0x00 7fff x:0x00 0400 reserved x:0x00 03ff x:0x00 0000 on-chip data ram 2 kb 2 2 this ram is shared with program space starting at p: 0x00 8000. see figure 8 and figure 9 .
memory maps mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 31 on-chip ram is also mapped into program space starting at p: 0x00 8000. this ma kes for easier online reprogramming of on-chip flash. figure 8. 56f8006 dual port ram map figure 9. 56f8002 dual port ram map 5.4 interrupt vector table and reset vector the location of the vector table is determin ed by the vector base address register (vba ). the value in this register is used as the upper 14 bits of the interrupt vector vab[20:0]. the lower seven bits are determined based on the highest priority interrup t and are then appended onto vba before pres enting the full vab to th e core. please see the mc56f8006 peripheral reference manual for detail. the reset startup addresse s of 56f8002 and 56f8006 are different. ? 56f8006 startup address is located at 0x00 0000. the reset va lue of vba is reset to a value of 0x0000 that corresponds to address 0x00 0000 ? 56f8002 startup address is located at 0x00 0800. the reset va lue of vba is reset to a value of 0x0010 that corresponds to address 0x00 0800 by default, the chip reset address and cop reset address correspo nd to vector 0 and 1 of the interrupt vector table. in these instances, the first two locations in the vector table must contai n branch or jmp instructions. all other entries must contain jsr instructions. the highest number vector, a user assignable vector user6 (vector 50), can be defined as a fast interrupt if the instruction located in this vector location is not a jsr or bsr instruction. please see section 9.3.3.3 of dsp56800e 16-bit core reference manual for detail. reserved ram reserved reserved eonce peripherals reserved ram dual port ram program data flash 0x00 0000 0x00 0400 0x00 f000 0x01 0000 0xff ff00 0x00 0000 0x00 2000 0x00 8000 0x00 8400 reserved ram reserved reserved eonce peripherals reserved ram dual port ram program data flash 0x00 0000 0x00 0400 0x00 f000 0x01 0000 0xff ff00 0x00 0000 0x00 0800 0x00 8000 0x00 8400 reserved 0x00 2000
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 memory maps freescale semiconductor 32 table 43 provides the 56f8006/56f8002?s reset and interrupt pr iority structure, including on-chip peripherals. 5.5 peripheral memory-mapped registers the locations of on-chip peripheral registers are part of the data memory map on the 56800e series. these locations may be accessed with the same addressing modes used for ordinary data memory, except all pe ripheral registers should be read or written using word accesses only. table 10 summarizes the base addresses for the set of peripherals on the 56f8006/56f8002 devices. peripherals are listed in order of the base address. table 10. data memory periphe ral base address map summary peripheral prefix base address dual channel timer tmr x:0x00 f000 pwm module pwm x:0x00 f020 interrupt controller intc x:0x00 f040 adca adca x:0x00 f060 adcb adcb x:0x00 f080 programmable gain amplifier 0 pga0 x:0x00 f0a0 programmable gain amplifier 1 pga1 x:0x00 f0c0 sci sci x:0x00 f0e0 spi spi x:0x00 f100 i 2 ci 2 c x:0x00 f120 computer operating properly cop x:0x00 f140 on-chip clock synthesis occs x:0x00 f160 gpio port a gpioa x:0x00 f180 gpio port b gpiob x:0x00 f1a0 gpio port c gpioc x:0x00 f1c0 gpio port d gpiod x:0x00 f1e0 gpio port e gpioe x:0x00 f200 gpio port f gpiof x:0x00 f220 system integration module sim x:0x00 f240 power management controller pmc x:0x00 f260 analog comparator 0 cmp0 x:0x00 f280 analog comparator 1 cmp1 x:0x00 f2a0 analog comparator 2 cmp2 x:0x00 f2c0 programmable interval timer pit x:0x00 f2e0 programmable delay block pdb x:0x00 f300 real timer clock rtc x:0x00 f320 flash memory interface fm x:0x00 f400
memory maps mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 33 5.6 eonce memory map control registers of the eonce are located at the top of data memory sp ace. these locations are fi xed by the 56f800e core. these registers can also be accessed through jtag port if flash secu rity is not set. table 11 lists all eonce registers necessary to access or control the eonce. table 11. eonce memory map address register acronym register name x:0xff ffff otx1/orx1 transmit register upper word receive register upper word x:0xff fffe otx/orx (32 bits) transmit register receive register x:0xff fffd otxrxsr transmit and re ceive status and control register x:0xff fffc oclsr core lock/unlock status register x:0xff fffb? x:0xff ffa1 reserved x:0xff ffa0 ocr control register x:0xff ff9f? x:0xff ff9e oscntr (24 bits) instruction step counter x:0xff ff9d osr status register x:0xff ff9c obase peripheral base address register x:0xff ff9b otbcr trace buffer control register x:0xff ff9a otbpr trace buffer pointer register x:0xff ff99? x:0xff ff98 otb (21?24 bits/stage) trace buffer register stages x:0xff ff97? x:0xff ff96 obcr (24 bits) breakpoint unit control register x:0xff ff95? x:0xff ff94 obar1 (24 bits) breakpoint unit address register 1 x:0xff ff93? x:0xff ff92 obar2 (32 bits) breakpoint unit address register 2 x:0xff ff91? x:0xff ff90 obmsk (32 bits) breakpoint unit mask register 2 x:0xff ff8f reserved x:0xff ff8e obcntr eonce breakpoint unit counter x:0xff ff8d reserved x:0xff ff8c reserved x:0xff ff8b reserved x:0xff ff8a oescr external signal control register x:0xff ff89 ? x:0xff ff00 reserved
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 general system control information freescale semiconductor 34 6 general system control information 6.1 overview this section discusses power pins, reset sources, interrupt sour ces, clock sources, the system in tegration module (sim), adc synchronization, and jtag/eonce interfaces. 6.2 power pins v dd , v ss and v dda , v ssa are the primary power supply pins for the devices . this voltage source supplies power to all on-chip peripherals, i/o buffer circuitry and to internal voltage regula tors. device has multiple internal voltages provide regulated lower-voltage source for the peripherals, core, memory, and on-chip relaxation oscillators. typically, there are at least two separate capacitors across the power pins to bypass the glitches and provide bulk charge stor age. in this case, there should be a bulk electrolytic or tantal um capacitor, such as a 10 ? f tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1 ? f ceramic bypass capacitor located as near to the device power pins as practical to suppress high-frequency nois e. each pin must have a bypass capacitor for best noise suppression. v dda and v ssa are the analog power supply pins fo r the device. this voltage source supplies power to the adc, pga, and cmp modules. a 0.1 ? f ceramic bypass capacitor should be located as near to the device v dda and v ssa pins as practical to suppress high-fre quency noise. v dda and v ssa are also the voltage reference high and voltage reference low inputs, respectively, for the adc module. 6.3 reset resetting the device provides a way to start processing from a known set of initial conditions. during reset, most control and status registers are forced to initial values and the program counter is loaded from the reset vector. on-chip peripheral modul es are disabled and i/o pins are initially configured as the reset status shown in table 5 . the 56f8006/56f8002 has the following sources for reset: ? power-on reset (por) ? partial power down reset (ppd) ? low-voltage detect (lvd) ? external pin reset (extr) ? computer operating properly loss of reference reset (cop_lor) ? computer operating properly time-out reset (cop_cpu) ? software reset (swr) each of these sources has an associated bit in the reset stat us register (rstat) in the system integration module (sim). the external pin reset function is shar ed with an gpio port a7 on the reset /gpioa7 pin. the reset function is enabled following any reset of the device. bit 7 of gpioa_per register mu st be cleared to use this pin as an gpio port pin. when enabled as the reset pin, an internal pullup de vice is automatically enabled. 6.4 on-chip clock synthesis the on-chip clock synthesis (occs) module allows designers using an internal relaxation oscillator, an external crystal, or an external clock to run 56f8000 family devices at user-selectable frequencies up to 32 mhz. the features of occs module include: ? ability to power down the internal relaxation oscillator or crystal oscillator ? ability to put the internal relaxation oscillator into standby mode ? ability to power down the pll
general system control information mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 35 ? provides a 3x system clock that operates at three ti mes the system clock to pwm, timer, and sci modules ? safety shutdown feature is available if the pll reference clock is lost ? can be driven from an external clock source the clock generation module provides the programming interface for the pll, internal relaxation oscillator, and crystal oscillator. it also provides a postscaler to divide clock frequenc y down by 1, 2, 4, 8, 16, 32, 64, 128, 256 before feeding to the sim. the sim is responsible for further dividing these frequencie s by two, which ensures a 50% du ty cycle in the system clock output. for detail, see the occs chapter in the mc56f8006 peripheral reference manual . 6.4.1 internal clock source an internal relaxation oscillator can supply the reference freque ncy when an external frequency source or crystal is not used. it is optimized for accuracy and programma bility while providi ng several power-saving conf igurations that accommodate different operating conditions. the internal relaxation oscillator has little temperature and voltage variability. to optimize power, the internal relaxation oscillator supports a run st ate (8 mhz), standby state (4 00 khz), and a power-down state. during a boot or reset sequence, the relaxation oscillator is enable d by default (the precs bit in the pllcr word is set to 0). application code can then also switch to the external clock source and power down the internal oscillator, if desired. if a changeover between internal and external cl ock sources is required at power-on, ensure that the clock source is not switched until the desired external clock source is enabled and stable. to compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator can be incrementally adjusted to within + 0.078% of 8 mhz by trimming an internal capacitor. bits 0?9 of the osctl (oscillator control) register allow you to set in an additional offset (trim) to this preset value to increase or decrease capacitance. each unit added or subtracted changes the output frequenc y by about 0.078% of 8 mhz, allowing in cremental adjustment until the desired frequency accuracy is achieved. the center frequency of the internal oscillat or is calibrated at the factory to 8 mhz an d the trim value is stored in the flash information block and loaded to the fmopt1 register at reset. wh en using the relaxation oscillator, the boot code should read the fmopt1 register and set this value as osctl trim. for further information, see the mc56f8006 peripheral reference manual . 6.4.2 crystal oscillator/ceramic resonator the internal crystal oscillator circuit is designed to interface with a parallel -resonant crystal resona tor in the frequency ra nge, specified for the external crystal, of 32.768 khz (typ) or 1 ?16 mhz. a ceramic resonator can be substituted for the 1?16 mhz range. when used to supply a source to the internal pll, the recommended crystal/resonator is in the 4 mhz to 8 mhz (recommend 8 mhz) range to achieve optimized pll perfor mance. oscillator circuits are shown in figure 10 , figure 11 , and figure 12 . follow the crystal supplier ? s recommendations when selec ting a crystal, because crysta l parameters determine the component values required to provide maximum stability and reliable start-up. the load cap acitance values used in the oscillator circuit design should include all stray layout capac itances. the crystal and associated components should be mounted as near as possible to the extal and xtal pins to minimize output distortion and start-up stabilization time. when using low-frequency, low-power mode, the only external component is th e crystal itself. in the other oscillator modes, load capacitor s (c x , c y ) and feedback resistor (r f ) are required. in additi on, a series resistor (r s ) may be used in high-gain modes. recommended component values are listed in table 28 .
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 general system control information freescale semiconductor 36 figure 10. typical crystal oscillator circuit: low-range, low-power mode figure 11. typical crystal or ceramic resonator circuit: high-range, low-power mode figure 12. typical crystal or ceramic resonator circuit: low range and high range, high-gain mode 6.4.3 external clock input ? crystal oscillator option the recommended method of connecting an external clock is illustrated in figure 13 . the external clock so urce is connected to xtal and the extal pin is grounded or configured as gpio while clk_mod bit in osctl register is set. the external clock input must be generated using a relatively low im pedance driver with maximum frequency less than 8 mhz. extal xtal 56f8002/56f8006 crystal frequency = 32?38.4 khz r f extal xtal 56f8002/56f8006 crystal frequency = 1?16 mhz c 1 c 2 r f extal xtal 56f8002/56f8006 r s low range: crystal frequency = 32?38.4 khz or high range: crystal frequency = 1?16 mhz c 1 c 2
general system control information mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 37 figure 13. connecting an external clock signal using xtal 6.4.4 alternate external clock input the recommended method of connecting an external clock is illustrated in figure 14 . the external clock source is connected to gpiob6/rxd/sda/ana13 and cmp0_p2/clki n while ext_sel bit in osctl register is set and corresponding bits in gpiob_per register gpio module and gpsb1 register in the sy stem integration module (sim) are set to the correct values. the external clock input must be generated using a relatively low impedance driver with maxi mum frequency not greater than 64 mhz. figure 14. connecting an external clock signal using gpio 6.5 interrupt controller the 56f8006/56f8002 interrupt controller (i ntc) module arbitrates the various interrupt requests (irqs). the intc signals to the 56800e core when an interrupt of sufficient priority ex ists and what address to jump to to service this interrupt. the interrupt controller co ntains registers that allow up to three interrupt sources to be set to priority level 1 and other up to three interrupt sources to be set to priority level 2. by defa ult, all peripheral interrupt sour ces are set to priority level 0 . next, all of the interrupt requests of a given le vel are priority encoded to determine the lowest numeric value of the active interru pt requests for that level. within a given priority level, the lowe st vector number is the highes t priority and the highest vector number is the lowest. the highest vector number, a user assignable vector user6 (vector 50), can be define d as a fast interrupt if the instruction located in this vector location is not a jsr or bsr instruction. please see section 9.3.3.3 of dsp56800e 16-bit core reference manual for detail. 6.6 system integration module (sim) the sim module is a system catch all for the glue logic that ties together the sy stem-on-chip. it controls distribution of reset s and clocks and provides a number of co ntrol features including the pin muxing control; inter-module connection control (for example connecting comparator ou tput to pwm fault input); individual peripheral enable/disable; pwm, timer, and sci clock rate control; enabling peripheral operation in stop mode; port c onfiguration overwrite protection. for further information, see the mc56f8006 peripheral reference manual. the sim is responsible for the following functions: ? chip reset sequencing ? core and peripheral clock control and distribution ? stop/wait mode control ? system status control extal xtal 56f8006/56f8002 external clock (<50 mhz) gnd or gpio clk_mod = 1 56f8002/56f8006 gpiob6/rxd/sda/ana13 and cmp0_p2/clkin external clock ( ? 64 mhz) ext_sel = 1; gpio_b_per[6] = 0; gps_b6 = 11
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 general system control information freescale semiconductor 38 ? registers containing the jtag id of the chip ? controls for programmable pe ripheral and gpio connections ? peripheral clocks for tmr and pwm and sci with a high-speed (3x) option ? power-saving clock gating for peripherals ? controls the enable/disable functions of large regu lator standby mode with write protection capability ? permits selected peripherals to run in stop mode to generate stop recovery interrupts ? controls for programmable pe ripheral and gpio connections ? software chip reset ? i/o short address base location control ? peripheral protection control to provide runaway code protection for safety-critical applications ? controls output of internal clock sources to clko pin ? four general-purpose software control registers are reset only at power-on ? peripherals stop mode clocking control 6.7 pwm, pdb, pga, and adc connections the comparators, timers, and pwm_reload_s ync output can be connected to the programmable delay block (pdb) trigger input. the pdb pre-trigger a and trigger a out puts are connected to the adca and pga0 hardware trigger inputs. the pdb pre-trigger b and trigger b outp uts are connected to the adcb and pga1 hardware trigger inputs. when the input trigger of pdb is asserted, pdb trigger and pre-trigger outputs are a sserted after a delay of a pr e-programmed period. see the mc56f8006 peripheral reference manual for additional information. figure 15. synchronization of adc, pdb triggera pre- triggera triggerb + ? pga0 controller ana15 ana9 ana7 adhwt adca trigger ssel[0] ssel[1] adca + ? pga1 controller anb15 anb8 anb6 adhwt adcb trigger ssel[0] ssel[1] adcb pre- triggerb system clock tmr0 tmr1 sw cmp0 cmp1 cmp2 pwm ext trigger0 trigger1 trigger2 trigger3 trigger4 trigger5 trigger6 trigger7 programmable delay block (pdb)
security features mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 39 each adc contains a temperature sensor. outputs of temperat ure sensors, pgas, on-chip regul ators and vdda are internally routed to adc inputs. ? internal pga0 output available on ana15 ? internal pga0 positive input calibration voltage available on ana16 ? internal pga0 negative input calibration voltage available on ana17 ? internal pga1 output available on anb15 ? internal pga1 positive input calibration voltage available on anb16 ? internal pga1 negative input calibration voltage available on anb17 ? adca temperature sens or available on ana26 ? adcb temperature sensor available on anb26 ? output of on-chip digital voltage regulator is routed to ana24 ? output of on-chip analog voltage regulator is routed to ana25 ? output of on-chip small voltage regu lator for rosc is routed to anb24 ? output of on-chip small voltage regulator for pll is routed to anb25 ? vdda is routed to ana27 and anb27 6.8 joint test action group (jta g)/enhanced on-chip emulator (eonce) the dsp56800e family includes extensive integrated support fo r application software development and real-time debugging. two modules, the enhanced on-chip emul ation module (eonce) and the core test access port (tap, commonly called the jtag port), work toge ther to provide these capabiliti es. both are accessed through a co mmon 4-pin jtag/eonce interface. these modules allow you to insert the 56f8006/56f8002 into a targ et system while retaining debug control. this capability is especially important for devices without an external bus, because it eliminates the need for a costly cable to bring out the footprint of the chip, as is required by a traditional emulator system. the dsp56800e eonce module is a freescale-designed module used to develop and debug application software used with the chip. this module allows non-intrusive in teraction with the cpu and is accessible th rough the pins of th e jtag interface or by software program control of the dsp56800e core. among the ma ny features of the eonce module is the support for data communication between the contro ller and the host software development and debug systems in real-time program execution. other features allow for hardware breakpoints, the monitoring and tracking of program execution, and the ability to examine and modify the contents of registers, me mory, and on-chip peripherals, all in a sp ecial debug environmen t. no user-accessible resources need to be sacrificed to perform debugging operations. the dsp56800e jtag port is used to provide an interface for the eonce module to the dsp jtag pins. joint test action group (jtag) boundary scan is an ieee 1149.1 standard meth odology enabling access to test features using a test access port (tap). a jtag boundary scan consists of a tap controll er and boundary scan registers. please contact your freescale sales representative or authorized distributo r for device-specific bsdl information. note in normal operation, an exte rnal pullup on the tm s pin is highly reco mmend to place the jtag state machine in reset state if this pin is not configured as gpio. 7 security features the 56f8006/56f8002 offers security featur es intended to prevent unauthorized user s from reading the co ntents of the flash memory (fm) array. the 56f8006/56f8002?s flash security consists of several hardware interloc ks that prevent unauthorized users from gaining access to the flash array. after flash security is set, an authorized user can be enabled to access on-chip memory if a user-defined software subroutine, which reads and transfers the contents of internal memory via peripherals, is incl uded in the application software. this
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 security features freescale semiconductor 40 application software could communicate over a serial port, for example, to validate the authenticity of the requested access, t hen grant it until the next device reset. the incl usion of such a back door technique is at the discretion of the system designer. 7.1 operation with security enabled after you have programmed flash with the application code, or as part of the programming of the flash with the application code, the 56f8006/56f8002 can be secured by programming the s ecurity word, 0x0002, into program memory location 0x00 1ff7. this can also be effected by use of the codewarrior id e menu flash lock command. this nonvolatile word keeps the device secured after reset, caused, for ex ample, by a power-down of the device. refer to the flash memory chapter in the mc56f8006 peripheral reference manual for detail. when flash security mode is enabled, the 56f8006/56f8002 disables the core eonce debug capabilities. normal program execution is otherwise unaffected. 7.2 flash access lock and unlock mechanisms there are several methods that effectiv ely lock or unlock the on-chip flash. 7.2.1 disabling eonce access on-chip flash can be read by issuing co mmands across the eonce port, which is th e debug interface for the 56800e cpu. the tck, tms, tdo, and tdi pins comprise a jtag interface onto which the eonce port functionality is mapped. when the device boots, the chip-level jtag tap (test access port) is ac tive and provides the chip?s boundary scan capability and access to the id register, but proper implementation of flash security blocks any atte mpt to access the internal flash memory via the eonce port when security is enabled. this protection is eff ective when the device comes out of reset, even prior to the execution of any code at startup. 7.2.2 flash lockout recovery using jtag if the device is secured, one lockout recove ry mechanism is the complete erasure of the internal flash contents, including the configuration field, thus disabling security (the protection regi ster is cleared). this does not compromise security, as the en tire contents of your secured code stored in flas h are erased before security is disabled on the device on the next reset or power-u p sequence. to start the lockout recovery sequence via jtag, the jtag public instruction (lockout_recovery) must first be shifted into the chip-level tap controller?s in struction register. after the lockout_rec overy instruction has been shifted into the instruction register, the clock divider value must be shifte d into the corresponding 7-bit data register. after the data re gister has been updated, you must transition the tap controller into the run-test/idle state for the lockout sequence to commence. the controller must rema in in this state until the erase sequence is complete. refer to the mc56f8006 peripheral reference manual for detail, or contact freescale. note after the lockout recovery sequence has completed, you must reset the jtag tap controller and device to return to normal uns ecured operation. power-on reset resets both too. 7.2.3 flash lockout recovery using codewarrior codewarrior can unlock a device by selecting the debug menu, then selecting dsp56800e , followed by unlock flash . another mechanism is also built into codewarrior using the device?s memory configuration file. the command ? unlock_flash_on_connect 1 ? in the . cfg file accomplishes the same task as using the debug menu. this lockout recovery mechanism is the comp lete erasure of the internal flash contents, including the configuration field, thus disabling security (the prot ection register is cleared).
specifications mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 41 7.2.4 flash lockout reco very without mass erase 7.2.4.1 without presenting back do or access keys to the flash unit a user can un-secure a secured device by programming the word 0x0000 into program flash location 0x00 1ff7. after completing the programming, the jtag tap controller and the devi ce must be reset to return to normal unsecured operation. you are responsible for directing the device to invoke the flash programming subroutine to reprogram the word 0x0000 into program flash location 0x00 1ff7. this is done by, for exampl e, toggling a specific pin or downloading a user-defined key through serial interfaces. note flash contents can be programmed only from 1s to 0s. 7.2.4.2 presenting back door ac cess key to the flash unit it is possible to temporarily bypass the s ecurity through a back door access scheme, using a 4-word key, to temporarily unlock of the flash. a back door access requires supp ort from the embedded software. this soft ware would typically permit an external user to enter a four word code through on e of the communications interfaces and then use it to attempt th e unlock sequence. if your input matches the four word code stored at location 0x00 1ffc?0x00 1fff in the flash memory, the part immediately becomes unsecured (at runtime) and you can access in ternal memory via jtag/eonce port. refer to the mc56f8006 peripheral reference manual for detail. the key must be entered in four cons ecutive accesses to the flash, so this routine should be designed to run in ram. 7.3 product analysis the recommended method of unsecuring a secured device for product analysis of field failures is via the method described in section 7.2.4.2, ?presenting back door access key to the flash unit .? the customer would need to supply technical support with the details of the protocol to access the subroutines in flash memory. an altern ative method for performing analysis on a secured device would be to mass-erase and re program the flash with the original code, but modify the security word or not program the security word. 8 specifications 8.1 general characteristics the 56f8006/56f8002 is fabricated in high-density low power an d low leakage cmos with a maximum voltage of 3.6 v digital inputs during normal operation without causing damage. absolute maximum ratings in table 12 are stress ratings only, and functional operat ion at the maximum is not guaranteed. stress beyond these ratings may affect device reliabil ity or cause permanent damage to the device. unless otherwise stated, all specifications within this chapter apply over the temp erature range of ?40oc to 105oc ambient temperature over the follo wing supply ranges: v ss =v ssa =0v,v dd =v dda = 3.0?3.6 v, cl < 50 pf, f op = 32 mhz caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 specifications freescale semiconductor 42 8.2 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the limits specified table 12 may affect device reliability or cause permanent damage to the device. for functional operating conditions, refer to the remaining tables in this section. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, take normal precautions to avoid application of any voltages higher than ma ximum-rated voltages to this hi gh-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage le vel (for instance, either v ss or v dd ) or the programmable pullup resistor associ ated with the pin is enabled. 8.2.1 esd protection and latch-up immunity although damage from electrostatic discharge (esd) is much le ss common on these devices than on early cmos circuits, use normal handling precautions to avoid exposure to static discharge. qualification tests are performed to ensure that these devic es can withstand exposure to reasonable levels of static without suffering any permanent damage. all esd testing is in conformity with aec-q100 stress test qu alification for automotive grade integrated circuits. during the device qualification esd stresses were performed for the human body model (hbm), the machine model (mm), and the charge device model (cdm). table 12. absolute maximum ratings (v ss = 0 v, v ssa = 0 v) characteristic symbol notes min max unit supply voltage range v dd ?0.3 3.8 v analog supply voltage range v dda ?0.3 3.6 v voltage difference v dd to v dda ? v dd ?0.3 0.3 v voltage difference v ss to v ssa ? v ss ?0.3 0.3 v digital input voltage range v in pin groups 1, 2 ?0.3 v dd +0.3 v oscillator voltage range v osc pin group 4 tbd tbd v analog input voltage range v ina pin group 3 ?0.3 3.6 v input clamp current, per pin (v in < 0) 1 2 3 1 input must be current limited to the value specified. to determine the value of the required current-limiting resistor, calcula te resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating vdd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd loads shunt current greater than maximum injection current. this is the greatest risk when the mcu is not consuming po wer. examples are: if no system clock is present or if the clock rate is low (which would reduce overall power consumption). v ic ? ?25.0 ma output clamp current, per pin (v o < 0) 1 2 3 v oc ? ?20.0 ma output voltage range (normal push-pull mode) v out pin group 1 ?0.3 v dd v ambient temperature industrial t a ?40 105 c storage temperature range (extended industrial) t stg ?55 150 c
specifications mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 43 a device is defined as a failure if after exposure to esd puls es the device no longer meets the device specification. complete dc parametric and functional testing is pe rformed per the applicable device specificat ion at room temperature followed by hot temperature, unless specified othe rwise in the device specification. 8.3 thermal characteristics this section provides information about ope rating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being c ontrolled by the mcu design. to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current fo r each i/o pin. except in cases of unusually high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. table 13. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 ? storage capacitance c 100 pf number of pulses per pin ? 3 machine series resistance r1 0 ? storage capacitance c 200 pf number of pulses per pin ? 3 latch-up minimum input voltage limit ?2.5 v maximum input voltage limit 7.5 v table 14. 56f8006/56f8002 esd protection characteristic 1 1 parameter is achieved by design characterization on a small sample size from typical devices un- der typical conditions unless otherwise noted. min typ max unit esd for human body model (hbm) 2000 ? ? v esd for machine model (mm) 200 ? ? v esd for charge device model (cdm) 750 ? ? v latch-up current at t a = 85 o c (i lat ) ? 100 ma table 15. 28soic package thermal characteristics characteristic comments symbol value (lqfp) unit junction to ambient natural convection single layer board (1s) r ? ja 70 c/w junction to ambient natural convection four layer board (2s2p) r ? jma 47 c/w junction to ambient (@200 ft/min) single layer board (1s) r ? jma 55 c/w
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 specifications freescale semiconductor 44 junction to ambient (@200 ft/min) four layer board (2s2p) r ? jma 42 c/w junction to board r ? jb 23 c/w junction to case r ? jc 26 c/w junction to package top natural convection ? jt 9c/w table 16. 32lqfp package thermal characteristics characteristic comments symbol value (lqfp) unit junction to ambient natural convection single layer board (1s) r ? ja 84 c/w junction to ambient natural convection four layer board (2s2p) r ? jma 56 c/w junction to ambient (@200 ft/min) single layer board (1s) r ? jma 70 c/w junction to ambient (@200 ft/min) four layer board (2s2p) r ? jma 49 c/w junction to board r ? jb 33 c/w junction to case r ? jc 20 c/w junction to package top natural convection ? jt 4c/w table 17. 32psdip package thermal characteristics characteristic comments symbol value (lqfp) unit junction to ambient natural convection single layer board (1s) r ? ja 56 c/w junction to ambient natural convection four layer board (2s2p) r ? jma 41 c/w junction to ambient (@200 ft/min) single layer board (1s) r ? jma 45 c/w junction to ambient (@200 ft/min) four layer board (2s2p) r ? jma 36 c/w junction to board r ? jb 18 c/w junction to case r ? jc 24 c/w junction to package top natural convection ? jt 10 c/w table 15. 28soic package thermal characteristics (continued) characteristic comments symbol value (lqfp) unit
specifications mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 45 note junction-to-ambient thermal resistance dete rmined per jedec jesd51?3 and jesd51?6. thermal test board meets jedec specification for this package. junction-to-board thermal resistance determ ined per jedec jesd51?8. thermal test board meets jedec specificatio n for the specified package. junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value includes the thermal resistance of the interface layer. thermal characterization parameter indicat ing the temperature difference between the package top and the junction temperature per jedec jesd51?2. when greek letters are not available, the therma l characterization parameter is written as psi-jt junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperatur e, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. see section 9.1, ?thermal design considerations ,? for more detail on thermal design considerations. 8.4 recommended oper ating conditions this section includes information ab out recommended operating conditions. table 18. 48lqfp package thermal characteristics characteristic comments symbol value (lqfp) unit junction to ambient natural convection single layer board (1s) r ? ja 79 c/w junction to ambient natural convection four layer board (2s2p) r ? jma 55 c/w junction to ambient (@200 ft/min) single layer board (1s) r ? jma 66 c/w junction to ambient (@200 ft/min) four layer board (2s2p) r ? jma 48 c/w junction to board r ? jb 34 c/w junction to case r ? jc 20 c/w junction to package top natural convection ? jt 4c/w
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 specifications freescale semiconductor 46 8.5 dc electrical characteristics this section includes informatio n about power supply requiremen ts and i/o pin characteristics. table 19. recommended operating conditions (v refl x = 0 v, v ssa = 0 v, v ss = 0 v) characteristic symbol notes min typ max unit supply voltage v dd, v dda 33.33.6 v voltage difference v dd to v dda ? v dd ?0.1 0 0.1 v voltage difference v ss to v ssa ? v ss ?0.1 0 0.1 v device clock frequency using relaxation oscillator using external clock source fsysclk 1 0 32 32 mhz input voltage high (digital inputs) v ih pin groups 1, 2 2.0 v dd v input voltage low (digital inputs) v il pin groups 1, 2 ?0.3 0.8 v oscillator input voltage high xtal driven by an external clock source v ihosc pin group 4 2.0 v dda + 0.3 v oscillator input voltage low v ilosc pin group 4 ?0.3 0.8 v output source current high at v oh min.) 1 when programmed for low drive strength when programmed for high drive strength 1 total chip source or sink current cannot exceed 75 ma. i oh pin group 1 pin group 1 ? ? ?4 ?8 ma output source current low (at v ol max.) 1 when programmed for low drive strength when programmed for high drive strength i ol pin groups 1, 2 pin groups 1, 2 ? ? 4 8 ma ambient operating te mperature (extended industrial) t a ?40 105 c flash endurance (program erase cycles) n f t a = ?40c to 125c 10,000 ? cycles flash data retention t r t j ? 85c avg 15 ? years flash data retention with <100 program/erase cycles t flret t j ? 85c avg 20 ? ? years table 20. default mode pin group 1 gpio, tdi, tdo, tms, tck pin group 2 scl, sda pin group 3 adc and comparator analog inputs and pga inputs pin group 4 xtal, extal
specifications mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 47 table 21. dc characteristics characteristic symbol condition min typ 1 max unit ambient temperature operating range operating voltage 1.8 2 3.6 v ?40 ? c ~ +125 ? c output high voltage all i/o pins, low-drive strength v oh 1.8 v, i load = ?2 ma v dd ? 0.5 ? ? v all i/o pins, high-drive strength 2.7 v, i load = ?10 ma v dd ? 0.5 ? ? 2.3 v, i load = ?6 ma v dd ? 0.5 ? ? 1.8 v, i load = ?3 ma v dd ? 0.5 ? ? output high current max total i oh for all ports i oht ??100ma output low voltage all i/o pins, low-drive strength v ol 1.8 v, i load = 2 ma ? ? 0.5 v all i/o pins, high-drive strength 2.7 v, i load = 10 ma ? ? 0.5 2.3 v, i load = 6 ma ? ? 0.5 1.8 v, i load = 3 ma ? ? 0.5 output low current max total i ol for all ports i olt ??100ma input high voltage all digital inputs v ih v dd ? 2.7 v 0.70 x v dd ??v v dd ?? 1.8 v 0.85 x v dd ?? input low voltage all digital inputs v il v dd ? 2.7 v ? ? 0.35 x v dd v dd ? 1.8 v ? ? 0.30 x v dd input hysteresis all digital inputs v hys 0.06 x v dd ??mv input leakage current all input only pins (per pin) |i in| v in = v dd or v ss ??1 ? a hi-z (off-state) leakage current all input/output (per pin) |i oz |v in = v dd or v ss ??1 ? a pullup resistors all digital inputs, when enabled r pu 17.5 ? 52.5 k ? dc injection current 3, 4, 5 single pin limit i ic v in < v ss , v in > v dd ?0.2 ? 0.2 ma total mcu limit, includes sum of all stressed pins ?5 ? 5 ma input capacitance, all pins c in ??8pf ram retention voltage v ram ?0.61.0v por re-arm voltage 6 v por 0.9 1.4 1.79 v por re-arm time t por 10 ? ? ? s
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 specifications freescale semiconductor 48 low-voltage detection threshold ? high range 7 v lv d h 8 v dd falling 2.31 2.34 2.36 v ?40 ? c ~ 105 ? c 2.16 2.3 2.48 ?40 ? c ~ +125 ? c v dd rising 2.38 2.44 2.47 ?40 ? c ~ 105 ? c 2.23 2.39 2.49 ?40 ? c ~ +125 ? c low-voltage detection threshold ? low range 7 v lv d l v dd falling 1.8 1.84 1.87 v ?40 ? c ~ 105 ? c n/a n/a n/a ?40 ? c ~ +125 ? c v dd rising 1.88 1.93 1.96 ?40 ? c ~ 105 ? c low-voltage warning threshold v lv w 9 v dd falling 2.58 2.62 2.71 v ?40 ? c ~ 105 ? c 2.5 2.61 2.74 ?40 ? c ~ +125 ? c v dd rising 2.59 2.67 2.74 ?40 ? c ~ 105 ? c 2.51 2.66 2.79 ?40 ? c ~ +125 ? c low-voltage inhibit reset/recover hysteresis 7 v hys ? 50 ? mv ?40 ? c ~ +105 ? c bandgap voltage reference 10 v bg 1.15 1.17 1.18 v ?40 ? c ~ 105 ? c 1.14 ?40 ? c ~ +125 ? c 1 typical values are measured at 25 ? c. characterized, not tested 2 as the supply voltage rises, the lvd circuit holds the mcu in reset until the supply has risen above v lv d l . if the system clock frequency < 16 mhz, v dd can be 1.7 v to 3.6 v. 3 all functional non-supply pins are internally clamped to v ss and v dd . 4 input must be current limited to the valu e specified. to determine the value of th e required current-limiting resistor, calcula te resistance values for positive and negative clamp voltages, then use the larger of the two values. 5 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load shunts current greater than maximum injection current. this is the greatest risk when the mcu is not consuming power. examples are: if no syst em clock is present or if clock rate is low (which would reduce overall power consumption). 6 maximum is highest voltage that por is guaranteed. 7 low voltage detection and warning limits measured at 32 mhz bus fr equency. this characteristic is not applicable to devices wit h a temperature range from ?40 ? c to 125 ? c. please see the pmc chapter in the reference manual for details. table 21. dc characteristics (continued) characteristic symbol condition min typ 1 max unit ambient temperature operating range
specifications mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 49 figure 16. pullup and pulldown typical resistor values figure 17. typical low-side driver (sink) characteristics ? low drive (gpio_x_driven = 0) figure 18. typical low-side driver (sink) characteristics ? high drive (gpio_x_driven = 1) 8 runs at 32 mhz bus frequency. 9 both low voltage warning (lvw) and out of regulation (oor) sample the same input source. the oor flag is a stick bit which is in the pmc_scr register. 10 factory trimmed at v dd = 3.3 v, temp = 25 ? c. pullup resistor typicals v dd (v) pullup resistor (k w ) 20 25 30 35 40 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 25 ? c 85 ? c ?40 ? c pulldown resistor typicals v dd (v) pulldown resistance (k w ) 20 25 30 35 40 1.8 2.3 2.8 3.3 25 ? c 85 ? c ?40 ? c 3.6 typical v ol vs i ol at v dd = 3.0 v i ol (ma) v ol (v) 0 0.2 0.4 0.6 0.8 1 1.2 0 5 10 15 20 typical v ol vs v dd v dd (v) v ol (v) 0 0.05 0.1 0.15 0.2 1234 25 ? c 85 ? c ?40 ? c 25 ? c, i ol = 2 ma 85 ? c, i ol = 2 ma ?40 ? c, i ol = 2 ma typical v ol vs i ol at v dd = 3.0 v i ol (ma) v ol (v) 0 0.2 0.4 0.6 0.8 1 0102030 typical v ol vs v dd v dd (v) v ol (v) 0 0.1 0.2 0.3 0.4 1234 i ol = 6 ma i ol = 3 ma i ol = 10 ma 25 ? c 85 ? c ?40 ? c 25 ? c 85 ? c ?40 ? c
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 specifications freescale semiconductor 50 figure 19. typical high-side (source) characteristics ? low drive (gpio_x_driven = 0) figure 20. typical high-side (source) characteristics ? high drive (gpio_x_driven = 1) typical v dd ? v oh vs i oh at v dd = 3.0 v i oh (ma)) 0 0.2 0.4 0.6 0.8 1 1.2 ?20 ?15 ?10 ?5 0 typical v dd ? v oh vs v dd at spec i oh v dd (v) v dd ? v oh (v) 0 0.05 0.1 0.15 0.2 0.25 1234 v dd ? v oh (v) 25 ? c 85 ? c ?40 ? c 25 ? c, i oh = 2 ma 85 ? c, i oh = 2 ma ?40 ? c, i oh = 2 ma typical v dd ? v oh vs i oh at v dd = 3.0 v i oh (ma) 0 0.2 0.4 0.6 0.8 ?30 ?25 ?20 ?15 ?10 ?5 0 typical v dd ? v oh vs v dd at spec i oh v dd (v) v dd ? v oh (v) 0 0.1 0.2 0.3 0.4 1234 i oh = ?10 ma i oh = ?6 ma i oh = ?3 ma v dd ? v oh (v) 25 ? c 85 ? c ?40 ? c 25 ? c 85 ? c ?40 ? c
specifications mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 51 8.6 supply current characteristics table 22. supply current consumption mode conditions typical @ 3.3 v, 25 c maximum @ 3.6 v, 105 c maximum @ 3.6 v, 125 c i dd 1 i dda i dd 1 i dda i dd 1 i dda run 32 mhz device clock; relaxation oscillator (rosc) in high speed mode; pll engaged; all peripheral modules enabled. tmr and pwm using 1x clock; continuous mac instructions with fetches from program flash; adc/dac powered on and clocked; comparator powered on. 41.52 ma 1.71 ma 53 ma 2.7 ma 53 ma 2.9 ma lsrun 2 200 khz device clock; relaxation oscillator (rosc) in standby mode; pll disabled all peripheral modules disabled and clock gated off; simple loop with fetches from program flash; 340.75 ? a 1.70 ma 480 ? a 2.5 ma 495 ? a 2.6 ma lprun 3 32.768 khz device clock; clocked by a 32.768 khz external crystal relaxation oscillator (rosc) in power down; pll disabled all peripheral modules disabled and clock gated off; simple loop with fetches from program flash; 166.30 ? a 1.74 ma 390 ? a 3.4 ma 399 ? a 3.8 ma wait 32 mhz device clock relaxation oscillator (rosc) in high speed mode pll engaged; all non-communication peripherals enabled and running; all communication peripherals disabled but clocked; processor core in wait state 19.3 ma 1.78 ma 28 ma 2.7 ma 28 ma 2.8 ma lswait 2 200 khz device clock; relaxation oscillator (rosc) in standby mode; pll disabled; all peripheral modules disabled and clock gated off; processor core in wait state 265.42 ? a 1.70 ma 380 ? a 2.5 ma 398 ? a 2.6 ma
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 specifications freescale semiconductor 52 lpwait 3 32.768 khz device clock; clocked by a 32.768 khz external crystal oscillator in power down; pll disabled; all peripheral modules disabled and clock gated off; processor core in wait state 157.55 ? a 1.57 ma 380 ? a 3.4 ma 398 ? a 3.6 ma stop 32 mhz device clock relaxation oscillator (rosc) in high speed mode; pll engaged; all peripheral module and core clocks are off; adc/dac/comparator powered off; processor core in stop state 8.21 ma 65.51 ? a 9.8 ma 130 ? a 10.3 ma 132 ? a lsstop 2 200 khz device clock; relaxation oscillator (rosc) in standby mode; pll disabled; all peripheral modules disabled and clock gated off; processor core in stop state. 194.69 ? a 65.51 ? a 340 ? a120 ? a357 ? a 123 ? a lpstop 2 32.768 khz device clock; clocked by a 32.768 khz external crystal relaxation oscillator (rosc) in power down; pll disabled; all peripheral modules disabled and clock gated off; processor core in stop state. 2.77 ? a 13.99 na 45 ? a3.0 ? a 58 ? a3.6 ? a ppd 4 with xosc 32.768 khz clock fed on xtal rtc or cop monitoring xosc (but no wakeup) processor core in stop state 879.72 na 11.56 na 18 ? a2.4 ? a 22 ? a3.0 ? a ppd with lp oscillator (1 khz) enabled rtc or cop monitoring lp oscillator (but no wakeup); processor core in stop state. 499.15 na 13.9 na 14 ? a2.4 ? a 17 ? a 2.8 ma ppd with no clock monitoring rtc and lp oscillator are disabled; processor core in stop state. 494.04 na 12.88 na 14 ? a2.4 ? a 17 ? a2.8 ? a 1 no output switching; all ports configured as inputs; all inputs low; no dc loads. 2 low speed mode: lpr (lower voltage regulator control bit) = 0 a nd voltage regulator is in full regulation. characterization onl y. 3 low power mode: lpr (lower voltage regulator control bi t) = 1; the voltage regulator is put into standby. 4 partial power down mode: ppde (partial power down enable bit) = 1; power management controller (pmc) enters partial power down mode the next time that the stop command is executed. table 22. supply current consumption (continued) mode conditions typical @ 3.3 v, 25 c maximum @ 3.6 v, 105 c maximum @ 3.6 v, 125 c i dd 1 i dda i dd 1 i dda i dd 1 i dda
specifications mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 53 8.7 flash memory characteristics 8.8 external clock operation timing figure 21. external clock timing table 23. flash timing parameters characteristic symbol min typ max unit program time 1 1 there is additional overhead that is part of the programming sequence. see the mc56f8006 peripheral reference manual for detail. t prog 20 ? 40 ? s erase time 2 2 specifies page erase time. there are 512 bytes per page in the program flash memory. t erase 20 ? ? ms mass erase time t me 100 ? ? ms table 24. external clock operation timing requirements 1 1 parameters listed are guaranteed by design. characteristic symbol min typ max unit frequency of operation (external clock driver) 2 2 see figure 21 for detail on using the recommended connection of an external clock driver. f osc ??64 mhz clock pulse width 3 3 the chip may not function if the high or low pulse width is smaller than 6.25 ns. t pw 6.25 ? ? ns external clock input rise time 4 4 external clock input rise time is measured from 10% to 90%. t rise ?? 3ns external clock input fall time 5 5 external clock input fall time is measured from 90% to 10%. t fall ?? 3ns input high voltage overdrive by an external clock v ih 0.85v dd ??v input high voltage overdrive by an external clock v il ??0.3v dd v 90% 50% 10% 90% 50% 10% external clock t pw t pw t fall t rise v il v ih note: the midpoint is v il + (v ih ? v il )/2.
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 specifications freescale semiconductor 54 8.9 phase locked loop timing 8.10 relaxation oscillator timing table 25. phase locked loop timing characteristic symbol min typ max unit pll input reference frequency 1 1 an externally supplied reference clock should be as free as possible from any phase jitter for the pll to work correctly. the pll is optimized for 8 mhz input. f ref 48? mhz pll output frequency 2 2 the core system clock operates at 1/6 of the pll output frequency. f op 120 192 ? mhz pll lock time 3 4 3 this is the time required after the pll is enabled to ensure reliable operation. 4 from powerdown to powerup state at 32 mhz system clock state. t plls ?40100s accumulated jitter using an 8 mhz external crystal as the pll source 5 5 this is measured on the clko signal (programmed as system clock) over 264 system clocks at 32 mhz system clock frequency and using an 8 mhz oscillator frequency. j a ? ? 0.37 % cycle-to-cycle jitter t jitterpll ?350? ps table 26. relaxation oscillator timing characteristic symbol mini mum typical maximum unit relaxation oscillator output frequency 1 normal mode standby mode 1 output frequency after factory trim. f op ? 8.05 400 ? mhz khz relaxation oscillator stabilization time 2 2 this is the time required from st andby to normal mode transition. t roscs ?1 3 ms cycle-to-cycle jitter. this is measured on the clko signal (programmed prescaler_clock) over 264 clocks 3 3 j a is required to meet qsci requirements. t jitterrosc ?400 ? ps variation over temperature ?40 ? c to 105 ? c 4 4 see figure 22 . the power supply vdd must be greater than or equal to 2.6 v. below 2.6 v, the maximum variation over the whole temperature and whole voltage range from 1.8 v to 2.6 v will be +/-16%. ? ? ?3.0 to +2.0 % variation over temperature 0 ? c to 105 ? c 5 5 this data is only applied to devices with temperature range from ?40 ? c to 105 ? c. ? ? ?2.0 to +2.0 % variation over temperature ?40 ? c to 125 ? c 4 ? ? ?3.5 to +3.0 %
specifications mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 55 figure 22. relaxation oscillator temperature variation (typical) after trim for devices with temperature operating range from ?40 ? c to 105 ? c figure 23. relaxation oscillator temperature variation (typical) after trim for devices with temperature operating range from ?40 ? c to 125 ? c degrees c (junction) mhz
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 specifications freescale semiconductor 56 8.11 reset, stop, wait, mode select, and interrupt timing note all address and data buses described here are internal. figure 24. gpio interrupt timi ng (negative edge-sensitive) 8.12 external oscillator (xosc) characteristics reference figure 10 , and figure 11 , and figure 12 for crystal or resonator circuits. table 27. reset, stop, wait, mode select, and interrupt timing 1,2 1 in the formulas, t = system clock cycle and t osc = oscillator clock cycle. for an operating frequency of 32 mhz, t = 31.25 ns. at 4 mhz (used coming out of reset and stop modes), t = 250 ns. 2 parameters listed are guaranteed by design. characteristic symbol typical mi n typical max unit see figure minimum reset assertion duration t ra 4t ? ns ? minimum gpio pin assertion for interrupt t iw 2t ? ns figure 24 reset deassertion to first address fetch t rda 96t osc + 64t 97t osc + 65t ns ? delay from interrupt assertion to fetch of first instruction (exiting stop) t if ?6tns? gpio pin (input) t iw
specifications mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 57 8.13 ac electrical characteristics tests are conducted using th e input levels specified in table 22 . unless otherwise specified, prop agation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in figure 25 . figure 25. input signal measurement references figure 26 shows the definitions of the following signal states: ? active state, when a bus or signal is driven, and enters a low impedance state table 28. crystal oscillator characteristics characteristic symbol min typ 1 1 data in typical column was characterized at 3.0 v, 25 ? c or is typical recommended value. max unit oscillator crystal or resonator (precs = 1, clk_mod = 0) low range (range = 0) high range (range = 1), high gain (cohl =0) high range (range = 1), low power (cohl =1) f lo f hi f hi 32 1 1 ? ? ? 38.4 16 8 khz mhz mhz load capacitors low range (range=0), low power (cohl =1) other oscillator settings c 1, c 2 see note 2 see note 3 2 load capacitors (c 1 ,c 2 ), feedback resistor (r f ) and series resistor (r s ) are incorporated internally when range=hgo=0. 3 see crystal or resonator manufacturer?s recommendation. feedback resistor low range, low power (range=0, cohl =1) 2 low range, high gain (range=0, cohl =0) high range (range=1, cohl=x) r f ? ? ? ? 10 1 ? ? ? m ? series resistor low range, low power (range = 0, cohl =1) 2 low range, high gain (range = 0, cohl =0) high range, low power (range = 1, cohl =1) high range, high gain (range = 1,cohl =0) ? 8 mhz 4 mhz 1 mhz r s ? ? ? ? ? ? 0 100 0 0 0 0 ? ? ? 0 10 20 k ? crystal start-up time 4 low range, low power low range, high gain high range, low power high range, high gain 4 proper pc board layout procedures must be followed to achieve specifications. t cstl t csth ? ? ? ? tbd tbd tbd tbd ? ? ? ? ms square wave input clock frequency (precs = 1, clk_mod = 1) f xtal ? ? 50.0 mhz v ih v il fall time midpoint1 low high 90% 50% 10% rise time the midpoint is v il + (v ih ? v il )/2. input signal
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 specifications freescale semiconductor 58 ? tri-stated, when a bu s or signal is placed in a high impedance state ? data valid state, when a signal level has reached v ol or v oh ? data invalid state, when a signal level is in transition between v ol and v oh figure 26. signal states 8.13.1 serial peripheral interface (spi) timing table 29. spi timing 1 characteristic symbol min max unit see figure cycle time master slave t c 125 62.5 ? ? ns ns figure 27 , figure 28 , figure 29 , figure 30 enable lead time master slave t eld ? 31 ? ? ns ns figure 30 enable lag time master slave t elg ? 125 ? ? ns ns figure 30 clock (sck) high time master slave t ch 50 31 ? ? ns ns figure 27 , figure 28 , figure 29 , figure 30 clock (sck) low time master slave t cl 50 31 ? ? ns ns figure 30 data set-up time required for inputs master slave t ds 20 0 ? ? ns ns figure 27 , figure 28 , figure 29 , figure 30 data hold time required for inputs master slave t dh 0 2 ? ? ns ns figure 27 , figure 28 , figure 29 , figure 30 access time (time to data active from high-impedance state) slave t a 4.8 15 ns figure 30 disable time (hold time to high-impedance state) slave t d 3.7 15.2 ns figure 30 data invalid state data1 data3 valid data2 data3 data1 valid data active data active data2 valid data three-stated
specifications mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 59 figure 27. spi master timing (cpha = 0) data valid for outputs master slave (after enable edge) t dv ? ? 4.5 20.4 ns ns figure 27 , figure 28 , figure 29 , figure 30 data invalid master slave t di 0 0 ? ? ns ns figure 27 , figure 28 , figure 29 , figure 30 rise time master slave t r ? ? 11.5 10.0 ns ns figure 27 , figure 28 , figure 29 , figure 30 fall time master slave t f ? ? 9.7 9.0 ns ns figure 27 , figure 28 , figure 29 , figure 30 1 parameters listed are guaranteed by design. table 29. spi timing 1 (continued) characteristic symbol min max unit see figure sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in t f t c t cl t cl t r t r t f t ds t dh t ch t di t dv t di (ref) t r master msb out bits 14?1 master lsb out ss (input) t ch ss is held high on master t f
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 specifications freescale semiconductor 60 figure 28. spi master timing (cpha = 1) figure 29. spi slave timing (cpha = 0) sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in t r t c t cl t cl t f t ch t dv (ref) t dv t di (ref) t r t f master msb out bits 14? 1 master lsb out ss (input) t ch ss is held high on master t ds t dh t di t r t f sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 t c t cl t cl t f t ch t di msb in bits 14?1 lsb in ss (input) t ch t dh t r t elg t eld t f slave lsb out t d t a t ds t dv t di t r
specifications mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 61 figure 30. spi slave timing (cpha = 1) 8.13.2 serial communication interface (sci) timing table 30. sci timing 1 1 parameters listed are guaranteed by design. characteristic symbol min max unit see figure baud rate 2 2 f max is the frequency of operation of the sc i in mhz, which can be selected system clock (max. 32 mhz) or 3x system clock (max. 96 mhz) for the 56f8006/56f8002 device. br ? (f max /16) mbps ? rxd pulse width rxd pw 0.965/br 1.04/br ns figure 31 txd pulse width txd pw 0.965/br 1.04/br ns figure 32 lin slave mode deviation of slave node clock from nominal clock rate before synchronization f tol_unsynch ?14 14 % ? deviation of slave node clock relative to the master node clock after synchronization f tol_synch ?2 2 % ? minimum break character length t break 13 ? master node bit periods ? 11 ? slave node bit periods ? sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 t c t cl t cl t ch t di msb in bits 14?1 lsb in ss (input) t ch t dh t f t r slave lsb out t d t a t eld t dv t f t r t elg t dv t ds
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 specifications freescale semiconductor 62 figure 31. rxd pulse width figure 32. txd pulse width 8.13.3 inter-integrated circuit interface (i 2 c) timing table 31. i 2 c timing characteristic symbol standard mode unit minimum maximum scl clock frequency f scl 0100 mhz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd; sta 4.0 ? ? s low period of the scl clock t low 4.7 ? ? s high period of the scl clock t high 4.0 ? ? s set-up time for a repeated start condition t su; sta 4.7 ? ? s data hold time for i 2 c bus devices t hd; dat 0 1 1 the master mode i 2 c deasserts ack of an address byte simultaneously with the falling edge of scl. if no slaves acknowledge this address byte, a negative hold time can result, depending on the edge rates of the sda and scl lines. 3.45 2 2 the maximum t hd; dat must be met only if the device does not stretch the low period (t low ) of the scl signal. ? s data set-up time t su; dat 250 ? ns rise time of sda and scl signals t r ? 1000 ns fall time of sda and scl signals t f ?300ns set-up time for stop condition t su; sto 4.0 ? ? s bus free time between stop and start condition t buf 4.7 ? ? s pulse width of spikes that must be suppressed by the input filter t sp n/a n/a ns rxd pw rxd sci receive data pin (input) txd pw txd sci receive data pin (input)
specifications mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 63 figure 33. timing defini tion for standard mode devices on the i 2 c bus 8.13.4 jtag timing figure 34. test clock input timing diagram table 32. jtag timing characteristic symbol min max unit see figure tck frequency of operation 1 1 tck frequency of operation must be le ss than 1/8 the processor rate. f op dc sys_clk/8 mhz figure 34 tck clock pulse width t pw 50 ? ns figure 34 tms, tdi data set-up time t ds 5?ns figure 35 tms, tdi data hold time t dh 5?ns figure 35 tck low to tdo data valid t dv ?30ns figure 35 tck low to tdo tri-state t ts ?30ns figure 35 sda scl t hd; sta t hd; dat t low t su; dat t high t su; sta sr p s s t hd; sta t sp t su; sto t buf t f t r t f t r tck (input) v m v il v m = v il + (v ih ? v il )/2 t pw 1/f op t pw v m v ih
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 specifications freescale semiconductor 64 figure 35. test access port timing diagram 8.13.5 dual timer timing figure 36. timer timing table 33. timer timing 1, 2 1 in the formulas listed, t = the clock cycle. for 32 mhz operation, t = 31.25ns. 2. parameters listed are guaranteed by design. characteristic symbol min max unit see figure timer input period p in 2t + 6 ? ns figure 36 timer input high/low period p inhl 1t + 3 ? ns figure 36 timer output period p out 125 ? ns figure 36 timer output high/low period p outhl 50 ? ns figure 36 input data valid output data valid t ds t dh t dv t ts tck (input) tdi (input) tdo (output) tdo (output) tms p out p outhl p outhl p in p inhl p inhl timer inputs timer outputs
specifications mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 65 8.14 cop specifications 8.15 pga specifications table 34. cop specifications parameter symbol min typ max unit oscillator output frequency lpfosc 500 1000 1500 hz oscillator current consumption in partial power down mode idd tbd na table 35. pga specifications parameter symbol min max unit digital logic inputs amplitude (_2p5 signal) v 2p5 2.75 v dc analog input level (@ v dd = avdd3p3) pga s/h stage enabled (bp=0) pga s/h stage disabled (bp=1) v il 0 v dd v dd ? 0.5 v max differential input voltage (@ gain and v dd = avdd3p3) v diffmax (v dd ? 1) x 0.5/gain v linearity (@ voltage gain) 1x 2x 4x 8x 16x 32x l v 1 ? 1/2 lsb 2 ? 1/2 lsb 4 ? 1 lsb 8 ? 1 lsb 16 ? 4 lsb 32 ? 4 lsb 1 + 1/2 lsb 2 + 1/2 lsb 4 + 1 lsb 8 + 1 lsb 16 + 4 lsb 32 + 4 lsb v/v gain error (@ voltage gain) 1x 2x 4x 8x 16x 32x a v 1% v/v sampling frequency (pga_clk_2p5) normal mode (pga_lp_2p5 asserted) low power mode (pga_lp_2p5 negated) sf max 8 4 mhz input signal bandwidth motor control mode (bp=0) general purpose mode (bp=1) bw max pga sampling rate/2 pga sampling rate/8 hz internal voltage doubler clock frequency(pga_clk_doubler_2p5) vd clk 100 2000 khz operating temperature t ?40 125 o c
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 specifications freescale semiconductor 66 8.16 adc specifications figure 37. adc input impedance equivalency diagram table 36. adc operating conditions characteristic conditions symb min typ 1 1 typical values assume v ddad = 3.0 v, temp = 25 ? c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. max unit comment input voltage v adin v refl 2 2 v refl = v ssa ?v refh 3 3 v refh = v dda v input capacitance c adin ?4.55.5pf input resistance r adin ?5 7k ? analog source resistance 12-bit mode f adck > 4 mhz f adck < 4 mhz r as ? ? ? ? 2 5 k ? external to mcu 10-bit mode f adck > 4 mhz f adck < 4 mhz ? ? ? ? 5 10 8-bit mode (all valid f adck )??10 adc conversion clock freq. high speed (adlpc=0) f adck 0.4 ? 8.0 mhz low power (adlpc=1) 0.4 ? 4.0 + ? + ? v as r as c as v adin z as pad leakage due to input protection z adin simplified input pin equivalent circuit r adin adc sar engine simplified channel select circuit input pin r adin c adin input pin r adin input pin r adin
specifications mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 67 table 37. adc characteristics (v refh = v dda , v refl = v ssa ) characteristic conditions symb min typ 1 max unit comment supply current adlpc=1 adlsmp=1 adco=1 i ddad ?120? ? a supply current adlpc=1 adlsmp=0 adco=1 i ddad ?202? ? a supply current adlpc=0 adlsmp=1 adco=1 i ddad ?288? ? a supply current adlpc=0 adlsmp=0 adco=1 i ddad ? 0.532 1 ma adc asynchronous clock source high speed (adlpc=0) f adack 23.35 mhzt adack = 1/f adack low power (adlpc=1) 1.25 2 3.3 conversion time (including sample time) short sample (adlsmp=0) t adc ? 20 ? adck cycles long sample (adlsmp=1) ? 40 ? sample time short sample (adlsmp=0) t ads ? 3.5 ? adck cycles long sample (adlsmp=1) ? 23.5 ? differential non-linearity 12-bit mode dnl ? ? 1.75 ? lsb 2 10-bit mode 3 ? ? 0.5 ? 1.0 8-bit mode 3 ? ? 0.3 ? 0.5 integral non-linearity 12-bit mode inl ? ? 1.5 ? lsb 2 10-bit mode ? ? 0.5 ? 1.0 8-bit mode ? ? 0.3 ? 0.5 quantization error 12-bit mode e q ? ?1 to 0 ? lsb 2 10-bit mode ? ? ? 0.5 8-bit mode ? ? ? 0.5 input leakage error 12-bit mode e il ? ? 2?lsb 2 pad leakage 4 * r as 10-bit mode ? ? 0.2 ? 4 8-bit mode ? ? 0.1 ? 1.2 temp sensor slope ?40 ? c?25 ? c m ? 1.646 ? mv/ ? c 25 ? c?125 ? c ? 1.769 ? temp sensor voltage 25 ? cv temp25 ? 701.2 ? mv
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 specifications freescale semiconductor 68 8.17 hscmp specifications 8.18 optimize power consumption see section 8.6, ?supply cu rrent characteristics ,? for a list of i dd requirements for the 56f8006/56f8002. this section provides additional detail that can be used to optimize power consumption for a given application. 1 typical values assume v dda = 3.0 v, temp = 25 ? c, f adck =1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2 1 lsb = (v refh ? v refl )/2 n 3 monotonicity and no-missing-codes guar anteed in 10-bit and 8-bit modes 4 based on input pad leakage current. refer to pad electricals. table 38. hscmp specifications parameter symbol min typ max unit supply voltage v pwr 1.8 3.6 v supply current, high speed mode (en=1, pmode=1, v dda ? v lvi_trip ) i ddahs 150 ? a supply current, low speed mode (en=1, pmode=0) i ddals 10 ? a supply current, off mode (en=0,) i ddaoff 100 na analog input voltage v ain v ssa ? 0.01 v dda + 0.01 v analog input offset voltage v aio 40 mv analog comparator hysteresis v h 3.0 20.0 mv propagation delay, high speed mode (en=1, pmode=1), 2.4 v < v dda < 3.6 v t dhsn 1 1 measured with an input waveform that switches 30 mv above and below the reference, to the cmpo output pin. v dda > v lvi_warning => lvi_warning not asserted. 70 140 ns propagation delay, high speed mode (en=1, pmode=1), 1.8 v < v dda < 2.4 v t dhsb 2 2 measured with an input waveform that switches 30mv abov e and below the reference, to the cmpo output pin. v dda < v lvi_warning => lvi_warning asserted. 70 249 ns propagation delay, low speed mode (en=1, pmode=0), 2.4 v < v dda < 3.6 v t ainit 3 3 measured with an input waveform that switches 30mv abov e and below the reference, to the cmpo output pin. v dda > v lvi_warning => lvi_warning not asserted. 400 600 ns propagation delay, low speed mode (en=1, pmode=0), 1.8 v < v dda < 2.4 v t ainit 4 4 measured with an input waveform that switches 30mv abov e and below the reference, to the cmpo output pin. v dda < v lvi_warning => lvi_warning asserted. 400 600 ns
specifications mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 69 power consumption is given by the following equation: eqn. 1 a, the internal [static] component, is comp rised of the dc bias currents for the os cillator, leakage curre nts, pll, and voltage references. these sources operate independentl y of processor state or operating frequency. b, the internal [state-dependent] componen t, reflects the supply current required by certain on-chip resour ces only when those resources are in use. these includ e ram, flash memory, and the adcs. c, the internal [dynamic] component, is classic c*v 2 *f cmos power dissipation corresponding to the 56800e core and standard cell logic. d, the external [dynamic] component, reflects power dissipated on-chip as a result of capacitive loading on the external pins o f the chip. this is also commonly described as c*v 2 *f, although simulations on two of the i/o cell types used on the 56800e reveal that the power-versus-load curve does have a non-zero y-intercept. power due to capacitive loading on output pins is (first order) a function of the capacitive lo ad and frequency at which the outputs change. table 39 provides coefficients for calcula ting power dissipated in the i/o ce lls as a function of capacitive load. in these cases: totalpower = ? ((intercept + slope*cload)*frequency/10 mhz) eqn. 2 where: ? summation is performed over all output pins with capacitive loads ? total power is expressed in mw ?c load is expressed in pf because of the low duty cycle on most device pins, power dissipa tion due to capacitive loads was found to be fairly low when averaged over a period of time. e, the external [static componen t], reflects the effects of placi ng resistive loads on the outputs of the device. sum the total of all v 2 /r or iv to arrive at the resistive load contribution to po wer. assume v = 0.5 for the purposes of these rough calculations. for instance, if there is a total of eight pwm outputs driving 10 ma into leds, then p = 8*0.5*0.01 = 40 mw. in previous discussions, power consumption due to parasitics associ ated with pure input pins is ignored, as it is assumed to be negligible. total power = a: internal [static component] +b: internal [state-dependent component] +c: internal [dynamic component] +d: external [dynamic component] +e: external [static component] table 39. i/o loading coefficients at 10 mhz intercept slope 8 ma drive 1.3 0.11 mw/pf 4 ma drive 1.15 mw 0.11 mw/pf
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 design considerations freescale semiconductor 70 9 design considerations 9.1 thermal design considerations an estimation of the chip junction temperature, t j , can be obtained from the equation: t j = t a + (r ? j ? x p d ) eqn. 3 where: the junction-to-ambient thermal resistance is an industry-standard value that provides a quick and eas y estimation of thermal performance. unfortunately, there are two values in common usage: the value determ ined on a single-layer board and the value obtained on a board with two planes. for pack ages such as the pbga, these values can be different by a factor of two. which value is closer to the application depends on the power dissipated by other components on the board. the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. th e value obtained on the board with the intern al planes is usually appropriate if the board has low- power dissipation and the components are well separated. when a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case therma l resistance and a case-to-ambient thermal resistance: r ? ja = r ? jc + r ? ca eqn. 4 where: r ? jc is device related and cannot be adjusted. you control the thermal environment to change the case to ambient thermal resistance, r ? ca . for instance, you can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change th e thermal dissipation on the printed circuit board surrounding the device. to determine the junction temperature of the device in the application when heat si nks are not used, the thermal characterizati on parameter ( ? jt ) can be used to determine the junction temperature with a measurement of the temper ature at the top center of the package case using the following equation: t j = t t + ( ? jt x p d ) eqn. 5 where: the thermal characterization parameter is measured per jesd5 1?2 specification using a 40-gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple juncti on and over about 1 mm of wire extending from the t a = ambient temperature for the package ( o c) r ? j ?? = junction-to-ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) r ? ja = package junction-to-ambient thermal resistance (c/w) r ? jc = package junction-to-case thermal resistance (c/w) r ? ca = package case-to-ambient thermal resistance (c/w) t t = thermocouple temperature on top of package ( o c) ? jt = thermal characterization parameter ( o c/w) p d = power dissipation in package (w)
design considerations mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 71 junction. the thermocouple wire is placed flat against the package case to av oid measurement errors caused by cooling effects of the thermocouple wire. when heat sink is used, the junction te mperature is determined from a thermocoupl e inserted at the interface between the case of the package and the interface material. a clearance slot or hole is normally required in the heat sink. minimizing the size of the clearance is important to mini mize the change in th ermal performance caused by removing part of the thermal interface to the heat sink. because of the experimental difficulties with this tec hnique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate m easurement of the thermal resistan ce of the interface. from this case temperature, the junction temp erature is determined from the junction-to-case thermal resistance. 9.2 electrical design considerations caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, take normal pr ecautions to avoid application of any voltages higher than maximum-rated voltages to th is high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. use the following list of considerations to assure correct operation of the 56f8006/56f8002: ? provide a low-impedance path from the board power supply to each v dd pin on the 56f8006/56f8002 and from the board ground to each v ss (gnd) pin. ? the minimum bypass requirement is to place 0.01?0.1f capaci tors positioned as near as possible to the package supply pins. the recommended bypass configuration is to place one bypass capacitor on each of the v dd /v ss pairs, including v dda /v ssa. ceramic and tantalum capacitors te nd to provide better tolerances. ? ensure that capacitor leads and associated prin ted circuit traces that connect to the chip v dd and v ss (gnd) pins are as short as possible. ? bypass the v dd and v ss with approximately 100 f, plus the number of 0.1 f ceramic capacitors. ? pcb trace lengths should be minimal for high-frequency signals. ? consider all device loads as well as parasitic capacitance due to pcb traces when calcu lating capacitance. this is especially critical in systems with higher capacitive load s that could create higher transient currents in the v dd and v ss circuits. ? take special care to minimize noise levels on the v ref , v dda , and v ssa pins. ? using separate power planes for v dd and v dda and separate ground planes for v ss and v ssa are recommended. connect the separate analog and digital power and ground plan es as near as possible to power supply outputs. if an analog circuit and digital circuit are powered by the same power supply, you should connect a small inductor or ferrite bead in serial with v dda and v ssa traces. ? physically separate analog components from noisy digital components by gr ound planes. do not place an analog trace in parallel with digital traces. place an analog ground trace ar ound an analog signal trace to isolate it from digital traces. ? because the flash memory is programmed thr ough the jtag/eonce por t, spi, sci, or i 2 c, the designer should provide an interface to this port if in-circuit flash programming is desired. ? if desired, connect an external rc circuit to the reset pin. the resistor value should be in the range of 4.7 k ? ?10 k ? ; the capacitor value should be in the range of 0.22 f?4.7 f. ? configuring the reset pin to gpio output in normal operation in a high-noise environment may help to improve the performance of noise transient immunity. ? add a 2.2 k ? external pullup on the tms pin of the jtag port to k eep eonce in a restate duri ng normal operation if jtag converter is not present. ? during reset and after reset but before i/o initialization, all i/o pins are at input state with internal pullup enabled. the typical value of internal pullup is around 33 k ? . these internal pullups can be disabled by software. ? to eliminate pcb trace impedance effect, each adc input should have a no less than 33 pf 10 ? rc filter. ? external clamp diodes on analog input pins are recommended.
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 design considerations freescale semiconductor 72 9.3 ordering information table 40 lists the pertinent information needed to place an order. consult a freescale se miconductor sales office or authorized distributor to determine availability and to order devices. table 40. 56f8006/56f8002 ordering information device supply voltag e package type pin count frequency (mhz) ambient temperature range order number mc56f8002 1.8?3.6 v small outline ic (soic) 28 32 ?40 to + 105 c ?40 to + 125 c mc56f8002vwl mc56f8002mwl 1 1 this package is rohs compliant. mc56f8006 1.8?3.6 v small outline ic (soic) 28 32 ?40 to + 105 c ?40 to + 125 c mc56f8006vwl mc56f8006mwl 1 mc56f8006 1.8?3.6 v low-profile quad flat pack (lqfp) 32 32 ?40 to + 105 c ?40 to + 125 c mc56f8006vlc mc56f8006mlc 1 mc56f8006 1.8?3.6 v low-profile quad flat pack (lqfp) 48 32 ?40 to + 105 c ?40 to + 125 c mc56f8006vlf mc56f8006mlf 1 mc56f8006 1.8?3.6 v plastic shrink dual in-line package (psdip) 32 32 ?40 to + 105 c mc56f8006vbm
package mechanical outline drawings mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 73 10 package mechanical outline drawings 10.1 28-pin soic package
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 package mechanical outline drawings freescale semiconductor 74
package mechanical outline drawings mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 75 figure 38. 56f8006/56f8002 28-pin soic mechanical information
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 package mechanical outline drawings freescale semiconductor 76 10.2 32-pin lqfp
package mechanical outline drawings mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 77
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 package mechanical outline drawings freescale semiconductor 78 figure 39. 56f8006/56f8002 32-pin lqfp mechanical information
package mechanical outline drawings mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 79 10.3 48-pin lqfp
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 package mechanical outline drawings freescale semiconductor 80 figure 40. 56f8006/56f8002 48-pin lqfp mechanical information
package mechanical outline drawings mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 81 10.4 32-pin psdip
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 package mechanical outline drawings freescale semiconductor 82 figure 41. 56f8006/56f8002 32-pin psdip mechanical information
revision history mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 83 11 revision history table 41 lists major changes between versions of the mc56f8006 document. appendix a interrupt vector table table 43 provides the 56f8006/56f8002?s reset and interrupt priority structure, includi ng on-chip peripherals. the table is organized with higher-priority vectors at the top and lower-priori ty interrupts lower in the table. as indicated, the priority of an interrupt can be assigned to different levels, allowing some c ontrol over interrupt priorities . all level 3 interrupts are serv iced before level 2 and so on. for a selected priority leve l, the lowest vector number has the highest priority. the location of the vector table is determined by the vector base addres s (vba). please see the mc56f8006 peripheral reference manual for detail. by default, the chip reset address and cop reset address correspo nd to vector 0 and 1 of the interrupt vector table. in these instances, the first two locations in the vector table must contai n branch or jmp instructions. all other entries must contain jsr instructions. table 41. changes between revisions 2 and 3 location description introduction on page 1 added part marking for devices covered by this document section 6.7, ?pwm, pd b, pga, and adc connections ,? on page 38 updated routing details for anb24 and anb25 ta bl e 1 2 on page 42 removed row about open drain mode (gpio supports only push-pull mode) ta bl e 2 1 on page 47 updated specifications for low-voltage det ection threshold (high and low range) and low-voltage warning threshold ta bl e 2 2 on page 51 updated all supply current consumption specifications ta bl e 2 6 and figure 22 on page 55 updated rosc variation over temper ature specifications (both ranges) ta bl e 3 1 on page 62 removed i 2 c fast mode specifications and footno te about setup time if the tx fifo is empty (fast mode and fifo not supported) appendix b on page 86 added note explaining adc and gpio naming conventions ta bl e 4 4 on page 86 for i2c_smb_csr, clarified that bits 7 and 6 are reserved table 42. changes between revisions 3 and 4 location description throughout document. added information for 32-pin psdip device and devices with temperature range from ?40 ? c to + 125 ? c.
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 interrupt vector table freescale semiconductor 84 table 43. interrupt vector table contents 1 peripheral vector number user encoding priority level vector base address + interrupt function core p:0x00 reserved for reset overlay 2 core p:0x02 reserved for cop reset overlay core 2 n/a 3 p:0x04 ill egal instruction core 3 n/a 3 p:0x06 hw stack overflow core 4 n/a 3 p:0x08 misaligned long word access core 5 n/a 3 p:0x0a eonce step counter core 6 n/a 3 p:0x0c eonce breakpoint unit core 7 n/a 3 p:0x0e eonce trace buffer core 9 n/a 3 p:0x10 eonce transmit register empty core 9 n/a 3 p:0x12 eonce receive register full pmc 10 0x0a 0 p:0x14 low-voltage detector pll 11 0x0b 0 p:0x16 phase-locked loop loss of locks and loss of clock adca 12 0x0c 0 p:0x18 adca conversion complete adcb 13 0x0d 0 p:0x1a adcb conversion complete pwm 14 0x0e 0 p:0x1c reload pwm and/or pwm faults cmp0 15 0x0f 0 p:0x1e comparator 0 rising/falling flag cmp1 16 0x10 0 p:0x20 comparator 1 rising/falling flag cmp2 17 0x11 0 p:0x22 comparator 2 rising/falling flag fm 18 0x12 0 p:0x24 flash memory access status spi 19 0x13 0 p:0x26 spi receiver full spi 20 0x14 0 p:0x28 spi transmitter empty sci 21 0x15 0 p:0x2a sci transmitter empty/idle sci 22 0x16 0 p:0x2c sci receiver full/overrun/errors i 2 c230x170 p:0x2e i 2 c interrupt pit 24 0x18 0 p:0x30 interval timer interrupt tmr0 25 0x19 0 p:0x32 dual timer, channel 0 interrupt tmr1 26 0x1a 0 p:0x34 dual timer, channel 1 interrupt gpioa 27 0x1b 0 p:0x36 gpioa interrupt gpiob 28 0x1c 0 p:0x38 gpiob interrupt gpioc 29 0x1d 0 p:0x3a gpioc interrupt gpiod 30 0x1e 0 p:0x3c gpiod interrupt gpioe 29 0x1f 0 p:0x3e gpioe interrupt gpiof 30 0x20 0 p:0x40 gpiof interrupt rtc 33 0x21 0 p:0x42 real time clock
interrupt vector table mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 85 reserved 34- 39 0x22-0x27 0 p:0x44 - p:0x4e reserved core 40 n/a 0 p:0x50 sw interrupt 0 core 41 n/a 1 p:0x52 sw interrupt 1 core 42 n/a 2 p:0x54 sw interrupt 2 core 43 n/a 3 p:0x56 sw interrupt 3 swilp 44 n/a -1 p:0x58 sw interrupt low priority user1 45 n/a 1 p:0x5a user programmable priority level 1 interrupt user2 46 n/a 1 p:0x5c user programmable priority level 1 interrupt user3 47 n/a 1 p:0x5e user programmable priority level 1 interrupt user4 48 n/a 2 p:0x60 user programmable priority level 2 interrupt user5 49 n/a 2 p:0x62 user programmable priority level 2 interrupt user6 3 50 n/a 2 p:0x64 user programmable priority level 2 interrupt 1 two words are allocated for each entry in the vector table. th is does not allow the full address range to be referenced from the vector table, providing only 19 bits of address. 2 if the vba is set to the reset value, the first two locations of the vector table ov erlay the chip reset addresses because the reset address would match the base of this vector table. 3 user6 vector can be defined as a fast inte rrupt if the instruction located in this ve ctor location is not a jsr or bsr instruct ion. please see section 9.3.3.3 of dsp56800e 16-bit core reference manual for detail. table 43. interrupt vector table contents 1 (continued) peripheral vector number user encoding priority level vector base address + interrupt function
peripheral register memo ry map and reset value mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 86 appendix b peripheral register memory map and reset value note in table 44 , adc0 stands for adca, adc1 stands for adcb, and gpion is the same as gpio_n (for example, gpioa_pur is the same as gpio_a_pur). table 44. detailed peripheral memory map offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0 00 0000 tmr0 tmr0_ comp1 comparison_1 01 0000 tmr0 tmr0_ comp2 comparison_2 02 0000 tmr0 tmr0_ capt capture 03 0000 tmr0 tmr0_ load load 04 0000 tmr0 tmr0_ hold hold 05 0000 tmr0 tmr0_ cntr counter 06 0000 tmr0 tmr0_ ctrl cm pcs scs once length dir co_init om 07 0000 tmr0 tmr0_ sctrl tcf tcfie tof tofie ief iefie ips input capture_ mode mstr eeof val force ops oen 08 0000 tmr0 tmr0_ cmpld1 comparator_load_1 09 0000 tmr0 tmr0_ cmpld2 comparator_load_2
peripheral register memo ry map and reset value mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 87 0a 0000 tmr0 tmr0_ csctrl dbg_en fault alt_load 0 0 0 0 tcf2en tcf1en tcf2 tcf1 cl2 cl1 0b 0000 tmr0 tmr0_ filt 0 0 0 0 0 filt_cnt filt_per 0c?0e ? tmr0 reserved reserved 0f 000f tmr0 tmr_ enbl 0 0 0 0 0 0 0 0 0 0 0 0enbl 10 0000 tmr1 tmr1_ comp1 comparison_1 11 0000 tmr1 tmr1_ comp2 comparison_2 12 0000 tmr1 tmr1_ capt capture 13 0000 tmr1 tmr1_ load load 14 0000 tmr1 tmr1_ hold hold 15 0000 tmr1 tmr1_ cntr counter 16 0000 tmr1 tmr1_ ctrl cm pcs scs once length dir coinit om 17 0000 tmr1 tmr1_ sctrl tcf tcfie tof tofie ief iefie ips input capture_ mode mstr eeof val force ops oen 18 0000 tmr1 tmr1_ cmpld1 comparator_load_1 19 0000 tmr1 tmr1_ cmpld2 comparator_load_2 table 44. detailed peripheral memory map (continued) offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 88 peripheral register memory map and reset value 1a 0000 tmr1 tmr1_ csctrl dbg_en fault alt_load 0 0 0 0 tcf2en tcf1en tcf2 tcf1 cl2 cl1 1b 0000 tmr1 tmr1_ filt 0 0 0 0 0 filt_cnt filt_per 1c?1f ? tmr1 reserved reserved 20 0000 pwm pwm_ ctrl ldfq half ipol2 ipol1 ipol0 prsc pwmrie pwmf isens ldok pwmen 21 0000 pwm pwm_ fctrl 0 0 0 0 fpol3 fpol2 fpol1 fpol0 fie3 fmode3 fie2 fmode2 fie1 fmode1 fie0 fmode0 22 0000 pwm pwm_ fltack fpin3 fflag3 fpin2 fflag2 fpin1 fflag1 fpin0 fflag0 ftack3 ftack2 ftack1 ftack0 23 0000 pwm pwm_ out pa d _ e n 0 outctl5 outctl4 outctl3 outctl2 outctl1 outctl0 0 0 out5 out4 out3 out2 out1 out0 24 0000 pwm pwm_ cntr 0cr 25 0000 pwm pwm_ cmod 0pwmcm 26 0000 pwm pwm_ val0 pmval 27 0000 pwm pwm_ val1 pmval 28 0000 pwm pwm_ val2 pmval table 44. detailed peripheral memory map (continued) offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0
peripheral register memo ry map and reset value mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 89 29 0000 pwm pwm_ val3 pmval 2a 0000 pwm pwm_ val4 pmval 2b 0000 pwm pwm_ val5 pmval 2c 0fff pwm pwm_ dtim0 0 0 0 0pwmdt0 2d 0fff pwm pwm_ dtim1 0 0 0 0pwmdt1 2e ffff pwm pwm_ dmap1 dismap_15_0 2f 00ff pwm pwm_ dmap2 0 0 0 0 0 0 0 0 dismap_23_16 30 0000 pwm pwm_ cnfg 0 dbg_en wait_en edg 0 topneg45 topneg23 topneg01 0 botneg45 botneg23 botneg01 indep45 indep23 indep01 wp 31 0000 pwm pwm_ cctrl enha nbx msk5 msk4 msk3 msk2 msk1 msk0 0 0vlmode 0 swp45 swp23 swp01 32 00-u 1 pwm pwm_ port 0 0 0 0 0 0 0 0 0port 33 0000 pwm pwm_ icctrl 0 0 0 0 0 0 0 0 0 0 pec2 pec1 pec0 icc2 icc1 icc0 34 0000 pwm pwm_ sctrl 0 0 cinv5 cinv4 cinv3 cinv2 cinv1 cinv0 0src2 0 src1 0 src0 table 44. detailed peripheral memory map (continued) offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 90 peripheral register memory map and reset value 35 0000 pwm pwm_ sync sync_out_en sync_window 36 0000 pwm pwm_ ffilt0 gstr0 0 0 0 0 filt0_cnt filt0_per 37 0000 pwm pwm_ ffilt1 gstr1 0 0 0 0 filt1_cnt filt1_per 38 0000 pwm pwm_ ffilt2 gstr2 0 0 0 0 filt2_cnt filt2_per 39 0000 pwm pwm_ ffilt3 gstr3 0 0 0 0 filt3_cnt filt3_per 3b?3f ? pwm reserved reserved 40 0000 intc intc_ icsr int ipic vab int_dis errf etre trbuf bkpt stpcnt 41 0000 intc intc_ vba 0 0 vector_base_address 42 0000 intc intc_ iar0 0 0 user2 0 0 user1 43 0000 intc intc_ iar1 0 0 user4 0 0 user3 44 0000 intc intc_ iar2 0 0 user6 0 0 user5 45?5f ? intc reserved reserved 60 001f adc0 adc0_ adcsc1a 0 0 0 0 0 0 0 0 coco aien adco adch table 44. detailed peripheral memory map (continued) offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0
peripheral register memo ry map and reset value mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 91 61 0000 adc0 adc0_ adcsc2 0 0 0 0 0 0 0 0 adact adtrg 0 0 0 ecc refsel 62?65 ? adc0 reserved reserved 66 0000 adc0 adc0_ adccfg 0 0 0 0 0 0 0 0 adlpc adiv adlsmp mode adiclk 67?69 ? adc0 reserved reserved 6a 001f adc0 adc0_ adcsc1b 0 0 0 0 0 0 0 0 coco aien adco adch 6b 0000 adc0 adc0_ adcra 0 adr11 adr10 adr9 adr8 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 0 0 0 6c 0000 adc0 adc0_ adcrb 0 adr11 adr10 adr9 adr8 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 0 0 0 6d?6f ? adc0 reserved reserved 80 001f adc1 adc1_ adcsc1a 0 0 0 0 0 0 0 0 coco aien adco adch 81 0000 adc1 adc1_ adcsc2 0 0 0 0 0 0 0 0 adact adtrg 0 0 0 ecc refsel 82?85 ? adc1 reserved reserved 86 0000 adc1 adc1_ adccfg 0 0 0 0 0 0 0 0 adlpc adiv adlsmp mode adiclk 87?89 ? adc1 reserved reserved 8a 001f adc1 adc1_ adcsc1b 0 0 0 0 0 0 0 0 coco aien adco adch table 44. detailed peripheral memory map (continued) offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 92 peripheral register memory map and reset value 8b 0000 adc1 adc1_ adcra 0 adr11 adr10 adr9 adr8 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 0 0 0 8c 0000 adc1 adc1_ adcrb 0 adr11 adr10 adr9 adr8 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 0 0 0 8d?8f ? adc1 reserved reserved a0 0000 pga0 pga0_ cntl0 0 0 0 0 0 0 0 0 tm gainsel lp en a1 0002 pga0 pga0_ cntl1 0 0 0 0 0 0 0 0 ppdis pa r m o d e 0calmode cpd a2 000e pga0 pga0_ cntl2 0 0 0 0 0 0 0 0 0 0 swtrig num_clk_gs adiv a3 0000 pga0 pga0_sts 0 0 0 0 0 0 0 0 0 0 0 0 0 0 running stcomp a4?bf ? pga0 reserved reserved c0 0000 pga1 pga1_ cntl0 0 0 0 0 0 0 0 0 tm gainsel lp en c1 0002 pga1 pga1_ cntl1 0 0 0 0 0 0 0 0 ppdis pa r m o d e 0calmode cpd c2 000e pga1 pga1_ cntl2 0 0 0 0 0 0 0 0 0 0 swtrig num_clk_gs adiv table 44. detailed peripheral memory map (continued) offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0
peripheral register memo ry map and reset value mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 93 c3 0000 pga1 pga1_sts 0 0 0 0 0 0 0 0 0 0 0 0 0 0 running stcomp c4?df ? pga1 reserved reserved e0 0200 sci sci_rate sbr frac_sbr e1 0000 sci sci_ ctrl1 loop swai rsrc m wake pol pe pt teie tiie rfie reie te re rwu sbk e2 0000 sci sci_ ctrl2 0 0 0 0 0 0 0 0 0 0 0 0 lin _mode 0 0 0 e3 c000 sci sci_stat tdre tidle rdrf ridle or nf fe pf 0 0 0 0lse 0 0raf e4 0000 sci sci_data 0 0 0 0 0 0 0 receive_transmit_data e5?ff ? sci reserved reserved 00 6141 spi spi_ sctrl spr dso errie modfen sprie spmstr cpol cpha spe sptie sprf ovrf modf spte 01 000f spi spi_ dsctrl wom 0 0bd2x ssb_in ssb_data ssb_odm ssb_auto ssb_ddr ssb_strb ssb_over spr3 ds 02 0000 spi spi_drcv r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 03 0000 spi spi_dxmit t15 t14 t13 t12 t11 t10 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 04?1f ? spi reserved reserved 20 0000 i2c i2c_addr 0 0 0 0 0 0 0 0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 0 21 0000 i2c i2c_ freqdiv 0 0 0 0 0 0 0 0mult icr table 44. detailed peripheral memory map (continued) offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 94 peripheral register memory map and reset value 22 0000 i2c i2c_cr1 0 0 0 0 0 0 0 0 iicen iicie mst tx txak rsta 0 0 23 0080 i2c i2c_sr 0 0 0 0 0 0 0 0 tcf iaas busy arbl 0 srw iicif rxak 24 0000 i2c i2c_data 0 0 0 0 0 0 0 0data 25 0000 i2c i2c_cr2 0 0 0 0 0 0 0 0 gcaen adext 0 0 0 ad10 ad9 ad8 26 0000 i2c i2c_smb_ csr 0 0 0 0 0 0 0 0 reserved reserved siicaen tcksel sltf shtf 0 0 27 0000 i2c i2c_ addr2 0 0 0 0 0 0 0 0 sad7 sad6 sad5 sad4 sad3 sad2 sad1 0 28 0000 i2c i2c_slt1 0 0 0 0 0 0 0 0 sslt15 sslt14 sslt13 sslt12 sslt11 sslt10 sslt9 sslt8 29 0000 i2c i2c_slt2 0 0 0 0 0 0 0 0 sslt7 sslt6 sslt5 sslt4 sslt3 sslt2 sslt1 sslt0 30?3f ? i2c reserved reserved 40 0302 cop cop_ ctrl 0 0 0 0 0 0 pss 0 clksel cloren csen cwen cen cwp 41 ffff cop cop_ tout timeout 42 ffff cop cop_ cntr count_service 43?5f ? cop reserved reserved table 44. detailed peripheral memory map (continued) offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0
peripheral register memo ry map and reset value mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 95 60 0011 occs occs_ ctrl pllie1 pllie0 locie 0 0 0 lckon 0 0 pllpd 0 precs zsrc 61 2000 occs occs_ divby lortp cod 0 0 0 0 0 0 0 0 62 0015 occs occs_ stat loli1 loli0 loci 0 0 0 0 0 0lck1lck0 pllpdn 0 cosc_rdy zsrc 64 1611 occs occs_ octrl ropd rosb cohl clk_mode range ext_sel trim 65 0000 occs occs_ clkchkr chk_ena reference_cnt 66 0000 occs occs_ clkchkt 0 0 0 0 0 0 0 0 0 target_cnt 67 0000 occs occs_ prot 0 0 0 0 0 0 0 0 0 0 frqep oscep pllep 68?7f ? occs reserved reserved 80 00ff gpioa gpioa_ pur 0 0 0 0 0 0 0 0pu 81 0000 gpioa gpioa_dr 0 0 0 0 0 0 0 0d 82 0000 gpioa gpioa_ ddr 0 0 0 0 0 0 0 0dd 83 0080 gpioa gpioa_ per 0 0 0 0 0 0 0 0pe 84 ? gpioa reserved reserved table 44. detailed peripheral memory map (continued) offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 96 peripheral register memory map and reset value 85 0000 gpioa gpioa_ ienr 0 0 0 0 0 0 0 0ien 86 0000 gpioa gpioa_ ipolr 0 0 0 0 0 0 0 0ipol 87 0000 gpioa gpioa_ ipr 0 0 0 0 0 0 0 0ip 88 0000 gpioa gpioa_ iesr 0 0 0 0 0 0 0 0ies 89 ? gpioa reserved reserved 8a 0000 gpioa gpioa_ rawdata 0 0 0 0 0 0 0 0rawdata 8b 0000 gpioa gpioa_ drive 0 0 0 0 0 0 0 0drive 8c 00ff gpioa gpioa_ife 0 0 0 0 0 0 0 0ife 8d 0000 gpioa gpioa_ slew 0 0 0 0 0 0 0 0slew 8e?9f ? gpioa reserved reserved a0 00ff gpiob gpiob_ pur 0 0 0 0 0 0 0 0pur a1 0000 gpiob gpiob_dr 0 0 0 0 0 0 0 0dr a2 0000 gpiob gpiob_ ddr 0 0 0 0 0 0 0 0 ddr a3 0080 gpiob gpiob_ per 0 0 0 0 0 0 0 0 per a4 ? gpiob reserved reserved a5 0000 gpiob gpiob_ ienr 0 0 0 0 0 0 0 0ienr a6 0000 gpiob gpiob_ ipolr 0 0 0 0 0 0 0 0ipolr table 44. detailed peripheral memory map (continued) offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0
peripheral register memo ry map and reset value mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 97 a7 0000 gpiob gpiob_ ipr 0 0 0 0 0 0 0 0ipr a8 0000 gpiob gpiob_ iesr 0 0 0 0 0 0 0 0 iesr a9 ? gpiob reserved reserved aa 0000 gpiob gpiob_ rawdata 0 0 0 0 0 0 0 0rawdata ab 0000 gpiob gpiob_ drive 0 0 0 0 0 0 0 0drive ac 00ff gpiob gpiob_ife 0 0 0 0 0 0 0 0ife ad 0000 gpiob gpiob_ slew 0 0 0 0 0 0 0 0slew ae?bf ? gpiob reserved reserved c0 00ff gpioc gpioc_ pur 0 0 0 0 0 0 0 0pur c1 0000 gpioc gpioc_dr 0 0 0 0 0 0 0 0dr c2 0000 gpioc gpioc_ ddr 0 0 0 0 0 0 0 0 ddr c3 0080 gpioc gpioc_ per 0 0 0 0 0 0 0 0 per c4 ? gpioc reserved reserved c5 0000 gpioc gpioc_ ienr 0 0 0 0 0 0 0 0ienr c6 0000 gpioc gpioc_ ipolr 0 0 0 0 0 0 0 0ipolr c7 0000 gpioc gpioc_ ipr 0 0 0 0 0 0 0 0ipr c8 0000 gpioc gpioc_ iesr 0 0 0 0 0 0 0 0 iesr table 44. detailed peripheral memory map (continued) offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 98 peripheral register memory map and reset value c9 ? gpioc reserved reserved ca 0000 gpioc gpioc_ rawdata 0 0 0 0 0 0 0 0rawdata cb 0000 gpioc gpioc_ drive 0 0 0 0 0 0 0 0drive cc 00ff gpioc gpioc_ ife 0 0 0 0 0 0 0 0ife cd 0000 gpioc gpioc_ slew 0 0 0 0 0 0 0 0slew ce?df ? gpioc reserved reserved e0 00ff gpiod gpiod_ pur 0 0 0 0 0 0 0 0 0 0 0 0pur e1 0000 gpiod gpiod_dr 0 0 0 0 0 0 0 0 0 0 0 0dr e2 0000 gpiod gpiod_ ddr 0 0 0 0 0 0 0 0 0 0 0 0 ddr e3 0080 gpiod gpiod_ per 0 0 0 0 0 0 0 0 0 0 0 0 per e4 ? gpiod reserved reserved e5 0000 gpiod gpiod_ ienr 0 0 0 0 0 0 0 0 0 0 0 0ienr e6 0000 gpiod gpiod_ ipolr 0 0 0 0 0 0 0 0 0 0 0 0ipolr e7 0000 gpiod gpiod_ ipr 0 0 0 0 0 0 0 0 0 0 0 0ipr e8 0000 gpiod gpiod_ iesr 0 0 0 0 0 0 0 0 0 0 0 0 iesr e9 ? gpiod reserved reserved ea 0000 gpiod gpiod_ rawdata 0 0 0 0 0 0 0 0 0 0 0 0rawdata table 44. detailed peripheral memory map (continued) offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0
peripheral register memo ry map and reset value mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 99 eb 0000 gpiod gpiod_ drive 0 0 0 0 0 0 0 0 0 0 0 0drive ec 00ff gpiod gpiod_ ife 0 0 0 0 0 0 0 0 0 0 0 0ife ed 0000 gpiod gpiod_ slew 0 0 0 0 0 0 0 0 0 0 0 0slew ee?9f ? gpiod reserved reserved 00 00ff gpioe gpioe_ pur 0 0 0 0 0 0 0 0pur 01 0000 gpioe gpioe_dr 0 0 0 0 0 0 0 0dr 02 0000 gpioe gpioe_ ddr 0 0 0 0 0 0 0 0 ddr 03 0080 gpioe gpioe_ per 0 0 0 0 0 0 0 0 per 04 ? gpioe reserved reserved 05 0000 gpioe gpioe_ ienr 0 0 0 0 0 0 0 0ienr 06 0000 gpioe gpioe_ ipolr 0 0 0 0 0 0 0 0ipolr 07 0000 gpioe gpioe_ ipr 0 0 0 0 0 0 0 0ipr 08 0000 gpioe gpioe_ iesr 0 0 0 0 0 0 0 0 iesr 09 ? gpioe reserved reserved 0a 0000 gpioe gpioe_ rawdata 0 0 0 0 0 0 0 0rawdata 0b 0000 gpioe gpioe_ drive 0 0 0 0 0 0 0 0drive 0c 00ff gpioe gpioe_ife 0 0 0 0 0 0 0 0ife table 44. detailed peripheral memory map (continued) offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 100 peripheral register memory map and reset value 0d 0000 gpioe gpioe_ slew 0 0 0 0 0 0 0 0slew 0e?1f ? gpioe reserved reserved 20 00ff gpiof gpiof_ pur 0 0 0 0 0 0 0 0 0 0 0 0pur 21 0000 gpiof gpiof_dr 0 0 0 0 0 0 0 0 0 0 0 0dr 22 0000 gpiof gpiof_ ddr 0 0 0 0 0 0 0 0 0 0 0 0 ddr 23 0080 gpiof gpiof_ per 0 0 0 0 0 0 0 0 0 0 0 0 per 24 ? gpiof reserved reserved 25 0000 gpiof gpiof_ ienr 0 0 0 0 0 0 0 0 0 0 0 0ienr 26 0000 gpiof gpiof_ ipolr 0 0 0 0 0 0 0 0 0 0 0 0ipolr 27 0000 gpiof gpiof_ ipr 0 0 0 0 0 0 0 0 0 0 0 0ipr 28 0000 gpiof gpiof_ iesr 0 0 0 0 0 0 0 0 0 0 0 0 iesr 29 ? gpiof reserved reserved 2a 0000 gpiof gpiof_ rawdata 0 0 0 0 0 0 0 0 0 0 0 0rawdata 2b 0000 gpiof gpiof_ drive 0 0 0 0 0 0 0 0 0 0 0 0drive 2c 00ff gpiof gpiof_ife 0 0 0 0 0 0 0 0 0 0 0 0ife 2d 0000 gpiof gpiof_ slew 0 0 0 0 0 0 0 0 0 0 0 0slew 2e?3f ? gpiof reserved reserved table 44. detailed peripheral memory map (continued) offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0
peripheral register memo ry map and reset value mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 101 40 0000 sim sim_ctrl 0 0 0 0 0 0 0 0 0 0 onceebl sw rst stop_ disable wait_ disable 41 0001 sim sim_ rstat 0 0 0 0 0 0 0 0 0swr cop_cpu cop_lor extr lv d r p p d p o r 42 01f2 sim sim_ mshid sim_msh_id 43 601d sim sim_ lshid sim_lsh_id 45 2020 sim sim_ clkout 0 0 clkdis1 0 0 clkosel1 0 0 clkdis0 clkosel0 46 0000 sim sim_pcr tmr_cr 0 pwm_cr sci_cr 0 0 0 0 0 0 0 0 0 0 0 0 47 0000 sim sim_pce cmp2 cmp1 cmp0 adc1 adc0 pga1 pga0 i2c sci spi pwm cop pdb pit ta1 ta0 48 0000 sim sim_sdr cmp2 cmp1 cmp0 adc1 adc0 pga1 pga0 i2c sci spi pwm cop pdb pit ta1 ta0 49 f000 sim sim_isal addr_15_6 0 0 0 0 0 0 4a 0000 sim sim_prot 0 0 0 0 0 0 0 0 0 0 0 0 pcep gipsp 4b 0000 sim sim_gpsa 0 0 0 0 0 0 0 gps_a6 gps_a5 gps_a4 gps_a3 4c 0000 sim sim_ gpsb0 gps_b5 gps_b4 gps_b3 gps_b2 0 gps_b1 gps_b0 4d 0000 sim sim_ gpsb1 0 0 0 0 0 0 0 0 0 0 0 0 gps_b7 gps_b6 table 44. detailed peripheral memory map (continued) offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 102 peripheral register memory map and reset value 4e 0000 sim sim_gpsc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gps_c6 gps_c0 4f 0000 sim sim_gpsd 0 0 0 0 0 0 0 gps_d3 gps_d2 gps_d1 gps_d0 50 0000 sim sim_ips0 0 0 0 0 ips_fault3 ips_fault2 ips_fault1 ips_psrc2 ips_psrc1 ips_psrc0 51 0000 sim sim_ips1 0 ips_c2_ws ips_c1_ws i ps_c0_ws ips_t1 ips_t0 52?5f ? sim reserved reserved 60 0208 pmc pmc_scr oorf lv d f ppdf porf oorie lv d i e lvdre ppde lpr lprs lpwui bgbe lv d e lv l s p rot 61 00-- 2 pmc pmc_cr2 0 0 0 0 0 0 0 lpo_en lpo_trim trim 7f ? pmc reserved reserved 80 0000 cmp0 cmp0_ cr0 0 0 0 0 0 0 0 0 0 filter_cnt pmc mmc 81 0000 cmp0 cmp0_ cr1 0 0 0 0 0 0 0 0sewe 0 pmode inv cos ope en 82 0000 cmp0 cmp0_ fpr 0 0 0 0 0 0 0 0 filt_per 83 0000 cmp0 cmp0_ scr 0 0 0 0 0 0 0 0 0 0 0ieriefcfrcff cout 84?9f ? cmp0 reserved reserved a0 0000 cmp1 cmp1_ cr0 0 0 0 0 0 0 0 0 0 filter_cnt pmc mmc table 44. detailed peripheral memory map (continued) offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0
peripheral register memo ry map and reset value mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 103 a1 0000 cmp1 cmp1_ cr1 0 0 0 0 0 0 0 0sewe 0 pmode inv cos ope en a2 0000 cmp1 cmp1_ fpr 0 0 0 0 0 0 0 0 filt_per a3 0000 cmp1 cmp1_ scr 0 0 0 0 0 0 0 0 0 0 0ieriefcfrcff cout a4?bf ? cmp1 reserved reserved c0 0000 cmp2 cmp2_ cr0 0 0 0 0 0 0 0 0 0 filter_cnt pmc mmc c1 0000 cmp2 cmp2_ cr1 0 0 0 0 0 0 0 0sewe 0 pmode inv cos ope en c2 0000 cmp2 cmp2_ fpr 0 0 0 0 0 0 0 0 filt_per c3 0000 cmp2 cmp2_ scr 0 0 0 0 0 0 0 0 0 0 0ieriefcfrcff cout c4?df ? cmp2 reserved reserved e0 0000 pit pit_ctrl 0 0 0 0 0 0 0 0 0 prescaler prf prie cnt_en e1 0000 pit pit_mod modulo_value e2 0000 pit pit_cntr counter_value e3?ff ? pit reserved reserved 00 0000 pdb pdb_scr prescaler 0aos 0bos cont swtrig trigsel ena enb 01 0000 pdb pdb_ delaya delaya table 44. detailed peripheral memory map (continued) offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 104 peripheral register memory map and reset value 02 0000 pdb pdb_ delayb delayb 03 ffff pdb pdb_mod mod 04 ffff pdb pdb_ count count 05?1f ? pdb reserved reserved 20 0000 rtc rtc_sc 0 0 0 0 0 0 0 0 rtif rtclks rtie rtcps 21 0000 rtc rtc_cnt 0 0 0 0 0 0 0 0 rtccnt 22 0000 rtc rtc_mod 0 0 0 0 0 0 0 0rtcmod 23?ff ? rtc reserved reserved 00 0000 hfm fm_ clkdiv 0 0 0 0 0 0 0 0 divld prdiv8 div 01 0000 hfm fm_cnfg 0 0 0 0 0 lock 0 aeie cbeie ccie keyacc 0 0 0lbtsbts 03 -000 3 hfm fm_sechi keyen secstat 0 0 0 0 0 0 0 0 0 0 0 0 0 0 04 0000 hfm fm_ seclo 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sec 06?0f ? hfm reserved reserved 10 ffff 6 hfm fm_prot protect 11 ? hfm reserved reserved 13 00c0 hfm fm_ustat 0 0 0 0 0 0 0 0 cbeif ccif pviol accerr 0 blank 0 0 14 0000 hfm fm_cmd 0 0 0 0 0 0 0 0 0cmd table 44. detailed peripheral memory map (continued) offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0
peripheral register memo ry map and reset value mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 105 17 ? hfm reserved reserved 18 0000 hfm fm_data fmdata 19 ? hfm reserved reserved 1a ffff 4 hfm fm_opt0 ifr_opt0 1b ffff 5 hfm fm_opt1 ifr_opt1 1d ffff 6 hfm fm_ tstsig tst_area_sig 1e?3f ? hfm reserved reserved 1 the binary reset value of this register is 0000 0000 0uuu uuuu, where u represents an undefined value. spaces have been added t o the value for clarity. 2 the binary reset value of this register is 0000 0000 111nc nc nc nc nc. spaces have been added to the value for clarity. 3 the binary reset value of this register is fs00 0000 0000 0000, where f indicates that the reset state is loaded from the flash array during reset, and where s indicates that the reset state is determined by the security st ate of the module. spaces have been added to the value for clari ty. 4 the reset state is loaded from the flash array during reset. 5 the reset state is loaded from the flash array during reset. 6 the reset state is loaded from the flash array during reset. table 44. detailed peripheral memory map (continued) offset addr. (hex) reset value (hex) periph. register bit 15 1413121110987654321 bit 0
document number: mc56f8006 rev. 4 06/2011 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2009?2011. all rights reserved.

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