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1 sed1353 description sed1353 is a dot matrix graphics lcd controller capable of supporting up to 1024 1024 (monochrome display) resolution. 256-color-display and monochrome display in up to 16-level gray scale display are avail- able. sed1353 allows easy connection with mc68000 families and other 8/16 bits mpus. as for memory for the display, it supports up to 128 kb sram. low operating power of sed1353 makes it a most suitable color lcd controller not only for factory automation equipments but also for small hand held equipments, too. sed1353 color/monochrome lcd controller pin convertible with sed1352 (monochrome lcd controller) low operating voltage (2.7v to 5.5v) supports interface with various types of mpus stn color lcd controller pf885-04 functions 16-bit, 16 mhz and mc68xxx mpu interface. ready or wait# terminal controlled 8/16 bits mpu interface. either index register approah or direct mapping can be selected when making access to the inter- nal register. support a crystal oscillator or external clock input. 8/16 bits sram interface. designed to operate at low power. designed for two types of power save mode. setup of virtual display sreen is available. supports split-screen (displays two different pages on a single screen). display mode: black and white binary display. 2/4 bits per pixel, 4/16-level gray scale display. 2/4/8 bits per pixel, 4/16/256 color display. display memory interface 128kb (one 64k 16 sram) 128kb (two 64k 8 sram) 64kb (two 32kb 8 sram) 40kb (8k x 8 sram and 32k 8 sram) 32kb (one 32k 8 sram) 16kb (two 8k 8 sram) 8kb (one 8k 8 sram) lcd panel supported: single screen drive stn panel dual screen drive stn panel maximum number of vertical lines: 1024 lines (for single screen drive) 2048 lines (for dual screen drive) sed1353d 0a : chip shipped. sed1353f 0a : qfp5-100 pin sed1353f 1a : qfp15-100 pin
2 sed1353 system configuration diagram lcd panel sram sed1353 clock data control address mup 80xx z80 68xxx system interface 16-bit mc68xxx mpu & 16kb sram (2 of 8k 8) a20 to a23 fc0 to fc1 a1 to a19 d0 to d15 dtack# uds# lds# as# r/w# decoder memcs# decoder a14 to a16 a10 to a19 vd8?5 vd0? iocs# vwe# ab1 to ab19 db0 to db15 ready ab0 bhe# ior# iow# vcs0# vcs1# va0?2 we# 64kbit cs# we# 64kbit cs# sed1353 mc68xxx note: example implemation, actual may vary 8-bit z80 mpu & 16kb sram (2 of 8k 8) decoder decoder vd0 7 vwe# vcs0# vcs1# va0 12 we# 64kbit cs# we# 64kbit cs# sed1353 memcs# iocs# ab0 to ab15 db0 to db7 ready memw# memr# ior# iow# reset a10 to a15 z80 mreq# mi# iorq# a0 to a15 d0 to d7 wait# wr# rd# reset# note: example implemation, actual may vary
3 sed1353 16-bit 8086 mpu & 64kb sram (2 of 32k 8) clk ready reset# rdy 8284a clk ready reset# s2# s1# s0# a16 to a19 bhe# ad0 to ad15 8086 (maximum mode) 8288 clk s2# s1# s0# den dt/r ale mrdc# amwc# iorc# aiowc# decoder m/io# bhe# a0 to a16 stb d0 to d15 t oe transceiver reset ready vcs1# vd8 15 db0 to db15 iocs# memcs# bhe# ab0 to ab15 ab16 to ab19 iow# ior# memw# memr# sed1353 vd0 7 vwe# vcs0# va0 14 we# 256kbit cs# we# 256kbit cs# a16 note: example implemation, actual may vary 8-bit isa bus & 40kb sram (1 of 8k 8 & 1 of 32k 8) 8 bit isa bus we# 256 kbit cs# we# 64 kbit cs# smemw# refresh smemr# iochrdy sd0 to sd7 sa0 to sa19 aen iow# ior# reset# 0ws# optional decoder decoder decoder sa10 to sa15 sa13 to sa16 sa(1or4) to sa9 sed1353 memcs# memw# memr# ready db0 to db7 ab0 to ab19 iocs# iow# ior# reset vd0 7 vwe# vcs0# va0 14 vcs1# note: example implemation, actual may vary 16-bit isa bus & 128kb sram (1 of 128k 8) decoder decoder decoder decoder 16 bit isa bus refresh smemw# smemr# iochrdy sd0 to sd15 sa0 to sa19 aen iow# ior# sbhe# reset# iocs16# la17 to la23 memcs16# sa14 to sa16 sa10 to sa15 sa(1or4) to sa9 sed1353 memcs# memw# memr# ready db0 to db15 ab0 to ab19 iocs# iow# ior# bhe# reset we# 1 mbit lb# ub# a0 15 i/o1 8 i/o9 16 vwe# vcs0# vcs1# va0 15 vd0 7 vd8 15 note: example implemation, actual may vary
4 sed1353 resolutions supported the above display sizes depend on number of gray scale (colors) and memory capacity. block diagram ior#,iow#,iocs#, memcs#,memr#, memw#,bhe#, ab[19:0] bus signal translation ready db[15:0] port decoder memory decoder data bus conversion timing generator power save oscillator control registers sequence controller address generator mpu/crt selctor sram interface display data formatter lookup table lcd panel interface lcdenb ud[3:0] ld[3:0] lp,yd, xscl, wf(xscl2) vd[15:0] va[15:0] vsc0#,vsc1# voe# osc2 osc1 vwe# example display size display monochrome 4 grays/ 16 grays/ 256 colors* sram cpu sram ram colors colors type interface interface xy xy xy xy 8kb 320 200 256 128 128 128 1 of 8k 8 8-bit 8-bit 16kb 512 256 320 200 200 160 160 100* 2 of 8k 8 8-bit 8-bit/16-bit 16-bit 16-bit 32kb 512 512 512 256 256 256 192 100* 1 of 32k 8 8-bit 8-bit 40kb 1024 320 512 320 320 256 320 128* 1 of 8k 8 & 8-bit 8-bit 1 of 32k 8 64kb 1024 512 512 512 512 256 256 256* 2 of 32k 8 8-bit 8-bit/16-bit 16-bit 16-bit 128kb 1024 1024 1024 512 512 512 512 256* 1 of 64k 16 16-bit 16-bit 2 of 64k 8 16-bit 16-bit note: * 256 colors must use 16-bit sram interface
5 sed1353 overview of the functional blocks bus signal translation this block converts the sed1353 internal bus so that it may be used for mc68000 series mpu or ready terminal controlled mpu series. this conversion is done through the setting of vd2 terminal from the configu- ration option (see page 11). control register this register block consists of 16 types of control registers. access to these registers are available either through the direct mapping approach or index register approach. sequence controller this block generates horizontal and vertical display timing being set up in the internal register. lcd panel interface this block selects a gray scale for passive monochrome and color lcd panels through timing, then outputs data to the lcd panel. lookup table this block consists of each rgb 16 4-bit palettes. in the monochrome gray scale mode, a gray scale pattern can be specified using the green palette. in the color mode, all rgb palettes are used to set up a color pattern out of 4096 colors. port decoder this decoder validates a given i/o cycle through setup of vd1 terminal, vd2 to vd4 terminals, iocs # terminal and address lines ab9 to 1 from the configuration option (see page 11). memory decoder this decoder validates a given memory cycle through setup of vd15 to vd13, memcs # terminal and address lines ab19 to 17 from the configuration option (see page 11). data bus conversion this block connects an external data bus (8 or 16 bits) to the internal data bus through the setup of v dd terminal from the configuration option (see page 11). address generator this block generates the address used to validate access to the display memory. mpu/crt selector this block arbitrates between mpu accees to the display memory and an access to it for lcd display. display data fomatter this block reads data from the display memory, then outputs it in the format consistant with the specified display mode (monochrome/color, levels of gray scale and number of colors). clock inputs/timing this block generates a master clock (mclk) conforming to the specified gray scale leves 1, number of colors and display memory interface. the following master clocks are available depeding on conditions specified: mclk = input clock: 16-grays/16-color mode (8-bit display memory) or 256-color mode (16-bit display memory). mclk = 1/2 input clock: b&w, 4-grays/4-color mode (8-bit display memory), or 16-grays scale/16-color mode (16-bit display memory). mclk = 1/4 input clck: b&w, 4-grays scale/4-color mode (16-bit display memory). pixel clock = input clock = f osc sram interface this block generates the interface signal to the display memory (sram).
6 sed1353 dc characteristics absolute maximum ratubgs recommended operation conditions input characteristics item code conditions min typ max unit supply voltage v dd v ss = 0 v 2.7 3.0/3.3/5.0 5.5 v input voltage v in v ss v dd v operating current i opr f osc = 6mhz, 256 colors 4.5/5.0/11 ma operating voltage t opr 40 25 85 c item code conditions min typ max unit low level input voltage v il v dd = 4.5v 0.8 v v dd = 3.0v 0.4 v dd = 2.7v 0.3 high level input voltage v ih v dd = 5.5v 2.0 v v dd = 3.6v 1.3 v dd = 3.3v 1.2 positive threshold v t+ v dd = 5.0v 2.4 v v dd = 3.3v 1.4 v dd = 3.0v 1.3 negative threshold v t v dd = 5.0v 0.6 v v dd = 3.3v 0.5 v dd = 3.0v 0.4 hysteresis voltage v h v dd = 5.0v 0.1 v v dd = 3.3v 0.1 v dd = 3.0v 0.1 leak voltage i iz 11 a input pin capacity c in f = 1mhz, v dd = 0v 12 pf pulldown resistance r pd v dd = 5.0v, v i = v dd 50 100 200 k ? pulldown resistance r pd v dd = 3.3v, v i = v dd 90 180 360 k ? pulldown resistance r pd v dd = 3.0v, v i = v dd 100 200 400 k ? item code rating unit supply voltage v dd v ss 0.3 + 6.0 v input voltage v in v ss 0.3 to v dd + 0.5 v output voltage v out v ss 0.3 to v dd + 0.5 v storage voltage t stg 65 to 150 c
7 sed1353 output characteristics sed1353f 0a pin layout 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 vd6 vd5 vd4 vd3 vd2 vd1 vd0 va10 va9 va8 va7 va6 va5 va4 va3 va2 va1 va0 reset ab19 xscl lcdenb voe# iocs# iow# ior# memcs# memw# memr# ready bhe# osc1 osc2 db0 db1 db2 db3 db4 db5 db6 db7 v ss v dd db8 db9 db10 db11 db12 db13 db14 db15 ab0 ab1 ab2 ab3 ab4 ab5 ab6 ab7 ab8 ab9 ab10 ab11 ab12 ab13 ab14 ab15 ab16 ab17 ab18 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 sed1353f 0a wf/xscl2* lp yd ld0 ld1 ld2 ld3 ud0 ud1 ud2 ud3 vcs1# vcs0# vwe# va15 va14 va13 va12 va11 vd15 vd14 vd13 vd12 vd11 vd10 vd9 vd8 v dd v ss vd7 * pin no.80 = wf: supports every display mode except for 8-bit single color panel interface (format 1). * pin no.80 = xscl2: supports 8-bit single color panel interface (format 1). item code conditions min typ max unit low level output voltage v ol v dd = min (5.0v) type 1: ts1d2, co1 i ol = 4ma 0.4 v type 2: ts2 i ol = 8ma type 3: ts3, co3, co3s i ol = 12ma low level output v ol v dd = min (3.3v) type 1: ts1d2, co1 i ol = 2ma 0.3 v type 2: ts2 i ol = 4ma type 3: ts3, co3, co3s i ol = 6ma low level output voltage v ol v dd = min (3.0v) type 1: ts1d2, co1 i ol = 1.8ma 0.3 v type 2: ts2 i ol = 3.5ma type 3: ts3, co3, co3s i ol = 5ma high level output voltage v oh v dd = min (5.0v) type 1: ts1d2, co1 i ol = 4ma v dd 0.4 v type 2: ts2 i ol = 8ma type 3: ts3, co3, co3s i ol = 12ma high level output voltage v oh v dd = min (3.3v) type 1: ts1d2, co1 i ol = 2ma v dd 0.3 v type 2: ts2 i ol = 4ma type 3: ts3, co3, co3s i ol = 6ma high level output voltage v oh v dd = min (3.0v) type 1: ts1d2, co1 i ol = 1.8ma v dd 0.3 v type 2: ts2 i ol = 3.5ma type 3: ts3, co3, co3s i ol = 5ma output leak current i oz 11 a output pin capacity c out f = 1mhz, v dd = 0v 12 pf bi-directional pin capacity c bid f = 1mhz, v dd = 0v 12 pf
8 sed1353 sed1353f 1a pin layout sed1353f 1a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 v dd v ss vd7 vd6 vd5 vd4 vd3 vd2 vd1 vd0 va10 va9 va8 va7 va6 va5 va4 va3 va2 va1 va0 reset ab19 ab18 ab17 lp wf/xscl2* xscl lcdenb voe# iocs# iow# ior# memcs# memw# memr# ready bhe# osc1 osc2 db0 db1 db2 db3 db4 db5 db6 db7 v ss v dd db8 db9 db10 db11 db12 db13 db14 db15 ab0 ab1 ab2 ab3 ab4 ab5 ab6 ab7 ab8 ab9 ab10 ab11 ab12 ab13 ab14 ab15 ab16 yd ld0 ld1 ld2 ld3 ud0 ud1 ud2 ud3 vcs1# vcs0# vwe# va15 va14 va13 va12 va11 vd15 vd14 vd13 vd12 vd11 vd10 vd9 vd8 * pin no. 77 = wf: supports every display mode except for 8-bit single color panel interface (format 1). * pin no. 77 = xscl2: supports 8-bit single color panel interface (format 1). sed1353d 0a pin layout sed1353d 0a 110 20 30 40 50 60 70 80 90 100 110 120 vd7 vd6 vd5 vd4 vd3 vd2 vd1 vd0 va10 va9 va8 va7 va6 va5 va4 va3 va2 va1 va0 reset ab19 v ss v dd db8 db9 db10 db11 db12 db13 db14 db15 ab0 ab1 ab2 ab3 ab4 ab5 ab6 ab7 ab8 ab9 ab10 ab11 ab12 ab13 ab14 ab15 ab16 ab17 ab18 lp yd ld0 ld1 ld2 ld3 ud0 ud1 ud2 ud3 vcs1# vcs0# vwe# va15 va14 va13 va12 va11 vd15 vd14 vd13 vd12 vd11 vd10 vd9 vd8 v dd v ss wf/xscl2* xscl lcdenb voe# iocs# iow# ior# memcs# memw# memr# ready bhe# osc1 osc2 db0 db1 db2 db3 db4 db5 db6 db7 dummy pad dummy pad chip size chip thickness pad size pad pitch = = = = 5.030 mm x 5.030 mm 0.400 mm 0.090 mm x 0.090 mm 0.126 mm ( min.) * pad no. 97 = wf: supports every display mode except for 8-bit single color panel interface (format 1). * pad no. 97 = xscl2: support 8-bit single color panel interface (format 1).
9 sed1353 pin description i = input o = output i/o = input and output p = power supply bus interface display memory interface pin name type f 0a pin no. f 1a pin no. d 0a pin no. description db0 db15 i/o 94 100, 91 98, 118 119, connects to the system data bus. in 8-bit bus mode, db8 to 1, 4 11 1 8 121 125, 128, db15 connect to vd0. 4 11 ab0 i 12 9 13 when mc68000 mpu interface is used, it connects to uds#pin (upper data strobe). when other bus interface is used, it connect to the system address bus. ab1 ab19 i 13 31 10 28 14 20, 22 30, connects to the system bus. 32 33, 36 bhe# i 91 88 113 when mc68000 mpu interface is used, it connects to lds# pin (lower data strobe). when other bus interface is used, this pin functions as the bus high enable input on the 16-bit system. on 8-bit bus system, it connects to v dd . iocs# i 84 81 103 select one of 15 internal registers. iow# i 85 82 104 when mc68000 mpu interface is used, it connects to r/w# pin. this input pin selects either read cycle (active high) or write cycle (active low) for data transmission. when other bus interface is used, it is active low to write data to the internal register. ior# i 86 83 106 when mc68000 mpu interface is used, it connects to as# pin. on the address bus, this input pin indicates an valid address is available. when other bus interface is used, this pin is active low and reads data from the internal register. memcs# i 87 84 107 accepts active low inputs, it displays access attempts to the display memory. memw# i 88 85 109 accepting active low inputs, it writes dat a to the display memory. when mc68000 mpu interface is used, it connects to v dd . memr# i 89 86 110 accepting active low inputs, it reads data from the display memory. when mc68000 mpu interface is used , it connects to v dd . ready o 90 87 112 when mc68000 mpu interface is used, it is connected with datck# pin. as data transfer completes, it is turned low. when other system bus interface is used, it outputs low if the system wait status is needed. as data transfer completes, ready state is reset to return to high-z. reset i 32 29 37 accepting active high, it turns all signals non-active. pin name type f 0a pin no. f 1a pin no. d 0a pin no. description vd0 vd15 i/o 44 51, 54 61 41 48, 51 58 54 55, 57 61, they connect to the display memory data bus. when 16-bit 64, 68 75 interface is used, vd0 to vd7 are connected to the display memory buses in even byte address, and vd8 to vd15 are connected to those in odd memory address. when reset is turned to high, output drivers of these pins are set to high-z. at the falling edge of reset, values of vd0 to vd15 are latched by this ic allowing to set various hardware options. va0 va15 o 33 43, 62 66 30 40, 59 63 38 40, 42 43, they connect to the display memory address buses. 45 46, 48 49, 51 52, 77 81 vcs1# o 69 66 84 it outputs active low chip select signal to the second sram or srams at odd byte address. vcs0# o 68 65 83 it outputs active low chip select signal to the first sram or srams at even byte address. vwe# o 67 64 82 it outputs active low used when writing data to the display memory. it is connected to the sram we# pin. voe# o 83 80 102 it outputs active low used for reading data from the display memory. it is connected to the sram oe# pin.
10 sed1353 lcd interface clock input power supply pin name fpdi-1* type f 0a f 1a d 0a description pin name pin no. pin no. pin no. ud3 ud0 ud3 ud0 o 70 73 67 70 86 89 display data in the dual panel mode. when 4-bit single panel ld3 ld0 ld3 ld0 74 77 71 74 90 93 is employed, ld3 to ld0 are driven to low. xscl fpshift o 81 78 100 shift clock of display data. aft the falling edge of this signal, data is shifted to x driver on the lcd. lp fpline o 79 76 96 latch clock of display data. at the falling edge of this signal, line data on the lcd x driver is latched and used for turning on the lcd y driver. wf/xscl2 mod o 80 77 97 the second shift clock for 8-bit single color panel (format) mode. in other modes, it becomes lcd back plane bias fpshift2 signal. this output is toggled one time at each frame. (setup of wf signal output may be changed from the internal register.) yd fpframe o 78 75 94 vertical scan start signal. lcdenb o 82 79 101 lcd enable signal. using this signal, you can externally turn off the panel power and back light. *: conforming to the vesa flat panel interface standard. pin name type f 0a pin no. f 1a pin no. d 0a pin no. description osc1 i 92 89 115 when 2-pin crystal is used for the clock input, this pin is con- nected to the crystal along with osc2. and, when an external oscillator circuit is used as the clock source, this pin inputs the clock. osc2 o 93 90 116 when 2-pin crystal is used for the clock input, this pin is con- nected to the crystal along with osc2. and, when an external oscillator circuit is used as the clock source, it is turned to nc. pin name type f 0a pin no. f 1a pin no. d 0a pin no. description v dd p 3, 53 50, 100 3, 67 power supply pin. v ss p 2, 52 49, 99 1, 65 grounding pin.
11 sed1353 pin name hardware configuration according to the pin status (1 or 0) 10 vd0 16-bit host bus interface 8-bit host bus interface vd1 direct mapping i/o access index mapping i/o access vd2 mc68000 mpu interface read (wait#) pin controlled mpu and bus interface vd3 when 16-bit bus interface is used, there is data swap when 16-bit bus interface is used, there is not data swap between higher-order data byte and lower-order data between higher-order and lower-order data byte. byte. vd12 vd4 i/o mapping address select bit [9:1] initial bits used for selecting the address mapping of i/o resistor. hey correspond to the address bit [9:1] of mpu interface. when valid address for i/o cycle is generated, the internal decoder is controlled so that addressing is as specified with these bits. vd15 vd13 memory mapping address select bit [3:1] initial bits used for selecting address mapping of memory. they correspond to address bit [19:17] of the mpu interface. when valid address for memory cycle is generated, the internal decoder is controlled so that addressing is done as specified with these bits. valid memory cycle denotes the the access where memcs # is turned low. specifications sed1353 sed1352 color display 4/16/256 colors not available monochrome display black/white binary. not available. 4/16-level gray scale. 4/16-level gray scale. display data format 4/8 bits single/dual monochrome. 4/8 bits single/dual monochrome. 4/8/16 bits signal/dual color. not available. setup of vertical scan period done programmable. not available. in horizontal direction look-up table 3 16, 4-bit width. 1 16, 4-bit width. optional hardware configuration during the reset, sed1353 latches state of sram data bus (1 or 0) to offer an optimum hardware configura- tion to the user system. since sed1353 has a pull down resistor inside the ic, if the following 1 applies, a 10k ? external pull up resistor must be provided . in case of 0 , the external pull up resistor is not required. comparison between sed1353 and sed1352 sed1353 is upward convertible and pin convertible with f sed1352. thus, up grading from sed1352 to 1353 is easy in terms of both hardware and software. the following list main difference between sed1353 and sed1352. for detailed specifications, refer to re- spective technical manual. functional comparison modifications or additions done on the internal register (see sed1353 technical manual for the detail) aux [01h] bit 2 lcd data width bit 0 bit 3 gray shade/color aux [03h] bit 1 color mode bit 2 bw/256 colors aux [0ch] bit 0:7 horizontal non-display period aux [0eh] bit 4 id bit/rgb index bit 0 bit 5 id bit/rgb index bit 1 bit 6 green bank bit 0 bit 7 green bank bit 1 aux [0fh] bit 4 blue bank bit 0 bit 5 blue bank bit 1 bit 6 red bank bit 0 bit 7 red bank bit 1
12 sed1353 electronic devices marketing division notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arisi ng out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no re presentation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material wil l be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject rela ting to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 2000 all right reserved. all other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. first issue september, 1998 printed in february, 2000 japan h ic marketing & engineering group ed international marketing department i (europe, u.s.a) 421-8 hino, hino-shi, tokyo 191-8501, japan phone: 042 587 5812 fax: 042 587 5564 ed international marketing department ii (asia) 421-8 hino, hino-shi, tokyo 191-8501, japan phone: 042 587 5814 fax: 042 587 5110 http://www.epson.co.jp/device/ electronic devices information on the epson www server.

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