View SI8442BB-D-IU_7316558.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0.1 6/10 copyright ? 2010 by silicon laboratories si845x/5x qsop si84x/5x qsop f our and f ive -c hannel d igital i solators features applications safety regulatory approvals (pending) description silicon lab's family of ultra low power digital isolators are cmos devices that employ an rf coupler to transmit di gital information across an isolation barrier. very high speed operation at low power levels is achieved. these devices are available in qsop packages. two speed grade options (1 and 150 mbps) are available and achieve wors t-case propagation delays of less than 10 ns. block diagram ? high-speed operation ?? dc to 150 mbps ?? 15 s startup time ? wide operating supply voltage: 2.6?5.5 v ? ultra low power (typical) 5 v operation: ?? <1.6 ma/channel at 1 mbps ?? <6 ma/channel at 100 mbps 2.70 v operation: ?? <1.4 ma/channel at 1 mbps ?? <4 ma/channel at 100 mbps ? 100-year life at rated working voltage ? high electromagnetic immunity ? precise timing (typical) ?? 10 ns propagation delay max ?? 1.5 ns pulse width distortion ?? 0.5 ns channel-channel skew ?? 2 ns propagation delay skew ?? 5 ns minimum pulse width ?? dc correct ? up to 2500 v rms isolation ? transient immunity: 25 kv/s ? tri-state outputs with enable control ? no start-up initialization required ? wide temperature range: ?40 to 125 c at 150 mbps ? rohs-compliant packages ?? qsop-16 ? industrial auto mation systems ? hybrid electric vehicles ? isolated switch mode supplies ? isolated adc, dac ? motor control ? power inverters ? ul 1577 recognized ?? 2500 v rms for 1 minute ? csa component notice 5a approval ?? iec 60950, 61010 reinforced insulation ? vde certification conformity ?? iec 60747-5-2 (vde0884 part 2) b1 a1 a3 a4 a2 b3 b4 b2 si8455 a5 b5 b1 a1 a3 a4 a2 b3 b4 b2 si8442 en1 en2 patents pending pin assignments qsop-16 v dd1 a1 a3 a4 gnd1 a2 1 2 3 4 5 6 7 8 v dd2 b2 b1 b4 b3 gnd2 9 12 11 10 13 14 15 16 top view (si8442) gnd1 gnd2 en1 en2 qsop-16 v dd1 a1 a3 a4 gnd1 a2 1 2 3 4 5 6 7 8 v dd2 b2 b1 b4 b3 gnd2 9 12 11 10 13 14 15 16 a5 b5 top view (si8455) gnd1 gnd2
si84x/5x qsop 2 rev. 0.1
si84x/5x qsop rev. 0.1 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3. application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.1. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2. eye diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 3.3. layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6. package outline: 16-pin qsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7. landing pattern: 16-pin qsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 8. top marking: 16-pin qsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
si84x/5x qsop 4 rev. 0.1 1. electrical specifications table 1. electrical characteristics (v dd1 =5v10%, v dd2 =5v10%, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 4.8 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance 1 z o ?8 5? ? enable input high current i enh v enx = v ih ?2 . 0? a enable input low current i enl v enx = v il ?2 . 0? a dc supply current (all inputs 0 v or at supply) si8455bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.6 2.9 7.0 3.1 2.4 4.4 10.5 4.7 ma si8442bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 2.3 2.3 4.5 4.5 3.5 3.5 6.8 6.8 ma 1 mbps supply current (all inputs = 500 khz square wave, ci = 15 pf on all outputs) si8455bx v dd1 v dd2 ? ? 4.3 3.5 6.5 5.3 ma si8442bx v dd1 v dd2 ? ? 3.6 3.6 5.4 5.4 ma 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8455bx v dd1 v dd2 ? ? 4.3 4.8 6.5 6.7 ma si8442bx v dd1 v dd2 ? ? 4.2 4.2 5.9 5.9 ma notes: 1. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channe l resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output.
si84x/5x qsop rev. 0.1 5 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8455bx v dd1 v dd2 ? ? 4.6 24 6.9 30 ma si8442bx v dd1 v dd2 ? ? 11.8 11.8 14.8 14.8 ma timing charac teristics si845xax, si8442bx maximum data rate 0 ? 1.0 mbps minimum pulse width ? ? 250 ns propagation delay t phl , t plh see figure 2 ? ? 35 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? ? 25 ns propagation delay skew 2 t psk(p-p) ? ? 40 ns channel-channel skew t psk ? ? 35 ns si845xbx, si8442bx maximum data rate 0 ? 150 mbps minimum pulse width ? ? 6.0 ns propagation delay t phl , t plh see figure 2 3.0 6.0 9.5 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? 1.5 2.5 ns propagation delay skew 2 t psk(p-p) ?2 . 03 . 0n s channel-channel skew t psk ?0 . 51 . 8n s all models output rise time t r c l =15pf see figure 2 ?3.85.0ns output fall time t f c l =15pf see figure 2 ?2.83.7ns common mode transient immunity cmti v i =v dd or 0 v ? 25 ? kv/s enable to data valid t en1 see figure 1 ? 5.0 8.0 ns enable to data tri-state t en2 see figure 1 ? 7.0 9.2 ns start-up time 3 t su ?1 54 0 s table 1. electrical characteristics (continued) (v dd1 =5v10%, v dd2 =5v10%, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channe l resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output.
si84x/5x qsop 6 rev. 0.1 figure 1. enable timing diagram figure 2. propagation delay timing enable outputs t en1 t en2 typical input t plh t phl typical output t r t f 90% 10% 90% 10% 1.4 v 1.4 v
si84x/5x qsop rev. 0.1 7 table 2. electrical characteristics (v dd1 = 3.3 v10%, v dd2 = 3.3 v10%, t a = ?40 to 125 oc; applies to narrow and wide-body soic packages) parameter symbol test condition min typ max unit high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 3.1 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance 1 z o ?8 5? ? enable input high current i enh v enx = v ih ?2 . 0? a enable input low current i enl v enx = v il ?2 . 0? a dc supply current (all inputs 0 v or at supply) si8455bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.6 2.9 7.0 3.1 2.4 4.4 10.5 4.7 ma si8442bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 2.3 2.3 4.5 4.5 3.5 3.5 6.8 6.8 ma 1 mbps supply current (all inputs = 500 khz square wave, ci = 15 pf on all outputs) si8455bx v dd1 v dd2 ? ? 4.3 3.5 6.5 5.3 ma si8442bx v dd1 v dd2 ? ? 3.6 3.6 5.4 5.4 ma 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8455bx v dd1 v dd2 ? ? 4.3 4.8 6.5 6.7 ma si8442bx v dd1 v dd2 ? ? 4.2 4.2 5.9 5.9 ma notes: 1. the nominal output impedance of an isol ator driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, l oad, and ambient temperature. 3. start-up time is the time period from the a pplication of power to valid data at the output.
si84x/5x qsop 8 rev. 0.1 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8455bx v dd1 v dd2 ? ? 4.4 16.8 6.6 21 ma si8442bx v dd1 v dd2 ? ? 8.6 8.6 10.8 10.8 ma timing characteristics si845xbx, si8442bx maximum data rate 0 ? 1.0 mbps minimum pulse width ? ? 250 ns propagation delay t phl ,t plh see figure 2 ? ? 35 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? ? 25 ns propagation delay skew 2 t psk(p-p) ? ? 40 ns channel-channel skew t psk ? ? 35 ns si845xbx, si8442bx maximum data rate 0 ? 150 mbps minimum pulse width ? ? 6.0 ns propagation delay t phl , t plh see figure 2 3.0 6.0 9.5 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? 1.5 2.5 ns propagation delay skew 2 t psk(p-p) ?2 . 03 . 0n s channel-channel skew t psk ?0 . 51 . 8n s all models output rise time t r c l = 15 pf see figure 2 ?4.36.1ns output fall time t f c l = 15 pf see figure 2 ?3.04.3ns common mode transient immunity at logic low output cmti v i =v dd or 0 v ? 25 ? kv/s enable to data valid t en1 see figure 1 ? 5.0 8.0 ns enable to data tri-state t en2 see figure 1 ? 7.0 9.2 ns start-up time 3 t su ?1 54 0 s table 2. electrical characteristics (continued) (v dd1 = 3.3 v10%, v dd2 = 3.3 v10%, t a = ?40 to 125 oc; applies to narrow and wide-body soic packages) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isol ator driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, l oad, and ambient temperature. 3. start-up time is the time period from the a pplication of power to valid data at the output.
si84x/5x qsop rev. 0.1 9 table 3. electrical characteristics 1 (v dd1 = 2.70 v, v dd2 = 2.70 v, t a = ?40 to 125 oc; applies to narrow and wide-body soic packages) parameter symbol test condition min typ max unit high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 2.3 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance 2 z o ?8 5? ? enable input high current i enh v enx = v ih ?2 . 0? a enable input low current i enl v enx = v il ?2 . 0? a dc supply current (all inputs 0 v or at supply) si8455bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.6 2.9 7.0 3.1 2.4 4.4 10.5 4.7 ma si8442bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 2.3 2.3 4.5 4.5 3.5 3.5 6.8 6.8 ma 1 mbps supply current (all inputs = 500 khz square wave, ci = 15 pf on all outputs) si8455bx v dd1 v dd2 ? ? 4.3 3.5 6.5 5.3 ma si8442bx v dd1 v dd2 ? ? 3.6 3.6 5.4 5.4 ma 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8455bx v dd1 v dd2 ? ? 4.3 4.8 6.5 6.7 ma si8442bx v dd1 v dd2 ? ? 4.2 4.2 5.9 5.9 ma notes: 1. specifications in this table are also valid at vdd1 = 2.6 v and vdd2 = 2.6 v when the operating temperature range is constrained to t a = 0 to 85 c. 2. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 3. t psk(p-p) is the magnitude of the difference in propagation del ay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. start-up time is the time period from the a pplication of power to valid data at the output.
si84x/5x qsop 10 rev. 0.1 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8455bx v dd1 v dd2 ? ? 4.3 13.3 6.5 16.6 ma si8442bx v dd1 v dd2 ? ? 7.2 7.2 9.0 9.0 ma timing characteristics si845xbx, si8442bx maximum data rate 0 ? 1.0 mbps minimum pulse width ? ? 250 ns propagation delay t phl ,t plh see figure 2 ? ? 35 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? ? 25 ns propagation delay skew 3 t psk(p-p) ? ? 40 ns channel-channel skew t psk ? ? 35 ns si845xbx, si8442bx maximum data rate 0 ? 150 mbps minimum pulse width ? ? 6.0 ns propagation delay t phl , t plh see figure 2 3.0 6.0 9.5 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? 1.5 2.5 ns propagation delay skew 3 t psk(p-p) ?2 . 03 . 0n s channel-channel skew t psk ?0 . 51 . 8n s all models output rise time t r c l =15pf see figure 2 ?4.86.5ns output fall time t f c l =15pf see figure 2 ?3.24.6ns common mode transient immunity at logic low output cmti v i =v dd or 0 v ? 25 ? kv/s enable to data valid t en1 see figure 1 ? 5.0 8.0 ns enable to data tri-state t en2 see figure 1 ? 7.0 9.2 ns start-up time 4 t su ?1 54 0 s table 3. electrical characteristics 1 (continued) (v dd1 = 2.70 v, v dd2 = 2.70 v, t a = ?40 to 125 oc; applies to narrow and wide-body soic packages) parameter symbol test condition min typ max unit notes: 1. specifications in this table are also valid at vdd1 = 2.6 v and vdd2 = 2.6 v when the operating temperature range is constrained to t a = 0 to 85 c. 2. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 3. t psk(p-p) is the magnitude of the difference in propagation del ay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. start-up time is the time period from the a pplication of power to valid data at the output.
si84x/5x qsop rev. 0.1 11 table 4. absolute maximum ratings 1 parameter symbol min typ max unit storage temperature 2 t stg ?65 ? 150 oc ambient temperature under bias t a ?40 ? 125 oc supply voltage v dd1 , v dd2 ?0.5 ? 6.0 v input voltage v i ?0.5 ? v dd + 0.5 v output voltage v o ?0.5 ? v dd + 0.5 v output current drive channel i o ??10ma lead solder temperature (10 s) ? ? 260 oc maximum isolation (input to output) (1 sec) qsop-16 ? ? 3600 v rms notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to conditions as specified in the operational sections of this data sheet. 2. vde certifies storage temper ature from ?40 to 150 c. table 5. recommended operating conditions parameter symbol test condition min typ max unit ambient operating temperature* t a 150 mbps, 15 pf, 5 v ?40 25 125 oc supply voltage v dd1 2.70 ? 5.5 v v dd2 2.70 ? 5.5 v *note: the maximum ambient temperature is dependent on data freque ncy, output loading, number of operating channels, and supply voltage. table 6. regulatory information* csa the si84xx is certified under csa component acceptan ce notice 5a. for more details, see file 232873. 61010: 300 v rms reinforced insulation working voltage; 600 v rms basic insulation working voltage. 60950: 130 v rms reinforced insulation working voltage; 600 v rms basic insulation working voltage. vde the si84xx is certified according to iec 60747-5-2. for more details, see file 5006301-4880-0001. rated up to 560 vpeak for basi c insulation working voltage. ul the si84xx is certified under ul1577 component recognition program. for more details, see file e257455. rated up to 2500 v rms isolation voltage for basic insulation. *note: pending. regulatory certifications apply to 2.5 kv rms rated devices which are production tested to 3.0 kv rms for 1 sec. for more information, see "5. ordering guide" on page 23.
si84x/5x qsop 12 rev. 0.1 table 7. insulation and safety-related specifications parameter symbol test condition value unit qsop-16 nominal air gap (clearance) l(io1) 3.6 mm nominal external tracking (creepage) l(io2) 3.6 mm minimum internal gap (internal clearance) 0.008 mm tracking resistance (proof tracking index) pti iec 60112 600 v rms erosion depth ed 0.031 mm resistance (input-output) 1 r io 10 12 ? capacitance (input-output) 1 c io f=1mhz 2.0 pf input capacitance 2 c i 4.0 pf notes: 1. to determine resistance and capacitance, the si84xx is converted into a 2-terminal device. pins 1?8 are shorted together to form the first terminal and pi ns 9?16 are shorted together to form th e second terminal. the parameters are then measured between these two terminals. 2. measured from input pin to ground. table 8. iec 60664-1 (vde 0884 part 2) ratings parameter test conditions specification basic isolation group material group i installation classification rated mains voltages < 150 v rms i-iv rated mains voltages < 300 v rms i-iii rated mains voltages < 600 v rms i-ii
si84x/5x qsop rev. 0.1 13 table 9. iec 60747-5-2 insulation characteristics for si84xxxb* parameter symbol test condition characteristic unit maximum working insulation voltage v iorm 560 vpeak input to output test voltage method b1 (v iorm x1.875=v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc) 1050 highest allowable over voltage (transient overvoltage, t tr =60sec) v tr 4000 vpeak pollution degree (din vde 0110, table 1) 2 insulation resistance at t s , v io =500v r s >10 9 ? *note: this isolator is suitable for basic electrical isolation only within the safety limit data. maintenance of the safety data is ensured by protective circuits. the si84xx pr ovides a climate classification of 40/125/21. table 10. iec safety limiting values 1 parameter symbol test condition min typ max unit si844x qsop-16 si845x qsop-16 case temperature t s ?? 150 150 c safety input, output, or supply current i s ? ja = 105 c/w (qsop-16), v i =5.5v, t j =150c, t a =25c ?? 210 215 ma device power dissipation 2 p d ?? 275 415 mw notes: 1. maximum value allowed in the event of a failure; also see the thermal derating curve in figure 3 and figure 4. 2. the si84xx is tested with vdd1 = vdd2 = 5.5 v, tj = 150 oc, cl = 15 pf, input a 150 mbps 50% duty cycle square wave.
si84x/5x qsop 14 rev. 0.1 figure 3. (si844x, qsop-16) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 figure 4. (si845x, qsop-16) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 table 11. thermal characteristics parameter symbol si84xx qsop-16 unit ic junction-to-air thermal resistance ? ja 105 oc/w 0 200 150 100 50 500 400 200 100 0 temperature (oc) safety-limiting current (ma) 430 300 360 210 v dd1 , v dd2 = 2.70 v v dd1 , v dd2 = 3.6 v v dd1 , v dd2 = 5.5 v 0 200 150 100 50 500 400 200 100 0 temperature (oc) safety-limiting current (ma) 430 300 360 215 v dd1 , v dd2 = 2.70 v v dd1 , v dd2 = 3.6 v v dd1 , v dd2 = 5.5 v
si84x/5x qsop rev. 0.1 15 table 12. si84xx logic operation table v i input 1,2 en input 1,2,3 vddi state 1,4,5 vddo state 1,4,5 v o output 1,2 comments h h or nc p p h enabled, normal operation. lh or nc p p l x l p p hi-z 6 disabled. x h or nc up p l upon transition of vddi from unpowered to pow- ered, v o returns to the same state as v i in less than 1 s. x l up p hi-z 6 disabled. x x p up undetermined upon transition of vddo from unpowered to pow- ered, v o returns to the same state as v i within 1 s, if en is in either th e h or nc state. upon tran- sition of vddo from unpowered to powered, v o returns to hi-z within 1 s if en is l. notes: 1. vddi and vddo are the input and output power supplies. v i and v o are the respective input and output terminals. en is the enable control input located on the same output side. 2. x = not applicable; h = logic high; l = logic low; hi-z = high impedance. 3. it is recommended that the enable inputs be connected to an external logic high or low level when the si84xx is operating in noisy environments. 4. "powered" state (p) is defined as 2.70 v < vdd < 5.5 v. 5. "unpowered" state (up) is defined as vdd = 0 v. 6. when using the enable pin (en) function, the output pin stat e goes into a high-impedance state when the en pin is disabled (en = 0).
si84x/5x qsop 16 rev. 0.1 table 13. enable input truth table 1 p/n en1 1,2 en2 1,2 operation si8442 h x outputs a3 and a4 are enabled and follow input state. l x outputs a3 and a4 are disabled and logic low or in high impedance state. 3 x h outputs b1 and b2 are enabled and follow input state. x l outputs b1 and b2 are disabled and logic low or in high impedance state. 3 si8455 ? ? outputs b1, b2, b3, b4, b5 are enabled and follow input state. notes: 1. enable inputs en1 and en2 can be used for multiplexing, fo r clock sync, or other output control. these inputs are internally pulled-up to local vdd by a 3 a current source allowing them to be connected to an external logic level (high or low) or left floating. to minimize noise coupling, do not c onnect circuit traces to en1 or en2 if they are left floating. if en1, en2 are unused, it is recommended they be connected to an external logi c level, especially if the si845x is operating in a noisy environment. 2. x = not applicable; h = logic high; l = logic low. 3. when using the enable pin (en) function, the output pin stat e goes into a high-impedance state when the en pin is disabled (en = 0).
si84x/5x qsop rev. 0.1 17 2. typical performance characteristics the typical performance characteristics de picted in the following diagrams are for information purposes only. refer to tables 1, 2, and 3 for actual specification limits. figure 5. si8455 typical v dd1 supply current vs. data rate 5, 3.3, and 2.70 v operation figure 6. si8442 typical v dd1 or v dd2 supply current vs. data rate 5, 3.3, and 2.70 v operation (15 pf load) figure 7. si8455 typical v dd2 supply current vs. data rate 5, 3.3, and 2.70 v operation (15 pf load) figure 8. propagation delay vs. temperature figure 9. time-dependent breakdown dielectric breakdown figure 10. electromagnetic immunity 0 5 10 15 20 25 30 35 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 35 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 3.3v 2.70v 5 6 7 8 9 10 -40 -20 0 20 40 60 80 100 120 temperature (degrees c) delay (ns) rising edge falling edge 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 10000 100000 1000000 10000000 100000000 0 2 5 0 5 0 0 7 5 0 1 0 0 0 1 2 5 0 1 5 0 0 1 7 5 0 2 0 0 0 2 2 5 0 2 5 0 0 2 7 5 0 3 0 0 0 3 2 5 0 3 5 0 0 3 7 5 0 4 0 0 0 time to failure, 10ppm (years) working voltage (vrms) si84xx ac 10ppm (25c) si84xx ac 10ppm (150c) max continous working voltage specification 1.00e-18 1.00e-16 1.00e-14 1.00e-12 1.00e-10 1.00e-08 1.00e-06 1.00e-04 1.00e-02 1.00e+00 1.00e+02 1.00e+04 1.00e+06 1.00e+08 0.001 0.01 0.1 1 10 100 magnetic flux density(wb/m 2 ) frequency (mhz) iec61000-4-8 iec61000-4-9 si84xx
si84x/5x qsop 18 rev. 0.1 3. application information 3.1. theory of operation the operation of an si84xx channel is analogous to that of an opto coupler, except an rf carrier is modulated instead of light. this simple archit ecture provides a robust isolated data path and requires no special considerations or initializat ion at start-up. a simplified block diagra m for a single si84xx channel is shown in figure 11. figure 11. simplified channel diagram a channel consists of an rf transmitter and rf receiver separated by a semiconductor-based isolation barrier. referring to the transmitter, input a modulates the carrier provided by an rf oscillator using on/off keying. the receiver contains a demodulator that decodes the input state according to its rf energy content and applies the result to output b via the output driv er. this rf on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consum ption, and better immunity to magnetic fields. see figure 12 for more details. figure 12. modulation scheme rf oscillator modulator demodulator a b semiconductor- based isolation barrier transmitter receiver input signal output signal modulation signal
si84x/5x qsop rev. 0.1 19 3.2. eye diagram figure 13 illustrates an eye-diag ram taken on an si8455. for the data source, the test used an anritsu (mp1763c) pulse pattern generator set to 1000 ns/div. the output of the generator's clock and data from an si8455 were captured on an oscillosc ope. the results illustra te that data integrity was mainta ined even at the high data rate of 150 mbps. the results also show that 2 ns pulse wid th distortion and 250 ps peak jitter were exhibited. figure 13. eye diagram
si84x/5x qsop 20 rev. 0.1 3.3. layout recommendations to ensure safety in the end us er application, high voltage circ uits (i.e., circuits with >30 v ac ) must be physically separated from the safety extra-low voltage circuits (selv is a circuit with <30 v ac ) by a certain distance (creepage/clearance). if a component, su ch as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). table 6 on page 11 and table 7 on page 12 detail the working voltage and creepage/clearan ce capabilities of the si84xx. thes e tables also detail the component standards (ul1577, iec60747, csa 5a), which are readily accepted by certif ication bodies to provide proof for end-system specifications requirements. refer to the end-system specification (61010, 60950, 60601, etc.) requirements before starting any design that uses a digital isolator. 3.3.1. supply bypass the si84xx requires a 1 f bypass capacitor between v dd1 and gnd1 and v dd2 and gnd2. the capacitor should be placed as close as possible to the package. to enha nce the robustness of a design, it is further recommended that the user include 100 ? resistors in series with the inputs and ou tputs if the supply or system is excessively noisy. 3.3.2. output pin termination the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series term ination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appr opriately terminated with controlled impedance pcb traces.
si84x/5x qsop rev. 0.1 21 3.3.3. rf radiated emissions the si84xx family uses a rf carrier frequency of ap proximately 700 mhz. this results in a small amount of radiated emissions at this frequency and its harmonics. the radiation is not from the ic chip but due to a small amount of rf energy driving the isolated grou nd planes which can act as a dipole antenna. the unshielded si84xx evaluation board passes fcc class b (part 15) requirements. table 14 shows measured emissions compared to fcc requirements. note that the da ta reflects worst-case conditions where all inputs are tied to logic 1 and the rf tr ansmitters are fully active. radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the pcb is a less efficient antenna. 3.3.4. rf, magnetic, and common mode transient immunity the si84xx families have very high common mode transient immunity while transmitting data. this is typically measured by applying a square pulse with very fast rise/fall times between the isolated grounds. measurements show no failures at 25 kv/s (typical). during a high surg e event, the output may glitch low for up to 20?30 ns, but the output corrects immediately after the surge event. the si84xx families pass the industrial requirements of cispr24 for rf immu nity of 10 v/m using an unshielded evaluation board. as shown in figure 14, the isolated ground planes form a parasitic dipole antenna. the pcb should be laid-out to not act as an ef ficient antenna for the rf frequency of interest. rf susceptibility is also significantly reduced when the end system is hous ed in a metal enclosure, or otherwise shielded. the si84xx digital isolator can be used in close proximity to large mo tors and various other magnetic-field producing equipment. in theory, data transmission errors can occur if the magnetic field is too large and the field is too close to the isolator. however, in actual use, the si84xx devices provide extremely high immunity to external magnetic fields and have been indepe ndently evaluated to withstand magn etic fields of at least 1000 a/m according to the iec 61000-4-8 and iec 61000-4-9 specifications. figure 14. dipole antenna table 14. radiated emissions frequency (mhz) measured (dbv/m) fcc spec (dbv/m) compared to spec (db) 712 29 37 ?8 1424 39 54 ?15 2136 42 54 ?12 2848 43 54 ?11 4272 44 54 ?10 4984 44 54 ?10 5696 44 54 ?10 isolator gnd1 gnd2 dipole antenna
si84x/5x qsop 22 rev. 0.1 4. pin descriptions name soic-16 pin# type description (si844 2) description (si8455) v dd1 1 supply side 1 power supply side 1 power supply gnd1 2 ground side 1 ground side 1 ground a1 3 digital input side 1 digital input side 1 digital input a2 4 digital input side 1 digital input side 1 digital input a3 5 digital i/o side 1 digital output side 1 digital input a4 6 digital i/o side 1 digital output side 1 digital input a5/en1 7 digital input side 1 active high enable side 1 digital input gnd1 8 ground side 1 ground side 1 ground gnd2 9 ground side 2 ground side 2 ground b5/en2 10 digital input or enable side 2 active high enable side 2 digital output b4 11 digital i/o side 2 digital input side 2 digital output b3 12 digital i/o side 2 digital input side 2 digital output b2 13 digital output side 2 digital output side 2 digital output b1 14 digital output side 2 digital output side 2 digital output gnd2 15 ground side 2 ground side 2 ground v dd2 16 supply side 2 power supply side 2 power supply qsop-16 v dd1 a1 a3 a4 gnd1 a2 1 2 3 4 5 6 7 8 v dd2 b2 b1 b4 b3 gnd2 9 12 11 10 13 14 15 16 top view (si8442) gnd1 gnd2 en1 en2 qsop-16 v dd1 a1 a3 a4 gnd1 a2 1 2 3 4 5 6 7 8 v dd2 b2 b1 b4 b3 gnd2 9 12 11 10 13 14 15 16 a5 b5 top view (si8455) gnd1 gnd2
si84x/5x qsop rev. 0.1 23 5. ordering guide table 15. ordering guide for valid opns* ordering part number (opn) number of inputs vdd1 side number of inputs vdd2 side maximum data rate (mbps) isolation rating temp range package type si8442ba-d-iu 2 2 150 1 kvrms ?40 to 125 c qsop-16 SI8442BB-D-IU 2 2 150 2.5 kvrms si8455ba-b-iu 5 0 150 1 kvrms si8455bb-b-iu 5 0 150 2.5 kvrms *note: all packages are rohs-compliant. moisture sensitivity le vel is msl2a with peak reflow temperature of 260 c according to the jedec industry standard classifications and peak solder temperature.
si84x/5x qsop 24 rev. 0.1 6. package outline: 16-pin qsop figure 15 illustrates the package details for the si84xx in a 16-pin qsop package. table 16 lists the values for the dimensions shown in the illustration. figure 15. 16-pin qsop package table 16. package diagram dimensions dimension min max a ? 1.75 a1 0.10 0.25 a2 1.25 ? b 0.20 0.30 c 0.17 0.25 d 4.89 bsc e 6.00 bsc e1 3.90 bsc e 0.635 bsc l 0.40 1.27 l2 0.25 bsc h 0.25 0.50 ?
si84x/5x qsop rev. 0.1 25 0 8 aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.25 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-137, variation ab. 4. recommended card reflow profile is per the jedec/ipc j-std-020d specification for small body components. table 16. package diagram dimensions (continued) dimension min max
si84x/5x qsop 26 rev. 0.1 7. landing patt ern: 16-pin qsop figure 16 illustrates the recommended landing pattern details for the si 84xx in a 16-pin qsop. table 17 lists the values for the di mensions shown in the illustration. figure 16. 16-pin qsop pcb landing pattern table 17. 16-pin qsop landing pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 0.635 x1 pad width 0.40 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern sop63p602x173-16n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. ?
si84x/5x qsop rev. 0.1 27 8. top marking: 16-pin qsop figure 17. 16-pin qsop top marking table 18. 16-pin qsop top marking table line 1 marking: base part number ordering options (see ordering guide for more information). si84 = isolator product series xy = channel configuration x = # of data channels (5, 4) y = # of reverse channels (2, 0)* s = speed grade a = 1 mbps; b = 150 mbps v = insulation rating a=1kv; b=2.5kv line 2 marking: circle = 1.2 mm diameter ?e3? pb-free symbol yy = year ww = work week assigned by the assembly subcontractor. corresponds to the year and work week of the mold date. tttttt = mfg code manufacturing code from assembly purchase order form. circle = 1.2 mm diameter ?e3? pb-free symbol. *note: si8455 has 0 reverse channels. si84xysv yywwtttttt e3
si84x/5x qsop 28 rev. 0.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

▲Up To Search▲

Price & Availability of SI8442BB-D-IU

	To Download SI8442BB-D-IU Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .