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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . s i n g l e b u c k p w m c o n t r o l l e r w i t h l i n e a r r e g u l a t o r a p w 8 8 1 6 f e a t u r e s g e n e r a l d e s c r i p t i o n pwm controller adjustable output voltage from +0.75v to +3.3v - 0 . 7 5 v r e f e r e n c e v o l t a g e - 1% accuracy over-temperature operates from an input battery voltage range of +3v to +28v power-on-reset monitoring on vcc pin and pvcc pin to avoid wrong sequence excellent line and load transient responses pfm mode for increased light load efficiency programmable pwm frequency from 100khz to 500khz integrated mosfet drivers integrated bootstrap forward p-ch mosfet integrated soft-start selectable forced pwm or automatic pfm/pwm mode power good monitoring 70% under-voltage protection 125% over-voltage protection adjustable current-limit protection - using sense low-side mosfet?s r ds(on) over-temperature protection ldo controller 0.75v reference voltage with 1.5% accuracy over temperature independent enable and power ok function notebook table pc hand-held portable aio pc the APW8816 is a single-phase, constant on-time, synchronous pwm controller with linear regulator, which drives n-channel mosfets. the APW8816 steps down high voltage to generate low-voltage chipset or ram supplies in notebook computers. the APW8816 provides excellent transient response and accurate dc voltage output in either pfm or pwm mode. in pulse frequency mode (pfm), the APW8816 provides very high efficiency over light to heavy loads with loading- modulated switching frequencies. in pwm mode, the converter works nearly at constant frequency for low-noise requirements. the APW8816 is equipped with accurate positive current limit, output under-voltage, and output over-voltage protections, perfect for various applications. the power- on-reset function monitors the voltage on vcc and pvcc to prevent wrong operation during power-on. the APW8816 has a 1.5ms digital soft start and built-in an integrated output discharge device for soft stop. an internal soft-start ramps up the output voltage with programmable slew rate to reduce the start-up current. a soft-stop function actively discharges the output capacitors. the integrated linear regulator could drive an external n- channel mosfet and provides an adjustable output by using an external resistive divider. it is easy to be used because there is independent enable function and power ok indicator at linear regulator part. moreover, linear regulator has soft start, under-voltage and over- temperature protection to become the great second output voltage of the APW8816. the APW8816 is available in 16pin tqfn packages respectively. 50% under-voltage protection integrated soft-start function tqfn-16 3x3 package lead free and green device available (rohs compliant) a p p l i c a t i o n s
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 a p w 8 8 1 6 s i m p l i f i e d a p p l i c a t i o n c i r c u i t v out 1 l q 2 len apw 8816 v in lfb vcc phase ugate lgate en pvcc q 1 q 3 lpok pok ldo v in v out 2 o r d e r i n g a n d m a r k i n g i n f o r m a t i o n n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . p i n c o n f i g u r a t i o n tqfn 3 x 3 - 16 ( top view ) v o u t v c c f b p o k l p o k l f b l d r v l g a t e t o n e n l e n b o o t u g a t e p h a s e o c s e t p v c c 1 10 8 7 6 5 4 3 2 9 1 3 12 11 1 6 1 5 1 4 = g n d a n d t h e r m a l p a d ( c o n n e c t e d t o g n d p l a n e f o r b e t t e r h e a t d i s s i p a t i o n ) apw 8816 handling code temperature range . package code assembly meterial package code temperature range i : - 40 to 85 o c handling code assembly meterial g : halogen and lead free device tr : tape & reel qb : tqfn 3 x 3 - 16 apw 8816 qb : apw 8816 xxxxx xxxxx - date code
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 a p w 8 8 1 6 a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) symbol parameter rating unit v cc vcc supply voltage (vcc to gnd) - 0.3 ~ 7 v v pvcc pvcc supply voltage (pvcc to gnd) - 0.3 ~ 7 v v boot - gnd boot supply voltage (boot to gnd or pgnd ) - 0.3 ~ 3 7 v v boot boot supply voltage (boot to phase) - 0.3 ~ 7 v all ot her pins (vout, ocset, ton, en, len, lfb and fb to gnd) - 0.3 ~ v cc +0.3 v ugate voltage (ugate to phase) < 20 ns p ulse w idth > 20 ns p ulse w idth - 5 ~ v boot +0.3 - 0.3 ~ v boot +0.3 v lgate vol tage (lgate to gnd) < 20 ns p ulse w idth > 20 ns p ulse w idth - 5 ~ v cc +0.3 - 0.3 ~ v cc +0.3 v v phase phase voltage (phase to gnd) < 20 ns p ulse w idth > 20 ns p ulse w idth - 5 ~ 3 5 - 1 ~ 30 v v pok p ok supply voltage ( pok to gnd) - 0.3 ~ 7 v v lpok lpok to gnd voltage - 0.3 ~ 7 v t j maximum junction temperature 150 o c t stg storage temperature - 65 ~ 150 o c t sdr maximum soldering temperature, 10 seconds 260 o c note1: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. t h e r m a l c h a r a c t e r i s t i c s symbol parameter typical value unit q ja thermal resistance - junction to ambient (note 2 ) tqfn3x3 - 16 40 c/w note 2: q ja are measured with the component mounted on a high effective the thermal conductivity test board in free air. the exposed pad of package is soldered directly on the pcb. symbol parameter range unit v in converter input voltage 3 ~ 28 v v cc , v pvcc vcc, pvcc supply voltage 4.5 ~ 5.5 v v out (pwm) pwm converter output voltage 0.75 ~ 3.3 v v out (ldo) linear regulator output voltage (note 4) 0.75~v in(ldo) - v drop v t a ambi ent temperature - 40 ~ 85 o c t j junction temperature - 40 ~ 125 o c r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( n o t e 3 ) note 3: refer to the typical application circuit. note 4: vdrop defined as the v in -v out voltage at v out = 98% normal v out . the linear regulator must provide the output mosfet with sufficient gate-to-source voltage (v gs = v cc - v out ) to regulate the output voltage.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 a p w 8 8 1 6 e l e c t r i c a l c h a r a c t e r i s t i c s APW8816 symbol parameter test condition s min. typ. max. unit v out and v fb v oltage v out output v oltage adjustable output range 0.75 - 3.3 v v ref reference voltage - 0.75 - v t a = 25 o c - 0.5 - +0.5 % regulation accuracy t a = - 40 o c ~ 85 o c - 1 .0 - +1.0 % i fb fb input bias current fb = 0.75v - 0.02 0.1 m a r dis vout d ischarge r esistance en = 0v, v out = 0.5v - 20 32 w supply current i cc 5v input bias current vcc plus pvcc current, en=float, len=5v, vfb=0.8v, phase= - 0.1v - - 900 m a i cc_shdn 5v shutdown current en =len =gnd, vcc= pvcc= 5v , vcc plus pvcc cu rrent - 4.5 8.5 m a on - ti me t imer and i nternal s oft - s tart t on nominal on time v in =15v, v out =1.25v, r ton =1m w 267 334 401 ns t on (min) - 110 - ns t off (min) minimum off time v fb =0.7v, v phase = - 0.1v, ocset=open 250 400 550 ns t ss internal s oft s tart t ime en high to v out regulatio n 95% - 1.5 - ms gate driver ug pull - up resistance boot - ug = 0.5v - 2 4 w ug sink resistance ug - phase = 0.5v - 1.5 3 w l g pull - up resistance pvcc - lg = 0.5v - 1.5 3 w l g sink resistance lg - pgnd = 0.5v - 0.7 1.4 w ug to lg dead t ime ug falling to lg rising, no load - 30 - ns lg to ug dead t ime lg falling to ug rising, no load - 30 - ns bootstrap switch v f bootstrap forward voltage v pvcc - v boot - gnd , i f = 10ma - 0.5 0.8 v i r reverse leakage v boot - gnd = 30v, v phase = 25v, v pvcc = 5v - - 0.5 m a vcc por threshold v vcc_thr rising vcc por threshold voltage 4.25 4.35 4.45 v vcc por hysteresis - 100 - mv v pvcc_th r rising p vcc por threshold voltage 4.25 4.35 4.45 v pvcc por hysteresis - 100 - mv t h e s e s p e c i f i c a t i o n s a p p l y f o r t a = - 4 0 c t o + 8 5 c , u n l e s s o t h e r w i s e s t a t e d . a l l t y p i c a l s p e c i f i c a t i o n s t a = + 2 5 c , v c c = 5 v , v p v c c = 5 v .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 5 a p w 8 8 1 6 e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) t h e s e s p e c i f i c a t i o n s a p p l y f o r t a = - 4 0 c t o + 8 5 c , u n l e s s o t h e r w i s e s t a t e d . a l l t y p i c a l s p e c i f i c a t i o n s t a = + 2 5 c , v c c = 5 v , v p v c c = 5 v . APW8816 symbol parameter test condition s min. typ. max. unit control inputs en high - level input voltage 2.9 - - v en float voltage 1.61 1.9 2.19 v en low - level input voltage - - 0.8 v hysteresis 350 400 450 mv en leakage en= 5 v - 0.1 1.0 m a power - ok indicator pok in from lower (pok goes high) 87 90 93 % v pok pok threshold pok out from normal high threshold (pok goes low) 120 125 130 % i pok p ok leakage current v pok =5v - 0.1 1.0 m a p ok sink current v pok =0.5v 1.25 7.5 - ma pok o ut debounce time1 when enter high threshold - 3 - m s pok out debounce time2 when run away 90% - 20 - m s pok enable delay time from en high to pok high - 4.5 - ms current sense i ocset i ocset ocp threshold i ocset sourc ing 18 20 22 m a t i ocset i ocset t e mperature c oefficient on t he b asis of 25c - 4700 - ppm/ o c v r ocset current l imit t hreshold s etting r ange v ocset - gnd voltage, over a ll t emperature 60 - 650 mv over current l imit c omparator o ffset (v ocset - phase - v gnd - phase ) voltage, v ocset - phase =200mv - 10 0 10 mv zero c rossing c omparator o ffset v gnd - phase voltage, en=3.3v - 5 0 5 mv protection v uv uvp threshold 60 70 80 % uvp debounce interval - 20 - m s uvp enable delay en high to uvp workable - 4.5 - ms v ovr ovp rising threshold 120 125 130 % ovp propagation delay v fb rising, over voltage=10mv - 3 - m s t otr otp rising threshold (note 5) - 155 - o c otp hyste r esis (note 5) - 10 - o c
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 6 a p w 8 8 1 6 e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) t h e s e s p e c i f i c a t i o n s a p p l y f o r t a = - 4 0 c t o + 8 5 c , u n l e s s o t h e r w i s e s t a t e d . a l l t y p i c a l s p e c i f i c a t i o n s t a = + 2 5 c , v c c = 5 v , v p v c c = 5 v . n o t e 5 : g u a r a n t e e d b y d e s i g n . APW8816 symbol parameter test condition s min. typ. max. unit ldo controller i q_ldo ldo quiescent current pwm off, ldo on, no load - - 350 m a l en high - level input voltage 1.2 - - v l en low - level input voltage - - 0.8 v l en leakage l en= 5 v - 0.1 1.0 m a v lref ldo reference voltage 0.739 0.75 0.761 v i lfb fb input bias current 0.02 1 m a sourcing, lfb=0.72v - - 12 ma i out_ldrv ldrv output current sinkin g, lfb=0.75v - - 4 ma ldo internal s oft s tart t ime ldo out ramp up to ldo out=95% - 2 - ms ldo enable delay len high to ldo out ramp up - 1 - ms v luv ldo uvp threshold measured lfb pin 40 50 60 % ldo uvp enable delay ldo ramp up to uvp workable - 4 - ms lpok in from lower (pok goes high) 87 90 93 % lpok debounce time when run away 90% - 20 - m s l p ok sink current v lpok =0.5v 1.25 7.5 - ma i lpok l p ok leakage current v lpok =5v - 0.1 1.0 m a t lotr ldo otp rising threshold (note 5) - 155 - o c o tp hyste r esis (note 5) - 10 - o c
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 7 a p w 8 8 1 6 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s output current ( a ) o u t p u t v o l t a g e ( v ) output voltage vs output current 0 5 10 15 20 1490 1 . 500 1 . 510 1 . 520 1 . 530 auto force vin = 8 v s w i t c h f r e q u e c y ( k h z ) input voltage ( v ) switch frequecy vs . input voltage 0 5 10 15 20 25 30 0 100 200 300 s w i t c h f r e q u e n c y ( k h z ) switch frequency vs . outpu t current outpue current ( a ) auto force 0 4 8 12 16 20 0 50 100 150 200 250 300 output voltage vs output current o u t p u t v o l t a g e ( v ) 0 5 10 15 20 1 . 490 1 . 500 1 . 510 1 . 520 1 . 530 output current ( a ) auto force vin = 19 v r e f e r e n c e v o l t a g e ( v ) reference voltage vs junction temperature junction temperature ( o c ) 0 . 7445 0 . 745 0 . 7455 0 . 746 0 . 7465 0 . 747 0 . 7475 0 . 748 0 . 7485 0 . 749 0 . 7495 - 20 0 20 40 60 80 100 120 output voltage vs . input voltage o u t p u t v o l t a g e ( v ) input voltage ( v ) 1 3 5 7 9 11 13 15 17 19 21 23 25 27 1 . 48 1 . 5 1 . 52 1 . 54 force auto 1 . 49 1 . 51 1 . 53
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 8 a p w 8 8 1 6 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s i o c s e t ( u a ) junction temperature iocset vs junction temperature - 20 0 20 40 60 80 100 120 0 5 10 15 20 25 30 35 ( o c )
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 9 a p w 8 8 1 6 o p e r a t i n g w a v e f o r m s refer to the typical application circuit. the test condition is v in =19v, t a = 25 o c unless otherwise specified. ch 1 : v en , 5 v / div ch 2 : v ugate , 20 v / div time : 10 us / div ch 4 : v out , 1 v / div ch 3 : v lgate , 5 v / div disable ( 15 a ) v l gate v out 1 2 3 v en 4 v u gate ch 1 : v out , 100 mv / div time : 20 us / div ch 3 : i l , 10 a / div ch 2 : v phase , 1 0 v / div ch 4 : i out , 10 a / div load transient i l v out 1 2 3 v phase 4 i out ch 2 : v phase , 1 0 v / div ch 3 : v out , 1 v / div time : 1 ms / div ch 4 : v pok , 5 v / div ch 1 : v en , 2 v / div enable ( auto ) 1 2 v en v phase 3 4 v out v pok ch 1 : v en , 2 v / div ch 2 : v phase , 1 0 v / div ch 3 : v out , 1 v / div time : 1 ms / div ch 4 : v pok , 5 v / div enable ( forced pwm ) 1 4 2 v en v pok 3 v out v phase
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 0 a p w 8 8 1 6 o p e r a t i n g w a v e f o r m s refer to the typical application circuit. the test condition is v in =19v, t a = 25 o c unless otherwise specified. ch 1 : v fb , 1 v / div ch 2 : v out , 1 v / div time : 100 us / div 1 3 2 ch 3 : v lgate , 5 v / div v out v fb i l ch 4 : i l , 10 a / div over - voltage - protection 4 v lgate under - voltage - protection ch 1 : v fb , 1 v / div ch 2 : v lgate , 5 v / div time : 20 us / div 1 3 2 ch 3 : v ugate , 10 v / div v u gate v fb v l gate ldo on by len ch 1 : v len , 5 v / div ch 2 : v out , 500 mv / div time : 2 ms / div 1 3 2 ch 3 : v pok , 5 v / div v out v len v ldrv ch 4 : v ldrv , 2 v / div v pok 4 ch 1 : v cc , 2 v / div ch 2 : v out , 500 mv / div time : 5 ms / div pre - short - protection 1 3 2 ch 3 : v ugate , 5 v / div v out v cc i l ch 4 : i l , 10 a / div 4 v ugate
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 1 a p w 8 8 1 6 o p e r a t i n g w a v e f o r m s refer to the typical application circuit. the test condition is v in =19v, t a = 25 o c unless otherwise specified. ch 1 : v out , 500 mv / div ch 2 : v pok , 5 v / div time : 20 us / div ch 3 : v ldrv , 2 v / div ldo short circuit 1 3 2 v out v pok v ldrv ch 1 : v out , 100 mv / div ch 2 : v ldrv , 2 v / div time : 100 us / div ch 3 : i l , 2 a / div 1 3 2 v out v ldrv i l ldo load transient
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 2 a p w 8 8 1 6 p i n d e s c r i p t i o n pin no. name pin function 1 v out the vout pin makes a direct measurement of the converter output voltage. the vout pin should be connected to the top feedback resistor at the converter output. 2 vcc supply v oltage i nput p in for c ontrol c ircuitry. conne ct +5v from the vcc pin to the gnd pin. decoupling at least 1f of a mlcc capacitor from the vcc pin to the gnd pin. 3 fb output v oltage f eedback p in. this pin is connected to the resistive divider that set the desired output voltage. the p ok , uvp, and ov p circuits detect this signal to report output voltage status. 4 pok power good output. po k i s a n o pen d rain o utput used to in dicate the status of the output voltage. connect the pok in to +5v through a pull - high resistor. 5 lpok ldo power good output. l po k i s a n o pen d rain o utput used to in dicate the status of the output voltage. connect the lpok in to +5v through a pull - high resistor. 6 lfb ldo output v oltage f eedback p in. this pin is connected to the resistive divider that set the desired output volta ge. the l p ok and uvp circuits detect this signal to report output voltage status. 7 ldrv this pin drives the gate of an external n - channel mosfet for linear regulator. 8 lgate output of t he l ow - side mosfet d river. connect this pin to gate of the low - side mosfet. swings from gnd to p vcc. 9 pvcc supply v oltage i nput p in for the lg low - side mosfet gate driver. connect +5v from the pvcc pin to the gnd pin. decoupling at least 1f of a mlcc capacitor from the pvcc pin to the gnd pin. 10 ocset current limit t hreshold setting pin . there is an internal source current 20 m a through a resistor from ocset pin to gnd. this pin is used to monitor the voltage drop across the drain and source of the low - side mo sfet for current limit. 11 phase junction p oint of t he h ig h - side mosfet source, o utput f ilter i nductor a nd t he l ow - side mosfet drain. connect this pin to the source of the high - side mosfet. phase serves as the lower supply rail for the u g high - side gate driver. 12 ugate output of t he h igh - side mosfet d river. con nect this pin to gate of the high - side mosfet. 13 boot supply input for t he ug gate driver a nd a n i nternal l evel - shift c ircuit. connect to an external capacitor to create a boosted voltage suitable to drive a logic - level n - channel mosfet. 14 len enable p in of t he linear regulator . when the len is above high logic level, the ldo is enable d. when the len is below low logic level , the ldo is disable d. 15 en enable p in of t he pwm c ontroller. when the en is above high logic level, the device is in automatic p fm/pwm mode. when the en is floating, t he device is in force pwm mode. when the en is below low logic level , the device is in shutdown. 16 ton this p in is a llowed to a djust t he s witching f requency. connect a resistor r ton from ton pin to v in . exposed pad gnd signal g round for t he ic
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 3 a p w 8 8 1 6 b l o c k d i a g r a m pwm controller fb error comparator ov uv 70 % v ref 125 % v ref v ref por vcc en digital soft start / soft sop p w m s i g n a l c o n t r o l l e r v cc boot ug phase pvcc lg thermal shutdown gnd pok vout force pwm or automatic pfm / pwm selection frequency adjustable ton fault latch logic on - time generator 90 % v ref 125 % v ref z c phase ocset 20 u a current limit delay v pv cc en por lfb 50 % v ref len ldrv gnd lpok delay enable _ ea pwok uvp comparator control logic 90 % v ref 1 . 2 v v ref 0 . 75 v enable soft - start power - ok comparator error amplifier uv linear regulator
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 4 a p w 8 8 1 6 t y p i c a l a p p l i c a t i o n c i r c u i t ldrv pok pvcc vcc gnd ug boot phase ocset lg en vout fb ton r pok r vcc + 5 v c vcc r top r gnd q 1 q 2 l out 1 . 0 m h c boot r ocset apw 8816 c in v pok v in ( pwm ) v out ( pwm ) 1 . 5 v / 20 a 6 . 8 k w , 5 % apm 4350 apm 4354 10 m f 10 k w , 1 % 10 k w , 1 % 19 v 100 k w 2 . 2 w 0 . 1 m f 1 m f c out 330 m f lfb v l pok r lpok 100 k w lpok r ton 1 m w len v out ( ldo ) 1 . 8 v v in ( ldo ) 3 . 3 v r ltop 14 k w , 1 % r lgnd 10 k w , 1 % ldo c out 1 22 m f ldo c out 2 10 m f q 3 apm 4354 r 1 c 1 c 2 c pvcc 1 m f
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 5 a p w 8 8 1 6 f u n c t i o n d e s c r i p t i o n constant-on-time pwm controller with input feed-for- ward the constant-on-time control architecture is a pseudofixed frequency with input voltage feed-forward. this architec- ture relies on the output filter capacitor?s effective series resistance (esr) to act as a current-sense resistor, so the output ripple voltage provides the pwm ramp signal. in pfm operation, the high-side switch on-time controlled by the on-time generator is determined solely by a oneshot whose pulse width is inversely proportional to input volt- age and directly proportional to output voltage. in pwm operation, the high-side switch on-time is determined by a switching frequency control circuit in the on-time gen- erator block. t h e s w i t c h i n g f r e q u e n c y c o n t r o l c i r c u i t s e n s e s t h e s w i t c h - i n g f r e q u e n c y o f t h e h i g h - s i d e s w i t c h a n d k e e p s r e g u l a t - i n g i t a t a c o n s t a n t f r e q u e n c y i n p w m m o d e . t h e d e s i g n i m p r o v e s t h e f r e q u e n c y v a r i a t i o n a n d i s m o r e o u t s t a n d - i n g t h a n a c o n v e n t i o n a l c o n s t a n t - o n - t i m e c o n t r o l l e r , w h i c h h a s l a r g e s w i t c h i n g f r e q u e n c y v a r i a t i o n o v e r i n p u t v o l t a g e , o u t p u t c u r r e n t , a n d t e m p e r a t u r e . b o t h i n p f m a n d p w m , t h e o n - t i m e g e n e r a t o r , w h i c h s e n s e s i n p u t v o l t a g e o n t o n p i n , p r o v i d e s v e r y f a s t o n - t i m e r e s p o n s e t o i n p u t l i n e t r a n s i e n t s . a n o t h e r o n e - s h o t s e t s a m i n i m u m o f f - t i m e ( t y p i c a l : 4 0 0 n s ) . t h e o n - t i m e o n e - s h o t i s t r i g g e r e d i f t h e e r r o r c o m - p a r a t o r i s h i g h , t h e l o w - s i d e s w i t c h c u r r e n t i s b e l o w t h e c u r r e n t - l i m i t t h r e s h o l d , a n d t h e m i n i m u m o f f - t i m e o n e s h o t h a s t i m e d o u t . pulse-frequency modulation (pfm) i n p f m m o d e , a n a u t o m a t i c s w i t c h o v e r t o p u l s e - f r e q u e n c y m o d u l a t i o n ( p f m ) t a k e s p l a c e a t l i g h t l o a d s . t h i s s w i t c h o v e r i s a f f e c t e d b y a c o m p a r a t o r t h a t t r u n c a t e s t h e l o w - s i d e s w i t c h o n - t i m e a t t h e i n d u c t o r c u r r e n t z e r o c r o s s i n g . t h i s m e c h a n i s m c a u s e s t h e t h r e s h o l d b e t w e e n p f m a n d p w m o p e r a t i o n t o c o i n c i d e w i t h t h e b o u n d a r y b e t w e e n c o n t i n u o u s a n d d i s c o n t i n u o u s i n d u c t o r - c u r r e n t o p e r a t i o n ( a l s o k n o w n a s t h e c r i t i c a l c o n d u c t i o n p o i n t ) . t h e o n - t i m e o f p f m i s g i v e n b y : w h e r e f s w i s t h e n o m i n a l s w i t c h i n g f r e q u e n c y o f t h e c o n - v e r t e r i n p w m m o d e . t h e l o a d c u r r e n t a t h a n d o f f f r o m p f m t o p w m m o d e i s g i v e n b y : v v f 1 t in out sw pfm - on = in out sw out in pfm - on out in pwm) to load(pfm v v x f 1 2l v v t l v v 2 1 i - = - = forced-pwm mode the forced-pwm mode disables the zero-crossing comparator, which truncates the low-side switch on-time at the inductor current zero crossing. this causes the low-side gate-drive waveform to become the complement of the high-side gate-drive waveform. this in turn causes the inductor current to reverse at light loads while ugate maintains a duty factor of v out /v in . the benefit of forced- pwm mode is to keep the switching frequency fairly constant. the forced-pwm mode is most useful for re- ducing audio frequency noise, improving load-transient response, and providing sink-current capability for dy- namic output voltage adjustment. power-on-reset a power-on-reset (por) function is designed to prevent wrong logic controls when the pvcc or vcc voltage is low. the por function continually monitors the bias sup- ply voltage on the pvcc and vcc pins if at least one of the enable pins is set high. when the rising pvcc volt- age reaches the rising pvcc por voltage threshold (4.35v, typical) and the rising vcc voltage reaches the rising vcc por threshold (4.35v, typical), the por sig- nal goes high and the chip initiates soft-start operations. there is almost no hysteresis to por voltage threshold ( a b o u t 1 0 0 m v t y p i c a l ) . when pvcc voltage drops lower than 4.25v (typical) or vcc voltage drops lower than 4.25v (typical), the por disables the chip. en pin control when v en is above the en high threshold (2.9v, minimum), the converter is enabled in automatic pfm/ pwm operation mode. when en pin is floating, APW8816 internal circuit will pull v en up to 1.9v (typical). furthermore, APW8816 is in forced-pwm operation mode.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 6 a p w 8 8 1 6 f u n c t i o n d e s c r i p t i o n ( c o n t . ) f i g u r e 1 . s o f t - s t a r t s e q u e n c e during soft-start stage before the pok pin is ready, the under-voltage protection is prohibited. the over-voltage and current-limit protection functions are enabled. if the output capacitor has residue voltage before start-up, both low-side and high-side mosfets are in off-state until the internal digital soft-start voltage equals to the v fb voltage. this will ensure that the output voltage starts from its existing voltage level. in the event of under-voltage, over-voltage, over- temperature, or shutdown, the chip enables the soft-stop function. the soft-stop function discharges the output voltages to the pgnd through an internal 20 w switch. the linear regulator controller provides an internal soft- start circuitry to control rise rate of the output voltage and limit the current surge during start-up. typical soft-start interval is about 2ms. power ok indicator the APW8816 features an open-drain pok pin to indi- cate output regulation status. in normal operation, when the output voltage rises 90% of its target value, the pok goes high. when the output voltage outruns 90% or 125% of the target voltage, pok signal will be pulled low after internal delay. since the fb pin is used for both feedback and monitor- ing purposes, the output voltage deviation can be coupled directly to the fb pin by the capacitor in parallel with the voltage divider as shown in the typical applications. in order to prevent false pok from dropping, capacitors need to parallel at the output to confine the voltage deviation with severe load step transient. the linear regulator controller indicates the status of the output voltage by monitoring the feedback voltage (v lfb ) on lfb pin. as the v lfb rises and reaches the rising power- ok voltage threshold (v pokth ), the ic turns off the internal nmos of the lpok to indicate that the output is ok. as the v lfb falls and reaches the falling power-ok voltage threshold, the ic turns on the nmos of the lpok (after a debounce time of 20 m s typical). when v en is below the en low threshold (0.8v, maximum), the chip is in the shutdown and only low leakage current is taken from vcc. t h e l i n e a r r e g u l a t o r c o n t r o l l e r h a s a d e d i c a t e d e n a b l e p i n ( l e n ) . a l o g i c l o w s i g n a l a p p l i e d t o t h i s p i n s h u t s d o w n t h e o u t p u t . f o l l o w i n g a s h u t d o w n , a l o g i c h i g h s i g - n a l r e - e n a b l e s t h e o u t p u t t h r o u g h i n i t i a t i o n o f a n e w s o f t - s t a r t c y c l e . i t ? s n o t n e c e s s a r y t o u s e a n e x t e r n a l t r a n s i s t o r t o s a v e c o s t . en pin control (cont.) d i g i t a l s o f t - s t a r t t h e a p w 8 8 1 6 i n t e g r a t e s d i g i t a l s o f t - s t a r t c i r c u i t s t o r a m p u p t h e o u t p u t v o l t a g e o f t h e c o n v e r t e r t o t h e p r o g r a m m e d r e g u l a t i o n s e t p o i n t a t a p r e d i c t a b l e s l e w r a t e . t h e s l e w r a t e o f o u t p u t v o l t a g e i s i n t e r n a l l y c o n t r o l l e d t o l i m i t t h e i n r u s h c u r r e n t t h r o u g h t h e o u t p u t c a p a c i t o r s d u r i n g s o f t - s t a r t p r o c e s s . t h e f i g u r e 1 s h o w s s o f t - s t a r t s e q u e n c e . w h e n t h e e n p i n i s p u l l e d a b o v e t h e r i s i n g e n t h r e s h o l d v o l t a g e , t h e d e v i c e i n i t i a t e s a s o f t - s t a r t p r o c e s s t o r a m p u p t h e o u t p u t v o l t a g e . t h e s o f t - s t a r t i n t e r v a l i s 1 . 5 m s ( t y p i c a l ) a n d i n d e p e n d e n t o f t h e u g a t e s w i t c h i n g f r e q u e n c y . 4 . 5 ms en v out v cc and v pvcc v p ok 1 . 5 ms
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 7 a p w 8 8 1 6 f u n c t i o n d e s c r i p t i o n ( c o n t . ) f i g u r e 2 . c u r r e n t - l i m i t a l g o r i t h m c u r r e n t - l i m i t the current-limit circuit employs a ?valley? current-sens- ing algorithm (see figure 2). the APW8816 uses the low-side mosfet?s r ds(on) of the synchronous rectifier as a current-sensing element. if the magnitude of the current-sense signal at phase pin is above the current- limit threshold, the pwm is not allowed to initiate a new cycle. the actual peak current is greater than the current- limit threshold by an amount equals to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are the functions of the sense resistance, inductor value, and input voltage. time i n d u c t o r c u r r e n t , i l 0 i out i peak i limit d i the pwm controller uses the low-side mosfets on-re- sistance r ds(on) to monitor the current for protection against shortened outputs. the mosfet?s r ds(on) is var- ied by temperature and gate to source voltage, the user should determine the maximum r ds(on) in manufacture?s datasheet. the ocset pin can source 20 m a through an external resistor for adjusting current-limit threshold. the voltage at ocset pin is equal to 20 m a x r ocset . the relationship between the sampled voltage v ocset and the current-limit threshold i limit is given by: 20 m a x r ocset = i limit x r ds(on) where r ocset is the resistor of current-limit setting threshold. r ds(on) is the low side mosfets conducive resistance. i limit is the setting current-limit threshold. i limit can be expressed as i out minus half of peak-to-peak in- ductor current. under-voltage protection (uvp) in the operational process, if a short-circuit occurs, the output voltage will drop quickly. when load current is big- ger than current-limit threshold value, the output voltage will fall out of the required regulation range. the under- voltage protection circuit continually monitors the fb volt- age after soft-start is completed. if a load step is strong enough to pull the output voltage lower than the under- voltage threshold, the under-voltage threshold is 70% of the nominal output voltage, the internal uvp delay counter starts to count. after 20 m s debounce time, the device turns off both high-side and low-side mosefet with latched and starts a soft-stop process to shut down the output gradually. toggling enable pin to low or recycling pvcc or vcc, will clear the latch and bring the chip back to operation. the linear regulator controller monitors the voltage on lfb. when the voltage on lfb falls below the under- voltage threshold, the uvp circuit shuts off the output volt- age immediately by pulling down ldrv to 0v and latches controller off, requiring either a vcc por or en re-en- able again to restart. o v e r - v o l t a g e p r o t e c t i o n ( o v p ) the over-voltage function monitors the output voltage by fb pin. when the fb voltage increases over 125% of the reference voltage due to the high-side mosfet failure or for other reasons, the over-voltage protection compara- tor designed with a 3 m s noise filter will force the low-side mosfet gate driver fully turn on and latch high. this ac- tion actively pulls down the output voltage. in the meantime, the output voltage is also pulled low by internal discharge transistor. this ovp scheme only clamps the voltage overshoot and does not invert the output voltage when otherwise acti- vated with a continuously high output from low-side mosfet driver. it?s a common problem for ovp schemes with a latch. once an over-voltage fault condition is set, it can only be reset by toggling en, pvcc or vcc power on reset signal.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 8 a p w 8 8 1 6 f u n c t i o n d e s c r i p t i o n ( c o n t . ) on in out sw sw on t v v f f d t = t = where: f sw is the pwm switching frequency. APW8816 doesn?t have vin pin to calculate on-time pulse width. therefore, monitoring v ton voltage as input voltage to calculate on-time. and then, use the relationship be- tween ontime and duty cycle to obtain the switching frequency. the pcb layout guidelines should ensure that noise and dc errors do not corrupt the current-sense signals at phase. place the hottest power mosefts as close to the ic as possible for best thermal coupling. when com- bined with the under-voltage protection circuit, this cur- rent-limit method is effective in almost every circumstance. c u r r e n t - l i m i t ( c o n t . ) over-temperature protection (otp) when the junction temperature increases above the ris- ing threshold temperature t otr , the ic will enter the over- temperature protection state that suspends the pwm, which forces the ugate and lgate gate drivers output low. the thermal sensor allows the converters to start a start-up process and regulate the output voltage again after the junction temperature cools by 10 o c. the otp is designed with a 10 o c hysteresis to lower the average t j during continuous thermal overload conditions, which in- creases lifetime of the APW8816. p r o g r a m m i n g t h e o n - t i m e c o n t r o l a n d p w m s w i t c h - i n g f r e q u e n c y t h e a p w 8 8 1 6 d o e s n o t u s e a c l o c k s i g n a l t o p r o d u c e p w m . t h e d e v i c e u s e s t h e c o n s t a n t - o n - t i m e c o n t r o l a r - c h i t e c t u r e t o p r o d u c e p s e u d o - f i x e d f r e q u e n c y w i t h i n p u t v o l t a g e f e e d - f o r w a r d . t h e o n - t i m e p u l s e w i d t h i s p r o p o r - t i o n a l t o o u t p u t v o l t a g e v o u t a n d i n v e r s e s p r o p o r t i o n a l t o i n p u t v o l t a g e v i n . i n p w m , t h e o n - t i m e c a l c u l a t i o n i s w r i t - t e n a s b e l o w : ( ) ? ? = 0.5 - vin vout r 10 3.85 t ton 12 - on w h e r e : r t o n i s t h e r e s i s t o r c o n n e c t e d f r o m t o n p i n t o v i n . f u r t h e r m o r e , t h e a p p r o x i m a t e p w m s w i t c h i n g f r e q u e n c y i s w r i t t e n a s :
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 9 a p w 8 8 1 6 a p p l i c a t i o n i n f o r m a t i o n where 0.75 is the reference voltage, r top is the resistor connected from converter?s output to fb, and r gnd is the resistor connected from fb to gnd. suggested r gnd is in the range from 1k to 20k w . to prevent stray pickup, locate resistors r top and r gnd close to APW8816. o u t p u t i n d u c t o r s e l e c t i o n t h e d u t y c y c l e ( d ) o f a b u c k c o n v e r t e r i s t h e f u n c t i o n o f t h e i n p u t v o l t a g e a n d o u t p u t v o l t a g e . o n c e a n o u t p u t v o l t a g e i s f i x e d , i t c a n b e w r i t t e n a s : in out v v d = in out sw out in ripple v v l f v - v i = o u t p u t c a p a c i t o r s e l e c t i o n the inductor value (l) determines the inductor ripple current, i ripple , and affects the load transient reponse. higher inductor value reduces the inductor?s ripple cur- rent and induces lower output ripple voltage. the ripple current and ripple voltage can be approximated by: esr ripple esr sw out ripple out c r i v f 8c i v = d = d o u t p u t v o l t a g e s e t t i n g the output voltage is adjustable from 0.75v to 3.3v with a resistor-divider connected with fb, gnd, and converter?s output. using 1% or better resistors for the resistor-di- vider is recommended. the output voltage is determined by: w h e r e f s w i s t h e s w i t c h i n g f r e q u e n c y o f t h e r e g u l a t o r . a l t h o u g h t h e i n d u c t o r v a l u e a n d f r e q u e n c y a r e i n c r e a s e d a n d t h e r i p p l e c u r r e n t a n d v o l t a g e a r e r e d u c e d , a t r a d e o f f e x i s t s b e t w e e n t h e i n d u c t o r ? s r i p p l e c u r r e n t a n d t h e r e g u - l a t o r l o a d t r a n s i e n t r e s p o n s e t i m e . a smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. increasing the switching frequency (f sw ) also reduces the ripple current and voltage, but it will increase the switching loss of the mosfets and the power dissipa- tion of the converter. the maximum ripple current occurs at the maximum input voltage. a good starting point is to choose the ripple current to be approximately 30% of the maximum output current. once the inductance value has been chosen, selecting an inductor which is capable of carrying the required peak current without going into saturation. in some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. this results in a larger output ripple voltage. besides, the inductor needs to have low dcr to reduce the loss of efficiency. o u tp ut voltage ripple and the transient volta ge devia- tion are factors which have to be taken into con sider- ation when selecting an output capacitor. higher capaci- tor value and lower esr reduce the out put ripple and the load transient drop. therefore, selecting high per- formance low esr capacitors is recommended for switching regulator applications. in addition to h igh frequency noise related to mosfet turn-on and turn - o ff, the output voltage ripple includes the capaci tance voltage drop d v cout and esr voltage drop d v esr caused by the ac peak-to-peak inductor?s current. t h e s e t w o v o l t a g e s c a n b e r e p r e s e n t e d b y : ? ? ? ? ? + = gnd top out r r 1 0.75 v the linear regulator controller,an external n-channel mosfet should be connected to ldrv as the pass element. the output voltage set by the resistor divider is determined by: ? ? ? ? ? + = lgnd ltop out(ldo) r r 1 0.75 v where r ltop is connected from vout to lfb and r lgnd is connected from lfb to gnd.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 0 a p w 8 8 1 6 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) m o s f e t s e l e c t i o n t h e a p p l i c a t i o n f o r a n o t e b o o k b a t t e r y w i t h a m a x i m u m v o l t a g e o f 2 8 v , a t l e a s t a m i n i m u m 3 0 v m o s f e t s s h o u l d b e u s e d . t h e d e s i g n h a s t o t r a d e o f f t h e g a t e c h a r g e w i t h t h e r ds(on) o f t h e m o s f e t : t h e s e l e c t i o n o f t h e n - c h a n n e l p o w e r m o s f e t s a r e d e t e r m i n e d b y t h e r ds(on) , r e v e r s i n g t r a n s f e r c a p a c i - t a n c e ( c r s s ) a n d m a x i m u m o u t p u t c u r r e n t r e q u i r e m e n t . t h e l o s s e s i n t h e m o s f e t s h a v e t w o c o m p o n e n t s : c o n d u c t i o n l o s s a n d t r a n s i t i o n l o s s . f o r t h e h i g h - s i d e a n d l o w - s i d e m o s f e t s , t h e l o s s e s a r e a p p r o x i m a t e l y g i v e n b y t h e f o l l o w i n g e q u a t i o n s : p high-side = i out 2 (1+ tc)(r ds(on) )d + (0.5)( i out )(v in )( t sw )f s w p low-side = i out 2 (1+ tc)(r ds(on) )(1-d) f o r t h e l o w - s i d e m o s f e t , b e f o r e i t i s t u r n e d o n , t h e b o d y d i o d e h a s b e e n c o n d u c t i n g . t h e l o w - s i d e m o s f e t d r i v e r w i l l n o t c h a r g e t h e m i l l e r c a p a c i t o r o f t h i s m o s f e t . i n t h e t u r n i n g o f f p r o c e s s o f t h e l o w - s i d e m o s f e t , t h e l o a d c u r r e n t w i l l s h i f t t o t h e b o d y d i o d e f i r s t . t h e h i g h d v / d t o f t h e p h a s e n o d e v o l t a g e w i l l c h a r g e t h e m i l l e r c a p a c i - t o r t h r o u g h t h e l o w - s i d e m o s f e t d r i v e r s i n k i n g c u r r e n t p a t h . t h i s r e s u l t s i n m u c h l e s s s w i t c h i n g l o s s o f t h e l o w - s i d e m o s f e t s . t h e d u t y c y c l e i s o f t e n v e r y s m a l l i n h i g h b a t t e r y v o l t a g e a p p l i c a t i o n s , a n d t h e l o w - s i d e m o s f e t w i l l c o n d u c t m o s t o f t h e s w i t c h i n g c y c l e ; t h e r e f o r e , when using smaller r ds(on) of the low-side mosfet, the con- verter can reduce power loss. t h e g a t e c h a r g e f o r t h i s m o s f e t i s u s u a l l y t h e s e c o n d a r y c o n s i d e r a t i o n . t h e h i g h - s i d e m o s f e t d o e s n o t h a v e t h i s z e r o v o l t a g e s w i t c h - i n g c o n d i t i o n ; i n a d d i t i o n , b e c a u s e i t c o n d u c t s f o r l e s s t i m e c o m p a r e d t o t h e l o w - s i d e m o s f e t , t h e s w i t c h i n g l o s s t e n d s t o b e d o m i n a n t . p r i o r i t y s h o u l d b e g i v e n t o t h e m o s f e t s w i t h l e s s g a t e c h a r g e , s o t h a t b o t h t h e g a t e d r i v e r l o s s a n d s w i t c h i n g l o s s w i l l b e m i n i m i z e d . where i out is the load current tc is the temperature dependency of r ds(on) f sw is the switching frequency t sw is the switching interval d is the duty cycle note that both mosfets have conduction losses while the high- side mosfet includes an additional transi tion loss. t he switching interval , t sw , is the function of the reverse transfer capacitance c rss . the (1+tc) term is a factor in the temperature dependency of the r ds(on) and can be extracted from the ?r ds(on) vs. temperature? curve of the power mosfet. h i g h e r t h a n t h e m a x i m u m i n p u t v o l t a g e . t h e m a x i m u m r m s c u r r e n t r a t i n g r e q u i r e m e n t i s a p p r o x i m a t e l y i o u t / 2 , w h e r e i o u t i s t h e l o a d c u r r e n t . d u r i n g p o w e r - u p , t h e i n p u t c a p a c i t o r s h a v e t o h a n d l e g r e a t a m o u n t o f s u r g e c u r r e n t . f o r l o w - d u t y n o t e b o o k a p p l i a c t i o n s , c e r a m i c c a p a c i t o r i s r e c o m m e n d e d . t h e c a p a c i t o r s m u s t b e c o n n e c t e d b e - t w e e n t h e d r a i n o f h i g h - s i d e m o s f e t a n d t h e s o u r c e o f l o w - s i d e m o s f e t w i t h v e r y l o w - i m p e a d a n c e p c b l a y o u t . these two components constitute a large portion of the total output voltage ripple. in some applications, multiple capacitors have to be paralleled to achieve the desired esr value. if the output of the converter has to support another load with high pulsating current, more capaci- tors are needed in order to reduce the equivalent esr and suppress the voltage ripple to a tolerable level. a small decoupling capacitor (1 m f) in parallel for bypass- ing the noise is also recommended, and the voltage rat- ing of the output capacitors are also must be considered. to support a load transient that is faster than the switch- ing frequency, more capacitors are needed for reducing the voltage excursion during load step change. another aspect of the capacitor selection is that the total ac cur- rent going through the capacitors has to be less than the rated rms current specified on the capacitors in order to prevent the capacitor from over-heating. i n p u t c a p a c i t o r s e l e c t i o n t h e i n p u t c a p a c i t o r i s c h o s e n b a s e d o n t h e v o l t a g e r a t i n g a n d t h e r m s c u r r e n t r a t i n g . f o r r e l i a b l e o p e r a t i o n , s e l e c t - i n g t h e c a p a c i t o r v o l t a g e r a t i n g t o b e a t l e a s t 1 . 3 t i m e s o u t p u t c a p a c i t o r s e l e c t i o n ( c o n t . )
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 1 a p w 8 8 1 6 locate the resistor-divider close to the fb pin to mini- mize the high impedance trace. in addition, fb pin traces can?t be close to the switching signal traces (ugate, lgate, boot, and phase). a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) t h e s i g n a l s g o i n g t h r o u g h t h e s e s t r a c e s h a v e b o t h h i g h d v / d t a n d h i g h d i / d t w i t h h i g h p e a k c h a r g i n g a n d d i s - c h a r g i n g c u r r e n t . t h e t r a c e s f r o m t h e g a t e d r i v e r s t o t h e m o s f e t s ( u g a t e a n d l g a t e ) s h o u l d b e s h o r t a n d w i d e . p l a c e t h e s o u r c e o f t h e h i g h - s i d e m o s f e t a n d t h e d r a i n o f t h e l o w - s i d e m o s f e t a s c l o s e a s p o s s i b l e . m i n i m i z - i n g t h e i m p e d a n c e w i t h w i d e l a y o u t p l a n e b e t w e e n t h e t w o p a d s r e d u c e s t h e v o l t a g e b o u n c e o f t h e n o d e . i n a d d i t i o n , t h e l a r g e l a y o u t p l a n e b e t w e e n t h e d r a i n o f t h e m o s f e t s ( v i n a n d p h a s e n o d e s ) c a n g e t b e t t e r h e a t s i n k i n g . the pgnd is the current sensing circuit reference ground and also the power ground of the lgate low- side mosfet. on the hand, the pgnd trace should be a separate trace and independently go to the source of the low-side mosfet. besides, the current sense resistor should be close to ocset pin to avoid parasitic capaci- tor effect and noise coupling. d e c o u p l i n g c a p a c i t o r s , t h e r e s i s t o r - d i v i d e r , a n d b o o t c a p a c i t o r s h o u l d b e c l o s e t o t h e i r p i n s . ( f o r e x a m p l e , p l a c e t h e d e c o u p l i n g c e r a m i c c a p a c i t o r c l o s e t o t h e d r a i n o f t h e h i g h - s i d e m o s f e t a s c l o s e a s p o s s i b l e . ) t h e i n p u t b u l k c a p a c i t o r s s h o u l d b e c l o s e t o t h e d r a i n o f t h e h i g h - s i d e m o s f e t , a n d t h e o u t p u t b u l k c a p a c i t o r s s h o u l d b e c l o s e t o t h e l o a d s . t h e i n p u t c a p a c i t o r ? s g r o u n d s h o u l d b e c l o s e t o t h e g r o u n d s o f t h e o u t p u t c a p a c i t o r s a n d l o w - s i d e m o s f e t . l a y o u t c o n s i d e r a t i o n i n a n y h i g h s w i t c h i n g f r e q u e n c y c o n v e r t e r , a c o r r e c t l a y o u t i s i m p o r t a n t t o e n s u r e p r o p e r o p e r a t i o n o f t h e r e g u l a t o r . w i t h p o w e r d e v i c e s s w i t c h i n g a t h i g h e r f r e q u e n c y , t h e r e s u l t i n g c u r r e n t t r a n s i e n t w i l l c a u s e v o l t a g e s p i k e a c r o s s t h e i n t e r c o n n e c t i n g i m p e d a n c e a n d p a r a s i t i c c i r c u i t e l e m e n t s . a s a n e x a m p l e , c o n s i d e r t h e t u r n - o f f t r a n s i t i o n o f t h e p w m m o s f e t . b e f o r e t u r n - o f f c o n d i t i o n , t h e m o s f e t i s c a r r y i n g t h e f u l l l o a d c u r r e n t . d u r i n g t u r n - o f f , c u r r e n t s t o p s f l o w i n g i n t h e m o s f e t a n d i s f r e e w h e e l i n g b y t h e l o w s i d e m o s f e t a n d p a r a s i t i c d i o d e . a n y p a r a s i t i c i n d u c t a n c e o f t h e c i r c u i t g e n e r a t e s a l a r g e v o l t a g e s p i k e d u r i n g t h e s w i t c h i n g i n t e r v a l . i n g e n e r a l , u s i n g s h o r t a n d w i d e p r i n t e d c i r c u i t t r a c e s s h o u l d m i n i m i z e i n t e r c o n n e c t - i n g i m p e d a n c e s a n d t h e m a g n i t u d e o f v o l t a g e s p i k e . b e s i d e s , s i g n a l a n d p o w e r g r o u n d s a r e t o b e k e p t s e p a - r a t i n g a n d f i n a l l y c o m b i n e d u s i n g g r o u n d p l a n e c o n s t r u c - t i o n o r s i n g l e p o i n t g r o u n d i n g . t h e b e s t t i e - p o i n t b e t w e e n the signal ground and the power ground is at the nega- tive side of the output capacitor on each channel, where there is less noise. noisy traces beneath the ic are not recommended. below is a checklist for your layout: k e e p t h e s w i t c h i n g n o d e s ( u g a t e , l g a t e , b o o t , a n d p h a s e ) a w a y f r o m s e n s i t i v e s m a l l s i g n a l n o d e s s i n c e t h e s e n o d e s a r e f a s t m o v i n g s i g n a l s . t h e r e f o r e , k e e p t r a c e s t o t h e s e n o d e s a s s h o r t a s p o s - s i b l e a n d t h e r e s h o u l d b e n o o t h e r w e a k s i g n a l t r a c e s i n p a r a l l e l w i t h t h e s e s t r a c e s o n a n y l a y e r . 0 . 5 mm 0 . 24 mm 0 . 508 mm 0 . 162 mm 1 . 66 mm 3 mm * just recommend tqfn 3 x 3 - 16 3 mm 1 . 6 6 m m 0 . 5 mm * r e c o m m e n d e d m i n i m u m f o o t p r i n t
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 2 a p w 8 8 1 6 p a c k a g e i n f o r m a t i o n t q f n 3 x 3 - 1 6 d e pin 1 a b a1 a3 d2 e 2 e pin 1 corner k l note : follow jedec mo-220 weed-4. s y m b o l min. max. 0.80 0.00 0.18 0.30 1.50 1.80 0.05 1.50 a a1 b d d2 e e2 e l millimeters a3 0.20 ref tqfn3x3-16 0.30 0.50 1.80 0.008 ref min. max. inches 0.031 0.000 0.007 0.012 0.059 0.071 0.059 0.012 0.020 0.70 0.071 0.028 0.002 0.50 bsc 0.020 bsc k 0.20 0.008 2.90 3.10 0.114 0.122 2.90 3.10 0.114 0.122
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 3 a p w 8 8 1 6 application a h t1 c d d w e1 f 330 ? 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 12.0 ? 0.30 1.75 ? 0.10 5.5 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 tqfn3x3 - 16 4.0 ? 0.10 8.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0 .40 3.30 ? 0.20 3.30 ? 0.20 1.30 ? 0.20 (mm) c a r r i e r t a p e & r e e l d i m e n s i o n s a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 h t1 a d d e v i c e s p e r u n i t package type unit quantity tqfn3x3 - 16 tape & reel 3000
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 4 a p w 8 8 1 6 t a p i n g d i r e c t i o n i n f o r m a t i o n t q f n 3 x 3 - 1 6 user direction of feed c l a s s i f i c a t i o n p r o f i l e
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 5 a p w 8 8 1 6 c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spec ified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined a s a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ t j =125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma r e l i a b i l i t y t e s t p r o g r a m
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 6 a p w 8 8 1 6 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8

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