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next generation op07 ultralow offset voltage operational amplifier op77 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2010 analog devices, inc. all rights reserved. features outstanding gain linearity ultrahigh gain, 5000 v/mv min low v os over temperature, 55 v max excellent tcv os , 0.3 v/c max high psrr, 3 v/v max low power consumption, 60 mw max fits op07, 725,108a/308a, 741 sockets available in die form pin connections v os trim 1 ?in 2 +in 3 v? 4 v os trim 8 v+ 7 out 6 nc 5 nc = no connect op77 top view (not to scale) 00320-001 figure 1. 8-pin hermetic dip_q-8 (z suffix) v os trim v os trim v+ 4v? (case) +in nc nc = no connect ?in out 00320-002 op77 top view (not to scale) 7 3 1 5 6 2 8 4 figure 2. to-99 (j suffix) general description the op77 significantly advances the state-of-the-art in precision op amps. the outstanding gain of 10,000,000 or more for the op77 is maintained over the full 10 v output range. this exceptional gain-linearity eliminates incorrectable system nonlinearities common in previous monolithic op amps and provides superior performance in high closed-loop gain applications. low initial v os drift and rapid stabilization time, combined with only 50 mw of power consumption, are significant improvements over previous designs. these characteristics, plus the exceptional tcv os of 0.3 v/c maximum and the low v os of 25 v maximum, eliminates the need for v os adjustment and increases system accuracy over temperature. a psrr of 3 v/v (110 db) and cmrr of 1.0 v/v maximum virtually eliminate errors caused by power supply drifts and common-mode signals. this combination of outstanding characteristics makes the op77 ideally suited for high resolution instrumentation and other tight error budget systems.
op77 rev. e | page 2 of 16 table of contents features .............................................................................................. 1 pin connections ............................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 electrical specifications ............................................................... 3 wafer test limits .......................................................................... 4 typical electrical characteristics ............................................... 5 absolute maximum ratings ............................................................ 6 thermal resistance .......................................................................6 esd caution...................................................................................6 typical performance characteristics ..............................................7 test circuits ..................................................................................... 10 applications ..................................................................................... 11 precision current sinks ............................................................. 12 outline dimensions ....................................................................... 15 ordering guide .......................................................................... 16 revision history 4/10rev. d to rev. e removed figure 33 and two subsequent paragraphs ............... 12 6/09rev. c to rev. d changes to figure 1 and figure 2 ................................................... 1 changes to table 1 ............................................................................ 3 removed endnote 1 and endnote 2 in table 3 ............................ 4 changes to figure 16 ........................................................................ 9 changes to figure 31 and figure 32 ............................................. 12 changes to figure 38 ...................................................................... 14 moved figure 39 ............................................................................. 14 10/02rev. b to rev. c edits to specifications ...................................................................... 2 figure 2 caption changed ............................................................ 10 figure 3 caption changed ............................................................ 10 edits to figure 10 ............................................................................ 11 updated outline dimensions ....................................................... 15 2/02rev. a to rev. b remove 8-lead so pin connection diagrams ........................... 1 changes to absolute maximum rating ......................................... 2 remove op77b column from specifications ................................ 2 remove op77b column from electrical characteristics ........ 3, 5 remove op77g column from wafer test limits ......................... 6 remove op77g column from typical electrical characteristics6
op77 rev. e | page 3 of 16 electrical specifications @ v s = 15 v, t a = 25c, unless otherwise noted. table 1. op77e op77f parameter symbol conditions min typ max min typ max unit input offset voltage v os 10 25 20 60 v long-term stability 1 v os /time 0.3 0.4 v/mo input offset current i os 0.3 1.5 0.3 2.8 na input bias current i b ?0.2 +1.2 +2.0 ?0.2 +1.2 +2.8 na input noise voltage 2 e np-p 0.1 hz to 10 hz 0.35 0.6 0.38 0.65 v p-p input noise voltage density e n f o = 10 hz 10.3 18.0 10.5 20.0 nv/hz f o = 100 hz 2 10.0 13.0 10.2 13.5 f o = 1000 hz 9.6 11.0 9.8 11.5 input noise current 2 i np-p 0.1 hz to 10 hz 14 30 15 35 pa p-p input noise current density i n f o = 10 hz 0.32 0.80 0.35 0.90 pahz f o = 100 hz 2 0.14 0.23 0.15 0.27 f o = 1000 hz 0.12 0.17 0.13 0.18 input resistance differential mode 3 r in 26 45 18.5 45 m common mode r incm 200 200 g input voltage range ivr 13 14 13 14 v common-mode rejection ratio cmrr v cm = 13 v 0.1 1.0 0.1 1.6 v/v power supply rejection ratio psrr v s = 3 v to 18 v 0.7 3.0 0.7 3.0 v/v large-signal voltage gain a vo r l 2 k 5000 12,000 2000 6000 v/mv v o = 10 v output voltage swing v o r l 10 k 13.5 14.0 13.5 14.0 v r l 2 k 12.5 13.0 12.5 13.0 r l 1 k 12.0 12.5 12.0 12.5 slew rate 2 sr r l 2 k 0.1 0.3 0.1 0.3 v/s closed-loop bandwidth 2 bw a vcl + 1 0.4 0.6 0.4 0.6 mhz open-loop output resistance r o 60 60 power consumption p d v s = 15 v, no load 50 60 50 60 mw v s = 3 v, no load 3.5 4.5 3.5 4.5 offset adjustment range rp = 20 kn 3 3 mv 1 long-term input offset voltage stability refers to the averaged trend line of v os vs. time over extended periods after the firs t 30 days of operation. excluding the initial hour of operation, changes in v os during the first 30 operating days are typically 2.5 v. 2 sample tested. 3 guaranteed by design.
op77 rev. e | page 4 of 16 @ v s = 15 v, ?25c t a +85c for op77fj and op77e/op77f, unless otherwise noted. table 2. op77e op77f parameter symbol conditions min typ max min typ max unit input offset voltage v os 10 45 20 100 v average input offset voltage drift 1 tcv os 0.1 0.3 0.2 0.6 v/c input offset current i os 0.5 2.2 0.5 4.5 na average input offset current drift 2 tci os 1.5 4.0 1.5 85 pa/c input bias current i b ?0.2 +2.4 +4.0 ?0.2 +2.4 +6.0 na average input bias current drift 2 tci b 8 40 15 60 pa/c input voltage range ivr 13.0 13.5 13.0 13.5 v common-mode rejection ratio cmrr v cm = 13 v 0.1 1.0 0.1 3.0 pv/v power supply rejection ratio psrr v s = 3 v to 18 v 1.0 3.0 1.0 5.0 v/v large-signal voltage gain a vo r l 2 k 2000 6000 1000 4000 v/mv v o = 10 v output voltage swing v o r l 2 k 12 13.0 12 13.0 v power consumption p d v s = 15 v, no load 60 75 60 75 mw 1 op77e: tcv os is 100% tested on j and z packages. 2 guaranteed by end-point limits. wafer test limits @ v s = 15 v, t a = 25c, for OP77NBC devices, unless otherwise noted. table 3. parameter symbol conditions OP77NBC limit unit input offset voltage v os 40 v max input offset current i os 2.0 na max input bias current i b 2 na max input resistance differential mode r in 26 m min input voltage range ivr 13 v min common-mode rejection ratio cmrr v cm = 13 v 1 v/v max power supply rejection ratio psrr v s = 3 v to 18 v 3 v/v max output voltage swing v o r l = 10 k 13.5 v min r l = 2 k 12.5 r l = 1 k 12.0 large-signal voltage gain a vo r l = 2 k 2000 v/mv min v o = 10 v differential input voltage 30 v max power consumption p d v o = 0 v 60 mw max
op77 rev. e | page 5 of 16 typical electrical characteristics @ v s = 15 v, t a = 25c, unless otherwise noted. table 4. parameter symbol conditions OP77NBC limit unit average input offset voltage drift tcv os r s = 50 0.1 v/c nulled input offset voltage drift tcv osn r s = 50 , r p = 20 k 0.1 v/c average input offset current drift tci os 0.5 pa/c slew rate sr r l 2 k 0.3 v/s bandwidth bw a vcl + 1 0.6 mhz
op77 rev. e | page 6 of 16 absolute maximum ratings table 5. parameter 1 rating supply voltage 22 v differential input voltage 30 v input voltage 2 22 v output short-circuit duration indefinite storage temperature range ?65c to +150c operating temperature range ?25c to +85c junction temperature (t j ) ?65c to +150c lead temperature (soldering, 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance table 6. package type ja 1 jc unit 8-pin to-99 h-08 (j suffix) 150 18 c/w 8-lead hermetic cerdip q-8 (z suffix) 148 16 c/w 1 absolute maximum ratings apply to both dice and packaged parts, unless otherwise noted. 2 for supply voltages less than 22 v, the absolute maximum input voltage is equal to the supply voltage. 1 ja is specified for worst-case mounting conditions, i.e., ja is specified for a device in socket for the to-99 and cerdip packages. esd caution
op77 rev. e | page 7 of 16 typical performance characteristics 2 1 0 ?1 ?2 ?10 ?5 0 5 10 output voltage (v) input voltage (v) (nulled to 0v @ v out = 0v) 00320-004 v s = 15v t a = 25c r l = 10k ? figure 3. gain linearity (input voltage vs. output voltage) 25 20 15 10 5 0 ?55 ?35 ?15 5 25 45 65 85 105 125 temperature (c) open-loop gain (v/v) 00320-005 v s = 15v figure 4. open-loop gain vs. temperature 16 12 8 4 0 0 5 10 15 20 power supply voltage (v) open-loop gain (v/v) 00320-006 t a = 25c r l = 2k ? figure 5. open-loop gain vs. power supply voltage 30 20 10 0 ?10 ?20 ?30 ?55 ?35 ?15 5 25 45 65 85 105 125 temperature (c) change in offset voltage (v) 00320-007 j, z packages +0.3v/c mean s.d. ?0.3v/c figure 6. untrimmed offset voltage vs. temperature 4 3 2 1 0 ?1 ?2 ?3 ?4 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 time after power supply turn-on (minutes) change in input offset voltage (v) 00320-008 v s = 15v t a = 25c figure 7. warm-up drift 30 25 20 15 10 5 0 ?10 0 1020304050 6070 time (seconds) absolute change in input offset voltage (v) 00320-009 v s = 15v device immersed in 70c oil bath (20 units) maximum mimimum average figure 8. offset voltage change due to thermal shock
op77 rev. e | page 8 of 16 100 80 60 40 20 0 ?20 10 100 1k 10k 100k 1m 10m frequency (hz) closed-loop gain (db) 00320-010 v s = 15v t a = 25c figure 9. closed-loop response for various gain configurations 160 140 120 100 80 60 40 20 0 0 45 90 135 180 0.01 0.1 1 10 100 1k 10k 100k 1m frequency (hz) open-loop gain (db) phase (degrees) 00320-011 v s = 15v t a = 25c figure 10. open-loop gain/phase response 150 140 130 120 110 100 90 80 1 10 100 1k 10k 100k frequency (hz) cmmr (db) 00320-012 t a = 25c figure 11. cmrr vs. frequency 130 120 110 100 90 80 70 60 0.1 1 10 100 1k 10k frequency (hz) psrr (db) 00320-013 t a = 25c figure 12. psrr vs. frequency 4 3 2 1 0 ?75 ?50 ?25 0 25 50 75 100 125 temperature (c) input bias current (na) 00320-014 v s = 15v figure 13. input bias current vs. temperature 2.0 1.5 1.0 0.5 0 ?75 ?50 ?25 0 25 50 75 100 125 temperature (c) input offset current (na) 00320-015 v s = 15v figure 14. input offset current vs. temperature
op77 rev. e | page 9 of 16 10 1 0.1 100 1k 10k 100k frequency (hz) rms noise (mv) 00320-016 v s = 15v t a = 25c figure 15. input wideband noise vs . bandwidth (0.1 hz to frequency indicated) 1k 100 10 1 1 10 100 1k frequency (hz) input noise voltage (nv/ hz) 00320-017 v s = 15v t a = 25c resistors included excluded r s = 0 rs1 = rs2 = 200k ? thermal noise of source figure 16. total input noise voltage vs. frequency 32 28 24 20 16 12 8 4 0 1k 10k 100k 1m frequency (hz) peak-to-peak amplitude (v) 00320-018 v s = 15v t a = 25c figure 17. maximum output swing vs. frequency 100 10 1 01 02 03 04 0 total supply voltage v+ to v? (v) power consumption (mw) 00320-019 t a = 25c figure 18. power consum ption vs. power supply 20 15 10 5 0 100 1k 10k load resistance to ground ( ? ) maximum output (v) 00320-020 v s = 15v t a = 25c v in = 10mv positive swing negative swing figure 19. maximum output voltage vs. load resistance 40 35 30 25 20 15 0123 time from output being shortened (minutes) output short-circuit current (ma) 00320-021 4 v s = 15v t a = 25c figure 20. output short-circuit current vs. time
op77 rev. e | page 10 of 16 test circuits op77 200k ? v o 50 ? v os = v o 4000 00320-022 figure 21. typical offset voltage test circuit input referred noise = v o 25,000 00320-023 op77 2.5m ? v+ v? output 100 ? 100 ? 3.3k ? 4.7f ( 10hz filter) 7 6 4 2 3 figure 22. typical low-freq uency noise test circuit 00320-024 op77 v+ output v? 20k? input + ? 1 8 7 6 4 2 3 figure 23. optional o ffset nulling circuit 00320-025 op77 100k? +18v ?18v 7 6 4 2 3 + 10f + 10f 0.1f 0.1f * * 10 ? 10 ? 10k? 10k ? notes * 1 per board figure 24. burn-in circuit 1m ? r l v x 10? 10k ? 100k ? v in = 10v typic a lprecision op amp v y v x ?10v 0v +10v notes 1. gain not consistant. causes nonlinear errors. 2 .a vo spec is only part of the solution. 3 . check specifi c ation table 1 and table 2 for performance. 00320-026 a vo 650v/mv r l = 2k ? figure 25. open-loop gain linearity actual open-loop voltage gain can vary greatly at various output voltages. all automated testers use endpoint testing and therefore only show the average gain. this causes errors in high closed- loop gain circuits. because this is difficult for manufacturers to test, users should make their own evaluations. this simple test circuit makes it easy. an ideal op amp would show a horizontal scope trace. v y v x ?10v 0v +10v 00320-027 figure 26. output gain linearity trace this is the output gain linearity trace for the new op77. the output trace is virtually horizontal at all points, assuring extremely high gain accuracy. the average open-loop gain is truly impressiveapproximately 10,000,000.
op77 rev. e | page 11 of 16 applications 00320-028 op77e r2 1m ? r4 1m ? +15v ?15v r1 1k ? r3 1k ? 7 6 4 2 3 0.1f 0.1f figure 27. precision high-gain differential amplifier the high gain, gain linearity, cmrr, and low tcv os of the op77 make it possible to obtain performance not previously available in single-stage, very high-gain amplifier applications. for best cmr, 2r 1r must equal 4r 3r . in this example, with a 10 mv differential signal, the maximum errors are as listed in table 7 . table 7. maximum errors type amount common-mode voltage 0.01%/v gain linearity, worst case 0.02% tcv os 0.003%/c tci os 0.008%/c 00320-029 +15v ?15v r s r f 100 ? 7 6 4 2 3 0.1f 0.1f 10f output input c load op77 figure 28. isolating large capacitive loads this circuit reduces maximum slew rate but allows driving capacitive loads of any size without instability. because the boon resistor is inside the feedback loop, its effect on output impedance is reduced to insignificance by the high open-loop gain of the op77. 00320-030 r1 100k ? r3 1k? r4 990? r5 10? 6 2 3 v in i out < 15ma r2 100k ? op77 figure 29. basic current source 00320-031 r1 r3 +15v ?15v r4 r5 6 2n2222 2n2907 2 3 v in r2 op77 i out = v in ( ) given r3 = r4 + r5, r1 = r2 r3 r1 ? r5 i out < 100ma figure 30. 100 ma current source these current sources can supply both positive and negative current into a grounded load. note that 1r 3r 2r 4r5r 2r 4r 5r z o + ? ? ? ? ? ? + = 1 and that for z o to be infinite 2 r 4r5r + must = 1r 3r
op77 rev. e | page 12 of 16 precision current sinks 0 0320-032 v + 200 ? r1 1 ? 1w r l irf520 i o v in op77 i o = v in > 0v full scale of 1v. i o = 1a/v v in r1 figure 31. positive current sink 00320-033 200 ? r l r1 irf520 i o v in v? op77 i o = v in > 0v v in r1 figure 32. positive current source the simple high-current sinks, shown figure 31 and figure 32 , require the load to float between the power supply and the sink. in these circuits, the high gain, high cmrr, and low tcv os of the op77 ensure high accuracy. the high gain and low tcv os ensure accurate operation with inputs from microvolts to volts. in figure 33 , the signal always appears as a common-mode signal to the op amps. the op77ez cmrr of 1 v/v ensures errors of less than 2 ppm. 00320-035 +15v ?15v 1k? 1k? r3 2k? c1 30pf d1 1n4148 7 6 4 2 3 0.1f 0.1f 2n4393 v in +15v v out 0 < v out < 10v d2 ?15v 7 6 4 2 3 0.1f 0.1f op77e op77e figure 33. precision absolute value amplifier 00320-036 100? v out 15 v 0.1f op77 100? 100? 10f 6 4 ref-01 v o 2 6 4 ref-01 v o 2 6 4 ref-01 v o 2 + figure 34. low noise precision reference
op77 rev. e | page 13 of 16 figure 34 relies upon low tcv os of the op77 and noise combined with very high cmrr to provide precision buffering of the averaged ref-01 voltage outputs. in figure 35 , c h must be of polystyrene, teflon*, or polyethylene to minimize dielectric absorption and leakage. the droop rate is determined by the size of c h and the bias current of the ad820. *teflon is a registered trad emark of the dupont company 00320-037 +15v ?15v 1k ? 1k? 1k? 1n4148 7 6 4 2 3 0.1f 0.1f 2n930 c h v in reset +15v v out ?15v 7 6 4 2 3 0.1f 0.1f ad820 op77 figure 35. precision positive peak detector
op77 rev. e | page 14 of 16 00320-038 +15v ?15v r s 1k? r1 2k? c c r f 100k ? d1 1n4148 7 6 4 2 3 0.1f 0.1f v out v th v in op77 figure 36. precision threshold detector/amplifier when v in < v th , amplifier output swings negative, reversing the biasing diode d1. v o = v th if r l = when v in > v th , the loop closes, () ? ? ? ? ? ? ? ? +?+= s f th in th o r r vvvv 1 c 00320-039 +15 v ?15v r a r b1 2 v in gnd v o trim temp 6 5 3 4 r bp 1.5k ? 50k ? r c 0.1f 0.1f v out op77 ref-02 figure 37. precision temperature sensor table 8. resistor values tcv out slope (s) 10 mv/c 100 mv/c 10 mv/f temperature range ?55c to +125c ?55c to +125c ?67f to +257c output voltage range ?0.55 v to +1.25 v ?5.5 v to +12.5v ?0.67 v to +2.57v zero-scale 0 v @ 0c 0 v @ 0c 0 v @ 0f r a (1% resistor) 9.09 k 15 k 7.5 k r b1 (1% resistor) 1.5 k 1.82 k 1.21 k r bp (potentiometer) 200 500 200 r c (1% resistor) 5.11 k 84.5 k 8.25 k c is selected to smooth the response of the loop. 00320-003 7 18 3 2 4 output 6 r9 r5 c3 c1 c2 r7 r8r6 q19 q18 q20 q16 q17 q11 q12 q10 q9 q13 q27 q4 q3 q8 q5 r3 r2a 1 r1a r2b 1 r1b r4 q1 q23 q7 q24 q21 q22 q6 q2 q26 q25 q14 q15 r10 v+ v? noninverting input inverting input 1 r2a and r2b are electronically adjusted on chip at factory. (optional null) figure 38. simplified schematic
op77 rev. e | page 15 of 16 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) min 0.055 (1.40) max 0.100 (2.54) bsc 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.405 (10.29) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 14 5 8 figure 39. 8-lead ceramic dual in-line package [cerdip] (q-8) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. compliant to jedec standards mo-002-ak 0.2500 (6.35) min 0.5000 (12.70) min 0.1850 (4.70) 0.1650 (4.19) reference plane 0.0500 (1.27) max 0.0190 (0.48) 0.0160 (0.41) 0.0210 (0.53) 0.0160 (0.41) 0.0400 (1.02) 0.0100 (0.25) 0.0400 (1.02) max 0.0340 (0.86) 0.0280 (0.71) 0.0450 (1.14) 0.0270 (0.69) 0.1600 (4.06) 0.1400 (3.56) 0.1000 (2.54) bsc 6 2 8 7 5 4 3 1 0.2000 (5.08) bsc 0.1000 (2.54) bsc 0.3700 (9.40) 0.3350 (8.51) 0.3350 (8.51) 0.3050 (7.75) 45 bsc base & seating plane 022306-a figure 40. 8-pin me tal header [to-99] (h-08) dimensions shown in inches and (millimeters)
op77 rev. e | page 16 of 16 ordering guide model 1 temperature range package description package option op77fj ?25c to +85c 8-pin metal header [to-99] h-08 (j suffix) op77fjz ?25c to +85c 8-pin metal header [to-99] h-08 (j suffix) op77ez ?25c to +85c 8-lead ceramic dual in-line package [cerdip] q-8 (z suffix) op77fz ?25c to +85c 8-lead ceramic dual in-line package [cerdip] q-8 (z suffix) OP77NBC die 1 z = rohs compliant part. ?2002C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00320-0-4/10(e)

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