tp5322 general description the supertex tp5322 is a low threshold enhancement- mode (normally-off) transistor utilizing an advanced vertical dmos structure and supertexs well-proven silicon-gate manufacturing process. this combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coef? cient inherent in mos devices. characteristic of all mos structures, this device is free from thermal runaway and thermally-induced secondary breakdown. supertexs vertical dmos fets are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. absolute maximum ratings parameter value drain-to-source voltage bv dss drain-to-gate voltage bv dgs gate-to-source voltage 20v operating and storage temperature -55 o c to +150 o c soldering temperature 3 300 o c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. 3 distance of 1.6mm from case for 10 seconds. ordering information package options bv dss /bv dgs r ds(on) (max) v gs(th) (max) i d(on) (min) to-236ab 1 to-243aa 2 tp5322k1 tp5322n8 -220v 12 -2.4v -0.7a tp5322k1-g tp5322n8-g -g indicates package is rohs compliant (green) notes: 1 same as sot-23, 2 same as sot-89. p-channel enhancement-mode vertical dmos fets pin con? gurations to-243aa (top view) g d s d product marking for to-243aa: where = 2-week alpha date code tp3c product marking for to-23 6ab: where = 2-week alpha date code p3c to-236ab (top view) gate source drain features high input impedance low threshold low input capacitance fast switching speeds low on resistance low input and output leakage free from secondary breakdown complementary n- and p-channel devices applications logic level interfaces - ideal for ttl and cmos battery operated systems photo voltaic devices analog switches general purpose line drivers telecom switches ? ? ? ? ? ? ? ? ? ? ? ? ? ?
2 tp5322 electrical characteristics symbol parameter min typ max units conditions bv dss drain-to-source breakdown voltage -220 - - v v gs = 0v, i d = -2.0ma v gs(th) gate threshold voltage -1.0 - -2.4 v v gs = v ds , i d = -1.0ma v gs(th) change in v gs(th) with temperature - - 4.5 mv/ o cv gs = v ds , i d = -1.0ma i gss gate body leakage current - - -100 na v gs = 20v, v ds = 0v i d(ss) zero gate voltage drain current - - -10 a v ds = max rating, v gs = 0v - - -1.0 ma v ds = 0.8 max rating, v gs = 0v, t a = 125 o c i d(on) on-state drain current -0.7 -0.95 - a v gs = -10v, v ds = -25v r ds(on) static drain-to-source on-state resistance -1015 v gs = -4.5v, i d = -100ma 8.0 12 v gs = -10v, i d = -200ma r ds(on) change in r ds(on) with temperature - - 1.7 %/ o cv gs = -10v, i d = -200ma g fs forward transconductance 100 250 - mmho v ds = -25v, i d = -200ma c iss input capacitance - 110 pf v gs = 0v, v ds = -25v, f = 1mhz c oss common source output capacitance - 45 c rss reverse transfer capacitance - 20 t d(on) turn-on delay time - - 10 ns v dd = -25v, i d = -0.7a, r gen = 25?, t r rise time - - 15 t d(off) turn-off delay time - - 20 t f fall time - - 15 v sd diode forward voltage drop - - -1.8 v v gs = 0v, i sd = -0.5a t rr reverse recovery time - 300 - ns v gs = 0v, i sd = -0.5a notes: 1.all d.c. parameters 100% tested at 25 o c unless otherwise stated. (pulse test: 300s pulse, 2% duty cycle.) 2.all a.c. parameters sample tested. thermal characteristics package i d (continuous) 1 i d (pulsed) power dissipation @t c = 25 o c jc ( o c/w) jc ( o c/w) i dr 1 i drm to-236ab -0.12a -0.70a 0.36w 200 350 -0.12a -0.7a to-243aa -0.26a -0.90a 1.6w 2 15 78 2 -0.26a -0.9a notes: 1. i d (continuous) is limited by max rated t j . 2. mounted on fr4 board, 25mm x 25mm x 1.57mm. signi? cant p d increase possible on ceramic substrate. switching waveforms and test circuit 90% 10% 90% 90% 10% 10% pulse generator v dd r l output d.u.t. t (on) t d(on) t (off) t d(off) t f t r input input output 0v v dd r gen 0v -10v
3 tp5322 3-lead to-236ab (sot-23) package outline (k1) 2 0.0173 0.0027 (0.4394 0.0685) 0.0906 0.0079 (2.299 0.199) 0.0754 0.0053 (1.915 0.135) 0.0512 0.004 (1.3004 0.1016) 0.0207 0.003 (0.5257 0.0762) 0.115 0.005 (2.920 0.121) 0.0400 0.007 (1.016 0.178) 0.0210 0.003 (0.5334 0.076) 0.0382 0.003 (0.9690 0.0762) 0.0035 0.0025 (0.0889 0.0635) 0.0043 0.0009 (0.1092 0.0229) nom 0.0197 (0.50) dimensions in inches (dimensions in millimeters) measurement legend = 3 1 top view side view end view
4 tp5322 (the package drawing(s) in this data sheet may not re? ect the most current speci? cations. for the latest package outline information go to http://www.supertex.com/packaging.html .) exclusion zone no vias/traces in this area. shape of pad may vary. 3.00 bsc 1.50 bsc 0.5 0.06 0.42 0.06 1.05 0.15 2.45 0.15 4.10 0.15 1.72 0.10 4.50 0.10 2.21 0.08 0.40 0.05 1.50 0.10 notes: all dimensions are in millimeters; all angles in degrees. top view side view bottom view 3-lead to-243aa (sot-89) surface mount package (n8) doc.# dsfp-tp5322 a032807
|
