1 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com sept. 2002 rev. 0 eco #15457 WED3DG648V-D1 64mb- 8mx64 sdram, unbuffered ? burst mode operation ? auto and self refresh capability ? lvttl compatible inputs and outputs ? serial presence detect with eeprom ? fully synchronous: all signals are registered on the positive edge of the system clock ? programmable burst lengths: 1, 2, 4, 8 or full page ? 3.3 volt + 0.3v power supply ? 144 pin so-dimm jedec the wed3dg648v is a 8mx64 synchronous dram module which consists of eight 4mx16 sdram components in tsop- 11 package, and one 2k eeprom in an 8- pin tssop package for serial presence detect which are mounted on a 144 pin so-dimm multilayer fr4 substrate. description features pin configurations (front side/back side) pin names * these pins are not used in this module. ** these pins should be nc in the system which does not support spd. pin front pin back pin front pin back pin back pin back 1 vss 2 vss 51 dq14 52 dq46 95 dq21 96 dq53 3 dq0 4 dq32 53 dq15 54 dq47 97 d q22 98 dq54 5 dq1 6 dq33 55 vss 56 vss 99 dq23 100 dq55 7 dq2 8 dq34 57 nc 58 nc 101 vdd 102 vdd 9 dq3 10 dq35 59 nc 60 nc 103 a6 104 a7 11 vdd 12 vdd 105 a8 106 ba0 13 dq4 14 dq36 107 vss 108 vss 15 dq5 16 dq37 109 a9 110 ba1 17 dq6 18 dq38 61 clk0 62 cke0 111 a10/a p 112 a11 19 dq7 20 dq39 63 vdd 64 vdd 113 v dd 114 vdd 21 vss 22 vss 65 ras 66 cas 115 dq m2 116 dqm6 23 dqm0 24 dqm4 67 we 68 cke1 117 dqm3 118 dqm7 25 dqm1 26 dqm5 69 cs0 70 *a12 119 vss 120 vss 27 vdd 28 vdd 71 cs1 72 *a13 121 dq24 122 dq56 29 a0 30 a3 73 dnu 74 clk1 123 dq25 124 dq57 31 a1 32 a4 75 vss 76 vss 125 dq26 126 dq58 33 a2 34 a5 77 nc 78 nc 127 dq27 128 dq59 35 vss 36 vss 79 nc 80 nc 129 vdd 130 vdd 37 dq8 38 dq40 81 vdd 82 vdd 131 dq 28 132 dq60 39 dq9 40 dq41 83 dq16 84 dq48 133 dq29 134 dq61 41 dq10 42 dq42 85 dq17 86 dq49 135 dq30 136 dq62 43 dq11 44 dq43 87 dq18 88 dq50 137 dq31 138 dq63 45 vdd 46 vdd 89 dq19 90 dq51 139 vs s 140 vss 47 dq12 48 dq44 91 vss 92 vss 141 **s da 142 **scl 49 dq13 50 dq45 93 dq20 94 dq52 143 vdd 144 vdd voltage key * this product is subject to change without notice. a0 ? a11 address input (multiplexed) ba0-1 select bank dq0-63 data input/output clk0,clk1 clock input cke0,cke1 clock enable input cs0,cs1 chip select input ras row address strobe cas column address strobe we write enable dqm0-7 dqm vdd power supply (3.3v) vss ground sda serial data i/o scl serial clock dnu do not use nc no connect
2 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com sept. 2002 rev. 0 eco #15457 WED3DG648V-D1 functional block diagram vss a0 cas ras cke0 vdd cke: sdram d0-d3 cke1 cke: sdram d4-d7 cas: sdram d0-d7 ras: sdram d0-d7 scl sda a2 a1 serial pd a0-a11: sdram d0-d8 a0-a11 ba0-ba1 ba0-ba1: sdram d0-d8 d0-d7 d0-d7 *clock wiring clock input sdrams *clk0 *clk1 4 sdrams 4 sdrams * wire per clock loading table/wiring diagrams d5 d1 d4 d0 d7 d3 d6 d2 s1 we s0 we we we we dqmb0 dqmb2 dqmb3 dqmb1 dqmb4 dqmb6 dqmb7 dqmb5 we we we we i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15
3 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com sept. 2002 rev. 0 eco #15457 WED3DG648V-D1 (voltage referenced to: v ss = 0v, t a = 0c to +70c) absolute maximum ratings parameter symbol value units voltage on any pin relative to vss v in , vout -1.0 ~ 4.6 v voltage on vdd supply relative to vss vdd, vddq -1.0 ~ 4.6 v storage temperature tstg -55 ~ +150 c power dissipation pd 8 w short circuit current ios 50 ma note: permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. recommended dc operating conditions parameter symbol min typ max unit note supply voltage vdd 3.0 3.3 3.6 v input high voltage vih 2.0 3.0 vddq+0.3 v 1 input low voltage vil -0.3 ? 0.8 v 2 output high voltage voh 2.4 ? ? v ioh= -2ma output low voltage vol ? ? 0.4 v iol= -2ma input leakage current ili -10 ? 10 a 3 note: 1. vih (max)= 5.6v ac. the overshoot voltage duration is 3ns. 2. vil (min)= -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v vin vddq input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. capacitance (t a = 23c, f = 1mhz, v dd = 3.3v, vref=1.4v 6 200mv) parameter symbol min max unit input capacitance (a0-a12) cin1 - 25 pf input capacitance (ras,cas,we) cin2 - 25 pf input capacitance (cke0,cke1) cin3 - 25 pf input capacitance (clk0,clk1) cin4 - 21 pf input capacitance (cs0,cs1) cin5 - 25 pf input capacitance (dqm0-dqm7) cin6 - 12 pf input capacitance (ba0-ba1) cin7 - 25 pf data input/output capacitance (dq0-dq63) cout - 12 pf
4 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com sept. 2002 rev. 0 eco #15457 WED3DG648V-D1 operating current characteristics (v cc = 3.3v, t a = 0c to +70c) notes: 1. measured with outputs open. 2. refresh period is 64ms. 3. unless otherwise noticed, input swing level is cmos (vih/vil = vddq/vssq) 1 bank version parameter symbol conditions 133 100units note operating current icc1 burst length = 1 460 400 ma 1 (one bank active) trc trc(min) iol = 0ma precharge standby current icc2p cke vil(max), tcc = 10ns 5 ma in power down mode icc2ps cke & clk vil(max), tcc = 5 icc2n cke vih(min), cs vih(min), tcc = 10ns precharge standby current input signals are charge d one time during 20 60 in non-power down mode icc2ns cke vih(min), clk vil(max), tcc = ma input signals are stable 30 active standby current in icc3p cke vil(max), tcc = 10ns 15 ma power-down mode icc3ps cke & clk vil(max), tcc = 15 icc3n cke vih(min), cs vih(min), tcc = 10ns active standby current in input signals are chang ed one time during 20ns 110 ma non power-down mode icc3ns cke vih(min), clk vil(max), tcc = input signals are stable 80 ma io = ma operating current (burst mode) icc4 page burst 560 440 ma 1 4 banks activated tccd = 2clk refresh current icc5 trc trc(min) 560 500 ma 2 self refresh current icc6 cke 0.2v 10 ma
5 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com sept. 2002 rev. 0 eco #15457 WED3DG648V-D1 all dimensions are in inches package dimensions ordering information speed cas latency wed3dg648v10d1 100mhz cl=2 wed3dg648v7d1 133mhz cl=2 wed3dg648v75d1 133mhz cl=3 .170 max.
6 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com sept. 2002 rev. 0 eco #15457 WED3DG648V-D1 rev. date requested by details a 11-15-01 paul marien created b 6-25-02 paul marien -correct part number on th e ordering inform ation table 0 9-6-02 paul marien -change from advanced to final
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