74act11652 octal bus transceiver and register with 3-state outputs scas087a april 1993 revised april 1996 1 post office box 655303 ? dallas, texas 75265 independent registers and enables for a and b buses multiplexed real-time and stored data flow-through architecture optimizes pcb layout center-pin v cc and gnd configurations minimize high-speed switching noise epic (enhanced-performance implanted cmos) 1- m process 500-ma typical latch-up immunity at 125 c description this device consists of bus transceiver circuits, d-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. enable gab and g ba are provided to control the transceiver functions. sab and sba control pins are provided to select whether real-time or stored data is transferred. the circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. a low input level selects real-time data, and a high selects stored data. figure 1 illustrates the four fundamental bus-management functions that can be performed with the octal bus transceivers and registers. data on the a or b data bus, or both, can be stored in the internal d flip-flops by low-to-high transitions at the appropriate clock pins (cab or cba), regardless of the select or enable control pins. when sab and sba are in the real-time transfer mode, it is also possible to store data without using the internal d-type flip-flops by simultaneously enabling gab and g ba. in this configuration, each output reinforces its input. thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state. the 74act11652 is characterized for operation from 40 c to 85 c. copyright ? 1996, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. epic is a trademark of texas instruments incorporated. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 gab a1 a2 a3 a4 gnd gnd gnd gnd a5 a6 a7 a8 g ba cab sab b1 b2 b3 b4 v cc v cc b5 b6 b7 b8 cba sba dw package (top view)
74act11652 octal bus transceiver and register with 3-state outputs scas087a april 1993 revised april 1996 2 post office box 655303 ? dallas, texas 75265 bus a bus b bus a bus b gab g ba cab cba sab sba gab g ba cab cba sab sba llxxxl hhxxlx real-time transfer bus b to bus a real-time transfer bus a to bus b bus a bus b bus a bus b gab g ba cab cba sab sba gab g ba cab cba sab sba xh x x x l l h or l h or l x h lxx xx lh xx storage from a and/or b transfer stored data to a and/or b figure 1. bus transfer diagram
74act11652 octal bus transceiver and register with 3-state outputs scas087a april 1993 revised april 1996 3 post office box 655303 ? dallas, texas 75265 function table inputs data i/o 2 operation or function gab g ba cab cba sab sba a1a8 b1b8 operation or function l h h or l h or l x x in p ut in p ut isolation l h x x inp u t inp u t store a and b data x h h or l x x input unspecified 2 store a, hold b h h x 3 x input output store a in both registers l x h or l x x unspecified 2 input hold a, store b l l x x 3 output input store b in both registers l l x x x l out p ut in p ut real-time b data to a bus l lx h or l x h o u tp u t inp u t stored b data to a bus h h x x l x in p ut out p ut real-time a data to b bus h h h or l xh x inp u t o u tp u t stored a data to b bus h l h or l h or l h h output output stored a data to b bus and stored b data to a bus 2 the data-output functions may be enabled or disabled by various signals at the gab or g ba inputs. data-input functions are always enabled, i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs. 3 select control = l: clocks can occur simultaneously. select control = h: clocks must be staggered to load both registers. logic symbol this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. 5 5 b8 b7 b6 b5 b4 b3 b2 b1 17 18 19 20 23 24 25 26 a8 a7 a6 a5 a4 a3 a2 a1 sab cab sba cba g ba 2 27 28 15 16 14 1 6d 7 7 4d g7 c6 g5 c4 en2 [ab] en1 [ba] 2 1 1 1 1 1 gba 3 4 5 10 11 12 13
74act11652 octal bus transceiver and register with 3-state outputs scas087a april 1993 revised april 1996 4 post office box 655303 ? dallas, texas 75265 logic diagram (positive logic) to seven other channels b1 26 a1 2 sab cab sba cba gab g ba 27 28 15 16 14 1 channels one of eight 1d c1 c1 1d absolute maximum rating over operating free-air temperature range (unless otherwise noted) 2 supply voltage, v cc 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (see note 1) 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o (see note 1) 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v cc ) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output current, i o (v o = 0 to v cc ) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through v cc or gnd 200 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . maximum power dissipation at t a = 55 c (in still air) (see note 2) 1.7 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. the maximum package power dissipation is calculated using a junction temperature of 150 c and a board trace length of 750 mils. recommended operating conditions (see note 3) min max unit v cc supply voltage 4.5 5.5 v v ih high-level input voltage 2 v v il low-level input voltage 0.8 v v i input voltage 0 v cc v v o output voltage 0 v cc v i oh high-level output current 24 ma i ol low-level output current 24 ma d t/ d v input transition rise or fall rate 0 10 ns/v t a operating free-air temperature 40 85 c note 3: unused inputs must be held high or low to prevent them from floating.
74act11652 octal bus transceiver and register with 3-state outputs scas087a april 1993 revised april 1996 5 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc t a = 25 c min max unit parameter test conditions v cc min typ max min max unit i oh =50 a 4.5 v 4.4 4.4 i oh = 50 a 5.5 v 5.4 5.4 v oh i oh =24ma 4.5 v 3.94 3.8 v i oh = 24 ma 5.5 v 4.94 4.8 i oh = 75 ma 5.5 v 3.85 i ol =50 a 4.5 v 0.1 0.1 i ol = 50 a 5.5 v 0.1 0.1 v ol i ol =24ma 4.5 v 0.36 0.44 v i ol = 24 ma 5.5 v 0.36 0.44 i ol = 75 ma 5.5 v 1.65 i oz a or b ports 3 v o = v cc or gnd 5.5 v 0.5 5 a i i gab or g ba v i = v cc or gnd 5.5 v 0.1 1 a i cc v i = v cc or gnd, i o = 0 5.5 v 8 80 a i cc one input at 3.4 v, other inputs at gnd or v cc 5.5 v 0.9 1 ma c i gab or g ba v i = v cc or gnd 5 v 4.5 pf c o a or b ports v o = v cc or gnd 5 v 12 pf 2 not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. 3 for i/o ports, the parameter i oz includes the input leakage current. this is the increase in supply current for each input that is at one of the specified ttl voltage levels rather than 0 v or v cc . timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see figure 2) parameter t a = 25 c min max unit parameter min max min max unit f clock clock frequency 0 105 0 105 mhz t w pulse duration, cab or cba high or low 4.8 4.8 ns t su setup time, a before clk or b before cba 4 4 ns t h hold time, a after cab or b after cba 2.5 2.5 ns
74act11652 octal bus transceiver and register with 3-state outputs scas087a april 1993 revised april 1996 6 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see figure 2) parameter from to t a = 25 c min max unit parameter (input) (output) min typ max min max unit f max 105 105 mhz t plh aorb bora 3.8 7 9.9 3.8 11.1 ns t phl a or b b or a 3.4 6.7 10.7 3.4 11.6 ns t plh cba or cab aorb 5.4 8.4 11.8 5.4 13.1 ns t phl cba or cab a or b 6.1 9.4 13.1 6.1 14.4 ns t plh sba or sab 2 aorb 2.8 6.2 10.1 2.8 11 ns t phl with a or b high a or b 5.5 8.7 12.1 5.5 13.3 ns t plh sba or sab 2 aorb 4.9 7.8 11 4.9 12.2 ns t phl with a or b low a or b 3.9 7.5 11.6 3.9 12.6 ns t pzh g ba a 3.3 7.2 11.4 3.3 12.6 ns t pzl gba a 4.1 7.8 12.6 4.1 13.8 ns t phz g ba a 5.2 7.2 9.3 5.2 9.9 ns t plz gba a 4.8 6.7 8.6 4.8 9.3 ns t pzh gab b 5.1 9.1 13.4 5.1 15.2 ns t pzl gab b 5.8 9.7 14.2 5.8 16.1 ns t phz gab b 3.4 6.8 9.7 3.4 10.3 ns t plz gab b 3.1 6 8.8 3.1 9.3 ns 2 these parameters are measured with the internal output state of the storage register opposite that of the bus input. operating characteristics, v cc = 5 v, t a = 25 c parameter test conditions typ unit c d power dissi p ation ca p acitance p er transceiver outputs enabled c l =50 p f f=1mhz 59 p f c pd po w er dissipation capacitance per transcei v er outputs disabled c l = 50 pf , f = 1 mh z 14 pf
74act11652 octal bus transceiver and register with 3-state outputs scas087a april 1993 revised april 1996 7 post office box 655303 ? dallas, texas 75265 parameter measurement information 50% v cc 1.5 v 1.5 v 1.5 v 3 v 3 v 0 v 0 v t h t su voltage waveforms data input t plh t phl t phl t plh v oh v oh v ol v ol 1.5 v 1.5 v 3 v 0 v 50% v cc 50% v cc input out-of-phase output in-phase output timing input 50% v cc voltage waveforms from output under test c l = 50 pf (see note a) load circuit s1 2 v cc 500 w 500 w output control (low-level enabling) output waveform 1 s1 at 2 v cc (see note b) output waveform 2 s1 at gnd (see note b) v ol v oh t pzl t pzh t plz t phz 1.5 v 1.5 v v cc 0 v 50% v cc 20% v cc 50% v cc 80% v cc 0 v 3 v gnd open voltage waveforms t plh /t phl t plz /t pzl t phz /t pzh open 2 v cc gnd test s1 3 v 0 v 1.5 v 1.5 v t w voltage waveforms input notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 1 mhz, z o = 50 w , t r = 3 ns, t f = 3 ns. d. the outputs are measured one at a time with one input transition per measurement. figure 2. load circuit and voltage waveforms
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